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* configure: Regenerate.
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
538a76d6 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
4e052eda 41#include "regcache.h"
d16aafd8 42#include "doublest.h"
c906108c 43
1a8629c7
MS		 44#include "solib-svr4.h"
45
53116e27 46void (*sh_show_regs) (void);
3bbfbb92
EZ		 47CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
48void (*do_pseudo_register) (int);
cc17453a 49
88e04cc1
EZ		 50#define SH_DEFAULT_NUM_REGS 59
51
cc17453a
EZ		 52/* Define other aspects of the stack frame.
53 we keep a copy of the worked out return pc lying around, since it
54 is a useful bit of info */
55
56struct frame_extra_info
57{
58 CORE_ADDR return_pc;
59 int leaf_function;
60 int f_offset;
63978407 61};
c906108c 62
cc17453a
EZ		 63static char *
64sh_generic_register_name (int reg_nr)
c5aa993b 65{
cc17453a 66 static char *register_names[] =
c5aa993b 67 {
cc17453a
EZ		 68 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
69 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
70 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
71 "fpul", "fpscr",
72 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
73 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
74 "ssr", "spc",
75 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
76 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
77 };
78 if (reg_nr < 0)
79 return NULL;
80 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
81 return NULL;
82 return register_names[reg_nr];
83}
84
85static char *
86sh_sh_register_name (int reg_nr)
87{
88 static char *register_names[] =
63978407 89 {
cc17453a
EZ		 90 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
91 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
92 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
93 "", "",
94 "", "", "", "", "", "", "", "",
95 "", "", "", "", "", "", "", "",
96 "", "",
97 "", "", "", "", "", "", "", "",
98 "", "", "", "", "", "", "", "",
99 };
100 if (reg_nr < 0)
101 return NULL;
102 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
103 return NULL;
104 return register_names[reg_nr];
105}
106
107static char *
108sh_sh3_register_name (int reg_nr)
109{
110 static char *register_names[] =
c5aa993b 111 {
cc17453a
EZ		 112 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
113 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
114 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
115 "", "",
116 "", "", "", "", "", "", "", "",
117 "", "", "", "", "", "", "", "",
118 "ssr", "spc",
119 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
120 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
121 };
122 if (reg_nr < 0)
123 return NULL;
124 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
125 return NULL;
126 return register_names[reg_nr];
127}
128
129static char *
130sh_sh3e_register_name (int reg_nr)
131{
132 static char *register_names[] =
63978407 133 {
cc17453a
EZ		 134 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
135 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
136 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
137 "fpul", "fpscr",
138 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
139 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
140 "ssr", "spc",
141 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
142 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
143 };
144 if (reg_nr < 0)
145 return NULL;
146 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
147 return NULL;
148 return register_names[reg_nr];
149}
150
151static char *
152sh_sh_dsp_register_name (int reg_nr)
153{
154 static char *register_names[] =
c5aa993b 155 {
cc17453a
EZ		 156 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
157 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
158 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
159 "", "dsr",
160 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
161 "y0", "y1", "", "", "", "", "", "mod",
162 "", "",
163 "rs", "re", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
165 };
166 if (reg_nr < 0)
167 return NULL;
168 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
169 return NULL;
170 return register_names[reg_nr];
171}
172
173static char *
174sh_sh3_dsp_register_name (int reg_nr)
175{
176 static char *register_names[] =
c5aa993b 177 {
cc17453a
EZ		 178 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
179 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
180 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
181 "", "dsr",
182 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
183 "y0", "y1", "", "", "", "", "", "mod",
184 "ssr", "spc",
185 "rs", "re", "", "", "", "", "", "",
186 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
187 "", "", "", "", "", "", "", "",
188 };
189 if (reg_nr < 0)
190 return NULL;
191 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
192 return NULL;
193 return register_names[reg_nr];
194}
195
53116e27
EZ		 196static char *
197sh_sh4_register_name (int reg_nr)
198{
199 static char *register_names[] =
200 {
a38d2a54 201 /* general registers 0-15 */
53116e27
EZ		 202 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
203 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 204 /* 16 - 22 */
53116e27 205 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 206 /* 23, 24 */
53116e27 207 "fpul", "fpscr",
a38d2a54 208 /* floating point registers 25 - 40 */
53116e27
EZ		 209 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
210 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 211 /* 41, 42 */
53116e27 212 "ssr", "spc",
a38d2a54 213 /* bank 0 43 - 50 */
53116e27 214 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 215 /* bank 1 51 - 58 */
53116e27 216 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 217 /* double precision (pseudo) 59 - 66 */
fe9f384f 218 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 219 /* vectors (pseudo) 67 - 70 */
fe9f384f 220 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 221 /* FIXME: missing XF 71 - 86 */
222 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 223 };
224 if (reg_nr < 0)
225 return NULL;
226 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
227 return NULL;
228 return register_names[reg_nr];
229}
230
cc17453a 231static unsigned char *
fba45db2 232sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 233{
234 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
235 static unsigned char breakpoint[] = {0xc3, 0xc3};
236
237 *lenptr = sizeof (breakpoint);
238 return breakpoint;
239}
c906108c
SS		 240
241/* Prologue looks like
c5aa993b
JM		 242 [mov.l <regs>,@-r15]...
243 [sts.l pr,@-r15]
244 [mov.l r14,@-r15]
245 [mov r15,r14]
8db62801
EZ		 246
247 Actually it can be more complicated than this. For instance, with
248 newer gcc's:
249
250 mov.l r14,@-r15
251 add #-12,r15
252 mov r15,r14
253 mov r4,r1
254 mov r5,r2
255 mov.l r6,@(4,r14)
256 mov.l r7,@(8,r14)
257 mov.b r1,@r14
258 mov r14,r1
259 mov r14,r1
260 add #2,r1
261 mov.w r2,@r1
262
c5aa993b 263 */
c906108c 264
8db62801
EZ		 265/* STS.L PR,@-r15 0100111100100010
266 r15-4-->r15, PR-->(r15) */
c906108c 267#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 268
269/* MOV.L Rm,@-r15 00101111mmmm0110
270 r15-4-->r15, Rm-->(R15) */
c906108c 271#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 272
c906108c 273#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 274
275/* MOV r15,r14 0110111011110011
276 r15-->r14 */
c906108c 277#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 278
279/* ADD #imm,r15 01111111iiiiiiii
280 r15+imm-->r15 */
c906108c 281#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 282
c906108c
SS		 283#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
284#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 285
286/* ADD r3,r15 0011111100111100
287 r15+r3-->r15 */
c906108c 288#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 289
290/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 291 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 292 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 293#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 294
8db62801 295/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 296 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 297 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
298 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
299#define IS_ARG_MOV(x) \
300(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 301 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
302 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 303
304/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
305 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
3bbfbb92 306#define IS_MOV_TO_R14(x) \
cc17453a 307 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 308
309#define FPSCR_SZ (1 << 20)
c906108c 310
c906108c
SS		 311/* Skip any prologue before the guts of a function */
312
8db62801
EZ		 313/* Skip the prologue using the debug information. If this fails we'll
314 fall back on the 'guess' method below. */
315static CORE_ADDR
fba45db2 316after_prologue (CORE_ADDR pc)
8db62801
EZ		 317{
318 struct symtab_and_line sal;
319 CORE_ADDR func_addr, func_end;
320
321 /* If we can not find the symbol in the partial symbol table, then
322 there is no hope we can determine the function's start address
323 with this code. */
324 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
325 return 0;
326
327 /* Get the line associated with FUNC_ADDR. */
328 sal = find_pc_line (func_addr, 0);
329
330 /* There are only two cases to consider. First, the end of the source line
331 is within the function bounds. In that case we return the end of the
332 source line. Second is the end of the source line extends beyond the
333 bounds of the current function. We need to use the slow code to
334 examine instructions in that case. */
335 if (sal.end < func_end)
336 return sal.end;
337 else
338 return 0;
339}
340
341/* Here we look at each instruction in the function, and try to guess
342 where the prologue ends. Unfortunately this is not always
343 accurate. */
344static CORE_ADDR
3bbfbb92 345sh_skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 346{
2bfa91ee 347 CORE_ADDR here, end;
8db62801 348 int updated_fp = 0;
2bfa91ee
EZ		 349
350 if (!start_pc)
351 return 0;
352
353 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 354 {
2bfa91ee
EZ		 355 int w = read_memory_integer (here, 2);
356 here += 2;
357 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801 358 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
3bbfbb92 359 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
2bfa91ee
EZ		 360 {
361 start_pc = here;
2bfa91ee 362 }
8db62801
EZ		 363 else if (IS_MOV_SP_FP (w))
364 {
365 start_pc = here;
366 updated_fp = 1;
367 }
368 else
369 /* Don't bail out yet, if we are before the copy of sp. */
370 if (updated_fp)
371 break;
c906108c
SS		 372 }
373
374 return start_pc;
375}
376
cc17453a 377static CORE_ADDR
fba45db2 378sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 379{
380 CORE_ADDR post_prologue_pc;
381
382 /* See if we can determine the end of the prologue via the symbol table.
383 If so, then return either PC, or the PC after the prologue, whichever
384 is greater. */
8db62801
EZ		 385 post_prologue_pc = after_prologue (pc);
386
387 /* If after_prologue returned a useful address, then use it. Else
388 fall back on the instruction skipping code. */
389 if (post_prologue_pc != 0)
390 return max (pc, post_prologue_pc);
391 else
392 return (skip_prologue_hard_way (pc));
393}
394
cc17453a
EZ		 395/* Immediately after a function call, return the saved pc.
396 Can't always go through the frames for this because on some machines
397 the new frame is not set up until the new function executes
398 some instructions.
399
400 The return address is the value saved in the PR register + 4 */
401static CORE_ADDR
fba45db2 402sh_saved_pc_after_call (struct frame_info *frame)
cc17453a 403{
3bbfbb92 404 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
cc17453a
EZ		 405}
406
407/* Should call_function allocate stack space for a struct return? */
408static int
fba45db2 409sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 410{
411 return (TYPE_LENGTH (type) > 1);
412}
413
414/* Store the address of the place in which to copy the structure the
415 subroutine will return. This is called from call_function.
416
3bbfbb92 417 We store structs through a pointer passed in R2 */
cc17453a 418static void
fba45db2 419sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 420{
421 write_register (STRUCT_RETURN_REGNUM, (addr));
422}
c906108c 423
cc17453a
EZ		 424/* Disassemble an instruction. */
425static int
fba45db2 426gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c 427{
d7449b42 428 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS		 429 return print_insn_sh (memaddr, info);
430 else
431 return print_insn_shl (memaddr, info);
432}
433
434/* Given a GDB frame, determine the address of the calling function's frame.
435 This will be used to create a new GDB frame struct, and then
436 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
437
438 For us, the frame address is its stack pointer value, so we look up
439 the function prologue to determine the caller's sp value, and return it. */
cc17453a 440static CORE_ADDR
fba45db2 441sh_frame_chain (struct frame_info *frame)
c906108c
SS		 442{
443 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
444 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 445 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 446 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 447 else
448 return 0;
449}
450
451/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
452 we might want to do here is to check REGNUM against the clobber mask, and
453 somehow flag it as invalid if it isn't saved on the stack somewhere. This
454 would provide a graceful failure mode when trying to get the value of
455 caller-saves registers for an inner frame. */
cc17453a 456static CORE_ADDR
fba45db2 457sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 458{
c906108c
SS		 459 for (; fi; fi = fi->next)
460 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
461 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 462 that's where the previous routine appears to have done a call from. */
c906108c 463 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 464 else
c906108c 465 {
cc17453a 466 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 467 if (!fi->pc)
468 return 0;
cc17453a
EZ		 469 if (fi->saved_regs[regnum] != 0)
470 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 471 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 472 }
473 return read_register (regnum);
474}
475
476/* Put here the code to store, into a struct frame_saved_regs, the
477 addresses of the saved registers of frame described by FRAME_INFO.
478 This includes special registers such as pc and fp saved in special
479 ways in the stack frame. sp is even more special: the address we
480 return for it IS the sp for the next frame. */
cc17453a 481static void
fba45db2 482sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c 483{
e7d717c0 484 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
c906108c
SS		 485 int rn;
486 int have_fp = 0;
487 int depth;
488 int pc;
489 int opc;
490 int insn;
491 int r3_val = 0;
c5aa993b 492 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 493
494 if (fi->saved_regs == NULL)
495 frame_saved_regs_zalloc (fi);
496 else
497 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
498
499 if (dummy_regs)
500 {
501 /* DANGER! This is ONLY going to work if the char buffer format of
502 the saved registers is byte-for-byte identical to the
503 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
504 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
505 return;
506 }
507
508 fi->extra_info->leaf_function = 1;
509 fi->extra_info->f_offset = 0;
510
cd4bffcf 511 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 512 where[rn] = -1;
513
514 depth = 0;
515
516 /* Loop around examining the prologue insns until we find something
517 that does not appear to be part of the prologue. But give up
518 after 20 of them, since we're getting silly then. */
519
520 pc = get_pc_function_start (fi->pc);
521 if (!pc)
522 {
523 fi->pc = 0;
524 return;
525 }
526
527 for (opc = pc + (2 * 28); pc < opc; pc += 2)
528 {
529 insn = read_memory_integer (pc, 2);
530 /* See where the registers will be saved to */
531 if (IS_PUSH (insn))
532 {
533 rn = GET_PUSHED_REG (insn);
534 where[rn] = depth;
535 depth += 4;
536 }
537 else if (IS_STS (insn))
538 {
3bbfbb92 539 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
cc17453a
EZ		 540 /* If we're storing the pr then this isn't a leaf */
541 fi->extra_info->leaf_function = 0;
542 depth += 4;
543 }
544 else if (IS_MOV_R3 (insn))
545 {
546 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
547 }
548 else if (IS_SHLL_R3 (insn))
549 {
550 r3_val <<= 1;
551 }
552 else if (IS_ADD_R3SP (insn))
553 {
554 depth += -r3_val;
555 }
556 else if (IS_ADD_SP (insn))
557 {
558 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
559 }
560 else if (IS_MOV_SP_FP (insn))
561 break;
562#if 0 /* This used to just stop when it found an instruction that
563 was not considered part of the prologue. Now, we just
564 keep going looking for likely instructions. */
565 else
566 break;
567#endif
568 }
569
570 /* Now we know how deep things are, we can work out their addresses */
571
cd4bffcf 572 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 573 {
574 if (where[rn] >= 0)
575 {
576 if (rn == FP_REGNUM)
577 have_fp = 1;
c906108c 578
cc17453a
EZ		 579 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
580 }
581 else
582 {
583 fi->saved_regs[rn] = 0;
584 }
585 }
586
587 if (have_fp)
588 {
589 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
590 }
591 else
592 {
593 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
594 }
595
596 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
597 /* Work out the return pc - either from the saved pr or the pr
598 value */
599}
600
3bbfbb92
EZ		 601/* For vectors of 4 floating point registers. */
602static int
603fv_reg_base_num (int fv_regnum)
604{
605 int fp_regnum;
606
607 fp_regnum = FP0_REGNUM +
608 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
609 return fp_regnum;
610}
611
612/* For double precision floating point registers, i.e 2 fp regs.*/
613static int
614dr_reg_base_num (int dr_regnum)
615{
616 int fp_regnum;
617
618 fp_regnum = FP0_REGNUM +
619 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
620 return fp_regnum;
621}
622
cc17453a 623static void
fba45db2 624sh_fp_frame_init_saved_regs (struct frame_info *fi)
cc17453a 625{
e7d717c0 626 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
cc17453a
EZ		 627 int rn;
628 int have_fp = 0;
629 int depth;
630 int pc;
631 int opc;
632 int insn;
633 int r3_val = 0;
634 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
f81353e4 635 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
cc17453a
EZ		 636
637 if (fi->saved_regs == NULL)
638 frame_saved_regs_zalloc (fi);
639 else
640 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
641
c906108c
SS		 642 if (dummy_regs)
643 {
644 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 645 the saved registers is byte-for-byte identical to the
646 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 647 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 648 return;
649 }
650
cc17453a
EZ		 651 fi->extra_info->leaf_function = 1;
652 fi->extra_info->f_offset = 0;
c906108c 653
cd4bffcf 654 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 655 where[rn] = -1;
656
657 depth = 0;
658
659 /* Loop around examining the prologue insns until we find something
660 that does not appear to be part of the prologue. But give up
661 after 20 of them, since we're getting silly then. */
662
2bfa91ee
EZ		 663 pc = get_pc_function_start (fi->pc);
664 if (!pc)
c906108c 665 {
2bfa91ee
EZ		 666 fi->pc = 0;
667 return;
668 }
669
670 for (opc = pc + (2 * 28); pc < opc; pc += 2)
671 {
672 insn = read_memory_integer (pc, 2);
c906108c
SS		 673 /* See where the registers will be saved to */
674 if (IS_PUSH (insn))
675 {
c906108c
SS		 676 rn = GET_PUSHED_REG (insn);
677 where[rn] = depth;
c906108c
SS		 678 depth += 4;
679 }
680 else if (IS_STS (insn))
681 {
f81353e4 682 where[tdep->PR_REGNUM] = depth;
c906108c 683 /* If we're storing the pr then this isn't a leaf */
cc17453a 684 fi->extra_info->leaf_function = 0;
c906108c
SS		 685 depth += 4;
686 }
687 else if (IS_MOV_R3 (insn))
688 {
689 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 690 }
691 else if (IS_SHLL_R3 (insn))
692 {
693 r3_val <<= 1;
c906108c
SS		 694 }
695 else if (IS_ADD_R3SP (insn))
696 {
697 depth += -r3_val;
c906108c
SS		 698 }
699 else if (IS_ADD_SP (insn))
700 {
c906108c 701 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 702 }
703 else if (IS_FMOV (insn))
704 {
f81353e4 705 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 706 {
707 depth += 8;
708 }
709 else
710 {
711 depth += 4;
712 }
713 }
2bfa91ee
EZ		 714 else if (IS_MOV_SP_FP (insn))
715 break;
716#if 0 /* This used to just stop when it found an instruction that
717 was not considered part of the prologue. Now, we just
718 keep going looking for likely instructions. */
c906108c
SS		 719 else
720 break;
2bfa91ee 721#endif
c906108c
SS		 722 }
723
724 /* Now we know how deep things are, we can work out their addresses */
725
cd4bffcf 726 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 727 {
728 if (where[rn] >= 0)
729 {
730 if (rn == FP_REGNUM)
731 have_fp = 1;
732
cc17453a 733 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 734 }
735 else
736 {
cc17453a 737 fi->saved_regs[rn] = 0;
c906108c
SS		 738 }
739 }
740
741 if (have_fp)
742 {
cd4bffcf
EZ		 743 fi->saved_regs[SP_REGNUM] =
744 read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 745 }
746 else
747 {
cc17453a 748 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 749 }
750
cc17453a 751 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 752 /* Work out the return pc - either from the saved pr or the pr
753 value */
754}
755
cc17453a
EZ		 756/* Initialize the extra info saved in a FRAME */
757static void
fba45db2 758sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 759{
cc17453a
EZ		 760
761 fi->extra_info = (struct frame_extra_info *)
762 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 763
764 if (fi->next)
765 fi->pc = FRAME_SAVED_PC (fi->next);
766
767 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
768 {
769 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 770 by assuming it's always FP. */
771 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
772 SP_REGNUM);
cd4bffcf
EZ		 773 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc,
774 fi->frame,
cc17453a
EZ		 775 PC_REGNUM);
776 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
777 fi->extra_info->leaf_function = 0;
c906108c
SS		 778 return;
779 }
780 else
781 {
cc17453a 782 FRAME_INIT_SAVED_REGS (fi);
cd4bffcf
EZ		 783 fi->extra_info->return_pc =
784 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
c906108c
SS		 785 }
786}
787
cc17453a
EZ		 788/* Extract from an array REGBUF containing the (raw) register state
789 the address in which a function should return its structure value,
790 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 791static CORE_ADDR
0c8053b6 792sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 793{
794 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
795}
796
797static CORE_ADDR
fba45db2 798sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 799{
800 return ((frame)->extra_info->return_pc);
801}
802
c906108c
SS		 803/* Discard from the stack the innermost frame,
804 restoring all saved registers. */
cc17453a 805static void
fba45db2 806sh_pop_frame (void)
c906108c
SS		 807{
808 register struct frame_info *frame = get_current_frame ();
809 register CORE_ADDR fp;
810 register int regnum;
c906108c
SS		 811
812 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
813 generic_pop_dummy_frame ();
814 else
c5aa993b
JM		 815 {
816 fp = FRAME_FP (frame);
cc17453a 817 FRAME_INIT_SAVED_REGS (frame);
c906108c 818
c5aa993b 819 /* Copy regs from where they were saved in the frame */
cd4bffcf 820 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
cc17453a 821 if (frame->saved_regs[regnum])
cd4bffcf
EZ		 822 write_register (regnum,
823 read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 824
cc17453a 825 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 826 write_register (SP_REGNUM, fp + 4);
827 }
c906108c
SS		 828 flush_cached_frames ();
829}
830
831/* Function: push_arguments
832 Setup the function arguments for calling a function in the inferior.
833
834 On the Hitachi SH architecture, there are four registers (R4 to R7)
835 which are dedicated for passing function arguments. Up to the first
836 four arguments (depending on size) may go into these registers.
837 The rest go on the stack.
838
839 Arguments that are smaller than 4 bytes will still take up a whole
840 register or a whole 32-bit word on the stack, and will be
841 right-justified in the register or the stack word. This includes
842 chars, shorts, and small aggregate types.
843
844 Arguments that are larger than 4 bytes may be split between two or
845 more registers. If there are not enough registers free, an argument
846 may be passed partly in a register (or registers), and partly on the
847 stack. This includes doubles, long longs, and larger aggregates.
848 As far as I know, there is no upper limit to the size of aggregates
849 that will be passed in this way; in other words, the convention of
850 passing a pointer to a large aggregate instead of a copy is not used.
851
852 An exceptional case exists for struct arguments (and possibly other
853 aggregates such as arrays) if the size is larger than 4 bytes but
854 not a multiple of 4 bytes. In this case the argument is never split
855 between the registers and the stack, but instead is copied in its
856 entirety onto the stack, AND also copied into as many registers as
857 there is room for. In other words, space in registers permitting,
858 two copies of the same argument are passed in. As far as I can tell,
859 only the one on the stack is used, although that may be a function
860 of the level of compiler optimization. I suspect this is a compiler
861 bug. Arguments of these odd sizes are left-justified within the
862 word (as opposed to arguments smaller than 4 bytes, which are
863 right-justified).
c5aa993b 864
c906108c
SS		 865 If the function is to return an aggregate type such as a struct, it
866 is either returned in the normal return value register R0 (if its
867 size is no greater than one byte), or else the caller must allocate
868 space into which the callee will copy the return value (if the size
869 is greater than one byte). In this case, a pointer to the return
870 value location is passed into the callee in register R2, which does
871 not displace any of the other arguments passed in via registers R4
872 to R7. */
873
cc17453a 874static CORE_ADDR
34e9d9bb 875sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
3bbfbb92 876 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 877{
878 int stack_offset, stack_alloc;
879 int argreg;
880 int argnum;
881 struct type *type;
882 CORE_ADDR regval;
883 char *val;
884 char valbuf[4];
885 int len;
886 int odd_sized_struct;
f81353e4 887 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS		 888
889 /* first force sp to a 4-byte alignment */
890 sp = sp & ~3;
891
892 /* The "struct return pointer" pseudo-argument has its own dedicated
893 register */
894 if (struct_return)
c5aa993b 895 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 896
897 /* Now make sure there's space on the stack */
cc17453a 898 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 899 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
900 sp -= stack_alloc; /* make room on stack for args */
c906108c 901
c906108c
SS		 902 /* Now load as many as possible of the first arguments into
903 registers, and push the rest onto the stack. There are 16 bytes
904 in four registers available. Loop thru args from first to last. */
905
f81353e4 906 argreg = tdep->ARG0_REGNUM;
c906108c
SS		 907 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
908 {
909 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 910 len = TYPE_LENGTH (type);
911 memset (valbuf, 0, sizeof (valbuf));
c906108c 912 if (len < 4)
cc17453a
EZ		 913 {
914 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 915 memcpy (valbuf + (4 - len),
916 (char *) VALUE_CONTENTS (args[argnum]), len);
917 val = valbuf;
918 }
c906108c 919 else
c5aa993b 920 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 921
922 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 923 odd_sized_struct = 1; /* such structs go entirely on stack */
924 else
c906108c
SS		 925 odd_sized_struct = 0;
926 while (len > 0)
927 {
f81353e4 928 if (argreg > tdep->ARGLAST_REGNUM
3bbfbb92
EZ		 929 || odd_sized_struct)
930 {
931 /* must go on the stack */
c906108c
SS		 932 write_memory (sp + stack_offset, val, 4);
933 stack_offset += 4;
934 }
935 /* NOTE WELL!!!!! This is not an "else if" clause!!!
936 That's because some *&^%$ things get passed on the stack
937 AND in the registers! */
f81353e4 938 if (argreg <= tdep->ARGLAST_REGNUM)
3bbfbb92
EZ		 939 {
940 /* there's room in a register */
c5aa993b 941 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 942 write_register (argreg++, regval);
943 }
944 /* Store the value 4 bytes at a time. This means that things
945 larger than 4 bytes may go partly in registers and partly
946 on the stack. */
c5aa993b
JM		 947 len -= REGISTER_RAW_SIZE (argreg);
948 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 949 }
950 }
951 return sp;
952}
953
954/* Function: push_return_address (pc)
955 Set up the return address for the inferior function call.
956 Needed for targets where we don't actually execute a JSR/BSR instruction */
957
cc17453a 958static CORE_ADDR
fba45db2 959sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c 960{
3bbfbb92 961 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM, CALL_DUMMY_ADDRESS ());
c906108c
SS		 962 return sp;
963}
964
965/* Function: fix_call_dummy
966 Poke the callee function's address into the destination part of
967 the CALL_DUMMY. The address is actually stored in a data word
968 following the actualy CALL_DUMMY instructions, which will load
969 it into a register using PC-relative addressing. This function
970 expects the CALL_DUMMY to look like this:
971
c5aa993b
JM		 972 mov.w @(2,PC), R8
973 jsr @R8
974 nop
975 trap
976 <destination>
977 */
c906108c
SS		 978
979#if 0
980void
fba45db2 981sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
ea7c478f 982 struct value **args, struct type *type, int gcc_p)
c906108c
SS		 983{
984 *(unsigned long *) (dummy + 8) = fun;
985}
986#endif
987
cc17453a
EZ		 988static int
989sh_coerce_float_to_double (struct type *formal, struct type *actual)
990{
991 return 1;
992}
c906108c 993
cc17453a
EZ		 994/* Find a function's return value in the appropriate registers (in
995 regbuf), and copy it into valbuf. Extract from an array REGBUF
996 containing the (raw) register state a function return value of type
997 TYPE, and copy that, in virtual format, into VALBUF. */
998static void
fba45db2 999sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 1000{
cc17453a 1001 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1002 int return_register = R0_REGNUM;
1003 int offset;
1004
cc17453a 1005 if (len <= 4)
3116c80a 1006 {
d7449b42 1007 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1008 offset = REGISTER_BYTE (return_register) + 4 - len;
1009 else
1010 offset = REGISTER_BYTE (return_register);
1011 memcpy (valbuf, regbuf + offset, len);
1012 }
cc17453a 1013 else if (len <= 8)
3116c80a 1014 {
d7449b42 1015 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1016 offset = REGISTER_BYTE (return_register) + 8 - len;
1017 else
1018 offset = REGISTER_BYTE (return_register);
1019 memcpy (valbuf, regbuf + offset, len);
1020 }
1021 else
1022 error ("bad size for return value");
1023}
1024
1025static void
1026sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1027{
1028 int return_register;
1029 int offset;
1030 int len = TYPE_LENGTH (type);
1031
1032 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1033 return_register = FP0_REGNUM;
1034 else
1035 return_register = R0_REGNUM;
1036
1037 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
1038 {
1039 DOUBLEST val;
778eb05e 1040 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
3116c80a
EZ		 1041 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1042 (char *) regbuf + REGISTER_BYTE (return_register),
1043 &val);
1044 else
1045 floatformat_to_doublest (&floatformat_ieee_double_big,
1046 (char *) regbuf + REGISTER_BYTE (return_register),
1047 &val);
1048 store_floating (valbuf, len, val);
1049 }
1050 else if (len <= 4)
1051 {
d7449b42 1052 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1053 offset = REGISTER_BYTE (return_register) + 4 - len;
1054 else
1055 offset = REGISTER_BYTE (return_register);
1056 memcpy (valbuf, regbuf + offset, len);
1057 }
1058 else if (len <= 8)
1059 {
d7449b42 1060 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1061 offset = REGISTER_BYTE (return_register) + 8 - len;
1062 else
1063 offset = REGISTER_BYTE (return_register);
1064 memcpy (valbuf, regbuf + offset, len);
1065 }
cc17453a
EZ		 1066 else
1067 error ("bad size for return value");
1068}
c906108c 1069
cc17453a
EZ		 1070/* Write into appropriate registers a function return value
1071 of type TYPE, given in virtual format.
1072 If the architecture is sh4 or sh3e, store a function's return value
1073 in the R0 general register or in the FP0 floating point register,
1074 depending on the type of the return value. In all the other cases
3bbfbb92 1075 the result is stored in r0, left-justified. */
cc17453a
EZ		 1076static void
1077sh_default_store_return_value (struct type *type, char *valbuf)
1078{
d19b71be
MS		 1079 char buf[32]; /* more than enough... */
1080
1081 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
1082 {
1083 /* Add leading zeros to the value. */
1084 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
1085 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
1086 valbuf, TYPE_LENGTH (type));
1087 write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
1088 REGISTER_RAW_SIZE (R0_REGNUM));
1089 }
1090 else
1091 write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
1092 TYPE_LENGTH (type));
cc17453a 1093}
c906108c 1094
cc17453a
EZ		 1095static void
1096sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1097{
1098 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1099 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1100 valbuf, TYPE_LENGTH (type));
1101 else
d19b71be 1102 sh_default_store_return_value (type, valbuf);
c906108c
SS		 1103}
1104
1105/* Print the registers in a form similar to the E7000 */
1106
1107static void
fba45db2 1108sh_generic_show_regs (void)
c906108c 1109{
f81353e4
EZ		 1110 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1111
cc17453a
EZ		 1112 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1113 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1114 (long) read_register (tdep->SR_REGNUM),
1115 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1116 (long) read_register (MACH_REGNUM),
1117 (long) read_register (MACL_REGNUM));
1118
1119 printf_filtered ("GBR=%08lx VBR=%08lx",
1120 (long) read_register (GBR_REGNUM),
1121 (long) read_register (VBR_REGNUM));
1122
1123 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1124 (long) read_register (0),
1125 (long) read_register (1),
1126 (long) read_register (2),
1127 (long) read_register (3),
1128 (long) read_register (4),
1129 (long) read_register (5),
1130 (long) read_register (6),
1131 (long) read_register (7));
1132 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1133 (long) read_register (8),
1134 (long) read_register (9),
1135 (long) read_register (10),
1136 (long) read_register (11),
1137 (long) read_register (12),
1138 (long) read_register (13),
1139 (long) read_register (14),
1140 (long) read_register (15));
1141}
c906108c 1142
cc17453a 1143static void
fba45db2 1144sh3_show_regs (void)
cc17453a 1145{
f81353e4
EZ		 1146 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1147
d4f3574e
SS		 1148 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1149 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1150 (long) read_register (tdep->SR_REGNUM),
1151 (long) read_register (tdep->PR_REGNUM),
d4f3574e
SS		 1152 (long) read_register (MACH_REGNUM),
1153 (long) read_register (MACL_REGNUM));
1154
1155 printf_filtered ("GBR=%08lx VBR=%08lx",
1156 (long) read_register (GBR_REGNUM),
1157 (long) read_register (VBR_REGNUM));
cc17453a 1158 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1159 (long) read_register (tdep->SSR_REGNUM),
1160 (long) read_register (tdep->SPC_REGNUM));
c906108c 1161
d4f3574e
SS		 1162 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1163 (long) read_register (0),
1164 (long) read_register (1),
1165 (long) read_register (2),
1166 (long) read_register (3),
1167 (long) read_register (4),
1168 (long) read_register (5),
1169 (long) read_register (6),
1170 (long) read_register (7));
1171 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1172 (long) read_register (8),
1173 (long) read_register (9),
1174 (long) read_register (10),
1175 (long) read_register (11),
1176 (long) read_register (12),
1177 (long) read_register (13),
1178 (long) read_register (14),
1179 (long) read_register (15));
c906108c
SS		 1180}
1181
53116e27 1182
cc17453a 1183static void
fba45db2 1184sh3e_show_regs (void)
cc17453a 1185{
f81353e4
EZ		 1186 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1187
cc17453a
EZ		 1188 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1189 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1190 (long) read_register (tdep->SR_REGNUM),
1191 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1192 (long) read_register (MACH_REGNUM),
1193 (long) read_register (MACL_REGNUM));
1194
1195 printf_filtered ("GBR=%08lx VBR=%08lx",
1196 (long) read_register (GBR_REGNUM),
1197 (long) read_register (VBR_REGNUM));
1198 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1199 (long) read_register (tdep->SSR_REGNUM),
1200 (long) read_register (tdep->SPC_REGNUM));
cc17453a 1201 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 1202 (long) read_register (tdep->FPUL_REGNUM),
1203 (long) read_register (tdep->FPSCR_REGNUM));
c906108c 1204
cc17453a
EZ		 1205 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1206 (long) read_register (0),
1207 (long) read_register (1),
1208 (long) read_register (2),
1209 (long) read_register (3),
1210 (long) read_register (4),
1211 (long) read_register (5),
1212 (long) read_register (6),
1213 (long) read_register (7));
1214 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1215 (long) read_register (8),
1216 (long) read_register (9),
1217 (long) read_register (10),
1218 (long) read_register (11),
1219 (long) read_register (12),
1220 (long) read_register (13),
1221 (long) read_register (14),
1222 (long) read_register (15));
1223
1224 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1225 (long) read_register (FP0_REGNUM + 0),
1226 (long) read_register (FP0_REGNUM + 1),
1227 (long) read_register (FP0_REGNUM + 2),
1228 (long) read_register (FP0_REGNUM + 3),
1229 (long) read_register (FP0_REGNUM + 4),
1230 (long) read_register (FP0_REGNUM + 5),
1231 (long) read_register (FP0_REGNUM + 6),
1232 (long) read_register (FP0_REGNUM + 7));
1233 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1234 (long) read_register (FP0_REGNUM + 8),
1235 (long) read_register (FP0_REGNUM + 9),
1236 (long) read_register (FP0_REGNUM + 10),
1237 (long) read_register (FP0_REGNUM + 11),
1238 (long) read_register (FP0_REGNUM + 12),
1239 (long) read_register (FP0_REGNUM + 13),
1240 (long) read_register (FP0_REGNUM + 14),
1241 (long) read_register (FP0_REGNUM + 15));
1242}
1243
1244static void
fba45db2 1245sh3_dsp_show_regs (void)
c906108c 1246{
f81353e4
EZ		 1247 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1248
cc17453a
EZ		 1249 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1250 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1251 (long) read_register (tdep->SR_REGNUM),
1252 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1253 (long) read_register (MACH_REGNUM),
1254 (long) read_register (MACL_REGNUM));
c906108c 1255
cc17453a
EZ		 1256 printf_filtered ("GBR=%08lx VBR=%08lx",
1257 (long) read_register (GBR_REGNUM),
1258 (long) read_register (VBR_REGNUM));
1259
1260 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1261 (long) read_register (tdep->SSR_REGNUM),
1262 (long) read_register (tdep->SPC_REGNUM));
cc17453a
EZ		 1263
1264 printf_filtered (" DSR=%08lx",
f81353e4 1265 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 1266
1267 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1268 (long) read_register (0),
1269 (long) read_register (1),
1270 (long) read_register (2),
1271 (long) read_register (3),
1272 (long) read_register (4),
1273 (long) read_register (5),
1274 (long) read_register (6),
1275 (long) read_register (7));
1276 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1277 (long) read_register (8),
1278 (long) read_register (9),
1279 (long) read_register (10),
1280 (long) read_register (11),
1281 (long) read_register (12),
1282 (long) read_register (13),
1283 (long) read_register (14),
1284 (long) read_register (15));
1285
1286 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 1287 (long) read_register (tdep->A0G_REGNUM) & 0xff,
1288 (long) read_register (tdep->A0_REGNUM),
1289 (long) read_register (tdep->M0_REGNUM),
1290 (long) read_register (tdep->X0_REGNUM),
1291 (long) read_register (tdep->Y0_REGNUM),
1292 (long) read_register (tdep->RS_REGNUM),
1293 (long) read_register (tdep->MOD_REGNUM));
cc17453a 1294 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 1295 (long) read_register (tdep->A1G_REGNUM) & 0xff,
1296 (long) read_register (tdep->A1_REGNUM),
1297 (long) read_register (tdep->M1_REGNUM),
1298 (long) read_register (tdep->X1_REGNUM),
1299 (long) read_register (tdep->Y1_REGNUM),
1300 (long) read_register (tdep->RE_REGNUM));
c906108c
SS		 1301}
1302
cc17453a 1303static void
fba45db2 1304sh4_show_regs (void)
cc17453a 1305{
f81353e4
EZ		 1306 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1307
1308 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
cc17453a
EZ		 1309 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1310 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1311 (long) read_register (tdep->SR_REGNUM),
1312 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1313 (long) read_register (MACH_REGNUM),
1314 (long) read_register (MACL_REGNUM));
1315
1316 printf_filtered ("GBR=%08lx VBR=%08lx",
1317 (long) read_register (GBR_REGNUM),
1318 (long) read_register (VBR_REGNUM));
1319 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1320 (long) read_register (tdep->SSR_REGNUM),
1321 (long) read_register (tdep->SPC_REGNUM));
cc17453a 1322 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 1323 (long) read_register (tdep->FPUL_REGNUM),
1324 (long) read_register (tdep->FPSCR_REGNUM));
cc17453a
EZ		 1325
1326 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1327 (long) read_register (0),
1328 (long) read_register (1),
1329 (long) read_register (2),
1330 (long) read_register (3),
1331 (long) read_register (4),
1332 (long) read_register (5),
1333 (long) read_register (6),
1334 (long) read_register (7));
1335 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1336 (long) read_register (8),
1337 (long) read_register (9),
1338 (long) read_register (10),
1339 (long) read_register (11),
1340 (long) read_register (12),
1341 (long) read_register (13),
1342 (long) read_register (14),
1343 (long) read_register (15));
1344
1345 printf_filtered ((pr
1346 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1347 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1348 (long) read_register (FP0_REGNUM + 0),
1349 (long) read_register (FP0_REGNUM + 1),
1350 (long) read_register (FP0_REGNUM + 2),
1351 (long) read_register (FP0_REGNUM + 3),
1352 (long) read_register (FP0_REGNUM + 4),
1353 (long) read_register (FP0_REGNUM + 5),
1354 (long) read_register (FP0_REGNUM + 6),
1355 (long) read_register (FP0_REGNUM + 7));
1356 printf_filtered ((pr
1357 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1358 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1359 (long) read_register (FP0_REGNUM + 8),
1360 (long) read_register (FP0_REGNUM + 9),
1361 (long) read_register (FP0_REGNUM + 10),
1362 (long) read_register (FP0_REGNUM + 11),
1363 (long) read_register (FP0_REGNUM + 12),
1364 (long) read_register (FP0_REGNUM + 13),
1365 (long) read_register (FP0_REGNUM + 14),
1366 (long) read_register (FP0_REGNUM + 15));
1367}
1368
1369static void
fba45db2 1370sh_dsp_show_regs (void)
cc17453a 1371{
f81353e4
EZ		 1372 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1373
cc17453a
EZ		 1374 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1375 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1376 (long) read_register (tdep->SR_REGNUM),
1377 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1378 (long) read_register (MACH_REGNUM),
1379 (long) read_register (MACL_REGNUM));
1380
1381 printf_filtered ("GBR=%08lx VBR=%08lx",
1382 (long) read_register (GBR_REGNUM),
1383 (long) read_register (VBR_REGNUM));
1384
1385 printf_filtered (" DSR=%08lx",
f81353e4 1386 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 1387
1388 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1389 (long) read_register (0),
1390 (long) read_register (1),
1391 (long) read_register (2),
1392 (long) read_register (3),
1393 (long) read_register (4),
1394 (long) read_register (5),
1395 (long) read_register (6),
1396 (long) read_register (7));
1397 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1398 (long) read_register (8),
1399 (long) read_register (9),
1400 (long) read_register (10),
1401 (long) read_register (11),
1402 (long) read_register (12),
1403 (long) read_register (13),
1404 (long) read_register (14),
1405 (long) read_register (15));
1406
1407 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 1408 (long) read_register (tdep->A0G_REGNUM) & 0xff,
1409 (long) read_register (tdep->A0_REGNUM),
1410 (long) read_register (tdep->M0_REGNUM),
1411 (long) read_register (tdep->X0_REGNUM),
1412 (long) read_register (tdep->Y0_REGNUM),
1413 (long) read_register (tdep->RS_REGNUM),
1414 (long) read_register (tdep->MOD_REGNUM));
cc17453a 1415 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 1416 (long) read_register (tdep->A1G_REGNUM) & 0xff,
1417 (long) read_register (tdep->A1_REGNUM),
1418 (long) read_register (tdep->M1_REGNUM),
1419 (long) read_register (tdep->X1_REGNUM),
1420 (long) read_register (tdep->Y1_REGNUM),
1421 (long) read_register (tdep->RE_REGNUM));
cc17453a
EZ		 1422}
1423
53116e27
EZ		 1424void sh_show_regs_command (char *args, int from_tty)
1425{
1426 if (sh_show_regs)
1427 (*sh_show_regs)();
1428}
1429
cc17453a
EZ		 1430/* Index within `registers' of the first byte of the space for
1431 register N. */
1432static int
fba45db2 1433sh_default_register_byte (int reg_nr)
8db62801 1434{
cc17453a
EZ		 1435 return (reg_nr * 4);
1436}
1437
53116e27 1438static int
fba45db2 1439sh_sh4_register_byte (int reg_nr)
53116e27 1440{
f81353e4
EZ		 1441 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1442
1443 if (reg_nr >= tdep->DR0_REGNUM
1444 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 1445 return (dr_reg_base_num (reg_nr) * 4);
f81353e4
EZ		 1446 else if (reg_nr >= tdep->FV0_REGNUM
1447 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1448 return (fv_reg_base_num (reg_nr) * 4);
1449 else
1450 return (reg_nr * 4);
1451}
1452
cc17453a
EZ		 1453/* Number of bytes of storage in the actual machine representation for
1454 register REG_NR. */
1455static int
fba45db2 1456sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 1457{
1458 return 4;
1459}
1460
53116e27 1461static int
fba45db2 1462sh_sh4_register_raw_size (int reg_nr)
53116e27 1463{
f81353e4
EZ		 1464 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1465
1466 if (reg_nr >= tdep->DR0_REGNUM
1467 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 1468 return 8;
f81353e4
EZ		 1469 else if (reg_nr >= tdep->FV0_REGNUM
1470 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1471 return 16;
1472 else
1473 return 4;
1474}
1475
cc17453a
EZ		 1476/* Number of bytes of storage in the program's representation
1477 for register N. */
1478static int
fba45db2 1479sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 1480{
1481 return 4;
1482}
1483
1484/* Return the GDB type object for the "standard" data type
1485 of data in register N. */
cc17453a 1486static struct type *
fba45db2 1487sh_sh3e_register_virtual_type (int reg_nr)
cc17453a 1488{
f81353e4
EZ		 1489 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1490
cc17453a 1491 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 1492 && (reg_nr <= tdep->FP_LAST_REGNUM))
1493 || (reg_nr == tdep->FPUL_REGNUM))
cc17453a 1494 return builtin_type_float;
8db62801 1495 else
cc17453a
EZ		 1496 return builtin_type_int;
1497}
1498
7f4dbe94
EZ		 1499static struct type *
1500sh_sh4_build_float_register_type (int high)
1501{
1502 struct type *temp;
1503
1504 temp = create_range_type (NULL, builtin_type_int, 0, high);
1505 return create_array_type (NULL, builtin_type_float, temp);
1506}
1507
53116e27 1508static struct type *
fba45db2 1509sh_sh4_register_virtual_type (int reg_nr)
53116e27 1510{
f81353e4
EZ		 1511 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1512
53116e27 1513 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 1514 && (reg_nr <= tdep->FP_LAST_REGNUM))
1515 || (reg_nr == tdep->FPUL_REGNUM))
53116e27 1516 return builtin_type_float;
f81353e4
EZ		 1517 else if (reg_nr >= tdep->DR0_REGNUM
1518 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 1519 return builtin_type_double;
f81353e4
EZ		 1520 else if (reg_nr >= tdep->FV0_REGNUM
1521 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1522 return sh_sh4_build_float_register_type (3);
1523 else
1524 return builtin_type_int;
1525}
1526
cc17453a 1527static struct type *
fba45db2 1528sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 1529{
1530 return builtin_type_int;
1531}
1532
fb409745
EZ		 1533/* On the sh4, the DRi pseudo registers are problematic if the target
1534 is little endian. When the user writes one of those registers, for
1535 instance with 'ser var $dr0=1', we want the double to be stored
1536 like this:
1537 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1538 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1539
1540 This corresponds to little endian byte order & big endian word
1541 order. However if we let gdb write the register w/o conversion, it
1542 will write fr0 and fr1 this way:
1543 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1544 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1545 because it will consider fr0 and fr1 as a single LE stretch of memory.
1546
1547 To achieve what we want we must force gdb to store things in
1548 floatformat_ieee_double_littlebyte_bigword (which is defined in
1549 include/floatformat.h and libiberty/floatformat.c.
1550
1551 In case the target is big endian, there is no problem, the
1552 raw bytes will look like:
1553 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1554 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1555
1556 The other pseudo registers (the FVs) also don't pose a problem
1557 because they are stored as 4 individual FP elements. */
1558
7bd872fe 1559static void
fb409745
EZ		 1560sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1561 char *from, char *to)
1562{
f81353e4
EZ		 1563 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1564
1565 if (regnum >= tdep->DR0_REGNUM
1566 && regnum <= tdep->DR_LAST_REGNUM)
fb409745
EZ		 1567 {
1568 DOUBLEST val;
1569 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3bbfbb92 1570 store_floating (to, TYPE_LENGTH (type), val);
fb409745
EZ		 1571 }
1572 else
3bbfbb92 1573 error ("sh_register_convert_to_virtual called with non DR register number");
fb409745
EZ		 1574}
1575
7bd872fe 1576static void
fb409745 1577sh_sh4_register_convert_to_raw (struct type *type, int regnum,
7bd872fe 1578 char *from, char *to)
fb409745 1579{
f81353e4
EZ		 1580 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1581
1582 if (regnum >= tdep->DR0_REGNUM
1583 && regnum <= tdep->DR_LAST_REGNUM)
fb409745
EZ		 1584 {
1585 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
1586 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1587 }
1588 else
1589 error("sh_register_convert_to_raw called with non DR register number");
1590}
1591
53116e27 1592void
7bd872fe 1593sh_pseudo_register_read (int reg_nr, char *buffer)
53116e27
EZ		 1594{
1595 int base_regnum, portion;
7bd872fe 1596 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
f81353e4 1597 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
53116e27 1598
7bd872fe
EZ		 1599 if (reg_nr >= tdep->DR0_REGNUM
1600 && reg_nr <= tdep->DR_LAST_REGNUM)
1601 {
1602 base_regnum = dr_reg_base_num (reg_nr);
1603
1604 /* Build the value in the provided buffer. */
1605 /* Read the real regs for which this one is an alias. */
1606 for (portion = 0; portion < 2; portion++)
1607 regcache_read (base_regnum + portion,
1608 temp_buffer
1609 + REGISTER_RAW_SIZE (base_regnum) * portion);
1610 /* We must pay attention to the endiannes. */
1611 sh_sh4_register_convert_to_virtual (reg_nr,
1612 REGISTER_VIRTUAL_TYPE (reg_nr),
1613 temp_buffer, buffer);
1614 }
1615 else if (reg_nr >= tdep->FV0_REGNUM
1616 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27 1617 {
7bd872fe
EZ		 1618 base_regnum = fv_reg_base_num (reg_nr);
1619
1620 /* Read the real regs for which this one is an alias. */
1621 for (portion = 0; portion < 4; portion++)
1622 regcache_read (base_regnum + portion,
1623 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27
EZ		 1624 }
1625}
1626
7bd872fe
EZ		 1627static void
1628sh4_register_read (struct gdbarch *gdbarch, int reg_nr, char *buffer)
1629{
1630 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
1631 /* It is a regular register. */
1632 regcache_read (reg_nr, buffer);
1633 else
1634 /* It is a pseudo register and we need to construct its value */
1635 sh_pseudo_register_read (reg_nr, buffer);
1636}
1637
53116e27 1638void
7bd872fe 1639sh_pseudo_register_write (int reg_nr, char *buffer)
53116e27
EZ		 1640{
1641 int base_regnum, portion;
7bd872fe 1642 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
f81353e4 1643 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
53116e27 1644
f81353e4
EZ		 1645 if (reg_nr >= tdep->DR0_REGNUM
1646 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27
EZ		 1647 {
1648 base_regnum = dr_reg_base_num (reg_nr);
1649
7bd872fe
EZ		 1650 /* We must pay attention to the endiannes. */
1651 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
1652 buffer, temp_buffer);
1653
53116e27
EZ		 1654 /* Write the real regs for which this one is an alias. */
1655 for (portion = 0; portion < 2; portion++)
7bd872fe
EZ		 1656 regcache_write (base_regnum + portion,
1657 temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27 1658 }
f81353e4
EZ		 1659 else if (reg_nr >= tdep->FV0_REGNUM
1660 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1661 {
1662 base_regnum = fv_reg_base_num (reg_nr);
1663
1664 /* Write the real regs for which this one is an alias. */
1665 for (portion = 0; portion < 4; portion++)
7bd872fe
EZ		 1666 regcache_write (base_regnum + portion,
1667 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27
EZ		 1668 }
1669}
1670
7bd872fe
EZ		 1671static void
1672sh4_register_write (struct gdbarch *gdbarch, int reg_nr, char *buffer)
1673{
1674 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
1675 /* It is a regular register. */
1676 regcache_write (reg_nr, buffer);
1677 else
1678 /* It is a pseudo register and we need to construct its value */
1679 sh_pseudo_register_write (reg_nr, buffer);
1680}
1681
3bbfbb92 1682/* Floating point vector of 4 float registers. */
53116e27
EZ		 1683static void
1684do_fv_register_info (int fv_regnum)
1685{
1686 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1687 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1688 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
1689 (int) read_register (first_fp_reg_num),
1690 (int) read_register (first_fp_reg_num + 1),
1691 (int) read_register (first_fp_reg_num + 2),
1692 (int) read_register (first_fp_reg_num + 3));
1693}
1694
3bbfbb92 1695/* Double precision registers. */
53116e27
EZ		 1696static void
1697do_dr_register_info (int dr_regnum)
1698{
1699 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1700
1701 printf_filtered ("dr%d\t0x%08x%08x\n",
1702 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
1703 (int) read_register (first_fp_reg_num),
1704 (int) read_register (first_fp_reg_num + 1));
1705}
1706
1707static void
1708sh_do_pseudo_register (int regnum)
1709{
f81353e4
EZ		 1710 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1711
53116e27 1712 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1713 internal_error (__FILE__, __LINE__,
1714 "Invalid pseudo register number %d\n", regnum);
f81353e4
EZ		 1715 else if (regnum >= tdep->DR0_REGNUM
1716 && regnum < tdep->DR_LAST_REGNUM)
53116e27 1717 do_dr_register_info (regnum);
f81353e4
EZ		 1718 else if (regnum >= tdep->FV0_REGNUM
1719 && regnum <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1720 do_fv_register_info (regnum);
1721}
1722
53116e27
EZ		 1723static void
1724sh_do_fp_register (int regnum)
1725{ /* do values for FP (float) regs */
1726 char *raw_buffer;
1727 double flt; /* double extracted from raw hex data */
1728 int inv;
1729 int j;
1730
1731 /* Allocate space for the float. */
1732 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
1733
1734 /* Get the data in raw format. */
cda5a58a 1735 if (!frame_register_read (selected_frame, regnum, raw_buffer))
53116e27
EZ		 1736 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1737
1738 /* Get the register as a number */
1739 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1740
1741 /* Print the name and some spaces. */
1742 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1743 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1744
1745 /* Print the value. */
93d56215
AC		 1746 if (inv)
1747 printf_filtered ("<invalid float>");
1748 else
1749 printf_filtered ("%-10.9g", flt);
53116e27
EZ		 1750
1751 /* Print the fp register as hex. */
1752 printf_filtered ("\t(raw 0x");
1753 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
1754 {
d7449b42 1755 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
53116e27
EZ		 1756 : REGISTER_RAW_SIZE (regnum) - 1 - j;
1757 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1758 }
1759 printf_filtered (")");
1760 printf_filtered ("\n");
1761}
1762
1763static void
1764sh_do_register (int regnum)
1765{
1766 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1767
1768 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1769 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1770
1771 /* Get the data in raw format. */
cda5a58a 1772 if (!frame_register_read (selected_frame, regnum, raw_buffer))
53116e27
EZ		 1773 printf_filtered ("*value not available*\n");
1774
1775 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1776 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1777 printf_filtered ("\t");
1778 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1779 gdb_stdout, 0, 1, 0, Val_pretty_default);
1780 printf_filtered ("\n");
1781}
1782
1783static void
1784sh_print_register (int regnum)
1785{
1786 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1787 internal_error (__FILE__, __LINE__,
1788 "Invalid register number %d\n", regnum);
53116e27 1789
e30839fe 1790 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27
EZ		 1791 {
1792 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1793 sh_do_fp_register (regnum); /* FP regs */
1794 else
1795 sh_do_register (regnum); /* All other regs */
1796 }
1797
1798 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
3bbfbb92 1799 do_pseudo_register (regnum);
53116e27
EZ		 1800}
1801
1802void
1803sh_do_registers_info (int regnum, int fpregs)
1804{
1805 if (regnum != -1) /* do one specified register */
1806 {
1807 if (*(REGISTER_NAME (regnum)) == '\0')
1808 error ("Not a valid register for the current processor type");
1809
1810 sh_print_register (regnum);
1811 }
1812 else
1813 /* do all (or most) registers */
1814 {
1815 regnum = 0;
1816 while (regnum < NUM_REGS)
1817 {
1818 /* If the register name is empty, it is undefined for this
1819 processor, so don't display anything. */
1820 if (REGISTER_NAME (regnum) == NULL
1821 || *(REGISTER_NAME (regnum)) == '\0')
1822 {
1823 regnum++;
1824 continue;
1825 }
1826
1827 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1828 {
1829 if (fpregs)
1830 {
1831 /* true for "INFO ALL-REGISTERS" command */
1832 sh_do_fp_register (regnum); /* FP regs */
1833 regnum ++;
1834 }
1835 else
e6c42fda 1836 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1837 }
1838 else
1839 {
1840 sh_do_register (regnum); /* All other regs */
1841 regnum++;
1842 }
1843 }
1844
1845 if (fpregs)
1846 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1847 {
3bbfbb92 1848 do_pseudo_register (regnum);
53116e27
EZ		 1849 regnum++;
1850 }
1851 }
1852}
1853
1a8629c7
MS		 1854#ifdef SVR4_SHARED_LIBS
1855
1856/* Fetch (and possibly build) an appropriate link_map_offsets structure
1857 for native i386 linux targets using the struct offsets defined in
1858 link.h (but without actual reference to that file).
1859
1860 This makes it possible to access i386-linux shared libraries from
1861 a gdb that was not built on an i386-linux host (for cross debugging).
1862 */
1863
1864struct link_map_offsets *
1865sh_linux_svr4_fetch_link_map_offsets (void)
1866{
1867 static struct link_map_offsets lmo;
1868 static struct link_map_offsets *lmp = 0;
1869
1870 if (lmp == 0)
1871 {
1872 lmp = &lmo;
1873
1874 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1875
1876 lmo.r_map_offset = 4;
1877 lmo.r_map_size = 4;
1878
1879 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1880
1881 lmo.l_addr_offset = 0;
1882 lmo.l_addr_size = 4;
1883
1884 lmo.l_name_offset = 4;
1885 lmo.l_name_size = 4;
1886
1887 lmo.l_next_offset = 12;
1888 lmo.l_next_size = 4;
1889
1890 lmo.l_prev_offset = 16;
1891 lmo.l_prev_size = 4;
1892 }
1893
1894 return lmp;
1895}
1896#endif /* SVR4_SHARED_LIBS */
1897
cc17453a
EZ		 1898static gdbarch_init_ftype sh_gdbarch_init;
1899
1900static struct gdbarch *
fba45db2 1901sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 1902{
1903 static LONGEST sh_call_dummy_words[] = {0};
1904 struct gdbarch *gdbarch;
1905 struct gdbarch_tdep *tdep;
1906 gdbarch_register_name_ftype *sh_register_name;
1907 gdbarch_store_return_value_ftype *sh_store_return_value;
1908 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1909
1910 /* Find a candidate among the list of pre-declared architectures. */
1911 arches = gdbarch_list_lookup_by_info (arches, &info);
1912 if (arches != NULL)
1913 return arches->gdbarch;
1914
1915 /* None found, create a new architecture from the information
1916 provided. */
1917 tdep = XMALLOC (struct gdbarch_tdep);
1918 gdbarch = gdbarch_alloc (&info, tdep);
1919
1920 /* Initialize the register numbers that are not common to all the
1921 variants to -1, if necessary thse will be overwritten in the case
1922 statement below. */
1923 tdep->FPUL_REGNUM = -1;
1924 tdep->FPSCR_REGNUM = -1;
3bbfbb92 1925 tdep->PR_REGNUM = 17;
c62a7c7b 1926 tdep->SR_REGNUM = 22;
cc17453a 1927 tdep->DSR_REGNUM = -1;
e6c42fda 1928 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 1929 tdep->A0G_REGNUM = -1;
1930 tdep->A0_REGNUM = -1;
1931 tdep->A1G_REGNUM = -1;
1932 tdep->A1_REGNUM = -1;
1933 tdep->M0_REGNUM = -1;
1934 tdep->M1_REGNUM = -1;
1935 tdep->X0_REGNUM = -1;
1936 tdep->X1_REGNUM = -1;
1937 tdep->Y0_REGNUM = -1;
1938 tdep->Y1_REGNUM = -1;
1939 tdep->MOD_REGNUM = -1;
1940 tdep->RS_REGNUM = -1;
1941 tdep->RE_REGNUM = -1;
1942 tdep->SSR_REGNUM = -1;
1943 tdep->SPC_REGNUM = -1;
53116e27 1944 tdep->DR0_REGNUM = -1;
e6c42fda 1945 tdep->DR_LAST_REGNUM = -1;
53116e27 1946 tdep->FV0_REGNUM = -1;
e6c42fda 1947 tdep->FV_LAST_REGNUM = -1;
3bbfbb92
EZ		 1948 tdep->ARG0_REGNUM = 4;
1949 tdep->ARGLAST_REGNUM = 7;
1950 tdep->RETURN_REGNUM = 0;
1951 tdep->FLOAT_ARGLAST_REGNUM = -1;
a38d2a54 1952
cc17453a 1953 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 1954 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1955 set_gdbarch_max_register_raw_size (gdbarch, 4);
1956 set_gdbarch_max_register_virtual_size (gdbarch, 4);
ec920329 1957 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
a38d2a54 1958 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
88e04cc1 1959 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
a38d2a54
EZ		 1960 set_gdbarch_sp_regnum (gdbarch, 15);
1961 set_gdbarch_fp_regnum (gdbarch, 14);
1962 set_gdbarch_pc_regnum (gdbarch, 16);
1963 set_gdbarch_register_size (gdbarch, 4);
88e04cc1 1964 set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
c5f7d19c 1965 set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info);
eaf90c5d 1966 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92
EZ		 1967 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
1968 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
1969 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
3116c80a 1970 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
3bbfbb92
EZ		 1971 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
1972 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
1973 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
1974 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
1975 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2bf0cb65 1976 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
3bbfbb92
EZ		 1977 skip_prologue_hard_way = sh_skip_prologue_hard_way;
1978 do_pseudo_register = sh_do_pseudo_register;
cc17453a
EZ		 1979
1980 switch (info.bfd_arch_info->mach)
8db62801 1981 {
cc17453a
EZ		 1982 case bfd_mach_sh:
1983 sh_register_name = sh_sh_register_name;
1984 sh_show_regs = sh_generic_show_regs;
1985 sh_store_return_value = sh_default_store_return_value;
1986 sh_register_virtual_type = sh_default_register_virtual_type;
1987 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1988 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1989 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1990 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1991 break;
1992 case bfd_mach_sh2:
1993 sh_register_name = sh_sh_register_name;
1994 sh_show_regs = sh_generic_show_regs;
1995 sh_store_return_value = sh_default_store_return_value;
1996 sh_register_virtual_type = sh_default_register_virtual_type;
1997 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1998 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1999 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2000 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2001 break;
2002 case bfd_mach_sh_dsp:
2003 sh_register_name = sh_sh_dsp_register_name;
2004 sh_show_regs = sh_dsp_show_regs;
2005 sh_store_return_value = sh_default_store_return_value;
2006 sh_register_virtual_type = sh_default_register_virtual_type;
2007 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2008 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2009 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2010 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2011 tdep->DSR_REGNUM = 24;
2012 tdep->A0G_REGNUM = 25;
2013 tdep->A0_REGNUM = 26;
2014 tdep->A1G_REGNUM = 27;
2015 tdep->A1_REGNUM = 28;
2016 tdep->M0_REGNUM = 29;
2017 tdep->M1_REGNUM = 30;
2018 tdep->X0_REGNUM = 31;
2019 tdep->X1_REGNUM = 32;
2020 tdep->Y0_REGNUM = 33;
2021 tdep->Y1_REGNUM = 34;
2022 tdep->MOD_REGNUM = 40;
2023 tdep->RS_REGNUM = 43;
2024 tdep->RE_REGNUM = 44;
2025 break;
2026 case bfd_mach_sh3:
2027 sh_register_name = sh_sh3_register_name;
2028 sh_show_regs = sh3_show_regs;
2029 sh_store_return_value = sh_default_store_return_value;
2030 sh_register_virtual_type = sh_default_register_virtual_type;
2031 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2032 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2033 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2034 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2035 tdep->SSR_REGNUM = 41;
2036 tdep->SPC_REGNUM = 42;
2037 break;
2038 case bfd_mach_sh3e:
2039 sh_register_name = sh_sh3e_register_name;
2040 sh_show_regs = sh3e_show_regs;
2041 sh_store_return_value = sh3e_sh4_store_return_value;
2042 sh_register_virtual_type = sh_sh3e_register_virtual_type;
2043 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 2044 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2045 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2046 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
3bbfbb92 2047 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a
EZ		 2048 set_gdbarch_fp0_regnum (gdbarch, 25);
2049 tdep->FPUL_REGNUM = 23;
2050 tdep->FPSCR_REGNUM = 24;
e6c42fda 2051 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2052 tdep->SSR_REGNUM = 41;
2053 tdep->SPC_REGNUM = 42;
2054 break;
2055 case bfd_mach_sh3_dsp:
2056 sh_register_name = sh_sh3_dsp_register_name;
2057 sh_show_regs = sh3_dsp_show_regs;
2058 sh_store_return_value = sh_default_store_return_value;
2059 sh_register_virtual_type = sh_default_register_virtual_type;
2060 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2061 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2062 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2063 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2064 tdep->DSR_REGNUM = 24;
2065 tdep->A0G_REGNUM = 25;
2066 tdep->A0_REGNUM = 26;
2067 tdep->A1G_REGNUM = 27;
2068 tdep->A1_REGNUM = 28;
2069 tdep->M0_REGNUM = 29;
2070 tdep->M1_REGNUM = 30;
2071 tdep->X0_REGNUM = 31;
2072 tdep->X1_REGNUM = 32;
2073 tdep->Y0_REGNUM = 33;
2074 tdep->Y1_REGNUM = 34;
2075 tdep->MOD_REGNUM = 40;
2076 tdep->RS_REGNUM = 43;
2077 tdep->RE_REGNUM = 44;
2078 tdep->SSR_REGNUM = 41;
2079 tdep->SPC_REGNUM = 42;
2080 break;
2081 case bfd_mach_sh4:
53116e27
EZ		 2082 sh_register_name = sh_sh4_register_name;
2083 sh_show_regs = sh4_show_regs;
cc17453a 2084 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 2085 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a 2086 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
3bbfbb92 2087 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a 2088 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 2089 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
2090 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
2091 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
2092 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2093 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
2094 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
7bd872fe
EZ		 2095 set_gdbarch_register_read (gdbarch, sh4_register_read);
2096 set_gdbarch_register_write (gdbarch, sh4_register_write);
cc17453a
EZ		 2097 tdep->FPUL_REGNUM = 23;
2098 tdep->FPSCR_REGNUM = 24;
e6c42fda 2099 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2100 tdep->SSR_REGNUM = 41;
2101 tdep->SPC_REGNUM = 42;
53116e27 2102 tdep->DR0_REGNUM = 59;
e6c42fda 2103 tdep->DR_LAST_REGNUM = 66;
53116e27 2104 tdep->FV0_REGNUM = 67;
e6c42fda 2105 tdep->FV_LAST_REGNUM = 70;
cc17453a
EZ		 2106 break;
2107 default:
2108 sh_register_name = sh_generic_register_name;
2109 sh_show_regs = sh_generic_show_regs;
2110 sh_store_return_value = sh_default_store_return_value;
2111 sh_register_virtual_type = sh_default_register_virtual_type;
2112 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2113 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2114 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2115 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 2116 break;
8db62801 2117 }
cc17453a
EZ		 2118
2119 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2120 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2121 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
cc17453a
EZ		 2122 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2123 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2124
cc17453a 2125 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 2126 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
2127
cc17453a
EZ		 2128 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2129 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
cc17453a
EZ		 2130 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2131 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2132 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2133 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/
cc17453a
EZ		 2134
2135 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2136 set_gdbarch_call_dummy_length (gdbarch, 0);
2137 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2138 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2139 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
2140 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2141 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2142 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2143 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
2144 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
2145 set_gdbarch_call_dummy_p (gdbarch, 1);
2146 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
cc17453a
EZ		 2147 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2148 set_gdbarch_coerce_float_to_double (gdbarch,
2149 sh_coerce_float_to_double);
2150
cc17453a
EZ		 2151 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2152 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
2153
cc17453a 2154 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
cc17453a
EZ		 2155 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2156 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2157 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2158 set_gdbarch_function_start_offset (gdbarch, 0);
cc17453a
EZ		 2159
2160 set_gdbarch_frame_args_skip (gdbarch, 0);
2161 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
cc17453a
EZ		 2162 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
2163 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
c347ee3e
MS		 2164 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
2165 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
cc17453a
EZ		 2166 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2167 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2168 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
cc17453a
EZ		 2169
2170 return gdbarch;
8db62801
EZ		 2171}
2172
c906108c 2173void
fba45db2 2174_initialize_sh_tdep (void)
c906108c
SS		 2175{
2176 struct cmd_list_element *c;
cc17453a
EZ		 2177
2178 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
c906108c 2179
53116e27 2180 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2181}
GDB Binutils - Deliverables
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