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[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
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c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
b4a20239
AC		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
3 Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
c906108c 41
1a8629c7
MS		 42#include "solib-svr4.h"
43
cc17453a
EZ		 44#undef XMALLOC
45#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
46
53116e27
EZ		 47
48/* Frame interpretation related functions. */
cc17453a
EZ		 49static gdbarch_breakpoint_from_pc_ftype sh_breakpoint_from_pc;
50static gdbarch_frame_chain_ftype sh_frame_chain;
51static gdbarch_frame_saved_pc_ftype sh_frame_saved_pc;
52static gdbarch_skip_prologue_ftype sh_skip_prologue;
53116e27 53
cc17453a
EZ		 54static gdbarch_frame_init_saved_regs_ftype sh_nofp_frame_init_saved_regs;
55static gdbarch_frame_init_saved_regs_ftype sh_fp_frame_init_saved_regs;
53116e27
EZ		 56static gdbarch_init_extra_frame_info_ftype sh_init_extra_frame_info;
57static gdbarch_pop_frame_ftype sh_pop_frame;
58static gdbarch_saved_pc_after_call_ftype sh_saved_pc_after_call;
59static gdbarch_frame_args_address_ftype sh_frame_args_address;
60static gdbarch_frame_locals_address_ftype sh_frame_locals_address;
61
62/* Function call related functions. */
cc17453a
EZ		 63static gdbarch_extract_return_value_ftype sh_extract_return_value;
64static gdbarch_extract_struct_value_address_ftype sh_extract_struct_value_address;
65static gdbarch_use_struct_convention_ftype sh_use_struct_convention;
cc17453a
EZ		 66static gdbarch_store_struct_return_ftype sh_store_struct_return;
67static gdbarch_push_arguments_ftype sh_push_arguments;
68static gdbarch_push_return_address_ftype sh_push_return_address;
53116e27
EZ		 69static gdbarch_coerce_float_to_double_ftype sh_coerce_float_to_double;
70static gdbarch_store_return_value_ftype sh_default_store_return_value;
71static gdbarch_store_return_value_ftype sh3e_sh4_store_return_value;
cc17453a
EZ		 72
73static gdbarch_register_name_ftype sh_generic_register_name;
74static gdbarch_register_name_ftype sh_sh_register_name;
75static gdbarch_register_name_ftype sh_sh3_register_name;
76static gdbarch_register_name_ftype sh_sh3e_register_name;
77static gdbarch_register_name_ftype sh_sh_dsp_register_name;
78static gdbarch_register_name_ftype sh_sh3_dsp_register_name;
79
53116e27
EZ		 80/* Registers display related functions */
81static gdbarch_register_raw_size_ftype sh_default_register_raw_size;
82static gdbarch_register_raw_size_ftype sh_sh4_register_raw_size;
cc17453a 83
cc17453a 84static gdbarch_register_virtual_size_ftype sh_register_virtual_size;
53116e27
EZ		 85
86static gdbarch_register_byte_ftype sh_default_register_byte;
87static gdbarch_register_byte_ftype sh_sh4_register_byte;
88
cc17453a 89static gdbarch_register_virtual_type_ftype sh_sh3e_register_virtual_type;
53116e27 90static gdbarch_register_virtual_type_ftype sh_sh4_register_virtual_type;
cc17453a
EZ		 91static gdbarch_register_virtual_type_ftype sh_default_register_virtual_type;
92
53116e27
EZ		 93static void sh_generic_show_regs (void);
94static void sh3_show_regs (void);
95static void sh3e_show_regs (void);
96static void sh3_dsp_show_regs (void);
97static void sh_dsp_show_regs (void);
98static void sh4_show_regs (void);
99static void sh_show_regs_command (char *, int);
100
101static struct type *sh_sh4_build_float_register_type (int high);
102
103static gdbarch_fetch_pseudo_register_ftype sh_fetch_pseudo_register;
104static gdbarch_store_pseudo_register_ftype sh_store_pseudo_register;
105static int fv_reg_base_num (int);
106static int dr_reg_base_num (int);
107static void do_fv_register_info (int fv_regnum);
108static void do_dr_register_info (int dr_regnum);
109static void sh_do_pseudo_register (int regnum);
110static void sh_do_fp_register (int regnum);
111static void sh_do_register (int regnum);
112static void sh_print_register (int regnum);
113
114void (*sh_show_regs) (void);
e6c42fda 115int (*print_sh_insn) (bfd_vma, disassemble_info*);
cc17453a 116
cc17453a
EZ		 117/* Define other aspects of the stack frame.
118 we keep a copy of the worked out return pc lying around, since it
119 is a useful bit of info */
120
121struct frame_extra_info
122{
123 CORE_ADDR return_pc;
124 int leaf_function;
125 int f_offset;
63978407 126};
c906108c 127
cc17453a 128#if 0
091be84d
CF		 129#ifdef _WIN32_WCE
130char **sh_register_names = sh3_reg_names;
131#else
c906108c 132char **sh_register_names = sh_generic_reg_names;
091be84d 133#endif
cc17453a 134#endif
c906108c 135
cc17453a
EZ		 136static char *
137sh_generic_register_name (int reg_nr)
c5aa993b 138{
cc17453a 139 static char *register_names[] =
c5aa993b 140 {
cc17453a
EZ		 141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "fpul", "fpscr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
147 "ssr", "spc",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156}
157
158static char *
159sh_sh_register_name (int reg_nr)
160{
161 static char *register_names[] =
63978407 162 {
cc17453a
EZ		 163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "", "",
167 "", "", "", "", "", "", "", "",
168 "", "", "", "", "", "", "", "",
169 "", "",
170 "", "", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178}
179
180static char *
181sh_sh3_register_name (int reg_nr)
182{
183 static char *register_names[] =
c5aa993b 184 {
cc17453a
EZ		 185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "", "",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "ssr", "spc",
192 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
193 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
194 };
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200}
201
202static char *
203sh_sh3e_register_name (int reg_nr)
204{
205 static char *register_names[] =
63978407 206 {
cc17453a
EZ		 207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "fpul", "fpscr",
211 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
212 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
213 "ssr", "spc",
214 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
215 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
216 };
217 if (reg_nr < 0)
218 return NULL;
219 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
220 return NULL;
221 return register_names[reg_nr];
222}
223
224static char *
225sh_sh_dsp_register_name (int reg_nr)
226{
227 static char *register_names[] =
c5aa993b 228 {
cc17453a
EZ		 229 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
230 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
231 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
232 "", "dsr",
233 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
234 "y0", "y1", "", "", "", "", "", "mod",
235 "", "",
236 "rs", "re", "", "", "", "", "", "",
237 "", "", "", "", "", "", "", "",
238 };
239 if (reg_nr < 0)
240 return NULL;
241 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
242 return NULL;
243 return register_names[reg_nr];
244}
245
246static char *
247sh_sh3_dsp_register_name (int reg_nr)
248{
249 static char *register_names[] =
c5aa993b 250 {
cc17453a
EZ		 251 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
252 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
253 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
254 "", "dsr",
255 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
256 "y0", "y1", "", "", "", "", "", "mod",
257 "ssr", "spc",
258 "rs", "re", "", "", "", "", "", "",
259 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
260 "", "", "", "", "", "", "", "",
261 };
262 if (reg_nr < 0)
263 return NULL;
264 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
265 return NULL;
266 return register_names[reg_nr];
267}
268
53116e27
EZ		 269static char *
270sh_sh4_register_name (int reg_nr)
271{
272 static char *register_names[] =
273 {
a38d2a54 274 /* general registers 0-15 */
53116e27
EZ		 275 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
276 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 277 /* 16 - 22 */
53116e27 278 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 279 /* 23, 24 */
53116e27 280 "fpul", "fpscr",
a38d2a54 281 /* floating point registers 25 - 40 */
53116e27
EZ		 282 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
283 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 284 /* 41, 42 */
53116e27 285 "ssr", "spc",
a38d2a54 286 /* bank 0 43 - 50 */
53116e27 287 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 288 /* bank 1 51 - 58 */
53116e27 289 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 290 /* double precision (pseudo) 59 - 66 */
fe9f384f 291 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 292 /* vectors (pseudo) 67 - 70 */
fe9f384f 293 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 294 /* FIXME: missing XF 71 - 86 */
295 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 296 };
297 if (reg_nr < 0)
298 return NULL;
299 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
300 return NULL;
301 return register_names[reg_nr];
302}
303
cc17453a 304static unsigned char *
fba45db2 305sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 306{
307 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
308 static unsigned char breakpoint[] = {0xc3, 0xc3};
309
310 *lenptr = sizeof (breakpoint);
311 return breakpoint;
312}
c906108c
SS		 313
314/* Prologue looks like
c5aa993b
JM		 315 [mov.l <regs>,@-r15]...
316 [sts.l pr,@-r15]
317 [mov.l r14,@-r15]
318 [mov r15,r14]
8db62801
EZ		 319
320 Actually it can be more complicated than this. For instance, with
321 newer gcc's:
322
323 mov.l r14,@-r15
324 add #-12,r15
325 mov r15,r14
326 mov r4,r1
327 mov r5,r2
328 mov.l r6,@(4,r14)
329 mov.l r7,@(8,r14)
330 mov.b r1,@r14
331 mov r14,r1
332 mov r14,r1
333 add #2,r1
334 mov.w r2,@r1
335
c5aa993b 336 */
c906108c 337
8db62801
EZ		 338/* STS.L PR,@-r15 0100111100100010
339 r15-4-->r15, PR-->(r15) */
c906108c 340#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 341
342/* MOV.L Rm,@-r15 00101111mmmm0110
343 r15-4-->r15, Rm-->(R15) */
c906108c 344#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 345
c906108c 346#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 347
348/* MOV r15,r14 0110111011110011
349 r15-->r14 */
c906108c 350#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 351
352/* ADD #imm,r15 01111111iiiiiiii
353 r15+imm-->r15 */
c906108c 354#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 355
c906108c
SS		 356#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
357#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 358
359/* ADD r3,r15 0011111100111100
360 r15+r3-->r15 */
c906108c 361#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 362
363/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 364 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 365 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 366#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 367
8db62801 368/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 369 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 370 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
371 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
372#define IS_ARG_MOV(x) \
373(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 374 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
375 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 376
377/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
378 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
379#define IS_MOV_R14(x) \
cc17453a 380 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 381
382#define FPSCR_SZ (1 << 20)
c906108c 383
c906108c
SS		 384/* Skip any prologue before the guts of a function */
385
8db62801
EZ		 386/* Skip the prologue using the debug information. If this fails we'll
387 fall back on the 'guess' method below. */
388static CORE_ADDR
fba45db2 389after_prologue (CORE_ADDR pc)
8db62801
EZ		 390{
391 struct symtab_and_line sal;
392 CORE_ADDR func_addr, func_end;
393
394 /* If we can not find the symbol in the partial symbol table, then
395 there is no hope we can determine the function's start address
396 with this code. */
397 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
398 return 0;
399
400 /* Get the line associated with FUNC_ADDR. */
401 sal = find_pc_line (func_addr, 0);
402
403 /* There are only two cases to consider. First, the end of the source line
404 is within the function bounds. In that case we return the end of the
405 source line. Second is the end of the source line extends beyond the
406 bounds of the current function. We need to use the slow code to
407 examine instructions in that case. */
408 if (sal.end < func_end)
409 return sal.end;
410 else
411 return 0;
412}
413
414/* Here we look at each instruction in the function, and try to guess
415 where the prologue ends. Unfortunately this is not always
416 accurate. */
417static CORE_ADDR
fba45db2 418skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 419{
2bfa91ee 420 CORE_ADDR here, end;
8db62801 421 int updated_fp = 0;
2bfa91ee
EZ		 422
423 if (!start_pc)
424 return 0;
425
426 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 427 {
2bfa91ee
EZ		 428 int w = read_memory_integer (here, 2);
429 here += 2;
430 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801
EZ		 431 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
432 || IS_ARG_MOV (w) || IS_MOV_R14 (w))
2bfa91ee
EZ		 433 {
434 start_pc = here;
2bfa91ee 435 }
8db62801
EZ		 436 else if (IS_MOV_SP_FP (w))
437 {
438 start_pc = here;
439 updated_fp = 1;
440 }
441 else
442 /* Don't bail out yet, if we are before the copy of sp. */
443 if (updated_fp)
444 break;
c906108c
SS		 445 }
446
447 return start_pc;
448}
449
cc17453a 450static CORE_ADDR
fba45db2 451sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 452{
453 CORE_ADDR post_prologue_pc;
454
455 /* See if we can determine the end of the prologue via the symbol table.
456 If so, then return either PC, or the PC after the prologue, whichever
457 is greater. */
458
459 post_prologue_pc = after_prologue (pc);
460
461 /* If after_prologue returned a useful address, then use it. Else
462 fall back on the instruction skipping code. */
463 if (post_prologue_pc != 0)
464 return max (pc, post_prologue_pc);
465 else
466 return (skip_prologue_hard_way (pc));
467}
468
cc17453a
EZ		 469/* Immediately after a function call, return the saved pc.
470 Can't always go through the frames for this because on some machines
471 the new frame is not set up until the new function executes
472 some instructions.
473
474 The return address is the value saved in the PR register + 4 */
475static CORE_ADDR
fba45db2 476sh_saved_pc_after_call (struct frame_info *frame)
cc17453a
EZ		 477{
478 return (ADDR_BITS_REMOVE(read_register(PR_REGNUM)));
479}
480
481/* Should call_function allocate stack space for a struct return? */
482static int
fba45db2 483sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 484{
485 return (TYPE_LENGTH (type) > 1);
486}
487
488/* Store the address of the place in which to copy the structure the
489 subroutine will return. This is called from call_function.
490
491 We store structs through a pointer passed in R0 */
492static void
fba45db2 493sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 494{
495 write_register (STRUCT_RETURN_REGNUM, (addr));
496}
c906108c 497
cc17453a
EZ		 498/* Disassemble an instruction. */
499static int
fba45db2 500gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c
SS		 501{
502 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
503 return print_insn_sh (memaddr, info);
504 else
505 return print_insn_shl (memaddr, info);
506}
507
508/* Given a GDB frame, determine the address of the calling function's frame.
509 This will be used to create a new GDB frame struct, and then
510 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
511
512 For us, the frame address is its stack pointer value, so we look up
513 the function prologue to determine the caller's sp value, and return it. */
cc17453a 514static CORE_ADDR
fba45db2 515sh_frame_chain (struct frame_info *frame)
c906108c
SS		 516{
517 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
518 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 519 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 520 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 521 else
522 return 0;
523}
524
525/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
526 we might want to do here is to check REGNUM against the clobber mask, and
527 somehow flag it as invalid if it isn't saved on the stack somewhere. This
528 would provide a graceful failure mode when trying to get the value of
529 caller-saves registers for an inner frame. */
530
cc17453a 531static CORE_ADDR
fba45db2 532sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 533{
c906108c
SS		 534 for (; fi; fi = fi->next)
535 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
536 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 537 that's where the previous routine appears to have done a call from. */
c906108c 538 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 539 else
c906108c 540 {
cc17453a 541 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 542 if (!fi->pc)
543 return 0;
cc17453a
EZ		 544 if (fi->saved_regs[regnum] != 0)
545 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 546 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 547 }
548 return read_register (regnum);
549}
550
551/* Put here the code to store, into a struct frame_saved_regs, the
552 addresses of the saved registers of frame described by FRAME_INFO.
553 This includes special registers such as pc and fp saved in special
554 ways in the stack frame. sp is even more special: the address we
555 return for it IS the sp for the next frame. */
cc17453a 556static void
fba45db2 557sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c
SS		 558{
559 int where[NUM_REGS];
560 int rn;
561 int have_fp = 0;
562 int depth;
563 int pc;
564 int opc;
565 int insn;
566 int r3_val = 0;
c5aa993b 567 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 568
569 if (fi->saved_regs == NULL)
570 frame_saved_regs_zalloc (fi);
571 else
572 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
573
574 if (dummy_regs)
575 {
576 /* DANGER! This is ONLY going to work if the char buffer format of
577 the saved registers is byte-for-byte identical to the
578 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
579 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
580 return;
581 }
582
583 fi->extra_info->leaf_function = 1;
584 fi->extra_info->f_offset = 0;
585
586 for (rn = 0; rn < NUM_REGS; rn++)
587 where[rn] = -1;
588
589 depth = 0;
590
591 /* Loop around examining the prologue insns until we find something
592 that does not appear to be part of the prologue. But give up
593 after 20 of them, since we're getting silly then. */
594
595 pc = get_pc_function_start (fi->pc);
596 if (!pc)
597 {
598 fi->pc = 0;
599 return;
600 }
601
602 for (opc = pc + (2 * 28); pc < opc; pc += 2)
603 {
604 insn = read_memory_integer (pc, 2);
605 /* See where the registers will be saved to */
606 if (IS_PUSH (insn))
607 {
608 rn = GET_PUSHED_REG (insn);
609 where[rn] = depth;
610 depth += 4;
611 }
612 else if (IS_STS (insn))
613 {
614 where[PR_REGNUM] = depth;
615 /* If we're storing the pr then this isn't a leaf */
616 fi->extra_info->leaf_function = 0;
617 depth += 4;
618 }
619 else if (IS_MOV_R3 (insn))
620 {
621 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
622 }
623 else if (IS_SHLL_R3 (insn))
624 {
625 r3_val <<= 1;
626 }
627 else if (IS_ADD_R3SP (insn))
628 {
629 depth += -r3_val;
630 }
631 else if (IS_ADD_SP (insn))
632 {
633 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
634 }
635 else if (IS_MOV_SP_FP (insn))
636 break;
637#if 0 /* This used to just stop when it found an instruction that
638 was not considered part of the prologue. Now, we just
639 keep going looking for likely instructions. */
640 else
641 break;
642#endif
643 }
644
645 /* Now we know how deep things are, we can work out their addresses */
646
647 for (rn = 0; rn < NUM_REGS; rn++)
648 {
649 if (where[rn] >= 0)
650 {
651 if (rn == FP_REGNUM)
652 have_fp = 1;
c906108c 653
cc17453a
EZ		 654 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
655 }
656 else
657 {
658 fi->saved_regs[rn] = 0;
659 }
660 }
661
662 if (have_fp)
663 {
664 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
665 }
666 else
667 {
668 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
669 }
670
671 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
672 /* Work out the return pc - either from the saved pr or the pr
673 value */
674}
675
676static void
fba45db2 677sh_fp_frame_init_saved_regs (struct frame_info *fi)
cc17453a
EZ		 678{
679 int where[NUM_REGS];
680 int rn;
681 int have_fp = 0;
682 int depth;
683 int pc;
684 int opc;
685 int insn;
686 int r3_val = 0;
687 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
688
689 if (fi->saved_regs == NULL)
690 frame_saved_regs_zalloc (fi);
691 else
692 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
693
c906108c
SS		 694 if (dummy_regs)
695 {
696 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 697 the saved registers is byte-for-byte identical to the
698 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 699 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 700 return;
701 }
702
cc17453a
EZ		 703 fi->extra_info->leaf_function = 1;
704 fi->extra_info->f_offset = 0;
c906108c
SS		 705
706 for (rn = 0; rn < NUM_REGS; rn++)
707 where[rn] = -1;
708
709 depth = 0;
710
711 /* Loop around examining the prologue insns until we find something
712 that does not appear to be part of the prologue. But give up
713 after 20 of them, since we're getting silly then. */
714
2bfa91ee
EZ		 715 pc = get_pc_function_start (fi->pc);
716 if (!pc)
c906108c 717 {
2bfa91ee
EZ		 718 fi->pc = 0;
719 return;
720 }
721
722 for (opc = pc + (2 * 28); pc < opc; pc += 2)
723 {
724 insn = read_memory_integer (pc, 2);
c906108c
SS		 725 /* See where the registers will be saved to */
726 if (IS_PUSH (insn))
727 {
c906108c
SS		 728 rn = GET_PUSHED_REG (insn);
729 where[rn] = depth;
c906108c
SS		 730 depth += 4;
731 }
732 else if (IS_STS (insn))
733 {
c906108c 734 where[PR_REGNUM] = depth;
c906108c 735 /* If we're storing the pr then this isn't a leaf */
cc17453a 736 fi->extra_info->leaf_function = 0;
c906108c
SS		 737 depth += 4;
738 }
739 else if (IS_MOV_R3 (insn))
740 {
741 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 742 }
743 else if (IS_SHLL_R3 (insn))
744 {
745 r3_val <<= 1;
c906108c
SS		 746 }
747 else if (IS_ADD_R3SP (insn))
748 {
749 depth += -r3_val;
c906108c
SS		 750 }
751 else if (IS_ADD_SP (insn))
752 {
c906108c 753 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 754 }
755 else if (IS_FMOV (insn))
756 {
cc17453a 757 if (read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 758 {
759 depth += 8;
760 }
761 else
762 {
763 depth += 4;
764 }
765 }
2bfa91ee
EZ		 766 else if (IS_MOV_SP_FP (insn))
767 break;
768#if 0 /* This used to just stop when it found an instruction that
769 was not considered part of the prologue. Now, we just
770 keep going looking for likely instructions. */
c906108c
SS		 771 else
772 break;
2bfa91ee 773#endif
c906108c
SS		 774 }
775
776 /* Now we know how deep things are, we can work out their addresses */
777
778 for (rn = 0; rn < NUM_REGS; rn++)
779 {
780 if (where[rn] >= 0)
781 {
782 if (rn == FP_REGNUM)
783 have_fp = 1;
784
cc17453a 785 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 786 }
787 else
788 {
cc17453a 789 fi->saved_regs[rn] = 0;
c906108c
SS		 790 }
791 }
792
793 if (have_fp)
794 {
cc17453a 795 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 796 }
797 else
798 {
cc17453a 799 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 800 }
801
cc17453a 802 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 803 /* Work out the return pc - either from the saved pr or the pr
804 value */
805}
806
cc17453a
EZ		 807/* Initialize the extra info saved in a FRAME */
808static void
fba45db2 809sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 810{
cc17453a
EZ		 811
812 fi->extra_info = (struct frame_extra_info *)
813 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 814
815 if (fi->next)
816 fi->pc = FRAME_SAVED_PC (fi->next);
817
818 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
819 {
820 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 821 by assuming it's always FP. */
822 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
823 SP_REGNUM);
cc17453a
EZ		 824 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
825 PC_REGNUM);
826 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
827 fi->extra_info->leaf_function = 0;
c906108c
SS		 828 return;
829 }
830 else
831 {
cc17453a
EZ		 832 FRAME_INIT_SAVED_REGS (fi);
833 fi->extra_info->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
c906108c
SS		 834 }
835}
836
cc17453a
EZ		 837/* Extract from an array REGBUF containing the (raw) register state
838 the address in which a function should return its structure value,
839 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 840static CORE_ADDR
0c8053b6 841sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 842{
843 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
844}
845
846static CORE_ADDR
fba45db2 847sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 848{
849 return ((frame)->extra_info->return_pc);
850}
851
852static CORE_ADDR
fba45db2 853sh_frame_args_address (struct frame_info *fi)
cc17453a
EZ		 854{
855 return (fi)->frame;
856}
857
858static CORE_ADDR
fba45db2 859sh_frame_locals_address (struct frame_info *fi)
cc17453a
EZ		 860{
861 return (fi)->frame;
862}
863
c906108c
SS		 864/* Discard from the stack the innermost frame,
865 restoring all saved registers. */
cc17453a 866static void
fba45db2 867sh_pop_frame (void)
c906108c
SS		 868{
869 register struct frame_info *frame = get_current_frame ();
870 register CORE_ADDR fp;
871 register int regnum;
c906108c
SS		 872
873 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
874 generic_pop_dummy_frame ();
875 else
c5aa993b
JM		 876 {
877 fp = FRAME_FP (frame);
cc17453a 878 FRAME_INIT_SAVED_REGS (frame);
c906108c 879
c5aa993b
JM		 880 /* Copy regs from where they were saved in the frame */
881 for (regnum = 0; regnum < NUM_REGS; regnum++)
cc17453a
EZ		 882 if (frame->saved_regs[regnum])
883 write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 884
cc17453a 885 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 886 write_register (SP_REGNUM, fp + 4);
887 }
c906108c
SS		 888 flush_cached_frames ();
889}
890
891/* Function: push_arguments
892 Setup the function arguments for calling a function in the inferior.
893
894 On the Hitachi SH architecture, there are four registers (R4 to R7)
895 which are dedicated for passing function arguments. Up to the first
896 four arguments (depending on size) may go into these registers.
897 The rest go on the stack.
898
899 Arguments that are smaller than 4 bytes will still take up a whole
900 register or a whole 32-bit word on the stack, and will be
901 right-justified in the register or the stack word. This includes
902 chars, shorts, and small aggregate types.
903
904 Arguments that are larger than 4 bytes may be split between two or
905 more registers. If there are not enough registers free, an argument
906 may be passed partly in a register (or registers), and partly on the
907 stack. This includes doubles, long longs, and larger aggregates.
908 As far as I know, there is no upper limit to the size of aggregates
909 that will be passed in this way; in other words, the convention of
910 passing a pointer to a large aggregate instead of a copy is not used.
911
912 An exceptional case exists for struct arguments (and possibly other
913 aggregates such as arrays) if the size is larger than 4 bytes but
914 not a multiple of 4 bytes. In this case the argument is never split
915 between the registers and the stack, but instead is copied in its
916 entirety onto the stack, AND also copied into as many registers as
917 there is room for. In other words, space in registers permitting,
918 two copies of the same argument are passed in. As far as I can tell,
919 only the one on the stack is used, although that may be a function
920 of the level of compiler optimization. I suspect this is a compiler
921 bug. Arguments of these odd sizes are left-justified within the
922 word (as opposed to arguments smaller than 4 bytes, which are
923 right-justified).
c5aa993b 924
c906108c
SS		 925 If the function is to return an aggregate type such as a struct, it
926 is either returned in the normal return value register R0 (if its
927 size is no greater than one byte), or else the caller must allocate
928 space into which the callee will copy the return value (if the size
929 is greater than one byte). In this case, a pointer to the return
930 value location is passed into the callee in register R2, which does
931 not displace any of the other arguments passed in via registers R4
932 to R7. */
933
cc17453a 934static CORE_ADDR
34e9d9bb
EZ		 935sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
936 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 937{
938 int stack_offset, stack_alloc;
939 int argreg;
940 int argnum;
941 struct type *type;
942 CORE_ADDR regval;
943 char *val;
944 char valbuf[4];
945 int len;
946 int odd_sized_struct;
947
948 /* first force sp to a 4-byte alignment */
949 sp = sp & ~3;
950
951 /* The "struct return pointer" pseudo-argument has its own dedicated
952 register */
953 if (struct_return)
c5aa993b 954 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 955
956 /* Now make sure there's space on the stack */
cc17453a 957 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 958 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
959 sp -= stack_alloc; /* make room on stack for args */
c906108c 960
c906108c
SS		 961 /* Now load as many as possible of the first arguments into
962 registers, and push the rest onto the stack. There are 16 bytes
963 in four registers available. Loop thru args from first to last. */
964
965 argreg = ARG0_REGNUM;
966 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
967 {
968 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 969 len = TYPE_LENGTH (type);
970 memset (valbuf, 0, sizeof (valbuf));
c906108c 971 if (len < 4)
cc17453a
EZ		 972 {
973 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 974 memcpy (valbuf + (4 - len),
975 (char *) VALUE_CONTENTS (args[argnum]), len);
976 val = valbuf;
977 }
c906108c 978 else
c5aa993b 979 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 980
981 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 982 odd_sized_struct = 1; /* such structs go entirely on stack */
983 else
c906108c
SS		 984 odd_sized_struct = 0;
985 while (len > 0)
986 {
987 if (argreg > ARGLAST_REGNUM || odd_sized_struct)
c5aa993b 988 { /* must go on the stack */
c906108c
SS		 989 write_memory (sp + stack_offset, val, 4);
990 stack_offset += 4;
991 }
992 /* NOTE WELL!!!!! This is not an "else if" clause!!!
993 That's because some *&^%$ things get passed on the stack
994 AND in the registers! */
995 if (argreg <= ARGLAST_REGNUM)
c5aa993b
JM		 996 { /* there's room in a register */
997 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 998 write_register (argreg++, regval);
999 }
1000 /* Store the value 4 bytes at a time. This means that things
1001 larger than 4 bytes may go partly in registers and partly
1002 on the stack. */
c5aa993b
JM		 1003 len -= REGISTER_RAW_SIZE (argreg);
1004 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 1005 }
1006 }
1007 return sp;
1008}
1009
1010/* Function: push_return_address (pc)
1011 Set up the return address for the inferior function call.
1012 Needed for targets where we don't actually execute a JSR/BSR instruction */
1013
cc17453a 1014static CORE_ADDR
fba45db2 1015sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c
SS		 1016{
1017 write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
1018 return sp;
1019}
1020
1021/* Function: fix_call_dummy
1022 Poke the callee function's address into the destination part of
1023 the CALL_DUMMY. The address is actually stored in a data word
1024 following the actualy CALL_DUMMY instructions, which will load
1025 it into a register using PC-relative addressing. This function
1026 expects the CALL_DUMMY to look like this:
1027
c5aa993b
JM		 1028 mov.w @(2,PC), R8
1029 jsr @R8
1030 nop
1031 trap
1032 <destination>
1033 */
c906108c
SS		 1034
1035#if 0
1036void
fba45db2
KB		 1037sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1038 value_ptr *args, struct type *type, int gcc_p)
c906108c
SS		 1039{
1040 *(unsigned long *) (dummy + 8) = fun;
1041}
1042#endif
1043
cc17453a
EZ		 1044static int
1045sh_coerce_float_to_double (struct type *formal, struct type *actual)
1046{
1047 return 1;
1048}
c906108c 1049
cc17453a
EZ		 1050/* Find a function's return value in the appropriate registers (in
1051 regbuf), and copy it into valbuf. Extract from an array REGBUF
1052 containing the (raw) register state a function return value of type
1053 TYPE, and copy that, in virtual format, into VALBUF. */
1054static void
fba45db2 1055sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 1056{
cc17453a 1057 int len = TYPE_LENGTH (type);
c906108c 1058
cc17453a
EZ		 1059 if (len <= 4)
1060 memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
1061 else if (len <= 8)
1062 memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
1063 else
1064 error ("bad size for return value");
1065}
c906108c 1066
cc17453a
EZ		 1067/* Write into appropriate registers a function return value
1068 of type TYPE, given in virtual format.
1069 If the architecture is sh4 or sh3e, store a function's return value
1070 in the R0 general register or in the FP0 floating point register,
1071 depending on the type of the return value. In all the other cases
1072 the result is stored in r0. */
1073static void
1074sh_default_store_return_value (struct type *type, char *valbuf)
1075{
1076 write_register_bytes (REGISTER_BYTE (0),
1077 valbuf, TYPE_LENGTH (type));
1078}
c906108c 1079
cc17453a
EZ		 1080static void
1081sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1082{
1083 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1084 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1085 valbuf, TYPE_LENGTH (type));
1086 else
1087 write_register_bytes (REGISTER_BYTE (0),
1088 valbuf, TYPE_LENGTH (type));
c906108c
SS		 1089}
1090
cc17453a 1091
c906108c
SS		 1092/* Print the registers in a form similar to the E7000 */
1093
1094static void
fba45db2 1095sh_generic_show_regs (void)
c906108c 1096{
cc17453a
EZ		 1097 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1098 paddr (read_register (PC_REGNUM)),
c62a7c7b 1099 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1100 (long) read_register (PR_REGNUM),
1101 (long) read_register (MACH_REGNUM),
1102 (long) read_register (MACL_REGNUM));
1103
1104 printf_filtered ("GBR=%08lx VBR=%08lx",
1105 (long) read_register (GBR_REGNUM),
1106 (long) read_register (VBR_REGNUM));
1107
1108 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1109 (long) read_register (0),
1110 (long) read_register (1),
1111 (long) read_register (2),
1112 (long) read_register (3),
1113 (long) read_register (4),
1114 (long) read_register (5),
1115 (long) read_register (6),
1116 (long) read_register (7));
1117 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1118 (long) read_register (8),
1119 (long) read_register (9),
1120 (long) read_register (10),
1121 (long) read_register (11),
1122 (long) read_register (12),
1123 (long) read_register (13),
1124 (long) read_register (14),
1125 (long) read_register (15));
1126}
c906108c 1127
cc17453a 1128static void
fba45db2 1129sh3_show_regs (void)
cc17453a 1130{
d4f3574e
SS		 1131 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1132 paddr (read_register (PC_REGNUM)),
c62a7c7b 1133 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
d4f3574e
SS		 1134 (long) read_register (PR_REGNUM),
1135 (long) read_register (MACH_REGNUM),
1136 (long) read_register (MACL_REGNUM));
1137
1138 printf_filtered ("GBR=%08lx VBR=%08lx",
1139 (long) read_register (GBR_REGNUM),
1140 (long) read_register (VBR_REGNUM));
cc17453a
EZ		 1141 printf_filtered (" SSR=%08lx SPC=%08lx",
1142 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1143 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
c906108c 1144
d4f3574e
SS		 1145 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1146 (long) read_register (0),
1147 (long) read_register (1),
1148 (long) read_register (2),
1149 (long) read_register (3),
1150 (long) read_register (4),
1151 (long) read_register (5),
1152 (long) read_register (6),
1153 (long) read_register (7));
1154 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1155 (long) read_register (8),
1156 (long) read_register (9),
1157 (long) read_register (10),
1158 (long) read_register (11),
1159 (long) read_register (12),
1160 (long) read_register (13),
1161 (long) read_register (14),
1162 (long) read_register (15));
c906108c
SS		 1163}
1164
53116e27 1165
cc17453a 1166static void
fba45db2 1167sh3e_show_regs (void)
cc17453a
EZ		 1168{
1169 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1170 paddr (read_register (PC_REGNUM)),
c62a7c7b 1171 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1172 (long) read_register (PR_REGNUM),
1173 (long) read_register (MACH_REGNUM),
1174 (long) read_register (MACL_REGNUM));
1175
1176 printf_filtered ("GBR=%08lx VBR=%08lx",
1177 (long) read_register (GBR_REGNUM),
1178 (long) read_register (VBR_REGNUM));
1179 printf_filtered (" SSR=%08lx SPC=%08lx",
1180 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1181 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1182 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1183 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1184 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
c906108c 1185
cc17453a
EZ		 1186 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1187 (long) read_register (0),
1188 (long) read_register (1),
1189 (long) read_register (2),
1190 (long) read_register (3),
1191 (long) read_register (4),
1192 (long) read_register (5),
1193 (long) read_register (6),
1194 (long) read_register (7));
1195 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1196 (long) read_register (8),
1197 (long) read_register (9),
1198 (long) read_register (10),
1199 (long) read_register (11),
1200 (long) read_register (12),
1201 (long) read_register (13),
1202 (long) read_register (14),
1203 (long) read_register (15));
1204
1205 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1206 (long) read_register (FP0_REGNUM + 0),
1207 (long) read_register (FP0_REGNUM + 1),
1208 (long) read_register (FP0_REGNUM + 2),
1209 (long) read_register (FP0_REGNUM + 3),
1210 (long) read_register (FP0_REGNUM + 4),
1211 (long) read_register (FP0_REGNUM + 5),
1212 (long) read_register (FP0_REGNUM + 6),
1213 (long) read_register (FP0_REGNUM + 7));
1214 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1215 (long) read_register (FP0_REGNUM + 8),
1216 (long) read_register (FP0_REGNUM + 9),
1217 (long) read_register (FP0_REGNUM + 10),
1218 (long) read_register (FP0_REGNUM + 11),
1219 (long) read_register (FP0_REGNUM + 12),
1220 (long) read_register (FP0_REGNUM + 13),
1221 (long) read_register (FP0_REGNUM + 14),
1222 (long) read_register (FP0_REGNUM + 15));
1223}
1224
1225static void
fba45db2 1226sh3_dsp_show_regs (void)
c906108c 1227{
cc17453a
EZ		 1228 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1229 paddr (read_register (PC_REGNUM)),
c62a7c7b 1230 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1231 (long) read_register (PR_REGNUM),
1232 (long) read_register (MACH_REGNUM),
1233 (long) read_register (MACL_REGNUM));
c906108c 1234
cc17453a
EZ		 1235 printf_filtered ("GBR=%08lx VBR=%08lx",
1236 (long) read_register (GBR_REGNUM),
1237 (long) read_register (VBR_REGNUM));
1238
1239 printf_filtered (" SSR=%08lx SPC=%08lx",
1240 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1241 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1242
1243 printf_filtered (" DSR=%08lx",
1244 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1245
1246 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1247 (long) read_register (0),
1248 (long) read_register (1),
1249 (long) read_register (2),
1250 (long) read_register (3),
1251 (long) read_register (4),
1252 (long) read_register (5),
1253 (long) read_register (6),
1254 (long) read_register (7));
1255 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1256 (long) read_register (8),
1257 (long) read_register (9),
1258 (long) read_register (10),
1259 (long) read_register (11),
1260 (long) read_register (12),
1261 (long) read_register (13),
1262 (long) read_register (14),
1263 (long) read_register (15));
1264
1265 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1266 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1267 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1268 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1269 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1270 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1271 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1272 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1273 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1274 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1275 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1276 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1277 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1278 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1279 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
c906108c
SS		 1280}
1281
cc17453a 1282static void
fba45db2 1283sh4_show_regs (void)
cc17453a
EZ		 1284{
1285 int pr = read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & 0x80000;
1286 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1287 paddr (read_register (PC_REGNUM)),
c62a7c7b 1288 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1289 (long) read_register (PR_REGNUM),
1290 (long) read_register (MACH_REGNUM),
1291 (long) read_register (MACL_REGNUM));
1292
1293 printf_filtered ("GBR=%08lx VBR=%08lx",
1294 (long) read_register (GBR_REGNUM),
1295 (long) read_register (VBR_REGNUM));
1296 printf_filtered (" SSR=%08lx SPC=%08lx",
1297 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1298 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1299 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1300 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1301 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
1302
1303 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1304 (long) read_register (0),
1305 (long) read_register (1),
1306 (long) read_register (2),
1307 (long) read_register (3),
1308 (long) read_register (4),
1309 (long) read_register (5),
1310 (long) read_register (6),
1311 (long) read_register (7));
1312 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1313 (long) read_register (8),
1314 (long) read_register (9),
1315 (long) read_register (10),
1316 (long) read_register (11),
1317 (long) read_register (12),
1318 (long) read_register (13),
1319 (long) read_register (14),
1320 (long) read_register (15));
1321
1322 printf_filtered ((pr
1323 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1324 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1325 (long) read_register (FP0_REGNUM + 0),
1326 (long) read_register (FP0_REGNUM + 1),
1327 (long) read_register (FP0_REGNUM + 2),
1328 (long) read_register (FP0_REGNUM + 3),
1329 (long) read_register (FP0_REGNUM + 4),
1330 (long) read_register (FP0_REGNUM + 5),
1331 (long) read_register (FP0_REGNUM + 6),
1332 (long) read_register (FP0_REGNUM + 7));
1333 printf_filtered ((pr
1334 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1335 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1336 (long) read_register (FP0_REGNUM + 8),
1337 (long) read_register (FP0_REGNUM + 9),
1338 (long) read_register (FP0_REGNUM + 10),
1339 (long) read_register (FP0_REGNUM + 11),
1340 (long) read_register (FP0_REGNUM + 12),
1341 (long) read_register (FP0_REGNUM + 13),
1342 (long) read_register (FP0_REGNUM + 14),
1343 (long) read_register (FP0_REGNUM + 15));
1344}
1345
1346static void
fba45db2 1347sh_dsp_show_regs (void)
cc17453a
EZ		 1348{
1349 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1350 paddr (read_register (PC_REGNUM)),
c62a7c7b 1351 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1352 (long) read_register (PR_REGNUM),
1353 (long) read_register (MACH_REGNUM),
1354 (long) read_register (MACL_REGNUM));
1355
1356 printf_filtered ("GBR=%08lx VBR=%08lx",
1357 (long) read_register (GBR_REGNUM),
1358 (long) read_register (VBR_REGNUM));
1359
1360 printf_filtered (" DSR=%08lx",
1361 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1362
1363 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1364 (long) read_register (0),
1365 (long) read_register (1),
1366 (long) read_register (2),
1367 (long) read_register (3),
1368 (long) read_register (4),
1369 (long) read_register (5),
1370 (long) read_register (6),
1371 (long) read_register (7));
1372 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1373 (long) read_register (8),
1374 (long) read_register (9),
1375 (long) read_register (10),
1376 (long) read_register (11),
1377 (long) read_register (12),
1378 (long) read_register (13),
1379 (long) read_register (14),
1380 (long) read_register (15));
1381
1382 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1383 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1384 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1385 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1386 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1387 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1388 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1389 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1390 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1391 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1392 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1393 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1394 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1395 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1396 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
1397}
1398
53116e27
EZ		 1399void sh_show_regs_command (char *args, int from_tty)
1400{
1401 if (sh_show_regs)
1402 (*sh_show_regs)();
1403}
1404
cc17453a
EZ		 1405/* Index within `registers' of the first byte of the space for
1406 register N. */
1407static int
fba45db2 1408sh_default_register_byte (int reg_nr)
8db62801 1409{
cc17453a
EZ		 1410 return (reg_nr * 4);
1411}
1412
53116e27 1413static int
fba45db2 1414sh_sh4_register_byte (int reg_nr)
53116e27
EZ		 1415{
1416 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1417 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1418 return (dr_reg_base_num (reg_nr) * 4);
1419 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1420 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1421 return (fv_reg_base_num (reg_nr) * 4);
1422 else
1423 return (reg_nr * 4);
1424}
1425
cc17453a
EZ		 1426/* Number of bytes of storage in the actual machine representation for
1427 register REG_NR. */
1428static int
fba45db2 1429sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 1430{
1431 return 4;
1432}
1433
53116e27 1434static int
fba45db2 1435sh_sh4_register_raw_size (int reg_nr)
53116e27
EZ		 1436{
1437 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1438 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1439 return 8;
1440 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1441 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1442 return 16;
1443 else
1444 return 4;
1445}
1446
cc17453a
EZ		 1447/* Number of bytes of storage in the program's representation
1448 for register N. */
1449static int
fba45db2 1450sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 1451{
1452 return 4;
1453}
1454
1455/* Return the GDB type object for the "standard" data type
1456 of data in register N. */
1457
1458static struct type *
fba45db2 1459sh_sh3e_register_virtual_type (int reg_nr)
cc17453a
EZ		 1460{
1461 if ((reg_nr >= FP0_REGNUM
e6c42fda 1462 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
cc17453a
EZ		 1463 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1464 return builtin_type_float;
8db62801 1465 else
cc17453a
EZ		 1466 return builtin_type_int;
1467}
1468
53116e27 1469static struct type *
fba45db2 1470sh_sh4_register_virtual_type (int reg_nr)
53116e27
EZ		 1471{
1472 if ((reg_nr >= FP0_REGNUM
e6c42fda 1473 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
53116e27
EZ		 1474 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1475 return builtin_type_float;
1476 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1477 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1478 return builtin_type_double;
1479 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1480 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1481 return sh_sh4_build_float_register_type (3);
1482 else
1483 return builtin_type_int;
1484}
1485
1486static struct type *
1487sh_sh4_build_float_register_type (int high)
1488{
1489 struct type *temp;
1490
1491 temp = create_range_type (NULL, builtin_type_int, 0, high);
1492 return create_array_type (NULL, builtin_type_float, temp);
1493}
1494
cc17453a 1495static struct type *
fba45db2 1496sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 1497{
1498 return builtin_type_int;
1499}
1500
fb409745
EZ		 1501/* On the sh4, the DRi pseudo registers are problematic if the target
1502 is little endian. When the user writes one of those registers, for
1503 instance with 'ser var $dr0=1', we want the double to be stored
1504 like this:
1505 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1506 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1507
1508 This corresponds to little endian byte order & big endian word
1509 order. However if we let gdb write the register w/o conversion, it
1510 will write fr0 and fr1 this way:
1511 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1512 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1513 because it will consider fr0 and fr1 as a single LE stretch of memory.
1514
1515 To achieve what we want we must force gdb to store things in
1516 floatformat_ieee_double_littlebyte_bigword (which is defined in
1517 include/floatformat.h and libiberty/floatformat.c.
1518
1519 In case the target is big endian, there is no problem, the
1520 raw bytes will look like:
1521 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1522 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1523
1524 The other pseudo registers (the FVs) also don't pose a problem
1525 because they are stored as 4 individual FP elements. */
1526
1527int
1528sh_sh4_register_convertible (int nr)
1529{
1530 if (TARGET_BYTE_ORDER == LITTLE_ENDIAN)
1531 return (gdbarch_tdep (current_gdbarch)->DR0_REGNUM <= nr
e6c42fda 1532 && nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM);
fb409745
EZ		 1533 else
1534 return 0;
1535}
1536
1537void
1538sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1539 char *from, char *to)
1540{
1541 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1542 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1543 {
1544 DOUBLEST val;
1545 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
1546 store_floating(to, TYPE_LENGTH(type), val);
1547 }
1548 else
1549 error("sh_register_convert_to_virtual called with non DR register number");
1550}
1551
1552void
1553sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1554 char *from, char *to)
1555{
1556 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1557 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1558 {
1559 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
1560 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1561 }
1562 else
1563 error("sh_register_convert_to_raw called with non DR register number");
1564}
1565
53116e27
EZ		 1566void
1567sh_fetch_pseudo_register (int reg_nr)
1568{
1569 int base_regnum, portion;
1570
1571 if (!register_cached (reg_nr))
1572 {
1573 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1574 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1575 {
1576 base_regnum = dr_reg_base_num (reg_nr);
1577
1578 /* Read the real regs for which this one is an alias. */
1579 for (portion = 0; portion < 2; portion++)
1580 if (!register_cached (base_regnum + portion))
1581 target_fetch_registers (base_regnum + portion);
1582 }
1583 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1584 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1585 {
1586 base_regnum = fv_reg_base_num (reg_nr);
1587
1588 /* Read the real regs for which this one is an alias. */
1589 for (portion = 0; portion < 4; portion++)
1590 if (!register_cached (base_regnum + portion))
1591 target_fetch_registers (base_regnum + portion);
1592
1593 }
1594 register_valid [reg_nr] = 1;
1595 }
1596}
1597
1598void
1599sh_store_pseudo_register (int reg_nr)
1600{
1601 int base_regnum, portion;
1602
1603 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1604 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1605 {
1606 base_regnum = dr_reg_base_num (reg_nr);
1607
1608 /* Write the real regs for which this one is an alias. */
1609 for (portion = 0; portion < 2; portion++)
1610 {
1611 register_valid[base_regnum + portion] = 1;
1612 target_store_registers (base_regnum + portion);
1613 }
1614 }
1615 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1616 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1617 {
1618 base_regnum = fv_reg_base_num (reg_nr);
1619
1620 /* Write the real regs for which this one is an alias. */
1621 for (portion = 0; portion < 4; portion++)
1622 {
1623 register_valid[base_regnum + portion] = 1;
1624 target_store_registers (base_regnum + portion);
1625 }
1626 }
1627}
1628
1629static int
1630fv_reg_base_num (int fv_regnum)
1631{
1632 int fp_regnum;
1633
1634 fp_regnum = FP0_REGNUM +
1635 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1636 return fp_regnum;
1637}
1638
1639static int
1640dr_reg_base_num (int dr_regnum)
1641{
1642 int fp_regnum;
1643
1644 fp_regnum = FP0_REGNUM +
1645 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1646 return fp_regnum;
1647}
1648
1649static void
1650do_fv_register_info (int fv_regnum)
1651{
1652 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1653 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1654 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
1655 (int) read_register (first_fp_reg_num),
1656 (int) read_register (first_fp_reg_num + 1),
1657 (int) read_register (first_fp_reg_num + 2),
1658 (int) read_register (first_fp_reg_num + 3));
1659}
1660
1661static void
1662do_dr_register_info (int dr_regnum)
1663{
1664 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1665
1666 printf_filtered ("dr%d\t0x%08x%08x\n",
1667 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
1668 (int) read_register (first_fp_reg_num),
1669 (int) read_register (first_fp_reg_num + 1));
1670}
1671
1672static void
1673sh_do_pseudo_register (int regnum)
1674{
1675 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e1a459b 1676 internal_error ("Invalid pseudo register number %d\n", regnum);
a38d2a54
EZ		 1677 else if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
1678 && regnum < gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27 1679 do_dr_register_info (regnum);
a38d2a54
EZ		 1680 else if (regnum >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
1681 && regnum <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1682 do_fv_register_info (regnum);
1683}
1684
1685
1686static void
1687sh_do_fp_register (int regnum)
1688{ /* do values for FP (float) regs */
1689 char *raw_buffer;
1690 double flt; /* double extracted from raw hex data */
1691 int inv;
1692 int j;
1693
1694 /* Allocate space for the float. */
1695 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
1696
1697 /* Get the data in raw format. */
1698 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1699 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1700
1701 /* Get the register as a number */
1702 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1703
1704 /* Print the name and some spaces. */
1705 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1706 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1707
1708 /* Print the value. */
1709 printf_filtered (inv ? "<invalid float>" : "%-10.9g", flt);
1710
1711 /* Print the fp register as hex. */
1712 printf_filtered ("\t(raw 0x");
1713 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
1714 {
1715 register int idx = TARGET_BYTE_ORDER == BIG_ENDIAN ? j
1716 : REGISTER_RAW_SIZE (regnum) - 1 - j;
1717 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1718 }
1719 printf_filtered (")");
1720 printf_filtered ("\n");
1721}
1722
1723static void
1724sh_do_register (int regnum)
1725{
1726 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1727
1728 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1729 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1730
1731 /* Get the data in raw format. */
1732 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1733 printf_filtered ("*value not available*\n");
1734
1735 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1736 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1737 printf_filtered ("\t");
1738 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1739 gdb_stdout, 0, 1, 0, Val_pretty_default);
1740 printf_filtered ("\n");
1741}
1742
1743static void
1744sh_print_register (int regnum)
1745{
1746 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1747 internal_error ("Invalid register number %d\n", regnum);
1748
1749 else if (regnum > 0 && regnum < NUM_REGS)
1750 {
1751 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1752 sh_do_fp_register (regnum); /* FP regs */
1753 else
1754 sh_do_register (regnum); /* All other regs */
1755 }
1756
1757 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1758 sh_do_pseudo_register (regnum);
1759}
1760
1761void
1762sh_do_registers_info (int regnum, int fpregs)
1763{
1764 if (regnum != -1) /* do one specified register */
1765 {
1766 if (*(REGISTER_NAME (regnum)) == '\0')
1767 error ("Not a valid register for the current processor type");
1768
1769 sh_print_register (regnum);
1770 }
1771 else
1772 /* do all (or most) registers */
1773 {
1774 regnum = 0;
1775 while (regnum < NUM_REGS)
1776 {
1777 /* If the register name is empty, it is undefined for this
1778 processor, so don't display anything. */
1779 if (REGISTER_NAME (regnum) == NULL
1780 || *(REGISTER_NAME (regnum)) == '\0')
1781 {
1782 regnum++;
1783 continue;
1784 }
1785
1786 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1787 {
1788 if (fpregs)
1789 {
1790 /* true for "INFO ALL-REGISTERS" command */
1791 sh_do_fp_register (regnum); /* FP regs */
1792 regnum ++;
1793 }
1794 else
e6c42fda 1795 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1796 }
1797 else
1798 {
1799 sh_do_register (regnum); /* All other regs */
1800 regnum++;
1801 }
1802 }
1803
1804 if (fpregs)
1805 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1806 {
1807 sh_do_pseudo_register (regnum);
1808 regnum++;
1809 }
1810 }
1811}
1812
1a8629c7
MS		 1813#ifdef SVR4_SHARED_LIBS
1814
1815/* Fetch (and possibly build) an appropriate link_map_offsets structure
1816 for native i386 linux targets using the struct offsets defined in
1817 link.h (but without actual reference to that file).
1818
1819 This makes it possible to access i386-linux shared libraries from
1820 a gdb that was not built on an i386-linux host (for cross debugging).
1821 */
1822
1823struct link_map_offsets *
1824sh_linux_svr4_fetch_link_map_offsets (void)
1825{
1826 static struct link_map_offsets lmo;
1827 static struct link_map_offsets *lmp = 0;
1828
1829 if (lmp == 0)
1830 {
1831 lmp = &lmo;
1832
1833 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1834
1835 lmo.r_map_offset = 4;
1836 lmo.r_map_size = 4;
1837
1838 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1839
1840 lmo.l_addr_offset = 0;
1841 lmo.l_addr_size = 4;
1842
1843 lmo.l_name_offset = 4;
1844 lmo.l_name_size = 4;
1845
1846 lmo.l_next_offset = 12;
1847 lmo.l_next_size = 4;
1848
1849 lmo.l_prev_offset = 16;
1850 lmo.l_prev_size = 4;
1851 }
1852
1853 return lmp;
1854}
1855#endif /* SVR4_SHARED_LIBS */
1856
cc17453a
EZ		 1857static gdbarch_init_ftype sh_gdbarch_init;
1858
1859static struct gdbarch *
fba45db2 1860sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 1861{
1862 static LONGEST sh_call_dummy_words[] = {0};
1863 struct gdbarch *gdbarch;
1864 struct gdbarch_tdep *tdep;
1865 gdbarch_register_name_ftype *sh_register_name;
1866 gdbarch_store_return_value_ftype *sh_store_return_value;
1867 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1868
1869 /* Find a candidate among the list of pre-declared architectures. */
1870 arches = gdbarch_list_lookup_by_info (arches, &info);
1871 if (arches != NULL)
1872 return arches->gdbarch;
1873
1874 /* None found, create a new architecture from the information
1875 provided. */
1876 tdep = XMALLOC (struct gdbarch_tdep);
1877 gdbarch = gdbarch_alloc (&info, tdep);
1878
1879 /* Initialize the register numbers that are not common to all the
1880 variants to -1, if necessary thse will be overwritten in the case
1881 statement below. */
1882 tdep->FPUL_REGNUM = -1;
1883 tdep->FPSCR_REGNUM = -1;
c62a7c7b 1884 tdep->SR_REGNUM = 22;
cc17453a 1885 tdep->DSR_REGNUM = -1;
e6c42fda 1886 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 1887 tdep->A0G_REGNUM = -1;
1888 tdep->A0_REGNUM = -1;
1889 tdep->A1G_REGNUM = -1;
1890 tdep->A1_REGNUM = -1;
1891 tdep->M0_REGNUM = -1;
1892 tdep->M1_REGNUM = -1;
1893 tdep->X0_REGNUM = -1;
1894 tdep->X1_REGNUM = -1;
1895 tdep->Y0_REGNUM = -1;
1896 tdep->Y1_REGNUM = -1;
1897 tdep->MOD_REGNUM = -1;
1898 tdep->RS_REGNUM = -1;
1899 tdep->RE_REGNUM = -1;
1900 tdep->SSR_REGNUM = -1;
1901 tdep->SPC_REGNUM = -1;
53116e27 1902 tdep->DR0_REGNUM = -1;
e6c42fda 1903 tdep->DR_LAST_REGNUM = -1;
53116e27 1904 tdep->FV0_REGNUM = -1;
e6c42fda 1905 tdep->FV_LAST_REGNUM = -1;
a38d2a54 1906
cc17453a 1907 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 1908 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1909 set_gdbarch_max_register_raw_size (gdbarch, 4);
1910 set_gdbarch_max_register_virtual_size (gdbarch, 4);
a38d2a54
EZ		 1911 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1912 set_gdbarch_num_regs (gdbarch, 59);
1913 set_gdbarch_sp_regnum (gdbarch, 15);
1914 set_gdbarch_fp_regnum (gdbarch, 14);
1915 set_gdbarch_pc_regnum (gdbarch, 16);
1916 set_gdbarch_register_size (gdbarch, 4);
1917 set_gdbarch_register_bytes (gdbarch, NUM_REGS * 4);
1918 set_gdbarch_fetch_pseudo_register (gdbarch, sh_fetch_pseudo_register);
1919 set_gdbarch_store_pseudo_register (gdbarch, sh_store_pseudo_register);
e6c42fda 1920 print_sh_insn = gdb_print_insn_sh;
cc17453a
EZ		 1921
1922 switch (info.bfd_arch_info->mach)
8db62801 1923 {
cc17453a
EZ		 1924 case bfd_mach_sh:
1925 sh_register_name = sh_sh_register_name;
1926 sh_show_regs = sh_generic_show_regs;
1927 sh_store_return_value = sh_default_store_return_value;
1928 sh_register_virtual_type = sh_default_register_virtual_type;
1929 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1930 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1931 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1932 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1933 break;
1934 case bfd_mach_sh2:
1935 sh_register_name = sh_sh_register_name;
1936 sh_show_regs = sh_generic_show_regs;
1937 sh_store_return_value = sh_default_store_return_value;
1938 sh_register_virtual_type = sh_default_register_virtual_type;
1939 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1940 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1941 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1942 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1943 break;
1944 case bfd_mach_sh_dsp:
1945 sh_register_name = sh_sh_dsp_register_name;
1946 sh_show_regs = sh_dsp_show_regs;
1947 sh_store_return_value = sh_default_store_return_value;
1948 sh_register_virtual_type = sh_default_register_virtual_type;
1949 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1950 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1951 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1952 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1953 tdep->DSR_REGNUM = 24;
1954 tdep->A0G_REGNUM = 25;
1955 tdep->A0_REGNUM = 26;
1956 tdep->A1G_REGNUM = 27;
1957 tdep->A1_REGNUM = 28;
1958 tdep->M0_REGNUM = 29;
1959 tdep->M1_REGNUM = 30;
1960 tdep->X0_REGNUM = 31;
1961 tdep->X1_REGNUM = 32;
1962 tdep->Y0_REGNUM = 33;
1963 tdep->Y1_REGNUM = 34;
1964 tdep->MOD_REGNUM = 40;
1965 tdep->RS_REGNUM = 43;
1966 tdep->RE_REGNUM = 44;
1967 break;
1968 case bfd_mach_sh3:
1969 sh_register_name = sh_sh3_register_name;
1970 sh_show_regs = sh3_show_regs;
1971 sh_store_return_value = sh_default_store_return_value;
1972 sh_register_virtual_type = sh_default_register_virtual_type;
1973 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1974 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1975 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1976 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1977 tdep->SSR_REGNUM = 41;
1978 tdep->SPC_REGNUM = 42;
1979 break;
1980 case bfd_mach_sh3e:
1981 sh_register_name = sh_sh3e_register_name;
1982 sh_show_regs = sh3e_show_regs;
1983 sh_store_return_value = sh3e_sh4_store_return_value;
1984 sh_register_virtual_type = sh_sh3e_register_virtual_type;
1985 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 1986 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1987 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1988 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1989 set_gdbarch_fp0_regnum (gdbarch, 25);
1990 tdep->FPUL_REGNUM = 23;
1991 tdep->FPSCR_REGNUM = 24;
e6c42fda 1992 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 1993 tdep->SSR_REGNUM = 41;
1994 tdep->SPC_REGNUM = 42;
1995 break;
1996 case bfd_mach_sh3_dsp:
1997 sh_register_name = sh_sh3_dsp_register_name;
1998 sh_show_regs = sh3_dsp_show_regs;
1999 sh_store_return_value = sh_default_store_return_value;
2000 sh_register_virtual_type = sh_default_register_virtual_type;
2001 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2002 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2003 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2004 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2005 tdep->DSR_REGNUM = 24;
2006 tdep->A0G_REGNUM = 25;
2007 tdep->A0_REGNUM = 26;
2008 tdep->A1G_REGNUM = 27;
2009 tdep->A1_REGNUM = 28;
2010 tdep->M0_REGNUM = 29;
2011 tdep->M1_REGNUM = 30;
2012 tdep->X0_REGNUM = 31;
2013 tdep->X1_REGNUM = 32;
2014 tdep->Y0_REGNUM = 33;
2015 tdep->Y1_REGNUM = 34;
2016 tdep->MOD_REGNUM = 40;
2017 tdep->RS_REGNUM = 43;
2018 tdep->RE_REGNUM = 44;
2019 tdep->SSR_REGNUM = 41;
2020 tdep->SPC_REGNUM = 42;
2021 break;
2022 case bfd_mach_sh4:
53116e27
EZ		 2023 sh_register_name = sh_sh4_register_name;
2024 sh_show_regs = sh4_show_regs;
cc17453a 2025 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 2026 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a
EZ		 2027 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
2028 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 2029 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
2030 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
2031 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
2032 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2033 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
2034 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
fb409745
EZ		 2035 set_gdbarch_register_convert_to_raw (gdbarch, sh_sh4_register_convert_to_raw);
2036 set_gdbarch_register_convert_to_virtual (gdbarch, sh_sh4_register_convert_to_virtual);
2037 set_gdbarch_register_convertible (gdbarch, sh_sh4_register_convertible);
cc17453a
EZ		 2038 tdep->FPUL_REGNUM = 23;
2039 tdep->FPSCR_REGNUM = 24;
e6c42fda 2040 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2041 tdep->SSR_REGNUM = 41;
2042 tdep->SPC_REGNUM = 42;
53116e27 2043 tdep->DR0_REGNUM = 59;
e6c42fda 2044 tdep->DR_LAST_REGNUM = 66;
53116e27 2045 tdep->FV0_REGNUM = 67;
e6c42fda 2046 tdep->FV_LAST_REGNUM = 70;
cc17453a
EZ		 2047 break;
2048 default:
2049 sh_register_name = sh_generic_register_name;
2050 sh_show_regs = sh_generic_show_regs;
2051 sh_store_return_value = sh_default_store_return_value;
2052 sh_register_virtual_type = sh_default_register_virtual_type;
2053 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2054 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2055 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2056 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 2057 break;
8db62801 2058 }
cc17453a
EZ		 2059
2060 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2061 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2062 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
2063 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
2064 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2065 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2066
cc17453a 2067 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 2068 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
2069
cc17453a
EZ		 2070 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2071 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2072 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2073 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2074 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2075 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2076 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/
cc17453a
EZ		 2077
2078 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2079 set_gdbarch_call_dummy_length (gdbarch, 0);
2080 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2081 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2082 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
2083 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2084 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2085 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2086 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
2087 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
2088 set_gdbarch_call_dummy_p (gdbarch, 1);
2089 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2090 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
2091 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2092 set_gdbarch_coerce_float_to_double (gdbarch,
2093 sh_coerce_float_to_double);
2094
2095 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
2096 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
2097 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2098 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
2099
2100 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
2101 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
2102 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2103 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2104 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
2105 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2106 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2107 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2108 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2109 set_gdbarch_function_start_offset (gdbarch, 0);
2110 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2111
2112 set_gdbarch_frame_args_skip (gdbarch, 0);
2113 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2114 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
2115 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
2116 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2117 set_gdbarch_frame_args_address (gdbarch, sh_frame_args_address);
2118 set_gdbarch_frame_locals_address (gdbarch, sh_frame_locals_address);
2119 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2120 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2121 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2122 set_gdbarch_ieee_float (gdbarch, 1);
a38d2a54 2123 tm_print_insn = print_sh_insn;
cc17453a
EZ		 2124
2125 return gdbarch;
8db62801
EZ		 2126}
2127
c906108c 2128void
fba45db2 2129_initialize_sh_tdep (void)
c906108c
SS		 2130{
2131 struct cmd_list_element *c;
cc17453a
EZ		 2132
2133 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
c906108c 2134
53116e27 2135 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2136}
GDB Binutils - Deliverables
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