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Demangling fixes
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
b4a20239
AC		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
3 Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
c906108c 40
cc17453a
EZ		 41#undef XMALLOC
42#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
43
44static gdbarch_register_raw_size_ftype sh_register_raw_size;
45static gdbarch_register_virtual_size_ftype sh_register_virtual_size;
46static gdbarch_register_virtual_type_ftype sh_register_virtual_type;
47static gdbarch_register_byte_ftype sh_register_byte;
48static gdbarch_breakpoint_from_pc_ftype sh_breakpoint_from_pc;
49static gdbarch_frame_chain_ftype sh_frame_chain;
50static gdbarch_frame_saved_pc_ftype sh_frame_saved_pc;
51static gdbarch_skip_prologue_ftype sh_skip_prologue;
52static gdbarch_frame_init_saved_regs_ftype sh_nofp_frame_init_saved_regs;
53static gdbarch_frame_init_saved_regs_ftype sh_fp_frame_init_saved_regs;
54static gdbarch_extract_return_value_ftype sh_extract_return_value;
55static gdbarch_extract_struct_value_address_ftype sh_extract_struct_value_address;
56static gdbarch_use_struct_convention_ftype sh_use_struct_convention;
57static gdbarch_init_extra_frame_info_ftype sh_init_extra_frame_info;
58static gdbarch_store_struct_return_ftype sh_store_struct_return;
59static gdbarch_push_arguments_ftype sh_push_arguments;
60static gdbarch_push_return_address_ftype sh_push_return_address;
61static gdbarch_pop_frame_ftype sh_pop_frame;
62static gdbarch_saved_pc_after_call_ftype sh_saved_pc_after_call;
63
64static gdbarch_register_name_ftype sh_generic_register_name;
65static gdbarch_register_name_ftype sh_sh_register_name;
66static gdbarch_register_name_ftype sh_sh3_register_name;
67static gdbarch_register_name_ftype sh_sh3e_register_name;
68static gdbarch_register_name_ftype sh_sh_dsp_register_name;
69static gdbarch_register_name_ftype sh_sh3_dsp_register_name;
70
71static gdbarch_frame_args_address_ftype sh_frame_args_address;
72static gdbarch_frame_locals_address_ftype sh_frame_locals_address;
73static gdbarch_coerce_float_to_double_ftype sh_coerce_float_to_double;
74static gdbarch_store_return_value_ftype sh_default_store_return_value;
75static gdbarch_store_return_value_ftype sh3e_sh4_store_return_value;
76
77static gdbarch_register_byte_ftype sh_register_byte;
78static gdbarch_register_raw_size_ftypesh_register_raw_size;
79static gdbarch_register_virtual_size_ftype sh_register_virtual_size;
80static gdbarch_register_virtual_type_ftype sh_sh3e_register_virtual_type;
81static gdbarch_register_virtual_type_ftype sh_default_register_virtual_type;
82
83static void sh_generic_show_regs (char *, int);
84static void sh3_show_regs (char *, int);
85static void sh3e_show_regs (char *, int);
86static void sh3_dsp_show_regs (char *, int);
87static void sh_dsp_show_regs (char *, int);
88static void sh4_show_regs (char *, int);
89
90void (*sh_show_regs) (char *, int);
91
92/* Define other aspects of the stack frame.
93 we keep a copy of the worked out return pc lying around, since it
94 is a useful bit of info */
95
96struct frame_extra_info
97{
98 CORE_ADDR return_pc;
99 int leaf_function;
100 int f_offset;
63978407 101};
c906108c 102
cc17453a 103#if 0
091be84d
CF		 104#ifdef _WIN32_WCE
105char **sh_register_names = sh3_reg_names;
106#else
c906108c 107char **sh_register_names = sh_generic_reg_names;
091be84d 108#endif
cc17453a 109#endif
c906108c 110
cc17453a
EZ		 111static char *
112sh_generic_register_name (int reg_nr)
c5aa993b 113{
cc17453a 114 static char *register_names[] =
c5aa993b 115 {
cc17453a
EZ		 116 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
117 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
118 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
119 "fpul", "fpscr",
120 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
121 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
122 "ssr", "spc",
123 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
124 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
125 };
126 if (reg_nr < 0)
127 return NULL;
128 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
129 return NULL;
130 return register_names[reg_nr];
131}
132
133static char *
134sh_sh_register_name (int reg_nr)
135{
136 static char *register_names[] =
63978407 137 {
cc17453a
EZ		 138 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
139 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
140 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
141 "", "",
142 "", "", "", "", "", "", "", "",
143 "", "", "", "", "", "", "", "",
144 "", "",
145 "", "", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "",
147 };
148 if (reg_nr < 0)
149 return NULL;
150 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
151 return NULL;
152 return register_names[reg_nr];
153}
154
155static char *
156sh_sh3_register_name (int reg_nr)
157{
158 static char *register_names[] =
c5aa993b 159 {
cc17453a
EZ		 160 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
162 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
163 "", "",
164 "", "", "", "", "", "", "", "",
165 "", "", "", "", "", "", "", "",
166 "ssr", "spc",
167 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
168 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
169 };
170 if (reg_nr < 0)
171 return NULL;
172 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
173 return NULL;
174 return register_names[reg_nr];
175}
176
177static char *
178sh_sh3e_register_name (int reg_nr)
179{
180 static char *register_names[] =
63978407 181 {
cc17453a
EZ		 182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
184 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
185 "fpul", "fpscr",
186 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
187 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
188 "ssr", "spc",
189 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
190 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
191 };
192 if (reg_nr < 0)
193 return NULL;
194 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
195 return NULL;
196 return register_names[reg_nr];
197}
198
199static char *
200sh_sh_dsp_register_name (int reg_nr)
201{
202 static char *register_names[] =
c5aa993b 203 {
cc17453a
EZ		 204 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
205 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
206 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
207 "", "dsr",
208 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
209 "y0", "y1", "", "", "", "", "", "mod",
210 "", "",
211 "rs", "re", "", "", "", "", "", "",
212 "", "", "", "", "", "", "", "",
213 };
214 if (reg_nr < 0)
215 return NULL;
216 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
217 return NULL;
218 return register_names[reg_nr];
219}
220
221static char *
222sh_sh3_dsp_register_name (int reg_nr)
223{
224 static char *register_names[] =
c5aa993b 225 {
cc17453a
EZ		 226 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
227 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
228 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
229 "", "dsr",
230 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
231 "y0", "y1", "", "", "", "", "", "mod",
232 "ssr", "spc",
233 "rs", "re", "", "", "", "", "", "",
234 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
235 "", "", "", "", "", "", "", "",
236 };
237 if (reg_nr < 0)
238 return NULL;
239 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
240 return NULL;
241 return register_names[reg_nr];
242}
243
244static unsigned char *
245sh_breakpoint_from_pc (pcptr, lenptr)
246 CORE_ADDR *pcptr;
247 int *lenptr;
248{
249 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
250 static unsigned char breakpoint[] = {0xc3, 0xc3};
251
252 *lenptr = sizeof (breakpoint);
253 return breakpoint;
254}
c906108c
SS		 255
256/* Prologue looks like
c5aa993b
JM		 257 [mov.l <regs>,@-r15]...
258 [sts.l pr,@-r15]
259 [mov.l r14,@-r15]
260 [mov r15,r14]
8db62801
EZ		 261
262 Actually it can be more complicated than this. For instance, with
263 newer gcc's:
264
265 mov.l r14,@-r15
266 add #-12,r15
267 mov r15,r14
268 mov r4,r1
269 mov r5,r2
270 mov.l r6,@(4,r14)
271 mov.l r7,@(8,r14)
272 mov.b r1,@r14
273 mov r14,r1
274 mov r14,r1
275 add #2,r1
276 mov.w r2,@r1
277
c5aa993b 278 */
c906108c 279
8db62801
EZ		 280/* STS.L PR,@-r15 0100111100100010
281 r15-4-->r15, PR-->(r15) */
c906108c 282#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 283
284/* MOV.L Rm,@-r15 00101111mmmm0110
285 r15-4-->r15, Rm-->(R15) */
c906108c 286#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 287
c906108c 288#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 289
290/* MOV r15,r14 0110111011110011
291 r15-->r14 */
c906108c 292#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 293
294/* ADD #imm,r15 01111111iiiiiiii
295 r15+imm-->r15 */
c906108c 296#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 297
c906108c
SS		 298#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 300
301/* ADD r3,r15 0011111100111100
302 r15+r3-->r15 */
c906108c 303#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 304
305/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
306 or
307 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
308 or
309 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 310#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 311
8db62801
EZ		 312/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
313 or
314 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
315 or
316 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
317 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
318#define IS_ARG_MOV(x) \
319(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 320 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
321 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 322
323/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
324 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
325#define IS_MOV_R14(x) \
cc17453a 326 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 327
328#define FPSCR_SZ (1 << 20)
c906108c 329
c906108c
SS		 330/* Skip any prologue before the guts of a function */
331
8db62801
EZ		 332/* Skip the prologue using the debug information. If this fails we'll
333 fall back on the 'guess' method below. */
334static CORE_ADDR
335after_prologue (pc)
336 CORE_ADDR pc;
337{
338 struct symtab_and_line sal;
339 CORE_ADDR func_addr, func_end;
340
341 /* If we can not find the symbol in the partial symbol table, then
342 there is no hope we can determine the function's start address
343 with this code. */
344 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
345 return 0;
346
347 /* Get the line associated with FUNC_ADDR. */
348 sal = find_pc_line (func_addr, 0);
349
350 /* There are only two cases to consider. First, the end of the source line
351 is within the function bounds. In that case we return the end of the
352 source line. Second is the end of the source line extends beyond the
353 bounds of the current function. We need to use the slow code to
354 examine instructions in that case. */
355 if (sal.end < func_end)
356 return sal.end;
357 else
358 return 0;
359}
360
361/* Here we look at each instruction in the function, and try to guess
362 where the prologue ends. Unfortunately this is not always
363 accurate. */
364static CORE_ADDR
365skip_prologue_hard_way (start_pc)
c906108c
SS		 366 CORE_ADDR start_pc;
367{
2bfa91ee 368 CORE_ADDR here, end;
8db62801 369 int updated_fp = 0;
2bfa91ee
EZ		 370
371 if (!start_pc)
372 return 0;
373
374 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 375 {
2bfa91ee
EZ		 376 int w = read_memory_integer (here, 2);
377 here += 2;
378 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801
EZ		 379 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
380 || IS_ARG_MOV (w) || IS_MOV_R14 (w))
2bfa91ee
EZ		 381 {
382 start_pc = here;
2bfa91ee 383 }
8db62801
EZ		 384 else if (IS_MOV_SP_FP (w))
385 {
386 start_pc = here;
387 updated_fp = 1;
388 }
389 else
390 /* Don't bail out yet, if we are before the copy of sp. */
391 if (updated_fp)
392 break;
c906108c
SS		 393 }
394
395 return start_pc;
396}
397
cc17453a 398static CORE_ADDR
8db62801
EZ		 399sh_skip_prologue (pc)
400 CORE_ADDR pc;
401{
402 CORE_ADDR post_prologue_pc;
403
404 /* See if we can determine the end of the prologue via the symbol table.
405 If so, then return either PC, or the PC after the prologue, whichever
406 is greater. */
407
408 post_prologue_pc = after_prologue (pc);
409
410 /* If after_prologue returned a useful address, then use it. Else
411 fall back on the instruction skipping code. */
412 if (post_prologue_pc != 0)
413 return max (pc, post_prologue_pc);
414 else
415 return (skip_prologue_hard_way (pc));
416}
417
cc17453a
EZ		 418/* Immediately after a function call, return the saved pc.
419 Can't always go through the frames for this because on some machines
420 the new frame is not set up until the new function executes
421 some instructions.
422
423 The return address is the value saved in the PR register + 4 */
424static CORE_ADDR
425sh_saved_pc_after_call (frame)
426 struct frame_info *frame;
427{
428 return (ADDR_BITS_REMOVE(read_register(PR_REGNUM)));
429}
430
431/* Should call_function allocate stack space for a struct return? */
432static int
433sh_use_struct_convention (gcc_p, type)
434 int gcc_p;
435 struct type *type;
436{
437 return (TYPE_LENGTH (type) > 1);
438}
439
440/* Store the address of the place in which to copy the structure the
441 subroutine will return. This is called from call_function.
442
443 We store structs through a pointer passed in R0 */
444static void
445sh_store_struct_return (addr, sp)
446 CORE_ADDR addr;
447 CORE_ADDR sp;
448{
449 write_register (STRUCT_RETURN_REGNUM, (addr));
450}
c906108c 451
cc17453a
EZ		 452/* Disassemble an instruction. */
453static int
c906108c
SS		 454gdb_print_insn_sh (memaddr, info)
455 bfd_vma memaddr;
456 disassemble_info *info;
457{
458 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
459 return print_insn_sh (memaddr, info);
460 else
461 return print_insn_shl (memaddr, info);
462}
463
464/* Given a GDB frame, determine the address of the calling function's frame.
465 This will be used to create a new GDB frame struct, and then
466 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
467
468 For us, the frame address is its stack pointer value, so we look up
469 the function prologue to determine the caller's sp value, and return it. */
cc17453a 470static CORE_ADDR
c906108c
SS		 471sh_frame_chain (frame)
472 struct frame_info *frame;
473{
474 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
475 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 476 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 477 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 478 else
479 return 0;
480}
481
482/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
483 we might want to do here is to check REGNUM against the clobber mask, and
484 somehow flag it as invalid if it isn't saved on the stack somewhere. This
485 would provide a graceful failure mode when trying to get the value of
486 caller-saves registers for an inner frame. */
487
cc17453a 488static CORE_ADDR
c906108c
SS		 489sh_find_callers_reg (fi, regnum)
490 struct frame_info *fi;
491 int regnum;
492{
c906108c
SS		 493 for (; fi; fi = fi->next)
494 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
495 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 496 that's where the previous routine appears to have done a call from. */
c906108c 497 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 498 else
c906108c 499 {
cc17453a 500 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 501 if (!fi->pc)
502 return 0;
cc17453a
EZ		 503 if (fi->saved_regs[regnum] != 0)
504 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 505 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 506 }
507 return read_register (regnum);
508}
509
510/* Put here the code to store, into a struct frame_saved_regs, the
511 addresses of the saved registers of frame described by FRAME_INFO.
512 This includes special registers such as pc and fp saved in special
513 ways in the stack frame. sp is even more special: the address we
514 return for it IS the sp for the next frame. */
cc17453a
EZ		 515static void
516sh_nofp_frame_init_saved_regs (fi)
c906108c 517 struct frame_info *fi;
c906108c
SS		 518{
519 int where[NUM_REGS];
520 int rn;
521 int have_fp = 0;
522 int depth;
523 int pc;
524 int opc;
525 int insn;
526 int r3_val = 0;
c5aa993b 527 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 528
529 if (fi->saved_regs == NULL)
530 frame_saved_regs_zalloc (fi);
531 else
532 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
533
534 if (dummy_regs)
535 {
536 /* DANGER! This is ONLY going to work if the char buffer format of
537 the saved registers is byte-for-byte identical to the
538 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
539 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
540 return;
541 }
542
543 fi->extra_info->leaf_function = 1;
544 fi->extra_info->f_offset = 0;
545
546 for (rn = 0; rn < NUM_REGS; rn++)
547 where[rn] = -1;
548
549 depth = 0;
550
551 /* Loop around examining the prologue insns until we find something
552 that does not appear to be part of the prologue. But give up
553 after 20 of them, since we're getting silly then. */
554
555 pc = get_pc_function_start (fi->pc);
556 if (!pc)
557 {
558 fi->pc = 0;
559 return;
560 }
561
562 for (opc = pc + (2 * 28); pc < opc; pc += 2)
563 {
564 insn = read_memory_integer (pc, 2);
565 /* See where the registers will be saved to */
566 if (IS_PUSH (insn))
567 {
568 rn = GET_PUSHED_REG (insn);
569 where[rn] = depth;
570 depth += 4;
571 }
572 else if (IS_STS (insn))
573 {
574 where[PR_REGNUM] = depth;
575 /* If we're storing the pr then this isn't a leaf */
576 fi->extra_info->leaf_function = 0;
577 depth += 4;
578 }
579 else if (IS_MOV_R3 (insn))
580 {
581 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
582 }
583 else if (IS_SHLL_R3 (insn))
584 {
585 r3_val <<= 1;
586 }
587 else if (IS_ADD_R3SP (insn))
588 {
589 depth += -r3_val;
590 }
591 else if (IS_ADD_SP (insn))
592 {
593 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
594 }
595 else if (IS_MOV_SP_FP (insn))
596 break;
597#if 0 /* This used to just stop when it found an instruction that
598 was not considered part of the prologue. Now, we just
599 keep going looking for likely instructions. */
600 else
601 break;
602#endif
603 }
604
605 /* Now we know how deep things are, we can work out their addresses */
606
607 for (rn = 0; rn < NUM_REGS; rn++)
608 {
609 if (where[rn] >= 0)
610 {
611 if (rn == FP_REGNUM)
612 have_fp = 1;
c906108c 613
cc17453a
EZ		 614 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
615 }
616 else
617 {
618 fi->saved_regs[rn] = 0;
619 }
620 }
621
622 if (have_fp)
623 {
624 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
625 }
626 else
627 {
628 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
629 }
630
631 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
632 /* Work out the return pc - either from the saved pr or the pr
633 value */
634}
635
636static void
637sh_fp_frame_init_saved_regs (fi)
638 struct frame_info *fi;
639{
640 int where[NUM_REGS];
641 int rn;
642 int have_fp = 0;
643 int depth;
644 int pc;
645 int opc;
646 int insn;
647 int r3_val = 0;
648 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
649
650 if (fi->saved_regs == NULL)
651 frame_saved_regs_zalloc (fi);
652 else
653 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
654
c906108c
SS		 655 if (dummy_regs)
656 {
657 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 658 the saved registers is byte-for-byte identical to the
659 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 660 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 661 return;
662 }
663
cc17453a
EZ		 664 fi->extra_info->leaf_function = 1;
665 fi->extra_info->f_offset = 0;
c906108c
SS		 666
667 for (rn = 0; rn < NUM_REGS; rn++)
668 where[rn] = -1;
669
670 depth = 0;
671
672 /* Loop around examining the prologue insns until we find something
673 that does not appear to be part of the prologue. But give up
674 after 20 of them, since we're getting silly then. */
675
2bfa91ee
EZ		 676 pc = get_pc_function_start (fi->pc);
677 if (!pc)
c906108c 678 {
2bfa91ee
EZ		 679 fi->pc = 0;
680 return;
681 }
682
683 for (opc = pc + (2 * 28); pc < opc; pc += 2)
684 {
685 insn = read_memory_integer (pc, 2);
c906108c
SS		 686 /* See where the registers will be saved to */
687 if (IS_PUSH (insn))
688 {
c906108c
SS		 689 rn = GET_PUSHED_REG (insn);
690 where[rn] = depth;
c906108c
SS		 691 depth += 4;
692 }
693 else if (IS_STS (insn))
694 {
c906108c 695 where[PR_REGNUM] = depth;
c906108c 696 /* If we're storing the pr then this isn't a leaf */
cc17453a 697 fi->extra_info->leaf_function = 0;
c906108c
SS		 698 depth += 4;
699 }
700 else if (IS_MOV_R3 (insn))
701 {
702 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 703 }
704 else if (IS_SHLL_R3 (insn))
705 {
706 r3_val <<= 1;
c906108c
SS		 707 }
708 else if (IS_ADD_R3SP (insn))
709 {
710 depth += -r3_val;
c906108c
SS		 711 }
712 else if (IS_ADD_SP (insn))
713 {
c906108c 714 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 715 }
716 else if (IS_FMOV (insn))
717 {
cc17453a 718 if (read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 719 {
720 depth += 8;
721 }
722 else
723 {
724 depth += 4;
725 }
726 }
2bfa91ee
EZ		 727 else if (IS_MOV_SP_FP (insn))
728 break;
729#if 0 /* This used to just stop when it found an instruction that
730 was not considered part of the prologue. Now, we just
731 keep going looking for likely instructions. */
c906108c
SS		 732 else
733 break;
2bfa91ee 734#endif
c906108c
SS		 735 }
736
737 /* Now we know how deep things are, we can work out their addresses */
738
739 for (rn = 0; rn < NUM_REGS; rn++)
740 {
741 if (where[rn] >= 0)
742 {
743 if (rn == FP_REGNUM)
744 have_fp = 1;
745
cc17453a 746 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 747 }
748 else
749 {
cc17453a 750 fi->saved_regs[rn] = 0;
c906108c
SS		 751 }
752 }
753
754 if (have_fp)
755 {
cc17453a 756 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 757 }
758 else
759 {
cc17453a 760 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 761 }
762
cc17453a 763 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 764 /* Work out the return pc - either from the saved pr or the pr
765 value */
766}
767
cc17453a
EZ		 768/* Initialize the extra info saved in a FRAME */
769static void
c906108c
SS		 770sh_init_extra_frame_info (fromleaf, fi)
771 int fromleaf;
772 struct frame_info *fi;
773{
cc17453a
EZ		 774
775 fi->extra_info = (struct frame_extra_info *)
776 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 777
778 if (fi->next)
779 fi->pc = FRAME_SAVED_PC (fi->next);
780
781 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
782 {
783 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 784 by assuming it's always FP. */
785 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
786 SP_REGNUM);
cc17453a
EZ		 787 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
788 PC_REGNUM);
789 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
790 fi->extra_info->leaf_function = 0;
c906108c
SS		 791 return;
792 }
793 else
794 {
cc17453a
EZ		 795 FRAME_INIT_SAVED_REGS (fi);
796 fi->extra_info->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
c906108c
SS		 797 }
798}
799
cc17453a
EZ		 800/* Extract from an array REGBUF containing the (raw) register state
801 the address in which a function should return its structure value,
802 as a CORE_ADDR (or an expression that can be used as one). */
803CORE_ADDR
804static sh_extract_struct_value_address (regbuf)
805 char *regbuf;
806{
807 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
808}
809
810static CORE_ADDR
811sh_frame_saved_pc (frame)
812 struct frame_info *frame;
813{
814 return ((frame)->extra_info->return_pc);
815}
816
817static CORE_ADDR
818sh_frame_args_address (fi)
819 struct frame_info *fi;
820{
821 return (fi)->frame;
822}
823
824static CORE_ADDR
825sh_frame_locals_address (fi)
826 struct frame_info *fi;
827{
828 return (fi)->frame;
829}
830
c906108c
SS		 831/* Discard from the stack the innermost frame,
832 restoring all saved registers. */
cc17453a 833static void
c906108c
SS		 834sh_pop_frame ()
835{
836 register struct frame_info *frame = get_current_frame ();
837 register CORE_ADDR fp;
838 register int regnum;
c906108c
SS		 839
840 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
841 generic_pop_dummy_frame ();
842 else
c5aa993b
JM		 843 {
844 fp = FRAME_FP (frame);
cc17453a 845 FRAME_INIT_SAVED_REGS (frame);
c906108c 846
c5aa993b
JM		 847 /* Copy regs from where they were saved in the frame */
848 for (regnum = 0; regnum < NUM_REGS; regnum++)
cc17453a
EZ		 849 if (frame->saved_regs[regnum])
850 write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 851
cc17453a 852 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 853 write_register (SP_REGNUM, fp + 4);
854 }
c906108c
SS		 855 flush_cached_frames ();
856}
857
858/* Function: push_arguments
859 Setup the function arguments for calling a function in the inferior.
860
861 On the Hitachi SH architecture, there are four registers (R4 to R7)
862 which are dedicated for passing function arguments. Up to the first
863 four arguments (depending on size) may go into these registers.
864 The rest go on the stack.
865
866 Arguments that are smaller than 4 bytes will still take up a whole
867 register or a whole 32-bit word on the stack, and will be
868 right-justified in the register or the stack word. This includes
869 chars, shorts, and small aggregate types.
870
871 Arguments that are larger than 4 bytes may be split between two or
872 more registers. If there are not enough registers free, an argument
873 may be passed partly in a register (or registers), and partly on the
874 stack. This includes doubles, long longs, and larger aggregates.
875 As far as I know, there is no upper limit to the size of aggregates
876 that will be passed in this way; in other words, the convention of
877 passing a pointer to a large aggregate instead of a copy is not used.
878
879 An exceptional case exists for struct arguments (and possibly other
880 aggregates such as arrays) if the size is larger than 4 bytes but
881 not a multiple of 4 bytes. In this case the argument is never split
882 between the registers and the stack, but instead is copied in its
883 entirety onto the stack, AND also copied into as many registers as
884 there is room for. In other words, space in registers permitting,
885 two copies of the same argument are passed in. As far as I can tell,
886 only the one on the stack is used, although that may be a function
887 of the level of compiler optimization. I suspect this is a compiler
888 bug. Arguments of these odd sizes are left-justified within the
889 word (as opposed to arguments smaller than 4 bytes, which are
890 right-justified).
c5aa993b 891
c906108c
SS		 892 If the function is to return an aggregate type such as a struct, it
893 is either returned in the normal return value register R0 (if its
894 size is no greater than one byte), or else the caller must allocate
895 space into which the callee will copy the return value (if the size
896 is greater than one byte). In this case, a pointer to the return
897 value location is passed into the callee in register R2, which does
898 not displace any of the other arguments passed in via registers R4
899 to R7. */
900
cc17453a 901static CORE_ADDR
c906108c
SS		 902sh_push_arguments (nargs, args, sp, struct_return, struct_addr)
903 int nargs;
904 value_ptr *args;
905 CORE_ADDR sp;
906 unsigned char struct_return;
907 CORE_ADDR struct_addr;
908{
909 int stack_offset, stack_alloc;
910 int argreg;
911 int argnum;
912 struct type *type;
913 CORE_ADDR regval;
914 char *val;
915 char valbuf[4];
916 int len;
917 int odd_sized_struct;
918
919 /* first force sp to a 4-byte alignment */
920 sp = sp & ~3;
921
922 /* The "struct return pointer" pseudo-argument has its own dedicated
923 register */
924 if (struct_return)
c5aa993b 925 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 926
927 /* Now make sure there's space on the stack */
cc17453a 928 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 929 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
930 sp -= stack_alloc; /* make room on stack for args */
c906108c 931
c906108c
SS		 932 /* Now load as many as possible of the first arguments into
933 registers, and push the rest onto the stack. There are 16 bytes
934 in four registers available. Loop thru args from first to last. */
935
936 argreg = ARG0_REGNUM;
937 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
938 {
939 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 940 len = TYPE_LENGTH (type);
941 memset (valbuf, 0, sizeof (valbuf));
c906108c 942 if (len < 4)
cc17453a
EZ		 943 {
944 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 945 memcpy (valbuf + (4 - len),
946 (char *) VALUE_CONTENTS (args[argnum]), len);
947 val = valbuf;
948 }
c906108c 949 else
c5aa993b 950 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 951
952 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 953 odd_sized_struct = 1; /* such structs go entirely on stack */
954 else
c906108c
SS		 955 odd_sized_struct = 0;
956 while (len > 0)
957 {
958 if (argreg > ARGLAST_REGNUM || odd_sized_struct)
c5aa993b 959 { /* must go on the stack */
c906108c
SS		 960 write_memory (sp + stack_offset, val, 4);
961 stack_offset += 4;
962 }
963 /* NOTE WELL!!!!! This is not an "else if" clause!!!
964 That's because some *&^%$ things get passed on the stack
965 AND in the registers! */
966 if (argreg <= ARGLAST_REGNUM)
c5aa993b
JM		 967 { /* there's room in a register */
968 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 969 write_register (argreg++, regval);
970 }
971 /* Store the value 4 bytes at a time. This means that things
972 larger than 4 bytes may go partly in registers and partly
973 on the stack. */
c5aa993b
JM		 974 len -= REGISTER_RAW_SIZE (argreg);
975 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 976 }
977 }
978 return sp;
979}
980
981/* Function: push_return_address (pc)
982 Set up the return address for the inferior function call.
983 Needed for targets where we don't actually execute a JSR/BSR instruction */
984
cc17453a 985static CORE_ADDR
c906108c
SS		 986sh_push_return_address (pc, sp)
987 CORE_ADDR pc;
988 CORE_ADDR sp;
989{
990 write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
991 return sp;
992}
993
994/* Function: fix_call_dummy
995 Poke the callee function's address into the destination part of
996 the CALL_DUMMY. The address is actually stored in a data word
997 following the actualy CALL_DUMMY instructions, which will load
998 it into a register using PC-relative addressing. This function
999 expects the CALL_DUMMY to look like this:
1000
c5aa993b
JM		 1001 mov.w @(2,PC), R8
1002 jsr @R8
1003 nop
1004 trap
1005 <destination>
1006 */
c906108c
SS		 1007
1008#if 0
1009void
1010sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p)
1011 char *dummy;
1012 CORE_ADDR pc;
1013 CORE_ADDR fun;
1014 int nargs;
1015 value_ptr *args;
1016 struct type *type;
1017 int gcc_p;
1018{
1019 *(unsigned long *) (dummy + 8) = fun;
1020}
1021#endif
1022
cc17453a
EZ		 1023static int
1024sh_coerce_float_to_double (struct type *formal, struct type *actual)
1025{
1026 return 1;
1027}
c906108c 1028
cc17453a
EZ		 1029/* Find a function's return value in the appropriate registers (in
1030 regbuf), and copy it into valbuf. Extract from an array REGBUF
1031 containing the (raw) register state a function return value of type
1032 TYPE, and copy that, in virtual format, into VALBUF. */
1033static void
1034sh_extract_return_value (type, regbuf, valbuf)
1035 struct type *type;
1036 char *regbuf;
1037 char *valbuf;
c906108c 1038{
cc17453a 1039 int len = TYPE_LENGTH (type);
c906108c 1040
cc17453a
EZ		 1041 if (len <= 4)
1042 memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
1043 else if (len <= 8)
1044 memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
1045 else
1046 error ("bad size for return value");
1047}
c906108c 1048
cc17453a
EZ		 1049/* Write into appropriate registers a function return value
1050 of type TYPE, given in virtual format.
1051 If the architecture is sh4 or sh3e, store a function's return value
1052 in the R0 general register or in the FP0 floating point register,
1053 depending on the type of the return value. In all the other cases
1054 the result is stored in r0. */
1055static void
1056sh_default_store_return_value (struct type *type, char *valbuf)
1057{
1058 write_register_bytes (REGISTER_BYTE (0),
1059 valbuf, TYPE_LENGTH (type));
1060}
c906108c 1061
cc17453a
EZ		 1062static void
1063sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1064{
1065 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1066 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1067 valbuf, TYPE_LENGTH (type));
1068 else
1069 write_register_bytes (REGISTER_BYTE (0),
1070 valbuf, TYPE_LENGTH (type));
c906108c
SS		 1071}
1072
cc17453a 1073
c906108c
SS		 1074/* Print the registers in a form similar to the E7000 */
1075
1076static void
cc17453a 1077sh_generic_show_regs (args, from_tty)
c906108c
SS		 1078 char *args;
1079 int from_tty;
1080{
cc17453a
EZ		 1081 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1082 paddr (read_register (PC_REGNUM)),
1083 (long) read_register (SR_REGNUM),
1084 (long) read_register (PR_REGNUM),
1085 (long) read_register (MACH_REGNUM),
1086 (long) read_register (MACL_REGNUM));
1087
1088 printf_filtered ("GBR=%08lx VBR=%08lx",
1089 (long) read_register (GBR_REGNUM),
1090 (long) read_register (VBR_REGNUM));
1091
1092 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1093 (long) read_register (0),
1094 (long) read_register (1),
1095 (long) read_register (2),
1096 (long) read_register (3),
1097 (long) read_register (4),
1098 (long) read_register (5),
1099 (long) read_register (6),
1100 (long) read_register (7));
1101 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1102 (long) read_register (8),
1103 (long) read_register (9),
1104 (long) read_register (10),
1105 (long) read_register (11),
1106 (long) read_register (12),
1107 (long) read_register (13),
1108 (long) read_register (14),
1109 (long) read_register (15));
1110}
c906108c 1111
cc17453a
EZ		 1112static void
1113sh3_show_regs (args, from_tty)
1114 char *args;
1115 int from_tty;
1116{
d4f3574e
SS		 1117 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1118 paddr (read_register (PC_REGNUM)),
1119 (long) read_register (SR_REGNUM),
1120 (long) read_register (PR_REGNUM),
1121 (long) read_register (MACH_REGNUM),
1122 (long) read_register (MACL_REGNUM));
1123
1124 printf_filtered ("GBR=%08lx VBR=%08lx",
1125 (long) read_register (GBR_REGNUM),
1126 (long) read_register (VBR_REGNUM));
cc17453a
EZ		 1127 printf_filtered (" SSR=%08lx SPC=%08lx",
1128 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1129 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
c906108c 1130
d4f3574e
SS		 1131 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1132 (long) read_register (0),
1133 (long) read_register (1),
1134 (long) read_register (2),
1135 (long) read_register (3),
1136 (long) read_register (4),
1137 (long) read_register (5),
1138 (long) read_register (6),
1139 (long) read_register (7));
1140 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1141 (long) read_register (8),
1142 (long) read_register (9),
1143 (long) read_register (10),
1144 (long) read_register (11),
1145 (long) read_register (12),
1146 (long) read_register (13),
1147 (long) read_register (14),
1148 (long) read_register (15));
c906108c
SS		 1149}
1150
cc17453a
EZ		 1151static void
1152sh3e_show_regs (args, from_tty)
1153 char *args;
1154 int from_tty;
1155{
1156 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1157 paddr (read_register (PC_REGNUM)),
1158 (long) read_register (SR_REGNUM),
1159 (long) read_register (PR_REGNUM),
1160 (long) read_register (MACH_REGNUM),
1161 (long) read_register (MACL_REGNUM));
1162
1163 printf_filtered ("GBR=%08lx VBR=%08lx",
1164 (long) read_register (GBR_REGNUM),
1165 (long) read_register (VBR_REGNUM));
1166 printf_filtered (" SSR=%08lx SPC=%08lx",
1167 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1168 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1169 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1170 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1171 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
c906108c 1172
cc17453a
EZ		 1173 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1174 (long) read_register (0),
1175 (long) read_register (1),
1176 (long) read_register (2),
1177 (long) read_register (3),
1178 (long) read_register (4),
1179 (long) read_register (5),
1180 (long) read_register (6),
1181 (long) read_register (7));
1182 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1183 (long) read_register (8),
1184 (long) read_register (9),
1185 (long) read_register (10),
1186 (long) read_register (11),
1187 (long) read_register (12),
1188 (long) read_register (13),
1189 (long) read_register (14),
1190 (long) read_register (15));
1191
1192 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1193 (long) read_register (FP0_REGNUM + 0),
1194 (long) read_register (FP0_REGNUM + 1),
1195 (long) read_register (FP0_REGNUM + 2),
1196 (long) read_register (FP0_REGNUM + 3),
1197 (long) read_register (FP0_REGNUM + 4),
1198 (long) read_register (FP0_REGNUM + 5),
1199 (long) read_register (FP0_REGNUM + 6),
1200 (long) read_register (FP0_REGNUM + 7));
1201 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1202 (long) read_register (FP0_REGNUM + 8),
1203 (long) read_register (FP0_REGNUM + 9),
1204 (long) read_register (FP0_REGNUM + 10),
1205 (long) read_register (FP0_REGNUM + 11),
1206 (long) read_register (FP0_REGNUM + 12),
1207 (long) read_register (FP0_REGNUM + 13),
1208 (long) read_register (FP0_REGNUM + 14),
1209 (long) read_register (FP0_REGNUM + 15));
1210}
1211
1212static void
1213sh3_dsp_show_regs (args, from_tty)
1214 char *args;
1215 int from_tty;
c906108c 1216{
cc17453a
EZ		 1217 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1218 paddr (read_register (PC_REGNUM)),
1219 (long) read_register (SR_REGNUM),
1220 (long) read_register (PR_REGNUM),
1221 (long) read_register (MACH_REGNUM),
1222 (long) read_register (MACL_REGNUM));
c906108c 1223
cc17453a
EZ		 1224 printf_filtered ("GBR=%08lx VBR=%08lx",
1225 (long) read_register (GBR_REGNUM),
1226 (long) read_register (VBR_REGNUM));
1227
1228 printf_filtered (" SSR=%08lx SPC=%08lx",
1229 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1230 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1231
1232 printf_filtered (" DSR=%08lx",
1233 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1234
1235 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1236 (long) read_register (0),
1237 (long) read_register (1),
1238 (long) read_register (2),
1239 (long) read_register (3),
1240 (long) read_register (4),
1241 (long) read_register (5),
1242 (long) read_register (6),
1243 (long) read_register (7));
1244 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1245 (long) read_register (8),
1246 (long) read_register (9),
1247 (long) read_register (10),
1248 (long) read_register (11),
1249 (long) read_register (12),
1250 (long) read_register (13),
1251 (long) read_register (14),
1252 (long) read_register (15));
1253
1254 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1255 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1256 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1257 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1258 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1259 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1260 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1261 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1262 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1263 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1264 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1265 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1266 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1267 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1268 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
c906108c
SS		 1269}
1270
cc17453a
EZ		 1271static void
1272sh4_show_regs (args, from_tty)
1273 char *args;
1274 int from_tty;
1275{
1276 int pr = read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & 0x80000;
1277 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1278 paddr (read_register (PC_REGNUM)),
1279 (long) read_register (SR_REGNUM),
1280 (long) read_register (PR_REGNUM),
1281 (long) read_register (MACH_REGNUM),
1282 (long) read_register (MACL_REGNUM));
1283
1284 printf_filtered ("GBR=%08lx VBR=%08lx",
1285 (long) read_register (GBR_REGNUM),
1286 (long) read_register (VBR_REGNUM));
1287 printf_filtered (" SSR=%08lx SPC=%08lx",
1288 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1289 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1290 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1291 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1292 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
1293
1294 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1295 (long) read_register (0),
1296 (long) read_register (1),
1297 (long) read_register (2),
1298 (long) read_register (3),
1299 (long) read_register (4),
1300 (long) read_register (5),
1301 (long) read_register (6),
1302 (long) read_register (7));
1303 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1304 (long) read_register (8),
1305 (long) read_register (9),
1306 (long) read_register (10),
1307 (long) read_register (11),
1308 (long) read_register (12),
1309 (long) read_register (13),
1310 (long) read_register (14),
1311 (long) read_register (15));
1312
1313 printf_filtered ((pr
1314 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1315 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1316 (long) read_register (FP0_REGNUM + 0),
1317 (long) read_register (FP0_REGNUM + 1),
1318 (long) read_register (FP0_REGNUM + 2),
1319 (long) read_register (FP0_REGNUM + 3),
1320 (long) read_register (FP0_REGNUM + 4),
1321 (long) read_register (FP0_REGNUM + 5),
1322 (long) read_register (FP0_REGNUM + 6),
1323 (long) read_register (FP0_REGNUM + 7));
1324 printf_filtered ((pr
1325 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1326 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1327 (long) read_register (FP0_REGNUM + 8),
1328 (long) read_register (FP0_REGNUM + 9),
1329 (long) read_register (FP0_REGNUM + 10),
1330 (long) read_register (FP0_REGNUM + 11),
1331 (long) read_register (FP0_REGNUM + 12),
1332 (long) read_register (FP0_REGNUM + 13),
1333 (long) read_register (FP0_REGNUM + 14),
1334 (long) read_register (FP0_REGNUM + 15));
1335}
1336
1337static void
1338sh_dsp_show_regs (args, from_tty)
1339 char *args;
1340 int from_tty;
1341{
1342 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1343 paddr (read_register (PC_REGNUM)),
1344 (long) read_register (SR_REGNUM),
1345 (long) read_register (PR_REGNUM),
1346 (long) read_register (MACH_REGNUM),
1347 (long) read_register (MACL_REGNUM));
1348
1349 printf_filtered ("GBR=%08lx VBR=%08lx",
1350 (long) read_register (GBR_REGNUM),
1351 (long) read_register (VBR_REGNUM));
1352
1353 printf_filtered (" DSR=%08lx",
1354 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1355
1356 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1357 (long) read_register (0),
1358 (long) read_register (1),
1359 (long) read_register (2),
1360 (long) read_register (3),
1361 (long) read_register (4),
1362 (long) read_register (5),
1363 (long) read_register (6),
1364 (long) read_register (7));
1365 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1366 (long) read_register (8),
1367 (long) read_register (9),
1368 (long) read_register (10),
1369 (long) read_register (11),
1370 (long) read_register (12),
1371 (long) read_register (13),
1372 (long) read_register (14),
1373 (long) read_register (15));
1374
1375 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1376 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1377 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1378 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1379 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1380 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1381 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1382 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1383 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1384 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1385 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1386 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1387 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1388 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1389 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
1390}
1391
1392/* Index within `registers' of the first byte of the space for
1393 register N. */
1394static int
1395sh_register_byte (reg_nr)
1396 int reg_nr;
8db62801 1397{
cc17453a
EZ		 1398 return (reg_nr * 4);
1399}
1400
1401/* Number of bytes of storage in the actual machine representation for
1402 register REG_NR. */
1403static int
1404sh_register_raw_size (reg_nr)
1405 int reg_nr;
1406{
1407 return 4;
1408}
1409
1410/* Number of bytes of storage in the program's representation
1411 for register N. */
1412static int
1413sh_register_virtual_size (reg_nr)
1414 int reg_nr;
1415{
1416 return 4;
1417}
1418
1419/* Return the GDB type object for the "standard" data type
1420 of data in register N. */
1421
1422static struct type *
1423sh_sh3e_register_virtual_type (reg_nr)
1424 int reg_nr;
1425{
1426 if ((reg_nr >= FP0_REGNUM
1427 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP15_REGNUM))
1428 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1429 return builtin_type_float;
8db62801 1430 else
cc17453a
EZ		 1431 return builtin_type_int;
1432}
1433
1434static struct type *
1435sh_default_register_virtual_type (reg_nr)
1436 int reg_nr;
1437{
1438 return builtin_type_int;
1439}
1440
1441static gdbarch_init_ftype sh_gdbarch_init;
1442
1443static struct gdbarch *
1444sh_gdbarch_init (info, arches)
1445 struct gdbarch_info info;
1446 struct gdbarch_list *arches;
1447{
1448 static LONGEST sh_call_dummy_words[] = {0};
1449 struct gdbarch *gdbarch;
1450 struct gdbarch_tdep *tdep;
1451 gdbarch_register_name_ftype *sh_register_name;
1452 gdbarch_store_return_value_ftype *sh_store_return_value;
1453 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1454
1455 /* Find a candidate among the list of pre-declared architectures. */
1456 arches = gdbarch_list_lookup_by_info (arches, &info);
1457 if (arches != NULL)
1458 return arches->gdbarch;
1459
1460 /* None found, create a new architecture from the information
1461 provided. */
1462 tdep = XMALLOC (struct gdbarch_tdep);
1463 gdbarch = gdbarch_alloc (&info, tdep);
1464
1465 /* Initialize the register numbers that are not common to all the
1466 variants to -1, if necessary thse will be overwritten in the case
1467 statement below. */
1468 tdep->FPUL_REGNUM = -1;
1469 tdep->FPSCR_REGNUM = -1;
1470 tdep->DSR_REGNUM = -1;
1471 tdep->FP15_REGNUM = -1;
1472 tdep->A0G_REGNUM = -1;
1473 tdep->A0_REGNUM = -1;
1474 tdep->A1G_REGNUM = -1;
1475 tdep->A1_REGNUM = -1;
1476 tdep->M0_REGNUM = -1;
1477 tdep->M1_REGNUM = -1;
1478 tdep->X0_REGNUM = -1;
1479 tdep->X1_REGNUM = -1;
1480 tdep->Y0_REGNUM = -1;
1481 tdep->Y1_REGNUM = -1;
1482 tdep->MOD_REGNUM = -1;
1483 tdep->RS_REGNUM = -1;
1484 tdep->RE_REGNUM = -1;
1485 tdep->SSR_REGNUM = -1;
1486 tdep->SPC_REGNUM = -1;
1487 set_gdbarch_fp0_regnum (gdbarch, -1);
1488
1489 switch (info.bfd_arch_info->mach)
8db62801 1490 {
cc17453a
EZ		 1491 case bfd_mach_sh:
1492 sh_register_name = sh_sh_register_name;
1493 sh_show_regs = sh_generic_show_regs;
1494 sh_store_return_value = sh_default_store_return_value;
1495 sh_register_virtual_type = sh_default_register_virtual_type;
1496 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
1497 break;
1498 case bfd_mach_sh2:
1499 sh_register_name = sh_sh_register_name;
1500 sh_show_regs = sh_generic_show_regs;
1501 sh_store_return_value = sh_default_store_return_value;
1502 sh_register_virtual_type = sh_default_register_virtual_type;
1503 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
1504 break;
1505 case bfd_mach_sh_dsp:
1506 sh_register_name = sh_sh_dsp_register_name;
1507 sh_show_regs = sh_dsp_show_regs;
1508 sh_store_return_value = sh_default_store_return_value;
1509 sh_register_virtual_type = sh_default_register_virtual_type;
1510 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
1511 tdep->DSR_REGNUM = 24;
1512 tdep->A0G_REGNUM = 25;
1513 tdep->A0_REGNUM = 26;
1514 tdep->A1G_REGNUM = 27;
1515 tdep->A1_REGNUM = 28;
1516 tdep->M0_REGNUM = 29;
1517 tdep->M1_REGNUM = 30;
1518 tdep->X0_REGNUM = 31;
1519 tdep->X1_REGNUM = 32;
1520 tdep->Y0_REGNUM = 33;
1521 tdep->Y1_REGNUM = 34;
1522 tdep->MOD_REGNUM = 40;
1523 tdep->RS_REGNUM = 43;
1524 tdep->RE_REGNUM = 44;
1525 break;
1526 case bfd_mach_sh3:
1527 sh_register_name = sh_sh3_register_name;
1528 sh_show_regs = sh3_show_regs;
1529 sh_store_return_value = sh_default_store_return_value;
1530 sh_register_virtual_type = sh_default_register_virtual_type;
1531 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
1532 tdep->SSR_REGNUM = 41;
1533 tdep->SPC_REGNUM = 42;
1534 break;
1535 case bfd_mach_sh3e:
1536 sh_register_name = sh_sh3e_register_name;
1537 sh_show_regs = sh3e_show_regs;
1538 sh_store_return_value = sh3e_sh4_store_return_value;
1539 sh_register_virtual_type = sh_sh3e_register_virtual_type;
1540 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
1541 set_gdbarch_fp0_regnum (gdbarch, 25);
1542 tdep->FPUL_REGNUM = 23;
1543 tdep->FPSCR_REGNUM = 24;
1544 tdep->FP15_REGNUM = 40;
1545 tdep->SSR_REGNUM = 41;
1546 tdep->SPC_REGNUM = 42;
1547 break;
1548 case bfd_mach_sh3_dsp:
1549 sh_register_name = sh_sh3_dsp_register_name;
1550 sh_show_regs = sh3_dsp_show_regs;
1551 sh_store_return_value = sh_default_store_return_value;
1552 sh_register_virtual_type = sh_default_register_virtual_type;
1553 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
1554 tdep->DSR_REGNUM = 24;
1555 tdep->A0G_REGNUM = 25;
1556 tdep->A0_REGNUM = 26;
1557 tdep->A1G_REGNUM = 27;
1558 tdep->A1_REGNUM = 28;
1559 tdep->M0_REGNUM = 29;
1560 tdep->M1_REGNUM = 30;
1561 tdep->X0_REGNUM = 31;
1562 tdep->X1_REGNUM = 32;
1563 tdep->Y0_REGNUM = 33;
1564 tdep->Y1_REGNUM = 34;
1565 tdep->MOD_REGNUM = 40;
1566 tdep->RS_REGNUM = 43;
1567 tdep->RE_REGNUM = 44;
1568 tdep->SSR_REGNUM = 41;
1569 tdep->SPC_REGNUM = 42;
1570 break;
1571 case bfd_mach_sh4:
1572 sh_register_name = sh_generic_register_name;
1573 sh_show_regs = sh_generic_show_regs;
1574 sh_store_return_value = sh3e_sh4_store_return_value;
1575 sh_register_virtual_type = sh_sh3e_register_virtual_type;
1576 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
1577 set_gdbarch_fp0_regnum (gdbarch, 25);
1578 tdep->FPUL_REGNUM = 23;
1579 tdep->FPSCR_REGNUM = 24;
1580 tdep->FP15_REGNUM = 40;
1581 tdep->SSR_REGNUM = 41;
1582 tdep->SPC_REGNUM = 42;
1583 break;
1584 default:
1585 sh_register_name = sh_generic_register_name;
1586 sh_show_regs = sh_generic_show_regs;
1587 sh_store_return_value = sh_default_store_return_value;
1588 sh_register_virtual_type = sh_default_register_virtual_type;
1589 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
1590 break;
8db62801 1591 }
cc17453a
EZ		 1592
1593 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
1594 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
1595 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
1596 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
1597 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
1598 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
1599
1600 set_gdbarch_num_regs (gdbarch, 59);
1601 set_gdbarch_sp_regnum (gdbarch, 15);
1602 set_gdbarch_fp_regnum (gdbarch, 14);
1603 set_gdbarch_pc_regnum (gdbarch, 16);
1604 set_gdbarch_register_name (gdbarch, sh_register_name);
1605 set_gdbarch_register_size (gdbarch, 4);
1606 set_gdbarch_register_bytes (gdbarch, NUM_REGS * 4);
1607 set_gdbarch_register_byte (gdbarch, sh_register_byte);
1608 set_gdbarch_register_raw_size (gdbarch, sh_register_raw_size);
1609 set_gdbarch_max_register_raw_size (gdbarch, 4);
1610 set_gdbarch_register_virtual_size (gdbarch, sh_register_virtual_size);
1611 set_gdbarch_max_register_virtual_size (gdbarch, 4);
1612 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
1613
1614 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1615 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1616 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1617 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1618 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1619 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1620 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1621 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
1622
1623 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
1624 set_gdbarch_call_dummy_length (gdbarch, 0);
1625 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
1626 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
1627 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
1628 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
1629 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
1630 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
1631 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
1632 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
1633 set_gdbarch_call_dummy_p (gdbarch, 1);
1634 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
1635 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
1636 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
1637 set_gdbarch_coerce_float_to_double (gdbarch,
1638 sh_coerce_float_to_double);
1639
1640 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
1641 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
1642 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
1643 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
1644
1645 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
1646 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
1647 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
1648 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
1649 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
1650 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
1651 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
1652 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1653 set_gdbarch_decr_pc_after_break (gdbarch, 0);
1654 set_gdbarch_function_start_offset (gdbarch, 0);
1655 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
1656
1657 set_gdbarch_frame_args_skip (gdbarch, 0);
1658 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
1659 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
1660 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
1661 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
1662 set_gdbarch_frame_args_address (gdbarch, sh_frame_args_address);
1663 set_gdbarch_frame_locals_address (gdbarch, sh_frame_locals_address);
1664 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
1665 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
1666 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
1667 set_gdbarch_ieee_float (gdbarch, 1);
1668
1669 return gdbarch;
8db62801
EZ		 1670}
1671
c906108c
SS		 1672void
1673_initialize_sh_tdep ()
1674{
1675 struct cmd_list_element *c;
cc17453a
EZ		 1676
1677 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
c906108c
SS		 1678 tm_print_insn = gdb_print_insn_sh;
1679
c906108c
SS		 1680 add_com ("regs", class_vars, sh_show_regs, "Print all registers");
1681}
GDB Binutils - Deliverables
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