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2004-04-30 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / sh64-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
cf5b2f1b
AC		 2
3 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
4 2002, 2003, 2004 Free Software Foundation, Inc.
55ff77ac
CV		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23/*
24 Contributed by Steve Chamberlain
25 sac@cygnus.com
26 */
27
28#include "defs.h"
29#include "frame.h"
30#include "symtab.h"
9ab9195f 31#include "objfiles.h"
55ff77ac
CV		 32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h"
38#include "gdb_string.h"
39#include "arch-utils.h"
40#include "floatformat.h"
41#include "regcache.h"
42#include "doublest.h"
43#include "osabi.h"
44
45#include "elf-bfd.h"
46#include "solib-svr4.h"
47
48/* sh flags */
49#include "elf/sh.h"
50/* registers numbers shared with the simulator */
51#include "gdb/sim-sh.h"
52
7bb11558 53/* Information that is dependent on the processor variant. */
55ff77ac
CV		 54enum sh_abi
55 {
56 SH_ABI_UNKNOWN,
57 SH_ABI_32,
58 SH_ABI_64
59 };
60
61struct gdbarch_tdep
62 {
63 enum sh_abi sh_abi;
64 };
65
66/* Registers of SH5 */
67enum
68 {
69 R0_REGNUM = 0,
70 DEFAULT_RETURN_REGNUM = 2,
71 STRUCT_RETURN_REGNUM = 2,
72 ARG0_REGNUM = 2,
73 ARGLAST_REGNUM = 9,
74 FLOAT_ARGLAST_REGNUM = 11,
75 PR_REGNUM = 18,
76 SR_REGNUM = 65,
77 DR0_REGNUM = 141,
78 DR_LAST_REGNUM = 172,
79 /* FPP stands for Floating Point Pair, to avoid confusion with
80 GDB's FP0_REGNUM, which is the number of the first Floating
81 point register. Unfortunately on the sh5, the floating point
7bb11558 82 registers are called FR, and the floating point pairs are called FP. */
55ff77ac
CV		 83 FPP0_REGNUM = 173,
84 FPP_LAST_REGNUM = 204,
85 FV0_REGNUM = 205,
86 FV_LAST_REGNUM = 220,
87 R0_C_REGNUM = 221,
88 R_LAST_C_REGNUM = 236,
89 PC_C_REGNUM = 237,
90 GBR_C_REGNUM = 238,
91 MACH_C_REGNUM = 239,
92 MACL_C_REGNUM = 240,
93 PR_C_REGNUM = 241,
94 T_C_REGNUM = 242,
95 FPSCR_C_REGNUM = 243,
96 FPUL_C_REGNUM = 244,
97 FP0_C_REGNUM = 245,
98 FP_LAST_C_REGNUM = 260,
99 DR0_C_REGNUM = 261,
100 DR_LAST_C_REGNUM = 268,
101 FV0_C_REGNUM = 269,
102 FV_LAST_C_REGNUM = 272,
103 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
104 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
105 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
106 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
107 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
108 };
109
110
111/* Define other aspects of the stack frame.
112 we keep a copy of the worked out return pc lying around, since it
113 is a useful bit of info */
114
115struct frame_extra_info
116{
117 CORE_ADDR return_pc;
118 int leaf_function;
119 int f_offset;
120};
121
122static const char *
39add00a 123sh64_register_name (int reg_nr)
55ff77ac
CV		 124{
125 static char *register_names[] =
126 {
127 /* SH MEDIA MODE (ISA 32) */
128 /* general registers (64-bit) 0-63 */
129 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
130 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
131 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
132 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
133 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
134 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
135 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
136 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
137
138 /* pc (64-bit) 64 */
139 "pc",
140
141 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
142 "sr", "ssr", "spc",
143
144 /* target registers (64-bit) 68-75*/
145 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
146
147 /* floating point state control register (32-bit) 76 */
148 "fpscr",
149
150 /* single precision floating point registers (32-bit) 77-140*/
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
153 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
154 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
155 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
156 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
157 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
158 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
159
160 /* double precision registers (pseudo) 141-172 */
161 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
162 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
163 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
164 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
165
166 /* floating point pairs (pseudo) 173-204*/
167 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
168 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
169 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
170 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
171
172 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
173 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
174 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
175
176 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
177 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
178 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
179 "pc_c",
180 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
181 "fpscr_c", "fpul_c",
182 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
183 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
184 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
185 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
186 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
187 };
188
189 if (reg_nr < 0)
190 return NULL;
191 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
192 return NULL;
193 return register_names[reg_nr];
194}
195
196#define NUM_PSEUDO_REGS_SH_MEDIA 80
197#define NUM_PSEUDO_REGS_SH_COMPACT 51
198
199/* Macros and functions for setting and testing a bit in a minimal
200 symbol that marks it as 32-bit function. The MSB of the minimal
f594e5e9 201 symbol's "info" field is used for this purpose.
55ff77ac
CV		 202
203 ELF_MAKE_MSYMBOL_SPECIAL
204 tests whether an ELF symbol is "special", i.e. refers
205 to a 32-bit function, and sets a "special" bit in a
206 minimal symbol to mark it as a 32-bit function
f594e5e9 207 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
55ff77ac
CV		 208
209#define MSYMBOL_IS_SPECIAL(msym) \
210 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
211
212static void
213sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
214{
215 if (msym == NULL)
216 return;
217
218 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
219 {
220 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
221 SYMBOL_VALUE_ADDRESS (msym) |= 1;
222 }
223}
224
225/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
226 are some macros to test, set, or clear bit 0 of addresses. */
227#define IS_ISA32_ADDR(addr) ((addr) & 1)
228#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
229#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
230
231static int
232pc_is_isa32 (bfd_vma memaddr)
233{
234 struct minimal_symbol *sym;
235
236 /* If bit 0 of the address is set, assume this is a
7bb11558 237 ISA32 (shmedia) address. */
55ff77ac
CV		 238 if (IS_ISA32_ADDR (memaddr))
239 return 1;
240
241 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
242 the high bit of the info field. Use this to decide if the function is
243 ISA16 or ISA32. */
244 sym = lookup_minimal_symbol_by_pc (memaddr);
245 if (sym)
246 return MSYMBOL_IS_SPECIAL (sym);
247 else
248 return 0;
249}
250
251static const unsigned char *
39add00a 252sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
55ff77ac
CV		 253{
254 /* The BRK instruction for shmedia is
255 01101111 11110101 11111111 11110000
256 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
257 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
258
259 /* The BRK instruction for shcompact is
260 00000000 00111011
261 which translates in big endian mode to 0x0, 0x3b
262 and in little endian mode to 0x3b, 0x0*/
263
264 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
265 {
266 if (pc_is_isa32 (*pcptr))
267 {
268 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
269 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
270 *lenptr = sizeof (big_breakpoint_media);
271 return big_breakpoint_media;
272 }
273 else
274 {
275 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
276 *lenptr = sizeof (big_breakpoint_compact);
277 return big_breakpoint_compact;
278 }
279 }
280 else
281 {
282 if (pc_is_isa32 (*pcptr))
283 {
284 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
285 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
286 *lenptr = sizeof (little_breakpoint_media);
287 return little_breakpoint_media;
288 }
289 else
290 {
291 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
292 *lenptr = sizeof (little_breakpoint_compact);
293 return little_breakpoint_compact;
294 }
295 }
296}
297
298/* Prologue looks like
299 [mov.l <regs>,@-r15]...
300 [sts.l pr,@-r15]
301 [mov.l r14,@-r15]
302 [mov r15,r14]
303
304 Actually it can be more complicated than this. For instance, with
305 newer gcc's:
306
307 mov.l r14,@-r15
308 add #-12,r15
309 mov r15,r14
310 mov r4,r1
311 mov r5,r2
312 mov.l r6,@(4,r14)
313 mov.l r7,@(8,r14)
314 mov.b r1,@r14
315 mov r14,r1
316 mov r14,r1
317 add #2,r1
318 mov.w r2,@r1
319
320 */
321
322/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
323 with l=1 and n = 18 0110101111110001010010100aaa0000 */
324#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
325
326/* STS.L PR,@-r0 0100000000100010
327 r0-4-->r0, PR-->(r0) */
328#define IS_STS_R0(x) ((x) == 0x4022)
329
330/* STS PR, Rm 0000mmmm00101010
331 PR-->Rm */
332#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
333
334/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
335 Rm-->(dispx4+r15) */
336#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
337
338/* MOV.L R14,@(disp,r15) 000111111110dddd
339 R14-->(dispx4+r15) */
340#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
341
342/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
343 R18-->(dispx8+R14) */
344#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
345
346/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
347 R18-->(dispx8+R15) */
348#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
349
350/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
351 R18-->(dispx4+R15) */
352#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
353
354/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
355 R14-->(dispx8+R15) */
356#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
357
358/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
359 R14-->(dispx4+R15) */
360#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
361
362/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
363 R15 + imm --> R15 */
364#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
365
366/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
367 R15 + imm --> R15 */
368#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
369
370/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
371 R15 + R63 --> R14 */
372#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
373
374/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
375 R15 + R63 --> R14 */
376#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
377
378#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
379
380/* MOV #imm, R0 1110 0000 ssss ssss
381 #imm-->R0 */
382#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
383
384/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
385#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
386
387/* ADD r15,r0 0011 0000 1111 1100
388 r15+r0-->r0 */
389#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
390
391/* MOV.L R14 @-R0 0010 0000 1110 0110
392 R14-->(R0-4), R0-4-->R0 */
393#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
394
395/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
7bb11558 396 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 397/* FIXME: Recognize the float and double register moves too! */
398#define IS_MEDIA_IND_ARG_MOV(x) \
399((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
400
401/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
402 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
7bb11558 403 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 404#define IS_MEDIA_ARG_MOV(x) \
405(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
406 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
407
408/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
409/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
410/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
411/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
412/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
413#define IS_MEDIA_MOV_TO_R14(x) \
414((((x) & 0xfffffc0f) == 0xa0e00000) \
415|| (((x) & 0xfffffc0f) == 0xa4e00000) \
416|| (((x) & 0xfffffc0f) == 0xa8e00000) \
417|| (((x) & 0xfffffc0f) == 0xb4e00000) \
418|| (((x) & 0xfffffc0f) == 0xbce00000))
419
420/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
421 where Rm is r2-r9 */
422#define IS_COMPACT_IND_ARG_MOV(x) \
423((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
424
425/* compact direct arg move!
426 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
427#define IS_COMPACT_ARG_MOV(x) \
428(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
429
430/* MOV.B Rm, @R14 0010 1110 mmmm 0000
431 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
432#define IS_COMPACT_MOV_TO_R14(x) \
433((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
434
435#define IS_JSR_R0(x) ((x) == 0x400b)
436#define IS_NOP(x) ((x) == 0x0009)
437
438
439/* MOV r15,r14 0110111011110011
440 r15-->r14 */
441#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
442
443/* ADD #imm,r15 01111111iiiiiiii
444 r15+imm-->r15 */
445#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
446
447/* Skip any prologue before the guts of a function */
448
7bb11558
MS		 449/* Skip the prologue using the debug information. If this fails we'll
450 fall back on the 'guess' method below. */
55ff77ac
CV		 451static CORE_ADDR
452after_prologue (CORE_ADDR pc)
453{
454 struct symtab_and_line sal;
455 CORE_ADDR func_addr, func_end;
456
457 /* If we can not find the symbol in the partial symbol table, then
458 there is no hope we can determine the function's start address
459 with this code. */
460 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
461 return 0;
462
463 /* Get the line associated with FUNC_ADDR. */
464 sal = find_pc_line (func_addr, 0);
465
466 /* There are only two cases to consider. First, the end of the source line
467 is within the function bounds. In that case we return the end of the
468 source line. Second is the end of the source line extends beyond the
469 bounds of the current function. We need to use the slow code to
470 examine instructions in that case. */
471 if (sal.end < func_end)
472 return sal.end;
473 else
474 return 0;
475}
476
477static CORE_ADDR
478look_for_args_moves (CORE_ADDR start_pc, int media_mode)
479{
480 CORE_ADDR here, end;
481 int w;
482 int insn_size = (media_mode ? 4 : 2);
483
484 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
485 {
486 if (media_mode)
487 {
488 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
489 here += insn_size;
490 if (IS_MEDIA_IND_ARG_MOV (w))
491 {
492 /* This must be followed by a store to r14, so the argument
493 is where the debug info says it is. This can happen after
7bb11558 494 the SP has been saved, unfortunately. */
55ff77ac
CV		 495
496 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
497 insn_size);
498 here += insn_size;
499 if (IS_MEDIA_MOV_TO_R14 (next_insn))
500 start_pc = here;
501 }
502 else if (IS_MEDIA_ARG_MOV (w))
503 {
7bb11558 504 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 505 start_pc = here;
506 }
507 else
508 break;
509 }
510 else
511 {
512 w = read_memory_integer (here, insn_size);
513 w = w & 0xffff;
514 here += insn_size;
515 if (IS_COMPACT_IND_ARG_MOV (w))
516 {
517 /* This must be followed by a store to r14, so the argument
518 is where the debug info says it is. This can happen after
7bb11558 519 the SP has been saved, unfortunately. */
55ff77ac
CV		 520
521 int next_insn = 0xffff & read_memory_integer (here, insn_size);
522 here += insn_size;
523 if (IS_COMPACT_MOV_TO_R14 (next_insn))
524 start_pc = here;
525 }
526 else if (IS_COMPACT_ARG_MOV (w))
527 {
7bb11558 528 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 529 start_pc = here;
530 }
531 else if (IS_MOVL_R0 (w))
532 {
533 /* There is a function that gcc calls to get the arguments
534 passed correctly to the function. Only after this
535 function call the arguments will be found at the place
536 where they are supposed to be. This happens in case the
537 argument has to be stored into a 64-bit register (for
538 instance doubles, long longs). SHcompact doesn't have
539 access to the full 64-bits, so we store the register in
540 stack slot and store the address of the stack slot in
541 the register, then do a call through a wrapper that
542 loads the memory value into the register. A SHcompact
543 callee calls an argument decoder
544 (GCC_shcompact_incoming_args) that stores the 64-bit
545 value in a stack slot and stores the address of the
546 stack slot in the register. GCC thinks the argument is
547 just passed by transparent reference, but this is only
548 true after the argument decoder is called. Such a call
7bb11558 549 needs to be considered part of the prologue. */
55ff77ac
CV		 550
551 /* This must be followed by a JSR @r0 instruction and by
552 a NOP instruction. After these, the prologue is over! */
553
554 int next_insn = 0xffff & read_memory_integer (here, insn_size);
555 here += insn_size;
556 if (IS_JSR_R0 (next_insn))
557 {
558 next_insn = 0xffff & read_memory_integer (here, insn_size);
559 here += insn_size;
560
561 if (IS_NOP (next_insn))
562 start_pc = here;
563 }
564 }
565 else
566 break;
567 }
568 }
569
570 return start_pc;
571}
572
573static CORE_ADDR
574sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
575{
576 CORE_ADDR here, end;
577 int updated_fp = 0;
578 int insn_size = 4;
579 int media_mode = 1;
580
581 if (!start_pc)
582 return 0;
583
584 if (pc_is_isa32 (start_pc) == 0)
585 {
586 insn_size = 2;
587 media_mode = 0;
588 }
589
590 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
591 {
592
593 if (media_mode)
594 {
595 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
596 here += insn_size;
597 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
598 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
599 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
600 {
601 start_pc = here;
602 }
603 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
604 {
605 start_pc = here;
606 updated_fp = 1;
607 }
608 else
609 if (updated_fp)
610 {
611 /* Don't bail out yet, we may have arguments stored in
612 registers here, according to the debug info, so that
7bb11558 613 gdb can print the frames correctly. */
55ff77ac
CV		 614 start_pc = look_for_args_moves (here - insn_size, media_mode);
615 break;
616 }
617 }
618 else
619 {
620 int w = 0xffff & read_memory_integer (here, insn_size);
621 here += insn_size;
622
623 if (IS_STS_R0 (w) || IS_STS_PR (w)
624 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
625 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
626 {
627 start_pc = here;
628 }
629 else if (IS_MOV_SP_FP (w))
630 {
631 start_pc = here;
632 updated_fp = 1;
633 }
634 else
635 if (updated_fp)
636 {
637 /* Don't bail out yet, we may have arguments stored in
638 registers here, according to the debug info, so that
7bb11558 639 gdb can print the frames correctly. */
55ff77ac
CV		 640 start_pc = look_for_args_moves (here - insn_size, media_mode);
641 break;
642 }
643 }
644 }
645
646 return start_pc;
647}
648
649static CORE_ADDR
650sh_skip_prologue (CORE_ADDR pc)
651{
652 CORE_ADDR post_prologue_pc;
653
654 /* See if we can determine the end of the prologue via the symbol table.
655 If so, then return either PC, or the PC after the prologue, whichever
656 is greater. */
657 post_prologue_pc = after_prologue (pc);
658
659 /* If after_prologue returned a useful address, then use it. Else
7bb11558 660 fall back on the instruction skipping code. */
55ff77ac
CV		 661 if (post_prologue_pc != 0)
662 return max (pc, post_prologue_pc);
663 else
664 return sh64_skip_prologue_hard_way (pc);
665}
666
667/* Immediately after a function call, return the saved pc.
668 Can't always go through the frames for this because on some machines
669 the new frame is not set up until the new function executes
670 some instructions.
671
672 The return address is the value saved in the PR register + 4 */
673static CORE_ADDR
674sh_saved_pc_after_call (struct frame_info *frame)
675{
676 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
677}
678
679/* Should call_function allocate stack space for a struct return? */
680static int
681sh64_use_struct_convention (int gcc_p, struct type *type)
682{
683 return (TYPE_LENGTH (type) > 8);
684}
685
686/* Store the address of the place in which to copy the structure the
687 subroutine will return. This is called from call_function.
688
689 We store structs through a pointer passed in R2 */
690static void
691sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
692{
693 write_register (STRUCT_RETURN_REGNUM, (addr));
694}
695
696/* Disassemble an instruction. */
697static int
698gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
699{
700 info->endian = TARGET_BYTE_ORDER;
701 return print_insn_sh (memaddr, info);
702}
703
704/* Given a register number RN as it appears in an assembly
705 instruction, find the corresponding register number in the GDB
7bb11558 706 scheme. */
55ff77ac
CV		 707static int
708translate_insn_rn (int rn, int media_mode)
709{
55ff77ac 710 /* FIXME: this assumes that the number rn is for a not pseudo
7bb11558 711 register only. */
55ff77ac
CV		 712 if (media_mode)
713 return rn;
714 else
715 {
7bb11558
MS		 716 /* These registers don't have a corresponding compact one. */
717 /* FIXME: This is probably not enough. */
55ff77ac
CV		 718#if 0
719 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
720 return rn;
721#endif
722 if (rn >= 0 && rn <= R0_C_REGNUM)
723 return R0_C_REGNUM + rn;
724 else
725 return rn;
726 }
727}
728
729/* Given a GDB frame, determine the address of the calling function's
730 frame. This will be used to create a new GDB frame struct, and
731 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
732 will be called for the new frame.
733
734 For us, the frame address is its stack pointer value, so we look up
735 the function prologue to determine the caller's sp value, and return it. */
736static CORE_ADDR
737sh64_frame_chain (struct frame_info *frame)
738{
739 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
740 get_frame_base (frame),
741 get_frame_base (frame)))
7bb11558 742 return get_frame_base (frame); /* dummy frame same as caller's frame */
2f72f850 743 if (get_frame_pc (frame))
55ff77ac
CV		 744 {
745 int media_mode = pc_is_isa32 (get_frame_pc (frame));
746 int size;
747 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
748 size = 4;
749 else
7bb11558
MS		 750 size = register_size (current_gdbarch,
751 translate_insn_rn (DEPRECATED_FP_REGNUM,
752 media_mode));
55ff77ac
CV		 753 return read_memory_integer (get_frame_base (frame)
754 + get_frame_extra_info (frame)->f_offset,
755 size);
756 }
757 else
758 return 0;
759}
760
761static CORE_ADDR
762sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
763{
764 int media_mode = 0;
765
766 for (; fi; fi = get_next_frame (fi))
767 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
768 get_frame_base (fi)))
7bb11558
MS		 769 /* When the caller requests PR from the dummy frame, we return
770 PC because that's where the previous routine appears to have
771 done a call from. */
55ff77ac
CV		 772 return deprecated_read_register_dummy (get_frame_pc (fi),
773 get_frame_base (fi), pr_regnum);
774 else
775 {
776 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
777 if (!get_frame_pc (fi))
778 return 0;
779
780 media_mode = pc_is_isa32 (get_frame_pc (fi));
781
1b1d3794 782 if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0)
55ff77ac
CV		 783 {
784 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
785 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
786 ? 4
7bb11558 787 : register_size (current_gdbarch, gdb_reg_num));
1b1d3794 788 return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size);
55ff77ac
CV		 789 }
790 }
791 return read_register (pr_regnum);
792}
793
7bb11558 794/* For vectors of 4 floating point registers. */
55ff77ac
CV		 795static int
796fv_reg_base_num (int fv_regnum)
797{
798 int fp_regnum;
799
800 fp_regnum = FP0_REGNUM +
801 (fv_regnum - FV0_REGNUM) * 4;
802 return fp_regnum;
803}
804
805/* For double precision floating point registers, i.e 2 fp regs.*/
806static int
807dr_reg_base_num (int dr_regnum)
808{
809 int fp_regnum;
810
811 fp_regnum = FP0_REGNUM +
812 (dr_regnum - DR0_REGNUM) * 2;
813 return fp_regnum;
814}
815
816/* For pairs of floating point registers */
817static int
818fpp_reg_base_num (int fpp_regnum)
819{
820 int fp_regnum;
821
822 fp_regnum = FP0_REGNUM +
823 (fpp_regnum - FPP0_REGNUM) * 2;
824 return fp_regnum;
825}
826
827static int
828is_media_pseudo (int rn)
829{
2a314ed5 830 return (rn >= DR0_REGNUM && rn <= FV_LAST_REGNUM);
55ff77ac
CV		 831}
832
55ff77ac
CV		 833static int
834sh64_media_reg_base_num (int reg_nr)
835{
836 int base_regnum = -1;
55ff77ac
CV		 837
838 if (reg_nr >= DR0_REGNUM
839 && reg_nr <= DR_LAST_REGNUM)
840 base_regnum = dr_reg_base_num (reg_nr);
841
842 else if (reg_nr >= FPP0_REGNUM
843 && reg_nr <= FPP_LAST_REGNUM)
844 base_regnum = fpp_reg_base_num (reg_nr);
845
846 else if (reg_nr >= FV0_REGNUM
847 && reg_nr <= FV_LAST_REGNUM)
848 base_regnum = fv_reg_base_num (reg_nr);
849
850 return base_regnum;
851}
852
853/* *INDENT-OFF* */
854/*
855 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
856 GDB_REGNUM BASE_REGNUM
857 r0_c 221 0
858 r1_c 222 1
859 r2_c 223 2
860 r3_c 224 3
861 r4_c 225 4
862 r5_c 226 5
863 r6_c 227 6
864 r7_c 228 7
865 r8_c 229 8
866 r9_c 230 9
867 r10_c 231 10
868 r11_c 232 11
869 r12_c 233 12
870 r13_c 234 13
871 r14_c 235 14
872 r15_c 236 15
873
874 pc_c 237 64
875 gbr_c 238 16
876 mach_c 239 17
877 macl_c 240 17
878 pr_c 241 18
879 t_c 242 19
880 fpscr_c 243 76
881 fpul_c 244 109
882
883 fr0_c 245 77
884 fr1_c 246 78
885 fr2_c 247 79
886 fr3_c 248 80
887 fr4_c 249 81
888 fr5_c 250 82
889 fr6_c 251 83
890 fr7_c 252 84
891 fr8_c 253 85
892 fr9_c 254 86
893 fr10_c 255 87
894 fr11_c 256 88
895 fr12_c 257 89
896 fr13_c 258 90
897 fr14_c 259 91
898 fr15_c 260 92
899
900 dr0_c 261 77
901 dr2_c 262 79
902 dr4_c 263 81
903 dr6_c 264 83
904 dr8_c 265 85
905 dr10_c 266 87
906 dr12_c 267 89
907 dr14_c 268 91
908
909 fv0_c 269 77
910 fv4_c 270 81
911 fv8_c 271 85
912 fv12_c 272 91
913*/
914/* *INDENT-ON* */
915static int
916sh64_compact_reg_base_num (int reg_nr)
917{
918 int base_regnum = -1;
55ff77ac
CV		 919
920 /* general register N maps to general register N */
921 if (reg_nr >= R0_C_REGNUM
922 && reg_nr <= R_LAST_C_REGNUM)
923 base_regnum = reg_nr - R0_C_REGNUM;
924
925 /* floating point register N maps to floating point register N */
926 else if (reg_nr >= FP0_C_REGNUM
927 && reg_nr <= FP_LAST_C_REGNUM)
928 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
929
930 /* double prec register N maps to base regnum for double prec register N */
931 else if (reg_nr >= DR0_C_REGNUM
932 && reg_nr <= DR_LAST_C_REGNUM)
933 base_regnum = dr_reg_base_num (DR0_REGNUM
934 + reg_nr - DR0_C_REGNUM);
935
936 /* vector N maps to base regnum for vector register N */
937 else if (reg_nr >= FV0_C_REGNUM
938 && reg_nr <= FV_LAST_C_REGNUM)
939 base_regnum = fv_reg_base_num (FV0_REGNUM
940 + reg_nr - FV0_C_REGNUM);
941
942 else if (reg_nr == PC_C_REGNUM)
943 base_regnum = PC_REGNUM;
944
945 else if (reg_nr == GBR_C_REGNUM)
946 base_regnum = 16;
947
948 else if (reg_nr == MACH_C_REGNUM
949 || reg_nr == MACL_C_REGNUM)
950 base_regnum = 17;
951
952 else if (reg_nr == PR_C_REGNUM)
953 base_regnum = 18;
954
955 else if (reg_nr == T_C_REGNUM)
956 base_regnum = 19;
957
958 else if (reg_nr == FPSCR_C_REGNUM)
7bb11558 959 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
55ff77ac
CV		 960
961 else if (reg_nr == FPUL_C_REGNUM)
962 base_regnum = FP0_REGNUM + 32;
963
964 return base_regnum;
965}
966
967/* Given a register number RN (according to the gdb scheme) , return
968 its corresponding architectural register. In media mode, only a
969 subset of the registers is pseudo registers. For compact mode, all
7bb11558 970 the registers are pseudo. */
55ff77ac
CV		 971static int
972translate_rn_to_arch_reg_num (int rn, int media_mode)
973{
974
975 if (media_mode)
976 {
977 if (!is_media_pseudo (rn))
978 return rn;
979 else
980 return sh64_media_reg_base_num (rn);
981 }
982 else
7bb11558 983 /* All compact registers are pseudo. */
55ff77ac
CV		 984 return sh64_compact_reg_base_num (rn);
985}
986
987static int
988sign_extend (int value, int bits)
989{
990 value = value & ((1 << bits) - 1);
991 return (value & (1 << (bits - 1))
992 ? value | (~((1 << bits) - 1))
993 : value);
994}
995
996static void
997sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
998{
999 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1000 int rn;
1001 int have_fp = 0;
1002 int fp_regnum;
1003 int sp_regnum;
1004 int depth;
1005 int pc;
1006 int opc;
1007 int insn;
1008 int r0_val = 0;
1009 int media_mode = 0;
1010 int insn_size;
1011 int gdb_register_number;
1012 int register_number;
2a314ed5
MS		 1013 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1014 get_frame_base (fi));
7bb11558 1015 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac 1016
1b1d3794 1017 if (deprecated_get_frame_saved_regs (fi) == NULL)
55ff77ac
CV		 1018 frame_saved_regs_zalloc (fi);
1019 else
1b1d3794 1020 memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1021
1022 if (dummy_regs)
1023 {
1024 /* DANGER! This is ONLY going to work if the char buffer format of
1025 the saved registers is byte-for-byte identical to the
1026 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1b1d3794 1027 memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1028 return;
1029 }
1030
1031 get_frame_extra_info (fi)->leaf_function = 1;
1032 get_frame_extra_info (fi)->f_offset = 0;
1033
1034 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1035 where[rn] = -1;
1036
1037 depth = 0;
1038
1039 /* Loop around examining the prologue insns until we find something
1040 that does not appear to be part of the prologue. But give up
7bb11558 1041 after 20 of them, since we're getting silly then. */
55ff77ac
CV		 1042
1043 pc = get_frame_func (fi);
1044 if (!pc)
1045 {
1046 deprecated_update_frame_pc_hack (fi, 0);
1047 return;
1048 }
1049
1050 if (pc_is_isa32 (pc))
1051 {
1052 media_mode = 1;
1053 insn_size = 4;
1054 }
1055 else
1056 {
1057 media_mode = 0;
1058 insn_size = 2;
1059 }
1060
1061 /* The frame pointer register is general register 14 in shmedia and
1062 shcompact modes. In sh compact it is a pseudo register. Same goes
7bb11558 1063 for the stack pointer register, which is register 15. */
55ff77ac
CV		 1064 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1065 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1066
1067 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1068 {
1069 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1070 insn_size);
1071
1072 if (media_mode == 0)
1073 {
1074 if (IS_STS_PR (insn))
1075 {
1076 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1077 if (IS_MOV_TO_R15 (next_insn))
1078 {
1079 int reg_nr = PR_C_REGNUM;
1080
1081 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1082 get_frame_extra_info (fi)->leaf_function = 0;
1083 pc += insn_size;
1084 }
1085 }
1086 else if (IS_MOV_R14 (insn))
1087 {
1088 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1089 }
1090
1091 else if (IS_MOV_R0 (insn))
1092 {
1093 /* Put in R0 the offset from SP at which to store some
1094 registers. We are interested in this value, because it
1095 will tell us where the given registers are stored within
1096 the frame. */
1097 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1098 }
1099 else if (IS_ADD_SP_R0 (insn))
1100 {
1101 /* This instruction still prepares r0, but we don't care.
7bb11558 1102 We already have the offset in r0_val. */
55ff77ac
CV		 1103 }
1104 else if (IS_STS_R0 (insn))
1105 {
1106 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1107 int reg_nr = PR_C_REGNUM;
1108 where[reg_nr] = depth - (r0_val - 4);
1109 r0_val -= 4;
1110 get_frame_extra_info (fi)->leaf_function = 0;
1111 }
1112 else if (IS_MOV_R14_R0 (insn))
1113 {
1114 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1115 where[fp_regnum] = depth - (r0_val - 4);
1116 r0_val -= 4;
1117 }
1118
1119 else if (IS_ADD_SP (insn))
1120 {
1121 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1122 }
1123 else if (IS_MOV_SP_FP (insn))
1124 break;
1125 }
1126 else
1127 {
1128 if (IS_ADDIL_SP_MEDIA (insn)
1129 || IS_ADDI_SP_MEDIA (insn))
1130 {
1131 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1132 }
1133
1134 else if (IS_STQ_R18_R15 (insn))
1135 {
1136 where[PR_REGNUM] =
1137 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1138 get_frame_extra_info (fi)->leaf_function = 0;
1139 }
1140
1141 else if (IS_STL_R18_R15 (insn))
1142 {
1143 where[PR_REGNUM] =
1144 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1145 get_frame_extra_info (fi)->leaf_function = 0;
1146 }
1147
1148 else if (IS_STQ_R14_R15 (insn))
1149 {
1150 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1151 }
1152
1153 else if (IS_STL_R14_R15 (insn))
1154 {
1155 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1156 }
1157
1158 else if (IS_MOV_SP_FP_MEDIA (insn))
1159 break;
1160 }
1161 }
1162
7bb11558 1163 /* Now we know how deep things are, we can work out their addresses. */
55ff77ac
CV		 1164 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1165 {
1166 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1167
1168 if (where[rn] >= 0)
1169 {
1170 if (rn == fp_regnum)
1171 have_fp = 1;
1172
1173 /* Watch out! saved_regs is only for the real registers, and
7bb11558
MS		 1174 doesn't include space for the pseudo registers. */
1175 deprecated_get_frame_saved_regs (fi)[register_number]
1176 = get_frame_base (fi) - where[rn] + depth;
55ff77ac
CV		 1177 }
1178 else
7bb11558 1179 deprecated_get_frame_saved_regs (fi)[register_number] = 0;
55ff77ac
CV		 1180 }
1181
1182 if (have_fp)
1183 {
1184 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1185 shcompact 15 is the arch register corresponding to the pseudo
7bb11558 1186 register r15 which still is the SP register. */
55ff77ac 1187 /* The place on the stack where fp is stored contains the sp of
7bb11558 1188 the caller. */
55ff77ac
CV		 1189 /* Again, saved_registers contains only space for the real
1190 registers, so we store in DEPRECATED_FP_REGNUM position. */
1191 int size;
1192 if (tdep->sh_abi == SH_ABI_32)
1193 size = 4;
1194 else
7bb11558
MS		 1195 size = register_size (current_gdbarch, fp_regnum);
1196 deprecated_get_frame_saved_regs (fi)[sp_regnum]
1197 = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum],
1198 size);
55ff77ac
CV		 1199 }
1200 else
1b1d3794 1201 deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
55ff77ac 1202
7bb11558 1203 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
55ff77ac
CV		 1204}
1205
1206/* Initialize the extra info saved in a FRAME */
1207static void
1208sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1209{
1210 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1211
1212 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1213
1214 if (get_next_frame (fi))
1215 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1216
1217 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1218 get_frame_base (fi)))
1219 {
1220 /* We need to setup fi->frame here because call_function_by_hand
1221 gets it wrong by assuming it's always FP. */
1222 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1223 get_frame_extra_info (fi)->return_pc =
1224 deprecated_read_register_dummy (get_frame_pc (fi),
1225 get_frame_base (fi), PC_REGNUM);
ddc135a4 1226 get_frame_extra_info (fi)->f_offset = -4;
55ff77ac
CV		 1227 get_frame_extra_info (fi)->leaf_function = 0;
1228 return;
1229 }
1230 else
1231 {
1232 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1233 get_frame_extra_info (fi)->return_pc =
1234 sh64_get_saved_pr (fi, PR_REGNUM);
1235 }
1236}
1237
1238static void
1239sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1240 struct frame_info *frame, int regnum,
1241 enum lval_type *lval)
1242{
1243 int media_mode;
1244 int live_regnum = regnum;
7bb11558 1245 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1246
1247 if (!target_has_registers)
1248 error ("No registers.");
1249
1250 /* Normal systems don't optimize out things with register numbers. */
1251 if (optimized != NULL)
1252 *optimized = 0;
1253
1254 if (addrp) /* default assumption: not found in memory */
1255 *addrp = 0;
1256
1257 if (raw_buffer)
1258 memset (raw_buffer, 0, sizeof (raw_buffer));
1259
1260 /* We must do this here, before the following while loop changes
1261 frame, and makes it NULL. If this is a media register number,
1262 but we are in compact mode, it will become the corresponding
1263 compact pseudo register. If there is no corresponding compact
1264 pseudo-register what do we do?*/
1265 media_mode = pc_is_isa32 (get_frame_pc (frame));
1266 live_regnum = translate_insn_rn (regnum, media_mode);
1267
1268 /* Note: since the current frame's registers could only have been
1269 saved by frames INTERIOR TO the current frame, we skip examining
1270 the current frame itself: otherwise, we would be getting the
1271 previous frame's registers which were saved by the current frame. */
1272
1273 while (frame && ((frame = get_next_frame (frame)) != NULL))
1274 {
1275 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1276 get_frame_base (frame),
1277 get_frame_base (frame)))
1278 {
1279 if (lval) /* found it in a CALL_DUMMY frame */
1280 *lval = not_lval;
1281 if (raw_buffer)
1282 memcpy (raw_buffer,
1283 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
62700349 1284 + DEPRECATED_REGISTER_BYTE (regnum)),
7bb11558 1285 register_size (current_gdbarch, regnum));
55ff77ac
CV		 1286 return;
1287 }
1288
1289 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1b1d3794
AC		 1290 if (deprecated_get_frame_saved_regs (frame) != NULL
1291 && deprecated_get_frame_saved_regs (frame)[regnum] != 0)
55ff77ac
CV		 1292 {
1293 if (lval) /* found it saved on the stack */
1294 *lval = lval_memory;
1295 if (regnum == SP_REGNUM)
1296 {
1297 if (raw_buffer) /* SP register treated specially */
7bb11558
MS		 1298 store_unsigned_integer (raw_buffer,
1299 register_size (current_gdbarch,
1300 regnum),
1b1d3794 1301 deprecated_get_frame_saved_regs (frame)[regnum]);
55ff77ac
CV		 1302 }
1303 else
1304 { /* any other register */
1305
1306 if (addrp)
1b1d3794 1307 *addrp = deprecated_get_frame_saved_regs (frame)[regnum];
55ff77ac
CV		 1308 if (raw_buffer)
1309 {
1310 int size;
1311 if (tdep->sh_abi == SH_ABI_32
1312 && (live_regnum == DEPRECATED_FP_REGNUM
1313 || live_regnum == PR_REGNUM))
1314 size = 4;
1315 else
7bb11558 1316 size = register_size (current_gdbarch, live_regnum);
55ff77ac 1317 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
39add00a
MS		 1318 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
1319 raw_buffer, size);
55ff77ac 1320 else
1b1d3794 1321 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac 1322 raw_buffer
7bb11558 1323 + register_size (current_gdbarch, live_regnum)
55ff77ac
CV		 1324 - size,
1325 size);
1326 }
1327 }
1328 return;
1329 }
1330 }
1331
1332 /* If we get thru the loop to this point, it means the register was
1333 not saved in any frame. Return the actual live-register value. */
1334
1335 if (lval) /* found it in a live register */
1336 *lval = lval_register;
1337 if (addrp)
62700349 1338 *addrp = DEPRECATED_REGISTER_BYTE (live_regnum);
55ff77ac
CV		 1339 if (raw_buffer)
1340 deprecated_read_register_gen (live_regnum, raw_buffer);
1341}
1342
1343static CORE_ADDR
07be497a 1344sh64_extract_struct_value_address (struct regcache *regcache)
55ff77ac 1345{
07be497a
AC		 1346 /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return
1347 address regster is preserved across function calls? Probably
1348 not, making this function wrong. */
1349 ULONGEST val;
1350 regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val);
1351 return val;
55ff77ac
CV		 1352}
1353
1354static CORE_ADDR
1355sh_frame_saved_pc (struct frame_info *frame)
1356{
1357 return (get_frame_extra_info (frame)->return_pc);
1358}
1359
1360/* Discard from the stack the innermost frame, restoring all saved registers.
7bb11558 1361 Used in the 'return' command. */
55ff77ac
CV		 1362static void
1363sh64_pop_frame (void)
1364{
52f0bd74
AC		 1365 struct frame_info *frame = get_current_frame ();
1366 CORE_ADDR fp;
1367 int regnum;
7bb11558 1368 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1369
1370 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1371
1372 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1373 get_frame_base (frame),
1374 get_frame_base (frame)))
8adf9e78 1375 deprecated_pop_dummy_frame ();
55ff77ac
CV		 1376 else
1377 {
1378 fp = get_frame_base (frame);
1379 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1380
1381 /* Copy regs from where they were saved in the frame */
1382 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1b1d3794 1383 if (deprecated_get_frame_saved_regs (frame)[regnum])
55ff77ac
CV		 1384 {
1385 int size;
1386 if (tdep->sh_abi == SH_ABI_32
1387 && (regnum == DEPRECATED_FP_REGNUM
1388 || regnum == PR_REGNUM))
1389 size = 4;
1390 else
7bb11558
MS		 1391 size = register_size (current_gdbarch,
1392 translate_insn_rn (regnum, media_mode));
55ff77ac 1393 write_register (regnum,
1b1d3794 1394 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac
CV		 1395 size));
1396 }
1397
1398 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1399 write_register (SP_REGNUM, fp + 8);
1400 }
1401 flush_cached_frames ();
1402}
1403
1404static CORE_ADDR
1405sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1406{
1407 return sp & ~3;
1408}
1409
1410/* Function: push_arguments
1411 Setup the function arguments for calling a function in the inferior.
1412
85a453d5 1413 On the Renesas SH architecture, there are four registers (R4 to R7)
55ff77ac
CV		 1414 which are dedicated for passing function arguments. Up to the first
1415 four arguments (depending on size) may go into these registers.
1416 The rest go on the stack.
1417
1418 Arguments that are smaller than 4 bytes will still take up a whole
1419 register or a whole 32-bit word on the stack, and will be
1420 right-justified in the register or the stack word. This includes
1421 chars, shorts, and small aggregate types.
1422
1423 Arguments that are larger than 4 bytes may be split between two or
1424 more registers. If there are not enough registers free, an argument
1425 may be passed partly in a register (or registers), and partly on the
1426 stack. This includes doubles, long longs, and larger aggregates.
1427 As far as I know, there is no upper limit to the size of aggregates
1428 that will be passed in this way; in other words, the convention of
1429 passing a pointer to a large aggregate instead of a copy is not used.
1430
1431 An exceptional case exists for struct arguments (and possibly other
1432 aggregates such as arrays) if the size is larger than 4 bytes but
1433 not a multiple of 4 bytes. In this case the argument is never split
1434 between the registers and the stack, but instead is copied in its
1435 entirety onto the stack, AND also copied into as many registers as
1436 there is room for. In other words, space in registers permitting,
1437 two copies of the same argument are passed in. As far as I can tell,
1438 only the one on the stack is used, although that may be a function
1439 of the level of compiler optimization. I suspect this is a compiler
1440 bug. Arguments of these odd sizes are left-justified within the
1441 word (as opposed to arguments smaller than 4 bytes, which are
1442 right-justified).
1443
1444 If the function is to return an aggregate type such as a struct, it
1445 is either returned in the normal return value register R0 (if its
1446 size is no greater than one byte), or else the caller must allocate
1447 space into which the callee will copy the return value (if the size
1448 is greater than one byte). In this case, a pointer to the return
1449 value location is passed into the callee in register R2, which does
1450 not displace any of the other arguments passed in via registers R4
1451 to R7. */
1452
1453/* R2-R9 for integer types and integer equivalent (char, pointers) and
1454 non-scalar (struct, union) elements (even if the elements are
1455 floats).
1456 FR0-FR11 for single precision floating point (float)
1457 DR0-DR10 for double precision floating point (double)
1458
1459 If a float is argument number 3 (for instance) and arguments number
1460 1,2, and 4 are integer, the mapping will be:
1461 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1462
1463 If a float is argument number 10 (for instance) and arguments number
1464 1 through 10 are integer, the mapping will be:
1465 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1466 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1467 I.e. there is hole in the stack.
1468
1469 Different rules apply for variable arguments functions, and for functions
7bb11558 1470 for which the prototype is not known. */
55ff77ac
CV		 1471
1472static CORE_ADDR
1473sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1474 int struct_return, CORE_ADDR struct_addr)
1475{
1476 int stack_offset, stack_alloc;
1477 int int_argreg;
1478 int float_argreg;
1479 int double_argreg;
1480 int float_arg_index = 0;
1481 int double_arg_index = 0;
1482 int argnum;
1483 struct type *type;
1484 CORE_ADDR regval;
1485 char *val;
1486 char valbuf[8];
1487 char valbuf_tmp[8];
1488 int len;
1489 int argreg_size;
1490 int fp_args[12];
55ff77ac
CV		 1491
1492 memset (fp_args, 0, sizeof (fp_args));
1493
1494 /* first force sp to a 8-byte alignment */
1495 sp = sp & ~7;
1496
1497 /* The "struct return pointer" pseudo-argument has its own dedicated
1498 register */
1499
1500 if (struct_return)
1501 write_register (STRUCT_RETURN_REGNUM, struct_addr);
1502
1503 /* Now make sure there's space on the stack */
1504 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1505 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
1506 sp -= stack_alloc; /* make room on stack for args */
1507
1508 /* Now load as many as possible of the first arguments into
1509 registers, and push the rest onto the stack. There are 64 bytes
1510 in eight registers available. Loop thru args from first to last. */
1511
1512 int_argreg = ARG0_REGNUM;
1513 float_argreg = FP0_REGNUM;
1514 double_argreg = DR0_REGNUM;
1515
1516 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1517 {
1518 type = VALUE_TYPE (args[argnum]);
1519 len = TYPE_LENGTH (type);
1520 memset (valbuf, 0, sizeof (valbuf));
1521
1522 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1523 {
7bb11558 1524 argreg_size = register_size (current_gdbarch, int_argreg);
55ff77ac
CV		 1525
1526 if (len < argreg_size)
1527 {
1528 /* value gets right-justified in the register or stack word */
1529 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1530 memcpy (valbuf + argreg_size - len,
1531 (char *) VALUE_CONTENTS (args[argnum]), len);
1532 else
1533 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
1534
1535 val = valbuf;
1536 }
1537 else
1538 val = (char *) VALUE_CONTENTS (args[argnum]);
1539
1540 while (len > 0)
1541 {
1542 if (int_argreg > ARGLAST_REGNUM)
1543 {
1544 /* must go on the stack */
1545 write_memory (sp + stack_offset, val, argreg_size);
1546 stack_offset += 8;/*argreg_size;*/
1547 }
1548 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1549 That's because some *&^%$ things get passed on the stack
1550 AND in the registers! */
1551 if (int_argreg <= ARGLAST_REGNUM)
1552 {
1553 /* there's room in a register */
1554 regval = extract_unsigned_integer (val, argreg_size);
1555 write_register (int_argreg, regval);
1556 }
1557 /* Store the value 8 bytes at a time. This means that
1558 things larger than 8 bytes may go partly in registers
1559 and partly on the stack. FIXME: argreg is incremented
7bb11558 1560 before we use its size. */
55ff77ac
CV		 1561 len -= argreg_size;
1562 val += argreg_size;
1563 int_argreg++;
1564 }
1565 }
1566 else
1567 {
1568 val = (char *) VALUE_CONTENTS (args[argnum]);
1569 if (len == 4)
1570 {
1571 /* Where is it going to be stored? */
1572 while (fp_args[float_arg_index])
1573 float_arg_index ++;
1574
1575 /* Now float_argreg points to the register where it
1576 should be stored. Are we still within the allowed
1577 register set? */
1578 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1579 {
1580 /* Goes in FR0...FR11 */
1581 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
1582 val);
1583 fp_args[float_arg_index] = 1;
7bb11558 1584 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1585 int_argreg ++;
1586 }
1587 else
1588 ;
1589 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1590 necessary spilling on the stack. */
55ff77ac
CV		 1591
1592 }
1593 else if (len == 8)
1594 {
1595 /* Where is it going to be stored? */
1596 while (fp_args[double_arg_index])
1597 double_arg_index += 2;
1598 /* Now double_argreg points to the register
1599 where it should be stored.
1600 Are we still within the allowed register set? */
1601 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1602 {
1603 /* Goes in DR0...DR10 */
1604 /* The numbering of the DRi registers is consecutive,
7bb11558 1605 i.e. includes odd numbers. */
55ff77ac
CV		 1606 int double_register_offset = double_arg_index / 2;
1607 int regnum = DR0_REGNUM +
1608 double_register_offset;
1609#if 0
1610 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1611 {
1612 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
1613 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
1614 type, val,
1615 valbuf_tmp);
1616 val = valbuf_tmp;
1617 }
1618#endif
1619 /* Note: must use write_register_gen here instead
1620 of regcache_raw_write, because
1621 regcache_raw_write works only for real
1622 registers, not pseudo. write_register_gen will
1623 call the gdbarch function to do register
1624 writes, and that will properly know how to deal
7bb11558 1625 with pseudoregs. */
55ff77ac
CV		 1626 deprecated_write_register_gen (regnum, val);
1627 fp_args[double_arg_index] = 1;
1628 fp_args[double_arg_index + 1] = 1;
7bb11558 1629 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1630 int_argreg ++;
1631 }
1632 else
1633 ;
1634 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1635 necessary spilling on the stack. */
55ff77ac
CV		 1636 }
1637 }
1638 }
1639 return sp;
1640}
1641
1642/* Function: push_return_address (pc)
1643 Set up the return address for the inferior function call.
1644 Needed for targets where we don't actually execute a JSR/BSR instruction */
1645
1646static CORE_ADDR
1647sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1648{
e8a7b686 1649 write_register (PR_REGNUM, entry_point_address ());
55ff77ac
CV		 1650 return sp;
1651}
1652
1653/* Find a function's return value in the appropriate registers (in
1654 regbuf), and copy it into valbuf. Extract from an array REGBUF
1655 containing the (raw) register state a function return value of type
1656 TYPE, and copy that, in virtual format, into VALBUF. */
1657static void
1658sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1659{
1660 int offset;
1661 int return_register;
1662 int len = TYPE_LENGTH (type);
55ff77ac
CV		 1663
1664 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1665 {
1666 if (len == 4)
1667 {
1668 /* Return value stored in FP0_REGNUM */
1669 return_register = FP0_REGNUM;
62700349 1670 offset = DEPRECATED_REGISTER_BYTE (return_register);
7bb11558 1671 memcpy (valbuf, (char *) regbuf + offset, len);
55ff77ac
CV		 1672 }
1673 else if (len == 8)
1674 {
1675 /* return value stored in DR0_REGNUM */
1676 DOUBLEST val;
1677
1678 return_register = DR0_REGNUM;
62700349 1679 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1680
1681 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1682 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1683 (char *) regbuf + offset, &val);
1684 else
1685 floatformat_to_doublest (&floatformat_ieee_double_big,
1686 (char *) regbuf + offset, &val);
7bb11558 1687 store_typed_floating (valbuf, type, val);
55ff77ac
CV		 1688 }
1689 }
1690 else
1691 {
1692 if (len <= 8)
1693 {
1694 /* Result is in register 2. If smaller than 8 bytes, it is padded
7bb11558 1695 at the most significant end. */
55ff77ac
CV		 1696 return_register = DEFAULT_RETURN_REGNUM;
1697 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
62700349 1698 offset = DEPRECATED_REGISTER_BYTE (return_register) +
7bb11558 1699 register_size (current_gdbarch, return_register) - len;
55ff77ac 1700 else
62700349 1701 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1702 memcpy (valbuf, (char *) regbuf + offset, len);
1703 }
1704 else
1705 error ("bad size for return value");
1706 }
1707}
1708
1709/* Write into appropriate registers a function return value
1710 of type TYPE, given in virtual format.
1711 If the architecture is sh4 or sh3e, store a function's return value
1712 in the R0 general register or in the FP0 floating point register,
1713 depending on the type of the return value. In all the other cases
7bb11558 1714 the result is stored in r0, left-justified. */
55ff77ac
CV		 1715
1716static void
1717sh64_store_return_value (struct type *type, char *valbuf)
1718{
7bb11558 1719 char buf[64]; /* more than enough... */
55ff77ac
CV		 1720 int len = TYPE_LENGTH (type);
1721
1722 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1723 {
1724 if (len == 4)
1725 {
1726 /* Return value stored in FP0_REGNUM */
1727 deprecated_write_register_gen (FP0_REGNUM, valbuf);
1728 }
1729 if (len == 8)
1730 {
1731 /* return value stored in DR0_REGNUM */
1732 /* FIXME: Implement */
1733 }
1734 }
1735 else
1736 {
1737 int return_register = DEFAULT_RETURN_REGNUM;
1738 int offset = 0;
1739
7bb11558 1740 if (len <= register_size (current_gdbarch, return_register))
55ff77ac 1741 {
7bb11558
MS		 1742 /* Pad with zeros. */
1743 memset (buf, 0, register_size (current_gdbarch, return_register));
55ff77ac 1744 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
7bb11558
MS		 1745 offset = 0; /*register_size (current_gdbarch,
1746 return_register) - len;*/
55ff77ac 1747 else
7bb11558 1748 offset = register_size (current_gdbarch, return_register) - len;
55ff77ac
CV		 1749
1750 memcpy (buf + offset, valbuf, len);
1751 deprecated_write_register_gen (return_register, buf);
1752 }
1753 else
1754 deprecated_write_register_gen (return_register, valbuf);
1755 }
1756}
1757
1758static void
1759sh64_show_media_regs (void)
1760{
1761 int i;
55ff77ac
CV		 1762
1763 printf_filtered ("PC=%s SR=%016llx \n",
1764 paddr (read_register (PC_REGNUM)),
1765 (long long) read_register (SR_REGNUM));
1766
1767 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1768 (long long) read_register (SSR_REGNUM),
1769 (long long) read_register (SPC_REGNUM));
1770 printf_filtered ("FPSCR=%016lx\n ",
1771 (long) read_register (FPSCR_REGNUM));
1772
1773 for (i = 0; i < 64; i = i + 4)
1774 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1775 i, i + 3,
1776 (long long) read_register (i + 0),
1777 (long long) read_register (i + 1),
1778 (long long) read_register (i + 2),
1779 (long long) read_register (i + 3));
1780
1781 printf_filtered ("\n");
1782
1783 for (i = 0; i < 64; i = i + 8)
1784 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1785 i, i + 7,
1786 (long) read_register (FP0_REGNUM + i + 0),
1787 (long) read_register (FP0_REGNUM + i + 1),
1788 (long) read_register (FP0_REGNUM + i + 2),
1789 (long) read_register (FP0_REGNUM + i + 3),
1790 (long) read_register (FP0_REGNUM + i + 4),
1791 (long) read_register (FP0_REGNUM + i + 5),
1792 (long) read_register (FP0_REGNUM + i + 6),
1793 (long) read_register (FP0_REGNUM + i + 7));
1794}
1795
1796static void
1797sh64_show_compact_regs (void)
1798{
1799 int i;
55ff77ac
CV		 1800
1801 printf_filtered ("PC=%s \n",
1802 paddr (read_register (PC_C_REGNUM)));
1803
1804 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1805 (long) read_register (GBR_C_REGNUM),
1806 (long) read_register (MACH_C_REGNUM),
1807 (long) read_register (MACL_C_REGNUM),
1808 (long) read_register (PR_C_REGNUM),
1809 (long) read_register (T_C_REGNUM));
1810 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1811 (long) read_register (FPSCR_C_REGNUM),
1812 (long) read_register (FPUL_C_REGNUM));
1813
1814 for (i = 0; i < 16; i = i + 4)
1815 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1816 i, i + 3,
1817 (long) read_register (i + 0),
1818 (long) read_register (i + 1),
1819 (long) read_register (i + 2),
1820 (long) read_register (i + 3));
1821
1822 printf_filtered ("\n");
1823
1824 for (i = 0; i < 16; i = i + 8)
1825 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1826 i, i + 7,
1827 (long) read_register (FP0_REGNUM + i + 0),
1828 (long) read_register (FP0_REGNUM + i + 1),
1829 (long) read_register (FP0_REGNUM + i + 2),
1830 (long) read_register (FP0_REGNUM + i + 3),
1831 (long) read_register (FP0_REGNUM + i + 4),
1832 (long) read_register (FP0_REGNUM + i + 5),
1833 (long) read_register (FP0_REGNUM + i + 6),
1834 (long) read_register (FP0_REGNUM + i + 7));
1835}
1836
7bb11558
MS		 1837/* FIXME!!! This only shows the registers for shmedia, excluding the
1838 pseudo registers. */
55ff77ac
CV		 1839void
1840sh64_show_regs (void)
1841{
1842 if (deprecated_selected_frame
1843 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1844 sh64_show_media_regs ();
1845 else
1846 sh64_show_compact_regs ();
1847}
1848
1849/* *INDENT-OFF* */
1850/*
1851 SH MEDIA MODE (ISA 32)
1852 general registers (64-bit) 0-63
18530 r0, r1, r2, r3, r4, r5, r6, r7,
185464 r8, r9, r10, r11, r12, r13, r14, r15,
1855128 r16, r17, r18, r19, r20, r21, r22, r23,
1856192 r24, r25, r26, r27, r28, r29, r30, r31,
1857256 r32, r33, r34, r35, r36, r37, r38, r39,
1858320 r40, r41, r42, r43, r44, r45, r46, r47,
1859384 r48, r49, r50, r51, r52, r53, r54, r55,
1860448 r56, r57, r58, r59, r60, r61, r62, r63,
1861
1862 pc (64-bit) 64
1863512 pc,
1864
1865 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1866520 sr, ssr, spc,
1867
1868 target registers (64-bit) 68-75
1869544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1870
1871 floating point state control register (32-bit) 76
1872608 fpscr,
1873
1874 single precision floating point registers (32-bit) 77-140
1875612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1876644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1877676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1878708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1879740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1880772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1881804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1882836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1883
1884TOTAL SPACE FOR REGISTERS: 868 bytes
1885
1886From here on they are all pseudo registers: no memory allocated.
1887REGISTER_BYTE returns the register byte for the base register.
1888
1889 double precision registers (pseudo) 141-172
1890 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1891 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1892 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1893 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1894
1895 floating point pairs (pseudo) 173-204
1896 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1897 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1898 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1899 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1900
1901 floating point vectors (4 floating point regs) (pseudo) 205-220
1902 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1903 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1904
1905 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1906 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1907 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1908 pc_c,
1909 gbr_c, mach_c, macl_c, pr_c, t_c,
1910 fpscr_c, fpul_c,
1911 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1912 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1913 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1914 fv0_c, fv4_c, fv8_c, fv12_c
1915*/
1916/* *INDENT-ON* */
1917static int
39add00a 1918sh64_register_byte (int reg_nr)
55ff77ac
CV		 1919{
1920 int base_regnum = -1;
55ff77ac
CV		 1921
1922 /* If it is a pseudo register, get the number of the first floating
7bb11558 1923 point register that is part of it. */
55ff77ac
CV		 1924 if (reg_nr >= DR0_REGNUM
1925 && reg_nr <= DR_LAST_REGNUM)
1926 base_regnum = dr_reg_base_num (reg_nr);
1927
1928 else if (reg_nr >= FPP0_REGNUM
1929 && reg_nr <= FPP_LAST_REGNUM)
1930 base_regnum = fpp_reg_base_num (reg_nr);
1931
1932 else if (reg_nr >= FV0_REGNUM
1933 && reg_nr <= FV_LAST_REGNUM)
1934 base_regnum = fv_reg_base_num (reg_nr);
1935
1936 /* sh compact pseudo register. FPSCR is a pathological case, need to
7bb11558 1937 treat it as special. */
55ff77ac
CV		 1938 else if ((reg_nr >= R0_C_REGNUM
1939 && reg_nr <= FV_LAST_C_REGNUM)
1940 && reg_nr != FPSCR_C_REGNUM)
1941 base_regnum = sh64_compact_reg_base_num (reg_nr);
1942
7bb11558
MS		 1943 /* Now return the offset in bytes within the register cache. */
1944 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
55ff77ac
CV		 1945 if (reg_nr >= DR0_REGNUM
1946 && reg_nr <= FV_LAST_REGNUM)
1947 return (base_regnum - FP0_REGNUM + 1) * 4
1948 + (TR7_REGNUM + 1) * 8;
1949
1950 /* sh compact pseudo register: general register */
1951 if ((reg_nr >= R0_C_REGNUM
1952 && reg_nr <= R_LAST_C_REGNUM))
1953 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1954 ? base_regnum * 8 + 4
1955 : base_regnum * 8);
1956
1957 /* sh compact pseudo register: */
1958 if (reg_nr == PC_C_REGNUM
1959 || reg_nr == GBR_C_REGNUM
1960 || reg_nr == MACL_C_REGNUM
1961 || reg_nr == PR_C_REGNUM)
1962 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1963 ? base_regnum * 8 + 4
1964 : base_regnum * 8);
1965
1966 if (reg_nr == MACH_C_REGNUM)
1967 return base_regnum * 8;
1968
1969 if (reg_nr == T_C_REGNUM)
1970 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
1971
1972 /* sh compact pseudo register: floating point register */
1973 else if (reg_nr >= FP0_C_REGNUM
1974 && reg_nr <= FV_LAST_C_REGNUM)
1975 return (base_regnum - FP0_REGNUM) * 4
1976 + (TR7_REGNUM + 1) * 8 + 4;
1977
1978 else if (reg_nr == FPSCR_C_REGNUM)
1979 /* This is complicated, for now return the beginning of the
7bb11558 1980 architectural FPSCR register. */
55ff77ac
CV		 1981 return (TR7_REGNUM + 1) * 8;
1982
1983 else if (reg_nr == FPUL_C_REGNUM)
1984 return ((base_regnum - FP0_REGNUM) * 4 +
1985 (TR7_REGNUM + 1) * 8 + 4);
1986
7bb11558
MS		 1987 /* It is not a pseudo register. */
1988 /* It is a 64 bit register. */
55ff77ac
CV		 1989 else if (reg_nr <= TR7_REGNUM)
1990 return reg_nr * 8;
1991
7bb11558 1992 /* It is a 32 bit register. */
55ff77ac
CV		 1993 else if (reg_nr == FPSCR_REGNUM)
1994 return (FPSCR_REGNUM * 8);
1995
1996 /* It is floating point 32-bit register */
1997 else
1998 return ((TR7_REGNUM + 1) * 8
1999 + (reg_nr - FP0_REGNUM + 1) * 4);
2000}
2001
55ff77ac 2002static struct type *
39add00a 2003sh64_build_float_register_type (int high)
55ff77ac
CV		 2004{
2005 struct type *temp;
2006
2007 temp = create_range_type (NULL, builtin_type_int, 0, high);
2008 return create_array_type (NULL, builtin_type_float, temp);
2009}
2010
7bb11558
MS		 2011/* Return the GDB type object for the "standard" data type
2012 of data in register REG_NR. */
55ff77ac 2013static struct type *
7bb11558 2014sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
55ff77ac 2015{
55ff77ac
CV		 2016 if ((reg_nr >= FP0_REGNUM
2017 && reg_nr <= FP_LAST_REGNUM)
2018 || (reg_nr >= FP0_C_REGNUM
2019 && reg_nr <= FP_LAST_C_REGNUM))
2020 return builtin_type_float;
2021 else if ((reg_nr >= DR0_REGNUM
2022 && reg_nr <= DR_LAST_REGNUM)
2023 || (reg_nr >= DR0_C_REGNUM
2024 && reg_nr <= DR_LAST_C_REGNUM))
2025 return builtin_type_double;
2026 else if (reg_nr >= FPP0_REGNUM
2027 && reg_nr <= FPP_LAST_REGNUM)
39add00a 2028 return sh64_build_float_register_type (1);
55ff77ac
CV		 2029 else if ((reg_nr >= FV0_REGNUM
2030 && reg_nr <= FV_LAST_REGNUM)
2031 ||(reg_nr >= FV0_C_REGNUM
2032 && reg_nr <= FV_LAST_C_REGNUM))
39add00a 2033 return sh64_build_float_register_type (3);
55ff77ac
CV		 2034 else if (reg_nr == FPSCR_REGNUM)
2035 return builtin_type_int;
2036 else if (reg_nr >= R0_C_REGNUM
2037 && reg_nr < FP0_C_REGNUM)
2038 return builtin_type_int;
2039 else
2040 return builtin_type_long_long;
2041}
2042
2043static void
39add00a 2044sh64_register_convert_to_virtual (int regnum, struct type *type,
55ff77ac
CV		 2045 char *from, char *to)
2046{
55ff77ac
CV		 2047 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2048 {
7bb11558
MS		 2049 /* It is a no-op. */
2050 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2051 return;
2052 }
2053
2054 if ((regnum >= DR0_REGNUM
2055 && regnum <= DR_LAST_REGNUM)
2056 || (regnum >= DR0_C_REGNUM
2057 && regnum <= DR_LAST_C_REGNUM))
2058 {
2059 DOUBLEST val;
7bb11558
MS		 2060 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2061 from, &val);
39add00a 2062 store_typed_floating (to, type, val);
55ff77ac
CV		 2063 }
2064 else
39add00a 2065 error ("sh64_register_convert_to_virtual called with non DR register number");
55ff77ac
CV		 2066}
2067
2068static void
39add00a 2069sh64_register_convert_to_raw (struct type *type, int regnum,
55ff77ac
CV		 2070 const void *from, void *to)
2071{
55ff77ac
CV		 2072 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2073 {
7bb11558
MS		 2074 /* It is a no-op. */
2075 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2076 return;
2077 }
2078
2079 if ((regnum >= DR0_REGNUM
2080 && regnum <= DR_LAST_REGNUM)
2081 || (regnum >= DR0_C_REGNUM
2082 && regnum <= DR_LAST_C_REGNUM))
2083 {
2084 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
7bb11558
MS		 2085 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2086 &val, to);
55ff77ac
CV		 2087 }
2088 else
39add00a 2089 error ("sh64_register_convert_to_raw called with non DR register number");
55ff77ac
CV		 2090}
2091
2092static void
2093sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2094 int reg_nr, void *buffer)
2095{
2096 int base_regnum;
2097 int portion;
2098 int offset = 0;
2099 char temp_buffer[MAX_REGISTER_SIZE];
55ff77ac
CV		 2100
2101 if (reg_nr >= DR0_REGNUM
2102 && reg_nr <= DR_LAST_REGNUM)
2103 {
2104 base_regnum = dr_reg_base_num (reg_nr);
2105
7bb11558 2106 /* Build the value in the provided buffer. */
55ff77ac 2107 /* DR regs are double precision registers obtained by
7bb11558 2108 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2109 for (portion = 0; portion < 2; portion++)
2110 regcache_raw_read (regcache, base_regnum + portion,
2111 (temp_buffer
7bb11558 2112 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2113
7bb11558 2114 /* We must pay attention to the endianness. */
39add00a
MS		 2115 sh64_register_convert_to_virtual (reg_nr,
2116 gdbarch_register_type (gdbarch,
2117 reg_nr),
2118 temp_buffer, buffer);
55ff77ac
CV		 2119
2120 }
2121
2122 else if (reg_nr >= FPP0_REGNUM
2123 && reg_nr <= FPP_LAST_REGNUM)
2124 {
2125 base_regnum = fpp_reg_base_num (reg_nr);
2126
7bb11558 2127 /* Build the value in the provided buffer. */
55ff77ac 2128 /* FPP regs are pairs of single precision registers obtained by
7bb11558 2129 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2130 for (portion = 0; portion < 2; portion++)
2131 regcache_raw_read (regcache, base_regnum + portion,
2132 ((char *) buffer
7bb11558 2133 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2134 }
2135
2136 else if (reg_nr >= FV0_REGNUM
2137 && reg_nr <= FV_LAST_REGNUM)
2138 {
2139 base_regnum = fv_reg_base_num (reg_nr);
2140
7bb11558 2141 /* Build the value in the provided buffer. */
55ff77ac 2142 /* FV regs are vectors of single precision registers obtained by
7bb11558 2143 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2144 for (portion = 0; portion < 4; portion++)
2145 regcache_raw_read (regcache, base_regnum + portion,
2146 ((char *) buffer
7bb11558 2147 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2148 }
2149
2150 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
2151 else if (reg_nr >= R0_C_REGNUM
2152 && reg_nr <= T_C_REGNUM)
2153 {
2154 base_regnum = sh64_compact_reg_base_num (reg_nr);
2155
7bb11558 2156 /* Build the value in the provided buffer. */
55ff77ac
CV		 2157 regcache_raw_read (regcache, base_regnum, temp_buffer);
2158 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2159 offset = 4;
2160 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
2161 }
2162
2163 else if (reg_nr >= FP0_C_REGNUM
2164 && reg_nr <= FP_LAST_C_REGNUM)
2165 {
2166 base_regnum = sh64_compact_reg_base_num (reg_nr);
2167
7bb11558 2168 /* Build the value in the provided buffer. */
55ff77ac 2169 /* Floating point registers map 1-1 to the media fp regs,
7bb11558 2170 they have the same size and endianness. */
55ff77ac
CV		 2171 regcache_raw_read (regcache, base_regnum, buffer);
2172 }
2173
2174 else if (reg_nr >= DR0_C_REGNUM
2175 && reg_nr <= DR_LAST_C_REGNUM)
2176 {
2177 base_regnum = sh64_compact_reg_base_num (reg_nr);
2178
2179 /* DR_C regs are double precision registers obtained by
7bb11558 2180 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2181 for (portion = 0; portion < 2; portion++)
2182 regcache_raw_read (regcache, base_regnum + portion,
2183 (temp_buffer
7bb11558 2184 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2185
7bb11558 2186 /* We must pay attention to the endianness. */
39add00a
MS		 2187 sh64_register_convert_to_virtual (reg_nr,
2188 gdbarch_register_type (gdbarch,
2189 reg_nr),
2190 temp_buffer, buffer);
55ff77ac
CV		 2191 }
2192
2193 else if (reg_nr >= FV0_C_REGNUM
2194 && reg_nr <= FV_LAST_C_REGNUM)
2195 {
2196 base_regnum = sh64_compact_reg_base_num (reg_nr);
2197
7bb11558 2198 /* Build the value in the provided buffer. */
55ff77ac 2199 /* FV_C regs are vectors of single precision registers obtained by
7bb11558 2200 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2201 for (portion = 0; portion < 4; portion++)
2202 regcache_raw_read (regcache, base_regnum + portion,
2203 ((char *) buffer
7bb11558 2204 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2205 }
2206
2207 else if (reg_nr == FPSCR_C_REGNUM)
2208 {
2209 int fpscr_base_regnum;
2210 int sr_base_regnum;
2211 unsigned int fpscr_value;
2212 unsigned int sr_value;
2213 unsigned int fpscr_c_value;
2214 unsigned int fpscr_c_part1_value;
2215 unsigned int fpscr_c_part2_value;
2216
2217 fpscr_base_regnum = FPSCR_REGNUM;
2218 sr_base_regnum = SR_REGNUM;
2219
7bb11558 2220 /* Build the value in the provided buffer. */
55ff77ac
CV		 2221 /* FPSCR_C is a very weird register that contains sparse bits
2222 from the FPSCR and the SR architectural registers.
2223 Specifically: */
2224 /* *INDENT-OFF* */
2225 /*
2226 FPSRC_C bit
2227 0 Bit 0 of FPSCR
2228 1 reserved
2229 2-17 Bit 2-18 of FPSCR
2230 18-20 Bits 12,13,14 of SR
2231 21-31 reserved
2232 */
2233 /* *INDENT-ON* */
2234 /* Get FPSCR into a local buffer */
2235 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
7bb11558 2236 /* Get value as an int. */
55ff77ac
CV		 2237 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2238 /* Get SR into a local buffer */
2239 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
7bb11558 2240 /* Get value as an int. */
55ff77ac 2241 sr_value = extract_unsigned_integer (temp_buffer, 4);
7bb11558 2242 /* Build the new value. */
55ff77ac
CV		 2243 fpscr_c_part1_value = fpscr_value & 0x3fffd;
2244 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
2245 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
2246 /* Store that in out buffer!!! */
2247 store_unsigned_integer (buffer, 4, fpscr_c_value);
7bb11558 2248 /* FIXME There is surely an endianness gotcha here. */
55ff77ac
CV		 2249 }
2250
2251 else if (reg_nr == FPUL_C_REGNUM)
2252 {
2253 base_regnum = sh64_compact_reg_base_num (reg_nr);
2254
2255 /* FPUL_C register is floating point register 32,
7bb11558 2256 same size, same endianness. */
55ff77ac
CV		 2257 regcache_raw_read (regcache, base_regnum, buffer);
2258 }
2259}
2260
2261static void
2262sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2263 int reg_nr, const void *buffer)
2264{
2265 int base_regnum, portion;
2266 int offset;
2267 char temp_buffer[MAX_REGISTER_SIZE];
55ff77ac
CV		 2268
2269 if (reg_nr >= DR0_REGNUM
2270 && reg_nr <= DR_LAST_REGNUM)
2271 {
2272 base_regnum = dr_reg_base_num (reg_nr);
7bb11558 2273 /* We must pay attention to the endianness. */
39add00a
MS		 2274 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
2275 reg_nr,
2276 buffer, temp_buffer);
55ff77ac
CV		 2277
2278 /* Write the real regs for which this one is an alias. */
2279 for (portion = 0; portion < 2; portion++)
2280 regcache_raw_write (regcache, base_regnum + portion,
2281 (temp_buffer
7bb11558
MS		 2282 + register_size (gdbarch,
2283 base_regnum) * portion));
55ff77ac
CV		 2284 }
2285
2286 else if (reg_nr >= FPP0_REGNUM
2287 && reg_nr <= FPP_LAST_REGNUM)
2288 {
2289 base_regnum = fpp_reg_base_num (reg_nr);
2290
2291 /* Write the real regs for which this one is an alias. */
2292 for (portion = 0; portion < 2; portion++)
2293 regcache_raw_write (regcache, base_regnum + portion,
2294 ((char *) buffer
7bb11558
MS		 2295 + register_size (gdbarch,
2296 base_regnum) * portion));
55ff77ac
CV		 2297 }
2298
2299 else if (reg_nr >= FV0_REGNUM
2300 && reg_nr <= FV_LAST_REGNUM)
2301 {
2302 base_regnum = fv_reg_base_num (reg_nr);
2303
2304 /* Write the real regs for which this one is an alias. */
2305 for (portion = 0; portion < 4; portion++)
2306 regcache_raw_write (regcache, base_regnum + portion,
2307 ((char *) buffer
7bb11558
MS		 2308 + register_size (gdbarch,
2309 base_regnum) * portion));
55ff77ac
CV		 2310 }
2311
2312 /* sh compact general pseudo registers. 1-to-1 with a shmedia
2313 register but only 4 bytes of it. */
2314 else if (reg_nr >= R0_C_REGNUM
2315 && reg_nr <= T_C_REGNUM)
2316 {
2317 base_regnum = sh64_compact_reg_base_num (reg_nr);
7bb11558 2318 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
55ff77ac
CV		 2319 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2320 offset = 4;
2321 else
2322 offset = 0;
2323 /* Let's read the value of the base register into a temporary
2324 buffer, so that overwriting the last four bytes with the new
7bb11558 2325 value of the pseudo will leave the upper 4 bytes unchanged. */
55ff77ac
CV		 2326 regcache_raw_read (regcache, base_regnum, temp_buffer);
2327 /* Write as an 8 byte quantity */
2328 memcpy (temp_buffer + offset, buffer, 4);
2329 regcache_raw_write (regcache, base_regnum, temp_buffer);
2330 }
2331
2332 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
7bb11558 2333 registers. Both are 4 bytes. */
55ff77ac
CV		 2334 else if (reg_nr >= FP0_C_REGNUM
2335 && reg_nr <= FP_LAST_C_REGNUM)
2336 {
2337 base_regnum = sh64_compact_reg_base_num (reg_nr);
2338 regcache_raw_write (regcache, base_regnum, buffer);
2339 }
2340
2341 else if (reg_nr >= DR0_C_REGNUM
2342 && reg_nr <= DR_LAST_C_REGNUM)
2343 {
2344 base_regnum = sh64_compact_reg_base_num (reg_nr);
2345 for (portion = 0; portion < 2; portion++)
2346 {
7bb11558 2347 /* We must pay attention to the endianness. */
39add00a
MS		 2348 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2349 reg_nr),
2350 reg_nr,
2351 buffer, temp_buffer);
55ff77ac
CV		 2352
2353 regcache_raw_write (regcache, base_regnum + portion,
2354 (temp_buffer
7bb11558
MS		 2355 + register_size (gdbarch,
2356 base_regnum) * portion));
55ff77ac
CV		 2357 }
2358 }
2359
2360 else if (reg_nr >= FV0_C_REGNUM
2361 && reg_nr <= FV_LAST_C_REGNUM)
2362 {
2363 base_regnum = sh64_compact_reg_base_num (reg_nr);
2364
2365 for (portion = 0; portion < 4; portion++)
2366 {
2367 regcache_raw_write (regcache, base_regnum + portion,
2368 ((char *) buffer
7bb11558
MS		 2369 + register_size (gdbarch,
2370 base_regnum) * portion));
55ff77ac
CV		 2371 }
2372 }
2373
2374 else if (reg_nr == FPSCR_C_REGNUM)
2375 {
2376 int fpscr_base_regnum;
2377 int sr_base_regnum;
2378 unsigned int fpscr_value;
2379 unsigned int sr_value;
2380 unsigned int old_fpscr_value;
2381 unsigned int old_sr_value;
2382 unsigned int fpscr_c_value;
2383 unsigned int fpscr_mask;
2384 unsigned int sr_mask;
2385
2386 fpscr_base_regnum = FPSCR_REGNUM;
2387 sr_base_regnum = SR_REGNUM;
2388
2389 /* FPSCR_C is a very weird register that contains sparse bits
2390 from the FPSCR and the SR architectural registers.
2391 Specifically: */
2392 /* *INDENT-OFF* */
2393 /*
2394 FPSRC_C bit
2395 0 Bit 0 of FPSCR
2396 1 reserved
2397 2-17 Bit 2-18 of FPSCR
2398 18-20 Bits 12,13,14 of SR
2399 21-31 reserved
2400 */
2401 /* *INDENT-ON* */
7bb11558 2402 /* Get value as an int. */
55ff77ac
CV		 2403 fpscr_c_value = extract_unsigned_integer (buffer, 4);
2404
7bb11558 2405 /* Build the new values. */
55ff77ac
CV		 2406 fpscr_mask = 0x0003fffd;
2407 sr_mask = 0x001c0000;
2408
2409 fpscr_value = fpscr_c_value & fpscr_mask;
2410 sr_value = (fpscr_value & sr_mask) >> 6;
2411
2412 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2413 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2414 old_fpscr_value &= 0xfffc0002;
2415 fpscr_value |= old_fpscr_value;
2416 store_unsigned_integer (temp_buffer, 4, fpscr_value);
2417 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
2418
2419 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2420 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
2421 old_sr_value &= 0xffff8fff;
2422 sr_value |= old_sr_value;
2423 store_unsigned_integer (temp_buffer, 4, sr_value);
2424 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
2425 }
2426
2427 else if (reg_nr == FPUL_C_REGNUM)
2428 {
2429 base_regnum = sh64_compact_reg_base_num (reg_nr);
2430 regcache_raw_write (regcache, base_regnum, buffer);
2431 }
2432}
2433
7bb11558 2434/* Floating point vector of 4 float registers. */
55ff77ac
CV		 2435static void
2436do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2437 int fv_regnum)
2438{
2439 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
2440 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2441 fv_regnum - FV0_REGNUM,
2442 (int) read_register (first_fp_reg_num),
2443 (int) read_register (first_fp_reg_num + 1),
2444 (int) read_register (first_fp_reg_num + 2),
2445 (int) read_register (first_fp_reg_num + 3));
2446}
2447
7bb11558 2448/* Floating point vector of 4 float registers, compact mode. */
55ff77ac
CV		 2449static void
2450do_fv_c_register_info (int fv_regnum)
2451{
2452 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
2453 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2454 fv_regnum - FV0_C_REGNUM,
2455 (int) read_register (first_fp_reg_num),
2456 (int) read_register (first_fp_reg_num + 1),
2457 (int) read_register (first_fp_reg_num + 2),
2458 (int) read_register (first_fp_reg_num + 3));
2459}
2460
2461/* Pairs of single regs. The DR are instead double precision
7bb11558 2462 registers. */
55ff77ac
CV		 2463static void
2464do_fpp_register_info (int fpp_regnum)
2465{
2466 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
2467
2468 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
2469 fpp_regnum - FPP0_REGNUM,
2470 (int) read_register (first_fp_reg_num),
2471 (int) read_register (first_fp_reg_num + 1));
2472}
2473
7bb11558 2474/* Double precision registers. */
55ff77ac
CV		 2475static void
2476do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2477 int dr_regnum)
2478{
2479 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
2480
2481 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
2482 dr_regnum - DR0_REGNUM,
2483 (int) read_register (first_fp_reg_num),
2484 (int) read_register (first_fp_reg_num + 1));
2485}
2486
7bb11558 2487/* Double precision registers, compact mode. */
55ff77ac
CV		 2488static void
2489do_dr_c_register_info (int dr_regnum)
2490{
2491 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
2492
2493 printf_filtered ("dr%d_c\t0x%08x%08x\n",
2494 dr_regnum - DR0_C_REGNUM,
2495 (int) read_register (first_fp_reg_num),
2496 (int) read_register (first_fp_reg_num +1));
2497}
2498
7bb11558 2499/* General register in compact mode. */
55ff77ac
CV		 2500static void
2501do_r_c_register_info (int r_c_regnum)
2502{
2503 int regnum = sh64_compact_reg_base_num (r_c_regnum);
2504
2505 printf_filtered ("r%d_c\t0x%08x\n",
2506 r_c_regnum - R0_C_REGNUM,
2507 /*FIXME!!!*/ (int) read_register (regnum));
2508}
2509
2510/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
7bb11558
MS		 2511 shmedia REGISTERS. */
2512/* Control registers, compact mode. */
55ff77ac
CV		 2513static void
2514do_cr_c_register_info (int cr_c_regnum)
2515{
2516 switch (cr_c_regnum)
2517 {
2518 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2519 break;
2520 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2521 break;
2522 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2523 break;
2524 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2525 break;
2526 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2527 break;
2528 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2529 break;
2530 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2531 break;
2532 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
2533 break;
2534 }
2535}
2536
2537static void
2538sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2539{ /* do values for FP (float) regs */
2540 char *raw_buffer;
2541 double flt; /* double extracted from raw hex data */
2542 int inv;
2543 int j;
2544
7bb11558 2545 /* Allocate space for the float. */
55ff77ac
CV		 2546 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2547
2548 /* Get the data in raw format. */
2549 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2550 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2551
2552 /* Get the register as a number */
2553 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2554
7bb11558 2555 /* Print the name and some spaces. */
55ff77ac
CV		 2556 fputs_filtered (REGISTER_NAME (regnum), file);
2557 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2558
7bb11558 2559 /* Print the value. */
55ff77ac
CV		 2560 if (inv)
2561 fprintf_filtered (file, "<invalid float>");
2562 else
2563 fprintf_filtered (file, "%-10.9g", flt);
2564
7bb11558 2565 /* Print the fp register as hex. */
55ff77ac
CV		 2566 fprintf_filtered (file, "\t(raw 0x");
2567 for (j = 0; j < register_size (gdbarch, regnum); j++)
2568 {
aa1ee363 2569 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
55ff77ac
CV		 2570 : register_size (gdbarch, regnum) - 1 - j;
2571 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2572 }
2573 fprintf_filtered (file, ")");
2574 fprintf_filtered (file, "\n");
2575}
2576
2577static void
2578sh64_do_pseudo_register (int regnum)
2579{
7bb11558 2580 /* All the sh64-compact mode registers are pseudo registers. */
55ff77ac
CV		 2581
2582 if (regnum < NUM_REGS
2583 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
2584 internal_error (__FILE__, __LINE__,
2585 "Invalid pseudo register number %d\n", regnum);
2586
2587 else if ((regnum >= DR0_REGNUM
2588 && regnum <= DR_LAST_REGNUM))
2589 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
2590
2591 else if ((regnum >= DR0_C_REGNUM
2592 && regnum <= DR_LAST_C_REGNUM))
2593 do_dr_c_register_info (regnum);
2594
2595 else if ((regnum >= FV0_REGNUM
2596 && regnum <= FV_LAST_REGNUM))
2597 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
2598
2599 else if ((regnum >= FV0_C_REGNUM
2600 && regnum <= FV_LAST_C_REGNUM))
2601 do_fv_c_register_info (regnum);
2602
2603 else if (regnum >= FPP0_REGNUM
2604 && regnum <= FPP_LAST_REGNUM)
2605 do_fpp_register_info (regnum);
2606
2607 else if (regnum >= R0_C_REGNUM
2608 && regnum <= R_LAST_C_REGNUM)
7bb11558
MS		 2609 /* FIXME, this function will not print the right format. */
2610 do_r_c_register_info (regnum);
55ff77ac
CV		 2611 else if (regnum >= FP0_C_REGNUM
2612 && regnum <= FP_LAST_C_REGNUM)
7bb11558
MS		 2613 /* This should work also for pseudoregs. */
2614 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum);
55ff77ac
CV		 2615 else if (regnum >= PC_C_REGNUM
2616 && regnum <= FPUL_C_REGNUM)
2617 do_cr_c_register_info (regnum);
55ff77ac
CV		 2618}
2619
2620static void
2621sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2622{
2623 char raw_buffer[MAX_REGISTER_SIZE];
2624
2625 fputs_filtered (REGISTER_NAME (regnum), file);
2626 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2627
2628 /* Get the data in raw format. */
2629 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2630 fprintf_filtered (file, "*value not available*\n");
2631
2632 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2633 file, 'x', 1, 0, Val_pretty_default);
2634 fprintf_filtered (file, "\t");
2635 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2636 file, 0, 1, 0, Val_pretty_default);
2637 fprintf_filtered (file, "\n");
2638}
2639
2640static void
2641sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2642{
2643 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2644 internal_error (__FILE__, __LINE__,
2645 "Invalid register number %d\n", regnum);
2646
2647 else if (regnum >= 0 && regnum < NUM_REGS)
2648 {
2649 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2650 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2651 else
2652 sh_do_register (gdbarch, file, regnum); /* All other regs */
2653 }
2654
2655 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2656 sh64_do_pseudo_register (regnum);
2657}
2658
2659static void
2660sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2661 struct frame_info *frame, int regnum, int fpregs)
2662{
2663 if (regnum != -1) /* do one specified register */
2664 {
2665 if (*(REGISTER_NAME (regnum)) == '\0')
2666 error ("Not a valid register for the current processor type");
2667
2668 sh_print_register (gdbarch, file, regnum);
2669 }
2670 else
2671 /* do all (or most) registers */
2672 {
2673 regnum = 0;
2674 while (regnum < NUM_REGS)
2675 {
2676 /* If the register name is empty, it is undefined for this
2677 processor, so don't display anything. */
2678 if (REGISTER_NAME (regnum) == NULL
2679 || *(REGISTER_NAME (regnum)) == '\0')
2680 {
2681 regnum++;
2682 continue;
2683 }
2684
2685 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2686 {
2687 if (fpregs)
2688 {
2689 /* true for "INFO ALL-REGISTERS" command */
2690 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2691 regnum ++;
2692 }
2693 else
2694 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2695 }
2696 else
2697 {
2698 sh_do_register (gdbarch, file, regnum); /* All other regs */
2699 regnum++;
2700 }
2701 }
2702
2703 if (fpregs)
2704 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2705 {
2706 sh64_do_pseudo_register (regnum);
2707 regnum++;
2708 }
2709 }
2710}
2711
2712static void
2713sh_compact_do_registers_info (int regnum, int fpregs)
2714{
55ff77ac
CV		 2715 if (regnum != -1) /* do one specified register */
2716 {
2717 if (*(REGISTER_NAME (regnum)) == '\0')
2718 error ("Not a valid register for the current processor type");
2719
2720 if (regnum >= 0 && regnum < R0_C_REGNUM)
2721 error ("Not a valid register for the current processor mode.");
2722
2723 sh_print_register (current_gdbarch, gdb_stdout, regnum);
2724 }
2725 else
2726 /* do all compact registers */
2727 {
2728 regnum = R0_C_REGNUM;
2729 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2730 {
2731 sh64_do_pseudo_register (regnum);
2732 regnum++;
2733 }
2734 }
2735}
2736
2737static void
2738sh64_do_registers_info (int regnum, int fpregs)
2739{
2740 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2741 sh_print_registers_info (current_gdbarch, gdb_stdout,
2742 deprecated_selected_frame, regnum, fpregs);
2743 else
7bb11558 2744 sh_compact_do_registers_info (regnum, fpregs);
55ff77ac
CV		 2745}
2746
2747#ifdef SVR4_SHARED_LIBS
2748
2749/* Fetch (and possibly build) an appropriate link_map_offsets structure
2750 for native i386 linux targets using the struct offsets defined in
2751 link.h (but without actual reference to that file).
2752
2753 This makes it possible to access i386-linux shared libraries from
2754 a gdb that was not built on an i386-linux host (for cross debugging).
2755 */
2756
2757struct link_map_offsets *
2758sh_linux_svr4_fetch_link_map_offsets (void)
2759{
2760 static struct link_map_offsets lmo;
2761 static struct link_map_offsets *lmp = 0;
2762
2763 if (lmp == 0)
2764 {
2765 lmp = &lmo;
2766
2767 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2768
2769 lmo.r_map_offset = 4;
2770 lmo.r_map_size = 4;
2771
2772 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2773
2774 lmo.l_addr_offset = 0;
2775 lmo.l_addr_size = 4;
2776
2777 lmo.l_name_offset = 4;
2778 lmo.l_name_size = 4;
2779
2780 lmo.l_next_offset = 12;
2781 lmo.l_next_size = 4;
2782
2783 lmo.l_prev_offset = 16;
2784 lmo.l_prev_size = 4;
2785 }
2786
2787 return lmp;
2788}
2789#endif /* SVR4_SHARED_LIBS */
2790
2791gdbarch_init_ftype sh64_gdbarch_init;
2792
2793struct gdbarch *
2794sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2795{
2796 static LONGEST sh64_call_dummy_words[] = {0};
2797 struct gdbarch *gdbarch;
2798 struct gdbarch_tdep *tdep;
2799
2800 /* If there is already a candidate, use it. */
2801 arches = gdbarch_list_lookup_by_info (arches, &info);
2802 if (arches != NULL)
2803 return arches->gdbarch;
2804
2805 /* None found, create a new architecture from the information
7bb11558 2806 provided. */
55ff77ac
CV		 2807 tdep = XMALLOC (struct gdbarch_tdep);
2808 gdbarch = gdbarch_alloc (&info, tdep);
2809
2810 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2811 ready to unwind the PC first (see frame.c:get_prev_frame()). */
0968aa8c 2812 set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default);
55ff77ac
CV		 2813
2814 /* Determine the ABI */
2815 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2816 {
7bb11558 2817 /* If the ABI is the 64-bit one, it can only be sh-media. */
55ff77ac
CV		 2818 tdep->sh_abi = SH_ABI_64;
2819 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2820 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2821 }
2822 else
2823 {
2824 /* If the ABI is the 32-bit one it could be either media or
7bb11558 2825 compact. */
55ff77ac
CV		 2826 tdep->sh_abi = SH_ABI_32;
2827 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2828 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2829 }
2830
2831 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2832 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2833 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2834 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2835 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2836 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2837
2838 set_gdbarch_sp_regnum (gdbarch, 15);
2839 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
2840
2841 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2842 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2843
2844 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2845
2846 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2847 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
55ff77ac 2848
19772a2c 2849 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, legacy_frameless_look_for_prologue);
55ff77ac
CV		 2850 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2851
2852 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2853 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2854 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2855
2856 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
2857 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2858 set_gdbarch_pc_regnum (gdbarch, 64);
2859
7bb11558
MS		 2860 /* The number of real registers is the same whether we are in
2861 ISA16(compact) or ISA32(media). */
55ff77ac 2862 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
55ff77ac
CV		 2863 set_gdbarch_deprecated_register_bytes (gdbarch,
2864 ((SIM_SH64_NR_FP_REGS + 1) * 4)
2865 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
2866
39add00a 2867 set_gdbarch_register_name (gdbarch, sh64_register_name);
7bb11558 2868 set_gdbarch_register_type (gdbarch, sh64_register_type);
55ff77ac 2869 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
39add00a 2870 set_gdbarch_deprecated_register_byte (gdbarch, sh64_register_byte);
55ff77ac
CV		 2871 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2872 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2873
2874 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
2875 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
39add00a 2876 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
55ff77ac
CV		 2877 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
2878 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
2879
2880 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
2881 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
2882 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
2883 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
2884 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
2885 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
2886 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
2887 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
74055713 2888 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
55ff77ac
CV		 2889 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
2890 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
2891 set_gdbarch_elf_make_msymbol_special (gdbarch,
2892 sh64_elf_make_msymbol_special);
2893
2894 /* Hook in ABI-specific overrides, if they have been registered. */
2895 gdbarch_init_osabi (info, gdbarch);
2896
2897 return gdbarch;
2898}
GDB Binutils - Deliverables
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