Commit | Line | Data |
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85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
cf5b2f1b | 2 | |
61baf725 | 3 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
55ff77ac CV |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
55ff77ac CV |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
55ff77ac | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
55ff77ac CV |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
c30dc700 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
55ff77ac | 28 | #include "symtab.h" |
55ff77ac CV |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
34 | #include "inferior.h" | |
55ff77ac | 35 | #include "arch-utils.h" |
55ff77ac | 36 | #include "regcache.h" |
55ff77ac | 37 | #include "osabi.h" |
f69fdf9b | 38 | #include "target-float.h" |
79a45b7d | 39 | #include "valprint.h" |
55ff77ac CV |
40 | |
41 | #include "elf-bfd.h" | |
55ff77ac CV |
42 | |
43 | /* sh flags */ | |
44 | #include "elf/sh.h" | |
c378eb4e | 45 | /* Register numbers shared with the simulator. */ |
55ff77ac | 46 | #include "gdb/sim-sh.h" |
d8ca156b | 47 | #include "language.h" |
04dcf5fa | 48 | #include "sh64-tdep.h" |
325fac50 | 49 | #include <algorithm> |
55ff77ac | 50 | |
7bb11558 | 51 | /* Information that is dependent on the processor variant. */ |
55ff77ac CV |
52 | enum sh_abi |
53 | { | |
54 | SH_ABI_UNKNOWN, | |
55 | SH_ABI_32, | |
56 | SH_ABI_64 | |
57 | }; | |
58 | ||
59 | struct gdbarch_tdep | |
60 | { | |
61 | enum sh_abi sh_abi; | |
96a5a1d3 UW |
62 | /* ISA-specific data types. */ |
63 | struct type *sh_littlebyte_bigword_type; | |
55ff77ac CV |
64 | }; |
65 | ||
96a5a1d3 UW |
66 | struct type * |
67 | sh64_littlebyte_bigword_type (struct gdbarch *gdbarch) | |
68 | { | |
69 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
70 | ||
71 | if (tdep->sh_littlebyte_bigword_type == NULL) | |
72 | tdep->sh_littlebyte_bigword_type | |
73 | = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword", | |
74 | floatformats_ieee_double_littlebyte_bigword); | |
75 | ||
76 | return tdep->sh_littlebyte_bigword_type; | |
77 | } | |
78 | ||
c30dc700 CV |
79 | struct sh64_frame_cache |
80 | { | |
81 | /* Base address. */ | |
82 | CORE_ADDR base; | |
83 | LONGEST sp_offset; | |
84 | CORE_ADDR pc; | |
85 | ||
c378eb4e | 86 | /* Flag showing that a frame has been created in the prologue code. */ |
c30dc700 CV |
87 | int uses_fp; |
88 | ||
89 | int media_mode; | |
90 | ||
91 | /* Saved registers. */ | |
92 | CORE_ADDR saved_regs[SIM_SH64_NR_REGS]; | |
93 | CORE_ADDR saved_sp; | |
94 | }; | |
95 | ||
55ff77ac CV |
96 | /* Registers of SH5 */ |
97 | enum | |
98 | { | |
99 | R0_REGNUM = 0, | |
100 | DEFAULT_RETURN_REGNUM = 2, | |
101 | STRUCT_RETURN_REGNUM = 2, | |
102 | ARG0_REGNUM = 2, | |
103 | ARGLAST_REGNUM = 9, | |
104 | FLOAT_ARGLAST_REGNUM = 11, | |
c30dc700 | 105 | MEDIA_FP_REGNUM = 14, |
55ff77ac CV |
106 | PR_REGNUM = 18, |
107 | SR_REGNUM = 65, | |
108 | DR0_REGNUM = 141, | |
109 | DR_LAST_REGNUM = 172, | |
110 | /* FPP stands for Floating Point Pair, to avoid confusion with | |
3e8c568d | 111 | GDB's gdbarch_fp0_regnum, which is the number of the first Floating |
c378eb4e | 112 | point register. Unfortunately on the sh5, the floating point |
7bb11558 | 113 | registers are called FR, and the floating point pairs are called FP. */ |
55ff77ac CV |
114 | FPP0_REGNUM = 173, |
115 | FPP_LAST_REGNUM = 204, | |
116 | FV0_REGNUM = 205, | |
117 | FV_LAST_REGNUM = 220, | |
118 | R0_C_REGNUM = 221, | |
119 | R_LAST_C_REGNUM = 236, | |
120 | PC_C_REGNUM = 237, | |
121 | GBR_C_REGNUM = 238, | |
122 | MACH_C_REGNUM = 239, | |
123 | MACL_C_REGNUM = 240, | |
124 | PR_C_REGNUM = 241, | |
125 | T_C_REGNUM = 242, | |
126 | FPSCR_C_REGNUM = 243, | |
127 | FPUL_C_REGNUM = 244, | |
128 | FP0_C_REGNUM = 245, | |
129 | FP_LAST_C_REGNUM = 260, | |
130 | DR0_C_REGNUM = 261, | |
131 | DR_LAST_C_REGNUM = 268, | |
132 | FV0_C_REGNUM = 269, | |
133 | FV_LAST_C_REGNUM = 272, | |
134 | FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, | |
135 | SSR_REGNUM = SIM_SH64_SSR_REGNUM, | |
136 | SPC_REGNUM = SIM_SH64_SPC_REGNUM, | |
137 | TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, | |
138 | FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 | |
139 | }; | |
140 | ||
55ff77ac | 141 | static const char * |
d93859e2 | 142 | sh64_register_name (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 143 | { |
a121b7c1 | 144 | static const char *register_names[] = |
55ff77ac CV |
145 | { |
146 | /* SH MEDIA MODE (ISA 32) */ | |
147 | /* general registers (64-bit) 0-63 */ | |
148 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
149 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
150 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
151 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
152 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
153 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
154 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
155 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
156 | ||
157 | /* pc (64-bit) 64 */ | |
158 | "pc", | |
159 | ||
160 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
161 | "sr", "ssr", "spc", | |
162 | ||
c378eb4e | 163 | /* target registers (64-bit) 68-75 */ |
55ff77ac CV |
164 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", |
165 | ||
166 | /* floating point state control register (32-bit) 76 */ | |
167 | "fpscr", | |
168 | ||
c378eb4e | 169 | /* single precision floating point registers (32-bit) 77-140 */ |
55ff77ac CV |
170 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
171 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
172 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
173 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
174 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
175 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
176 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
177 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
178 | ||
179 | /* double precision registers (pseudo) 141-172 */ | |
180 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
181 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
182 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
183 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
184 | ||
c378eb4e | 185 | /* floating point pairs (pseudo) 173-204 */ |
55ff77ac CV |
186 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", |
187 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
188 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
189 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
190 | ||
c378eb4e | 191 | /* floating point vectors (4 floating point regs) (pseudo) 205-220 */ |
55ff77ac CV |
192 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", |
193 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
194 | ||
c378eb4e | 195 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */ |
55ff77ac CV |
196 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", |
197 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
198 | "pc_c", | |
199 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
200 | "fpscr_c", "fpul_c", | |
c378eb4e MS |
201 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", |
202 | "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
203 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", | |
204 | "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
205 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", | |
206 | "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
55ff77ac | 207 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", |
c378eb4e | 208 | /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */ |
55ff77ac CV |
209 | }; |
210 | ||
211 | if (reg_nr < 0) | |
212 | return NULL; | |
213 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
214 | return NULL; | |
215 | return register_names[reg_nr]; | |
216 | } | |
217 | ||
218 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
219 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
220 | ||
221 | /* Macros and functions for setting and testing a bit in a minimal | |
222 | symbol that marks it as 32-bit function. The MSB of the minimal | |
f594e5e9 | 223 | symbol's "info" field is used for this purpose. |
55ff77ac | 224 | |
95f1da47 UW |
225 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
226 | i.e. refers to a 32-bit function, and sets a "special" bit in a | |
55ff77ac | 227 | minimal symbol to mark it as a 32-bit function |
f594e5e9 | 228 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
55ff77ac CV |
229 | |
230 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 231 | MSYMBOL_TARGET_FLAG_1 (msym) |
55ff77ac CV |
232 | |
233 | static void | |
234 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
235 | { | |
236 | if (msym == NULL) | |
237 | return; | |
238 | ||
239 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
240 | { | |
b887350f | 241 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
77e371c0 | 242 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
55ff77ac CV |
243 | } |
244 | } | |
245 | ||
246 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
247 | are some macros to test, set, or clear bit 0 of addresses. */ | |
248 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
249 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
250 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
251 | ||
252 | static int | |
253 | pc_is_isa32 (bfd_vma memaddr) | |
254 | { | |
7cbd4a93 | 255 | struct bound_minimal_symbol sym; |
55ff77ac CV |
256 | |
257 | /* If bit 0 of the address is set, assume this is a | |
7bb11558 | 258 | ISA32 (shmedia) address. */ |
55ff77ac CV |
259 | if (IS_ISA32_ADDR (memaddr)) |
260 | return 1; | |
261 | ||
262 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
263 | the high bit of the info field. Use this to decide if the function is | |
264 | ISA16 or ISA32. */ | |
265 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
266 | if (sym.minsym) |
267 | return MSYMBOL_IS_SPECIAL (sym.minsym); | |
55ff77ac CV |
268 | else |
269 | return 0; | |
270 | } | |
271 | ||
d19280ad YQ |
272 | static int |
273 | sh64_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
55ff77ac | 274 | { |
d19280ad YQ |
275 | if (pc_is_isa32 (*pcptr)) |
276 | { | |
277 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
278 | return 4; | |
279 | } | |
280 | else | |
281 | return 2; | |
282 | } | |
283 | ||
284 | static const gdb_byte * | |
285 | sh64_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
286 | { | |
287 | *size = kind; | |
288 | ||
289 | /* The BRK instruction for shmedia is | |
55ff77ac CV |
290 | 01101111 11110101 11111111 11110000 |
291 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
292 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
293 | ||
294 | /* The BRK instruction for shcompact is | |
295 | 00000000 00111011 | |
296 | which translates in big endian mode to 0x0, 0x3b | |
c378eb4e | 297 | and in little endian mode to 0x3b, 0x0 */ |
55ff77ac | 298 | |
d19280ad | 299 | if (kind == 4) |
55ff77ac | 300 | { |
d19280ad YQ |
301 | static unsigned char big_breakpoint_media[] = { |
302 | 0x6f, 0xf5, 0xff, 0xf0 | |
303 | }; | |
304 | static unsigned char little_breakpoint_media[] = { | |
305 | 0xf0, 0xff, 0xf5, 0x6f | |
306 | }; | |
307 | ||
308 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
309 | return big_breakpoint_media; | |
55ff77ac | 310 | else |
d19280ad | 311 | return little_breakpoint_media; |
55ff77ac CV |
312 | } |
313 | else | |
314 | { | |
d19280ad YQ |
315 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; |
316 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
317 | ||
318 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
319 | return big_breakpoint_compact; | |
55ff77ac | 320 | else |
d19280ad | 321 | return little_breakpoint_compact; |
55ff77ac CV |
322 | } |
323 | } | |
324 | ||
325 | /* Prologue looks like | |
326 | [mov.l <regs>,@-r15]... | |
327 | [sts.l pr,@-r15] | |
328 | [mov.l r14,@-r15] | |
329 | [mov r15,r14] | |
330 | ||
331 | Actually it can be more complicated than this. For instance, with | |
332 | newer gcc's: | |
333 | ||
334 | mov.l r14,@-r15 | |
335 | add #-12,r15 | |
336 | mov r15,r14 | |
337 | mov r4,r1 | |
338 | mov r5,r2 | |
339 | mov.l r6,@(4,r14) | |
340 | mov.l r7,@(8,r14) | |
341 | mov.b r1,@r14 | |
342 | mov r14,r1 | |
343 | mov r14,r1 | |
344 | add #2,r1 | |
345 | mov.w r2,@r1 | |
346 | ||
347 | */ | |
348 | ||
349 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 | |
350 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
351 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
352 | ||
353 | /* STS.L PR,@-r0 0100000000100010 | |
354 | r0-4-->r0, PR-->(r0) */ | |
355 | #define IS_STS_R0(x) ((x) == 0x4022) | |
356 | ||
357 | /* STS PR, Rm 0000mmmm00101010 | |
358 | PR-->Rm */ | |
359 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
360 | ||
361 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
362 | Rm-->(dispx4+r15) */ | |
363 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
364 | ||
365 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
366 | R14-->(dispx4+r15) */ | |
367 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
368 | ||
369 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
370 | R18-->(dispx8+R14) */ | |
371 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
372 | ||
373 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
374 | R18-->(dispx8+R15) */ | |
375 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
376 | ||
377 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
378 | R18-->(dispx4+R15) */ | |
379 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
380 | ||
381 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
382 | R14-->(dispx8+R15) */ | |
383 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
384 | ||
385 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
386 | R14-->(dispx4+R15) */ | |
387 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
388 | ||
389 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
390 | R15 + imm --> R15 */ | |
391 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
392 | ||
393 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
394 | R15 + imm --> R15 */ | |
395 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
396 | ||
397 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
398 | R15 + R63 --> R14 */ | |
399 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
400 | ||
401 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
402 | R15 + R63 --> R14 */ | |
403 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
404 | ||
c378eb4e MS |
405 | #define IS_MOV_SP_FP_MEDIA(x) \ |
406 | (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
55ff77ac CV |
407 | |
408 | /* MOV #imm, R0 1110 0000 ssss ssss | |
409 | #imm-->R0 */ | |
410 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
411 | ||
412 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
413 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
414 | ||
415 | /* ADD r15,r0 0011 0000 1111 1100 | |
416 | r15+r0-->r0 */ | |
417 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
418 | ||
419 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
420 | R14-->(R0-4), R0-4-->R0 */ | |
421 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
422 | ||
423 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
7bb11558 | 424 | where Rm is one of r2-r9 which are the argument registers. */ |
c378eb4e | 425 | /* FIXME: Recognize the float and double register moves too! */ |
55ff77ac | 426 | #define IS_MEDIA_IND_ARG_MOV(x) \ |
c378eb4e MS |
427 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) \ |
428 | && (((x) & 0x03f00000) >= 0x00200000 \ | |
429 | && ((x) & 0x03f00000) <= 0x00900000)) | |
55ff77ac CV |
430 | |
431 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
432 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
7bb11558 | 433 | where Rm is one of r2-r9 which are the argument registers. */ |
55ff77ac CV |
434 | #define IS_MEDIA_ARG_MOV(x) \ |
435 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
436 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
437 | ||
c378eb4e MS |
438 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */ |
439 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */ | |
440 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */ | |
441 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */ | |
442 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */ | |
55ff77ac CV |
443 | #define IS_MEDIA_MOV_TO_R14(x) \ |
444 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
445 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
446 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
447 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
448 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
449 | ||
450 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
451 | where Rm is r2-r9 */ | |
452 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
c378eb4e MS |
453 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \ |
454 | && (((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
455 | |
456 | /* compact direct arg move! | |
457 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
458 | #define IS_COMPACT_ARG_MOV(x) \ | |
c378eb4e MS |
459 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \ |
460 | && ((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
461 | |
462 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
463 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
464 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
465 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
466 | ||
467 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
468 | #define IS_NOP(x) ((x) == 0x0009) | |
469 | ||
470 | ||
471 | /* MOV r15,r14 0110111011110011 | |
472 | r15-->r14 */ | |
473 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
474 | ||
475 | /* ADD #imm,r15 01111111iiiiiiii | |
476 | r15+imm-->r15 */ | |
477 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
478 | ||
c378eb4e | 479 | /* Skip any prologue before the guts of a function. */ |
55ff77ac | 480 | |
7bb11558 MS |
481 | /* Skip the prologue using the debug information. If this fails we'll |
482 | fall back on the 'guess' method below. */ | |
55ff77ac CV |
483 | static CORE_ADDR |
484 | after_prologue (CORE_ADDR pc) | |
485 | { | |
486 | struct symtab_and_line sal; | |
487 | CORE_ADDR func_addr, func_end; | |
488 | ||
489 | /* If we can not find the symbol in the partial symbol table, then | |
490 | there is no hope we can determine the function's start address | |
491 | with this code. */ | |
492 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
493 | return 0; | |
494 | ||
c30dc700 | 495 | |
55ff77ac CV |
496 | /* Get the line associated with FUNC_ADDR. */ |
497 | sal = find_pc_line (func_addr, 0); | |
498 | ||
499 | /* There are only two cases to consider. First, the end of the source line | |
500 | is within the function bounds. In that case we return the end of the | |
501 | source line. Second is the end of the source line extends beyond the | |
502 | bounds of the current function. We need to use the slow code to | |
503 | examine instructions in that case. */ | |
504 | if (sal.end < func_end) | |
505 | return sal.end; | |
506 | else | |
507 | return 0; | |
508 | } | |
509 | ||
510 | static CORE_ADDR | |
e17a4113 UW |
511 | look_for_args_moves (struct gdbarch *gdbarch, |
512 | CORE_ADDR start_pc, int media_mode) | |
55ff77ac | 513 | { |
e17a4113 | 514 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
515 | CORE_ADDR here, end; |
516 | int w; | |
517 | int insn_size = (media_mode ? 4 : 2); | |
518 | ||
519 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
520 | { | |
521 | if (media_mode) | |
522 | { | |
e17a4113 UW |
523 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
524 | insn_size, byte_order); | |
55ff77ac CV |
525 | here += insn_size; |
526 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
527 | { | |
528 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 529 | is where the debug info says it is. This can happen after |
7bb11558 | 530 | the SP has been saved, unfortunately. */ |
55ff77ac CV |
531 | |
532 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
e17a4113 | 533 | insn_size, byte_order); |
55ff77ac CV |
534 | here += insn_size; |
535 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
536 | start_pc = here; | |
537 | } | |
538 | else if (IS_MEDIA_ARG_MOV (w)) | |
539 | { | |
7bb11558 | 540 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
541 | start_pc = here; |
542 | } | |
543 | else | |
544 | break; | |
545 | } | |
546 | else | |
547 | { | |
e17a4113 | 548 | w = read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
549 | w = w & 0xffff; |
550 | here += insn_size; | |
551 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
552 | { | |
553 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 554 | is where the debug info says it is. This can happen after |
7bb11558 | 555 | the SP has been saved, unfortunately. */ |
55ff77ac | 556 | |
e17a4113 UW |
557 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
558 | byte_order); | |
55ff77ac CV |
559 | here += insn_size; |
560 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
561 | start_pc = here; | |
562 | } | |
563 | else if (IS_COMPACT_ARG_MOV (w)) | |
564 | { | |
7bb11558 | 565 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
566 | start_pc = here; |
567 | } | |
568 | else if (IS_MOVL_R0 (w)) | |
569 | { | |
570 | /* There is a function that gcc calls to get the arguments | |
c378eb4e | 571 | passed correctly to the function. Only after this |
55ff77ac | 572 | function call the arguments will be found at the place |
c378eb4e | 573 | where they are supposed to be. This happens in case the |
55ff77ac CV |
574 | argument has to be stored into a 64-bit register (for |
575 | instance doubles, long longs). SHcompact doesn't have | |
576 | access to the full 64-bits, so we store the register in | |
577 | stack slot and store the address of the stack slot in | |
578 | the register, then do a call through a wrapper that | |
579 | loads the memory value into the register. A SHcompact | |
580 | callee calls an argument decoder | |
581 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
582 | value in a stack slot and stores the address of the | |
583 | stack slot in the register. GCC thinks the argument is | |
584 | just passed by transparent reference, but this is only | |
c378eb4e | 585 | true after the argument decoder is called. Such a call |
7bb11558 | 586 | needs to be considered part of the prologue. */ |
55ff77ac CV |
587 | |
588 | /* This must be followed by a JSR @r0 instruction and by | |
c378eb4e | 589 | a NOP instruction. After these, the prologue is over! */ |
55ff77ac | 590 | |
e17a4113 UW |
591 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
592 | byte_order); | |
55ff77ac CV |
593 | here += insn_size; |
594 | if (IS_JSR_R0 (next_insn)) | |
595 | { | |
e17a4113 UW |
596 | next_insn = 0xffff & read_memory_integer (here, insn_size, |
597 | byte_order); | |
55ff77ac CV |
598 | here += insn_size; |
599 | ||
600 | if (IS_NOP (next_insn)) | |
601 | start_pc = here; | |
602 | } | |
603 | } | |
604 | else | |
605 | break; | |
606 | } | |
607 | } | |
608 | ||
609 | return start_pc; | |
610 | } | |
611 | ||
612 | static CORE_ADDR | |
e17a4113 | 613 | sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
55ff77ac | 614 | { |
e17a4113 | 615 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
616 | CORE_ADDR here, end; |
617 | int updated_fp = 0; | |
618 | int insn_size = 4; | |
619 | int media_mode = 1; | |
620 | ||
621 | if (!start_pc) | |
622 | return 0; | |
623 | ||
624 | if (pc_is_isa32 (start_pc) == 0) | |
625 | { | |
626 | insn_size = 2; | |
627 | media_mode = 0; | |
628 | } | |
629 | ||
630 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
631 | { | |
632 | ||
633 | if (media_mode) | |
634 | { | |
e17a4113 UW |
635 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
636 | insn_size, byte_order); | |
55ff77ac CV |
637 | here += insn_size; |
638 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
639 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
c378eb4e MS |
640 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) |
641 | || IS_PTABSL_R18 (w)) | |
55ff77ac CV |
642 | { |
643 | start_pc = here; | |
644 | } | |
645 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
646 | { | |
647 | start_pc = here; | |
648 | updated_fp = 1; | |
649 | } | |
650 | else | |
651 | if (updated_fp) | |
652 | { | |
653 | /* Don't bail out yet, we may have arguments stored in | |
654 | registers here, according to the debug info, so that | |
7bb11558 | 655 | gdb can print the frames correctly. */ |
e17a4113 UW |
656 | start_pc = look_for_args_moves (gdbarch, |
657 | here - insn_size, media_mode); | |
55ff77ac CV |
658 | break; |
659 | } | |
660 | } | |
661 | else | |
662 | { | |
e17a4113 | 663 | int w = 0xffff & read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
664 | here += insn_size; |
665 | ||
666 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
667 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
668 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
669 | { | |
670 | start_pc = here; | |
671 | } | |
672 | else if (IS_MOV_SP_FP (w)) | |
673 | { | |
674 | start_pc = here; | |
675 | updated_fp = 1; | |
676 | } | |
677 | else | |
678 | if (updated_fp) | |
679 | { | |
680 | /* Don't bail out yet, we may have arguments stored in | |
681 | registers here, according to the debug info, so that | |
7bb11558 | 682 | gdb can print the frames correctly. */ |
e17a4113 UW |
683 | start_pc = look_for_args_moves (gdbarch, |
684 | here - insn_size, media_mode); | |
55ff77ac CV |
685 | break; |
686 | } | |
687 | } | |
688 | } | |
689 | ||
690 | return start_pc; | |
691 | } | |
692 | ||
693 | static CORE_ADDR | |
6093d2eb | 694 | sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
55ff77ac CV |
695 | { |
696 | CORE_ADDR post_prologue_pc; | |
697 | ||
698 | /* See if we can determine the end of the prologue via the symbol table. | |
699 | If so, then return either PC, or the PC after the prologue, whichever | |
700 | is greater. */ | |
701 | post_prologue_pc = after_prologue (pc); | |
702 | ||
703 | /* If after_prologue returned a useful address, then use it. Else | |
7bb11558 | 704 | fall back on the instruction skipping code. */ |
55ff77ac | 705 | if (post_prologue_pc != 0) |
325fac50 | 706 | return std::max (pc, post_prologue_pc); |
55ff77ac | 707 | else |
e17a4113 | 708 | return sh64_skip_prologue_hard_way (gdbarch, pc); |
55ff77ac CV |
709 | } |
710 | ||
55ff77ac CV |
711 | /* Should call_function allocate stack space for a struct return? */ |
712 | static int | |
c30dc700 | 713 | sh64_use_struct_convention (struct type *type) |
55ff77ac CV |
714 | { |
715 | return (TYPE_LENGTH (type) > 8); | |
716 | } | |
717 | ||
7bb11558 | 718 | /* For vectors of 4 floating point registers. */ |
55ff77ac | 719 | static int |
d93859e2 | 720 | sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
55ff77ac CV |
721 | { |
722 | int fp_regnum; | |
723 | ||
d93859e2 | 724 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4; |
55ff77ac CV |
725 | return fp_regnum; |
726 | } | |
727 | ||
c378eb4e | 728 | /* For double precision floating point registers, i.e 2 fp regs. */ |
55ff77ac | 729 | static int |
d93859e2 | 730 | sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
55ff77ac CV |
731 | { |
732 | int fp_regnum; | |
733 | ||
d93859e2 | 734 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2; |
55ff77ac CV |
735 | return fp_regnum; |
736 | } | |
737 | ||
c378eb4e | 738 | /* For pairs of floating point registers. */ |
55ff77ac | 739 | static int |
d93859e2 | 740 | sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum) |
55ff77ac CV |
741 | { |
742 | int fp_regnum; | |
743 | ||
d93859e2 | 744 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2; |
55ff77ac CV |
745 | return fp_regnum; |
746 | } | |
747 | ||
55ff77ac CV |
748 | /* *INDENT-OFF* */ |
749 | /* | |
750 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
751 | GDB_REGNUM BASE_REGNUM | |
752 | r0_c 221 0 | |
753 | r1_c 222 1 | |
754 | r2_c 223 2 | |
755 | r3_c 224 3 | |
756 | r4_c 225 4 | |
757 | r5_c 226 5 | |
758 | r6_c 227 6 | |
759 | r7_c 228 7 | |
760 | r8_c 229 8 | |
761 | r9_c 230 9 | |
762 | r10_c 231 10 | |
763 | r11_c 232 11 | |
764 | r12_c 233 12 | |
765 | r13_c 234 13 | |
766 | r14_c 235 14 | |
767 | r15_c 236 15 | |
768 | ||
769 | pc_c 237 64 | |
770 | gbr_c 238 16 | |
771 | mach_c 239 17 | |
772 | macl_c 240 17 | |
773 | pr_c 241 18 | |
774 | t_c 242 19 | |
775 | fpscr_c 243 76 | |
776 | fpul_c 244 109 | |
777 | ||
778 | fr0_c 245 77 | |
779 | fr1_c 246 78 | |
780 | fr2_c 247 79 | |
781 | fr3_c 248 80 | |
782 | fr4_c 249 81 | |
783 | fr5_c 250 82 | |
784 | fr6_c 251 83 | |
785 | fr7_c 252 84 | |
786 | fr8_c 253 85 | |
787 | fr9_c 254 86 | |
788 | fr10_c 255 87 | |
789 | fr11_c 256 88 | |
790 | fr12_c 257 89 | |
791 | fr13_c 258 90 | |
792 | fr14_c 259 91 | |
793 | fr15_c 260 92 | |
794 | ||
795 | dr0_c 261 77 | |
796 | dr2_c 262 79 | |
797 | dr4_c 263 81 | |
798 | dr6_c 264 83 | |
799 | dr8_c 265 85 | |
800 | dr10_c 266 87 | |
801 | dr12_c 267 89 | |
802 | dr14_c 268 91 | |
803 | ||
804 | fv0_c 269 77 | |
805 | fv4_c 270 81 | |
806 | fv8_c 271 85 | |
807 | fv12_c 272 91 | |
808 | */ | |
809 | /* *INDENT-ON* */ | |
810 | static int | |
d93859e2 | 811 | sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 812 | { |
c30dc700 | 813 | int base_regnum = reg_nr; |
55ff77ac CV |
814 | |
815 | /* general register N maps to general register N */ | |
816 | if (reg_nr >= R0_C_REGNUM | |
817 | && reg_nr <= R_LAST_C_REGNUM) | |
818 | base_regnum = reg_nr - R0_C_REGNUM; | |
819 | ||
820 | /* floating point register N maps to floating point register N */ | |
821 | else if (reg_nr >= FP0_C_REGNUM | |
822 | && reg_nr <= FP_LAST_C_REGNUM) | |
d93859e2 | 823 | base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch); |
55ff77ac CV |
824 | |
825 | /* double prec register N maps to base regnum for double prec register N */ | |
826 | else if (reg_nr >= DR0_C_REGNUM | |
827 | && reg_nr <= DR_LAST_C_REGNUM) | |
d93859e2 UW |
828 | base_regnum = sh64_dr_reg_base_num (gdbarch, |
829 | DR0_REGNUM + reg_nr - DR0_C_REGNUM); | |
55ff77ac CV |
830 | |
831 | /* vector N maps to base regnum for vector register N */ | |
832 | else if (reg_nr >= FV0_C_REGNUM | |
833 | && reg_nr <= FV_LAST_C_REGNUM) | |
d93859e2 UW |
834 | base_regnum = sh64_fv_reg_base_num (gdbarch, |
835 | FV0_REGNUM + reg_nr - FV0_C_REGNUM); | |
55ff77ac CV |
836 | |
837 | else if (reg_nr == PC_C_REGNUM) | |
d93859e2 | 838 | base_regnum = gdbarch_pc_regnum (gdbarch); |
55ff77ac CV |
839 | |
840 | else if (reg_nr == GBR_C_REGNUM) | |
841 | base_regnum = 16; | |
842 | ||
843 | else if (reg_nr == MACH_C_REGNUM | |
844 | || reg_nr == MACL_C_REGNUM) | |
845 | base_regnum = 17; | |
846 | ||
847 | else if (reg_nr == PR_C_REGNUM) | |
c30dc700 | 848 | base_regnum = PR_REGNUM; |
55ff77ac CV |
849 | |
850 | else if (reg_nr == T_C_REGNUM) | |
851 | base_regnum = 19; | |
852 | ||
853 | else if (reg_nr == FPSCR_C_REGNUM) | |
7bb11558 | 854 | base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ |
55ff77ac CV |
855 | |
856 | else if (reg_nr == FPUL_C_REGNUM) | |
d93859e2 | 857 | base_regnum = gdbarch_fp0_regnum (gdbarch) + 32; |
55ff77ac CV |
858 | |
859 | return base_regnum; | |
860 | } | |
861 | ||
55ff77ac CV |
862 | static int |
863 | sign_extend (int value, int bits) | |
864 | { | |
865 | value = value & ((1 << bits) - 1); | |
866 | return (value & (1 << (bits - 1)) | |
867 | ? value | (~((1 << bits) - 1)) | |
868 | : value); | |
869 | } | |
870 | ||
871 | static void | |
c30dc700 CV |
872 | sh64_analyze_prologue (struct gdbarch *gdbarch, |
873 | struct sh64_frame_cache *cache, | |
874 | CORE_ADDR func_pc, | |
875 | CORE_ADDR current_pc) | |
55ff77ac | 876 | { |
55ff77ac CV |
877 | int pc; |
878 | int opc; | |
879 | int insn; | |
880 | int r0_val = 0; | |
55ff77ac | 881 | int insn_size; |
e17a4113 | 882 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 883 | |
c30dc700 | 884 | cache->sp_offset = 0; |
55ff77ac CV |
885 | |
886 | /* Loop around examining the prologue insns until we find something | |
887 | that does not appear to be part of the prologue. But give up | |
7bb11558 | 888 | after 20 of them, since we're getting silly then. */ |
55ff77ac | 889 | |
c30dc700 | 890 | pc = func_pc; |
55ff77ac | 891 | |
c30dc700 CV |
892 | if (cache->media_mode) |
893 | insn_size = 4; | |
55ff77ac | 894 | else |
c30dc700 | 895 | insn_size = 2; |
55ff77ac | 896 | |
c30dc700 CV |
897 | opc = pc + (insn_size * 28); |
898 | if (opc > current_pc) | |
899 | opc = current_pc; | |
900 | for ( ; pc <= opc; pc += insn_size) | |
55ff77ac | 901 | { |
c30dc700 CV |
902 | insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc) |
903 | : pc, | |
e17a4113 | 904 | insn_size, byte_order); |
55ff77ac | 905 | |
c30dc700 | 906 | if (!cache->media_mode) |
55ff77ac CV |
907 | { |
908 | if (IS_STS_PR (insn)) | |
909 | { | |
e17a4113 UW |
910 | int next_insn = read_memory_integer (pc + insn_size, |
911 | insn_size, byte_order); | |
55ff77ac CV |
912 | if (IS_MOV_TO_R15 (next_insn)) |
913 | { | |
c378eb4e MS |
914 | cache->saved_regs[PR_REGNUM] |
915 | = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) | |
916 | - 0x8) << 2); | |
55ff77ac CV |
917 | pc += insn_size; |
918 | } | |
919 | } | |
c30dc700 | 920 | |
55ff77ac | 921 | else if (IS_MOV_R14 (insn)) |
9ca10714 JB |
922 | { |
923 | cache->saved_regs[MEDIA_FP_REGNUM] = | |
924 | cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
925 | cache->uses_fp = 1; | |
926 | } | |
55ff77ac CV |
927 | |
928 | else if (IS_MOV_R0 (insn)) | |
929 | { | |
930 | /* Put in R0 the offset from SP at which to store some | |
c378eb4e | 931 | registers. We are interested in this value, because it |
55ff77ac CV |
932 | will tell us where the given registers are stored within |
933 | the frame. */ | |
934 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
935 | } | |
c30dc700 | 936 | |
55ff77ac CV |
937 | else if (IS_ADD_SP_R0 (insn)) |
938 | { | |
939 | /* This instruction still prepares r0, but we don't care. | |
7bb11558 | 940 | We already have the offset in r0_val. */ |
55ff77ac | 941 | } |
c30dc700 | 942 | |
55ff77ac CV |
943 | else if (IS_STS_R0 (insn)) |
944 | { | |
c378eb4e | 945 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 | 946 | cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4); |
55ff77ac | 947 | r0_val -= 4; |
55ff77ac | 948 | } |
c30dc700 | 949 | |
55ff77ac CV |
950 | else if (IS_MOV_R14_R0 (insn)) |
951 | { | |
c378eb4e | 952 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 CV |
953 | cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset |
954 | - (r0_val - 4); | |
9ca10714 | 955 | cache->uses_fp = 1; |
55ff77ac CV |
956 | r0_val -= 4; |
957 | } | |
958 | ||
959 | else if (IS_ADD_SP (insn)) | |
c30dc700 CV |
960 | cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80; |
961 | ||
55ff77ac CV |
962 | else if (IS_MOV_SP_FP (insn)) |
963 | break; | |
964 | } | |
965 | else | |
966 | { | |
c30dc700 CV |
967 | if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn)) |
968 | cache->sp_offset -= | |
969 | sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
55ff77ac CV |
970 | |
971 | else if (IS_STQ_R18_R15 (insn)) | |
c378eb4e MS |
972 | cache->saved_regs[PR_REGNUM] |
973 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
974 | 9) << 3); | |
55ff77ac CV |
975 | |
976 | else if (IS_STL_R18_R15 (insn)) | |
c378eb4e MS |
977 | cache->saved_regs[PR_REGNUM] |
978 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
979 | 9) << 2); | |
55ff77ac CV |
980 | |
981 | else if (IS_STQ_R14_R15 (insn)) | |
9ca10714 JB |
982 | { |
983 | cache->saved_regs[MEDIA_FP_REGNUM] | |
984 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
985 | 9) << 3); | |
986 | cache->uses_fp = 1; | |
987 | } | |
55ff77ac CV |
988 | |
989 | else if (IS_STL_R14_R15 (insn)) | |
9ca10714 JB |
990 | { |
991 | cache->saved_regs[MEDIA_FP_REGNUM] | |
992 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
993 | 9) << 2); | |
994 | cache->uses_fp = 1; | |
995 | } | |
55ff77ac CV |
996 | |
997 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
998 | break; | |
999 | } | |
1000 | } | |
55ff77ac CV |
1001 | } |
1002 | ||
55ff77ac | 1003 | static CORE_ADDR |
c30dc700 | 1004 | sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp) |
55ff77ac | 1005 | { |
c30dc700 | 1006 | return sp & ~7; |
55ff77ac CV |
1007 | } |
1008 | ||
c30dc700 | 1009 | /* Function: push_dummy_call |
55ff77ac CV |
1010 | Setup the function arguments for calling a function in the inferior. |
1011 | ||
85a453d5 | 1012 | On the Renesas SH architecture, there are four registers (R4 to R7) |
55ff77ac CV |
1013 | which are dedicated for passing function arguments. Up to the first |
1014 | four arguments (depending on size) may go into these registers. | |
1015 | The rest go on the stack. | |
1016 | ||
1017 | Arguments that are smaller than 4 bytes will still take up a whole | |
1018 | register or a whole 32-bit word on the stack, and will be | |
1019 | right-justified in the register or the stack word. This includes | |
1020 | chars, shorts, and small aggregate types. | |
1021 | ||
1022 | Arguments that are larger than 4 bytes may be split between two or | |
1023 | more registers. If there are not enough registers free, an argument | |
1024 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 1025 | stack. This includes doubles, long longs, and larger aggregates. |
55ff77ac CV |
1026 | As far as I know, there is no upper limit to the size of aggregates |
1027 | that will be passed in this way; in other words, the convention of | |
1028 | passing a pointer to a large aggregate instead of a copy is not used. | |
1029 | ||
1030 | An exceptional case exists for struct arguments (and possibly other | |
1031 | aggregates such as arrays) if the size is larger than 4 bytes but | |
1032 | not a multiple of 4 bytes. In this case the argument is never split | |
1033 | between the registers and the stack, but instead is copied in its | |
1034 | entirety onto the stack, AND also copied into as many registers as | |
1035 | there is room for. In other words, space in registers permitting, | |
1036 | two copies of the same argument are passed in. As far as I can tell, | |
1037 | only the one on the stack is used, although that may be a function | |
1038 | of the level of compiler optimization. I suspect this is a compiler | |
1039 | bug. Arguments of these odd sizes are left-justified within the | |
1040 | word (as opposed to arguments smaller than 4 bytes, which are | |
1041 | right-justified). | |
1042 | ||
1043 | If the function is to return an aggregate type such as a struct, it | |
1044 | is either returned in the normal return value register R0 (if its | |
1045 | size is no greater than one byte), or else the caller must allocate | |
1046 | space into which the callee will copy the return value (if the size | |
1047 | is greater than one byte). In this case, a pointer to the return | |
1048 | value location is passed into the callee in register R2, which does | |
1049 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 1050 | to R7. */ |
55ff77ac CV |
1051 | |
1052 | /* R2-R9 for integer types and integer equivalent (char, pointers) and | |
1053 | non-scalar (struct, union) elements (even if the elements are | |
1054 | floats). | |
1055 | FR0-FR11 for single precision floating point (float) | |
1056 | DR0-DR10 for double precision floating point (double) | |
1057 | ||
1058 | If a float is argument number 3 (for instance) and arguments number | |
1059 | 1,2, and 4 are integer, the mapping will be: | |
c378eb4e | 1060 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. |
55ff77ac CV |
1061 | |
1062 | If a float is argument number 10 (for instance) and arguments number | |
1063 | 1 through 10 are integer, the mapping will be: | |
1064 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
c378eb4e MS |
1065 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, |
1066 | arg11->stack(16,SP). I.e. there is hole in the stack. | |
55ff77ac CV |
1067 | |
1068 | Different rules apply for variable arguments functions, and for functions | |
7bb11558 | 1069 | for which the prototype is not known. */ |
55ff77ac CV |
1070 | |
1071 | static CORE_ADDR | |
c30dc700 CV |
1072 | sh64_push_dummy_call (struct gdbarch *gdbarch, |
1073 | struct value *function, | |
1074 | struct regcache *regcache, | |
1075 | CORE_ADDR bp_addr, | |
1076 | int nargs, struct value **args, | |
1077 | CORE_ADDR sp, int struct_return, | |
1078 | CORE_ADDR struct_addr) | |
55ff77ac | 1079 | { |
e17a4113 | 1080 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1081 | int stack_offset, stack_alloc; |
1082 | int int_argreg; | |
55ff77ac CV |
1083 | int float_arg_index = 0; |
1084 | int double_arg_index = 0; | |
1085 | int argnum; | |
1086 | struct type *type; | |
1087 | CORE_ADDR regval; | |
948f8e3d PA |
1088 | const gdb_byte *val; |
1089 | gdb_byte valbuf[8]; | |
55ff77ac CV |
1090 | int len; |
1091 | int argreg_size; | |
1092 | int fp_args[12]; | |
55ff77ac CV |
1093 | |
1094 | memset (fp_args, 0, sizeof (fp_args)); | |
1095 | ||
c378eb4e | 1096 | /* First force sp to a 8-byte alignment. */ |
c30dc700 | 1097 | sp = sh64_frame_align (gdbarch, sp); |
55ff77ac CV |
1098 | |
1099 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
c378eb4e | 1100 | register. */ |
55ff77ac CV |
1101 | |
1102 | if (struct_return) | |
c30dc700 CV |
1103 | regcache_cooked_write_unsigned (regcache, |
1104 | STRUCT_RETURN_REGNUM, struct_addr); | |
55ff77ac | 1105 | |
c378eb4e | 1106 | /* Now make sure there's space on the stack. */ |
55ff77ac | 1107 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 1108 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7); |
c378eb4e | 1109 | sp -= stack_alloc; /* Make room on stack for args. */ |
55ff77ac CV |
1110 | |
1111 | /* Now load as many as possible of the first arguments into | |
1112 | registers, and push the rest onto the stack. There are 64 bytes | |
1113 | in eight registers available. Loop thru args from first to last. */ | |
1114 | ||
1115 | int_argreg = ARG0_REGNUM; | |
55ff77ac CV |
1116 | |
1117 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
1118 | { | |
4991999e | 1119 | type = value_type (args[argnum]); |
55ff77ac CV |
1120 | len = TYPE_LENGTH (type); |
1121 | memset (valbuf, 0, sizeof (valbuf)); | |
1122 | ||
1123 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
1124 | { | |
58643501 | 1125 | argreg_size = register_size (gdbarch, int_argreg); |
55ff77ac CV |
1126 | |
1127 | if (len < argreg_size) | |
1128 | { | |
c378eb4e | 1129 | /* value gets right-justified in the register or stack word. */ |
58643501 | 1130 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1131 | memcpy (valbuf + argreg_size - len, |
948f8e3d | 1132 | value_contents (args[argnum]), len); |
55ff77ac | 1133 | else |
948f8e3d | 1134 | memcpy (valbuf, value_contents (args[argnum]), len); |
55ff77ac CV |
1135 | |
1136 | val = valbuf; | |
1137 | } | |
1138 | else | |
948f8e3d | 1139 | val = value_contents (args[argnum]); |
55ff77ac CV |
1140 | |
1141 | while (len > 0) | |
1142 | { | |
1143 | if (int_argreg > ARGLAST_REGNUM) | |
1144 | { | |
c378eb4e | 1145 | /* Must go on the stack. */ |
948f8e3d | 1146 | write_memory (sp + stack_offset, val, argreg_size); |
55ff77ac CV |
1147 | stack_offset += 8;/*argreg_size;*/ |
1148 | } | |
1149 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1150 | That's because some *&^%$ things get passed on the stack | |
1151 | AND in the registers! */ | |
1152 | if (int_argreg <= ARGLAST_REGNUM) | |
1153 | { | |
c378eb4e | 1154 | /* There's room in a register. */ |
e17a4113 UW |
1155 | regval = extract_unsigned_integer (val, argreg_size, |
1156 | byte_order); | |
c378eb4e MS |
1157 | regcache_cooked_write_unsigned (regcache, |
1158 | int_argreg, regval); | |
55ff77ac CV |
1159 | } |
1160 | /* Store the value 8 bytes at a time. This means that | |
1161 | things larger than 8 bytes may go partly in registers | |
c378eb4e | 1162 | and partly on the stack. FIXME: argreg is incremented |
7bb11558 | 1163 | before we use its size. */ |
55ff77ac CV |
1164 | len -= argreg_size; |
1165 | val += argreg_size; | |
1166 | int_argreg++; | |
1167 | } | |
1168 | } | |
1169 | else | |
1170 | { | |
948f8e3d | 1171 | val = value_contents (args[argnum]); |
55ff77ac CV |
1172 | if (len == 4) |
1173 | { | |
c378eb4e | 1174 | /* Where is it going to be stored? */ |
55ff77ac CV |
1175 | while (fp_args[float_arg_index]) |
1176 | float_arg_index ++; | |
1177 | ||
1178 | /* Now float_argreg points to the register where it | |
1179 | should be stored. Are we still within the allowed | |
c378eb4e | 1180 | register set? */ |
55ff77ac CV |
1181 | if (float_arg_index <= FLOAT_ARGLAST_REGNUM) |
1182 | { | |
1183 | /* Goes in FR0...FR11 */ | |
c30dc700 | 1184 | regcache_cooked_write (regcache, |
58643501 | 1185 | gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1186 | + float_arg_index, |
c30dc700 | 1187 | val); |
55ff77ac | 1188 | fp_args[float_arg_index] = 1; |
7bb11558 | 1189 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1190 | int_argreg ++; |
1191 | } | |
1192 | else | |
d4fb63e1 TT |
1193 | { |
1194 | /* Store it as the integers, 8 bytes at the time, if | |
1195 | necessary spilling on the stack. */ | |
1196 | } | |
55ff77ac CV |
1197 | } |
1198 | else if (len == 8) | |
1199 | { | |
c378eb4e | 1200 | /* Where is it going to be stored? */ |
55ff77ac CV |
1201 | while (fp_args[double_arg_index]) |
1202 | double_arg_index += 2; | |
1203 | /* Now double_argreg points to the register | |
1204 | where it should be stored. | |
c378eb4e | 1205 | Are we still within the allowed register set? */ |
55ff77ac CV |
1206 | if (double_arg_index < FLOAT_ARGLAST_REGNUM) |
1207 | { | |
1208 | /* Goes in DR0...DR10 */ | |
1209 | /* The numbering of the DRi registers is consecutive, | |
7bb11558 | 1210 | i.e. includes odd numbers. */ |
55ff77ac | 1211 | int double_register_offset = double_arg_index / 2; |
c30dc700 CV |
1212 | int regnum = DR0_REGNUM + double_register_offset; |
1213 | regcache_cooked_write (regcache, regnum, val); | |
55ff77ac CV |
1214 | fp_args[double_arg_index] = 1; |
1215 | fp_args[double_arg_index + 1] = 1; | |
7bb11558 | 1216 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1217 | int_argreg ++; |
1218 | } | |
1219 | else | |
d4fb63e1 TT |
1220 | { |
1221 | /* Store it as the integers, 8 bytes at the time, if | |
1222 | necessary spilling on the stack. */ | |
1223 | } | |
55ff77ac CV |
1224 | } |
1225 | } | |
1226 | } | |
c378eb4e | 1227 | /* Store return address. */ |
c30dc700 | 1228 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
55ff77ac | 1229 | |
c30dc700 | 1230 | /* Update stack pointer. */ |
3e8c568d | 1231 | regcache_cooked_write_unsigned (regcache, |
58643501 | 1232 | gdbarch_sp_regnum (gdbarch), sp); |
55ff77ac | 1233 | |
55ff77ac CV |
1234 | return sp; |
1235 | } | |
1236 | ||
1237 | /* Find a function's return value in the appropriate registers (in | |
1238 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1239 | containing the (raw) register state a function return value of type | |
1240 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1241 | static void | |
c30dc700 | 1242 | sh64_extract_return_value (struct type *type, struct regcache *regcache, |
7c543f7b | 1243 | gdb_byte *valbuf) |
55ff77ac | 1244 | { |
ac7936df | 1245 | struct gdbarch *gdbarch = regcache->arch (); |
55ff77ac | 1246 | int len = TYPE_LENGTH (type); |
d93859e2 | 1247 | |
55ff77ac CV |
1248 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
1249 | { | |
1250 | if (len == 4) | |
1251 | { | |
c378eb4e | 1252 | /* Return value stored in gdbarch_fp0_regnum. */ |
3e8c568d | 1253 | regcache_raw_read (regcache, |
d93859e2 | 1254 | gdbarch_fp0_regnum (gdbarch), valbuf); |
55ff77ac CV |
1255 | } |
1256 | else if (len == 8) | |
1257 | { | |
c378eb4e | 1258 | /* return value stored in DR0_REGNUM. */ |
18cf8b5b | 1259 | gdb_byte buf[8]; |
18cf8b5b | 1260 | regcache_cooked_read (regcache, DR0_REGNUM, buf); |
55ff77ac | 1261 | |
96a5a1d3 UW |
1262 | convert_typed_floating (buf, sh64_littlebyte_bigword_type (gdbarch), |
1263 | valbuf, type); | |
55ff77ac CV |
1264 | } |
1265 | } | |
1266 | else | |
1267 | { | |
1268 | if (len <= 8) | |
1269 | { | |
c30dc700 | 1270 | int offset; |
e362b510 | 1271 | gdb_byte buf[8]; |
c378eb4e | 1272 | /* Result is in register 2. If smaller than 8 bytes, it is padded |
7bb11558 | 1273 | at the most significant end. */ |
c30dc700 CV |
1274 | regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf); |
1275 | ||
d93859e2 UW |
1276 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
1277 | offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM) | |
c30dc700 | 1278 | - len; |
55ff77ac | 1279 | else |
c30dc700 CV |
1280 | offset = 0; |
1281 | memcpy (valbuf, buf + offset, len); | |
55ff77ac CV |
1282 | } |
1283 | else | |
a73c6dcd | 1284 | error (_("bad size for return value")); |
55ff77ac CV |
1285 | } |
1286 | } | |
1287 | ||
1288 | /* Write into appropriate registers a function return value | |
1289 | of type TYPE, given in virtual format. | |
1290 | If the architecture is sh4 or sh3e, store a function's return value | |
1291 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e | 1292 | depending on the type of the return value. In all the other cases |
7bb11558 | 1293 | the result is stored in r0, left-justified. */ |
55ff77ac CV |
1294 | |
1295 | static void | |
c30dc700 | 1296 | sh64_store_return_value (struct type *type, struct regcache *regcache, |
948f8e3d | 1297 | const gdb_byte *valbuf) |
55ff77ac | 1298 | { |
ac7936df | 1299 | struct gdbarch *gdbarch = regcache->arch (); |
e362b510 | 1300 | gdb_byte buf[64]; /* more than enough... */ |
55ff77ac CV |
1301 | int len = TYPE_LENGTH (type); |
1302 | ||
1303 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1304 | { | |
d93859e2 | 1305 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
c30dc700 | 1306 | for (i = 0; i < len; i += 4) |
d93859e2 | 1307 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c30dc700 | 1308 | regcache_raw_write (regcache, regnum++, |
948f8e3d | 1309 | valbuf + len - 4 - i); |
c30dc700 | 1310 | else |
948f8e3d | 1311 | regcache_raw_write (regcache, regnum++, valbuf + i); |
55ff77ac CV |
1312 | } |
1313 | else | |
1314 | { | |
1315 | int return_register = DEFAULT_RETURN_REGNUM; | |
1316 | int offset = 0; | |
1317 | ||
d93859e2 | 1318 | if (len <= register_size (gdbarch, return_register)) |
55ff77ac | 1319 | { |
7bb11558 | 1320 | /* Pad with zeros. */ |
d93859e2 UW |
1321 | memset (buf, 0, register_size (gdbarch, return_register)); |
1322 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
1323 | offset = 0; /*register_size (gdbarch, | |
7bb11558 | 1324 | return_register) - len;*/ |
55ff77ac | 1325 | else |
d93859e2 | 1326 | offset = register_size (gdbarch, return_register) - len; |
55ff77ac CV |
1327 | |
1328 | memcpy (buf + offset, valbuf, len); | |
c30dc700 | 1329 | regcache_raw_write (regcache, return_register, buf); |
55ff77ac CV |
1330 | } |
1331 | else | |
c30dc700 | 1332 | regcache_raw_write (regcache, return_register, valbuf); |
55ff77ac CV |
1333 | } |
1334 | } | |
1335 | ||
c30dc700 | 1336 | static enum return_value_convention |
6a3a010b | 1337 | sh64_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1338 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1339 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c30dc700 CV |
1340 | { |
1341 | if (sh64_use_struct_convention (type)) | |
1342 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1343 | if (writebuf) | |
1344 | sh64_store_return_value (type, regcache, writebuf); | |
1345 | else if (readbuf) | |
1346 | sh64_extract_return_value (type, regcache, readbuf); | |
1347 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1348 | } | |
1349 | ||
55ff77ac CV |
1350 | /* *INDENT-OFF* */ |
1351 | /* | |
1352 | SH MEDIA MODE (ISA 32) | |
1353 | general registers (64-bit) 0-63 | |
1354 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
1355 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
1356 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
1357 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
1358 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
1359 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
1360 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
1361 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
1362 | ||
1363 | pc (64-bit) 64 | |
1364 | 512 pc, | |
1365 | ||
1366 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
1367 | 520 sr, ssr, spc, | |
1368 | ||
1369 | target registers (64-bit) 68-75 | |
1370 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
1371 | ||
1372 | floating point state control register (32-bit) 76 | |
1373 | 608 fpscr, | |
1374 | ||
1375 | single precision floating point registers (32-bit) 77-140 | |
1376 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
1377 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
1378 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
1379 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
1380 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
1381 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
1382 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
1383 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
1384 | ||
1385 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
1386 | ||
1387 | From here on they are all pseudo registers: no memory allocated. | |
1388 | REGISTER_BYTE returns the register byte for the base register. | |
1389 | ||
1390 | double precision registers (pseudo) 141-172 | |
1391 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
1392 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
1393 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
1394 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
1395 | ||
1396 | floating point pairs (pseudo) 173-204 | |
1397 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
1398 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
1399 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
1400 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
1401 | ||
1402 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
1403 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
1404 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
1405 | ||
1406 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1407 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
1408 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
1409 | pc_c, | |
1410 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
1411 | fpscr_c, fpul_c, | |
1412 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
1413 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
1414 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
1415 | fv0_c, fv4_c, fv8_c, fv12_c | |
1416 | */ | |
55ff77ac | 1417 | |
55ff77ac | 1418 | static struct type * |
0dfff4cb | 1419 | sh64_build_float_register_type (struct gdbarch *gdbarch, int high) |
55ff77ac | 1420 | { |
e3506a9f UW |
1421 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1422 | 0, high); | |
55ff77ac CV |
1423 | } |
1424 | ||
7bb11558 MS |
1425 | /* Return the GDB type object for the "standard" data type |
1426 | of data in register REG_NR. */ | |
55ff77ac | 1427 | static struct type * |
7bb11558 | 1428 | sh64_register_type (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 1429 | { |
58643501 | 1430 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
55ff77ac CV |
1431 | && reg_nr <= FP_LAST_REGNUM) |
1432 | || (reg_nr >= FP0_C_REGNUM | |
1433 | && reg_nr <= FP_LAST_C_REGNUM)) | |
0dfff4cb | 1434 | return builtin_type (gdbarch)->builtin_float; |
55ff77ac CV |
1435 | else if ((reg_nr >= DR0_REGNUM |
1436 | && reg_nr <= DR_LAST_REGNUM) | |
1437 | || (reg_nr >= DR0_C_REGNUM | |
1438 | && reg_nr <= DR_LAST_C_REGNUM)) | |
0dfff4cb | 1439 | return builtin_type (gdbarch)->builtin_double; |
55ff77ac CV |
1440 | else if (reg_nr >= FPP0_REGNUM |
1441 | && reg_nr <= FPP_LAST_REGNUM) | |
0dfff4cb | 1442 | return sh64_build_float_register_type (gdbarch, 1); |
55ff77ac CV |
1443 | else if ((reg_nr >= FV0_REGNUM |
1444 | && reg_nr <= FV_LAST_REGNUM) | |
1445 | ||(reg_nr >= FV0_C_REGNUM | |
1446 | && reg_nr <= FV_LAST_C_REGNUM)) | |
0dfff4cb | 1447 | return sh64_build_float_register_type (gdbarch, 3); |
55ff77ac | 1448 | else if (reg_nr == FPSCR_REGNUM) |
0dfff4cb | 1449 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac CV |
1450 | else if (reg_nr >= R0_C_REGNUM |
1451 | && reg_nr < FP0_C_REGNUM) | |
0dfff4cb | 1452 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac | 1453 | else |
0dfff4cb | 1454 | return builtin_type (gdbarch)->builtin_long_long; |
55ff77ac CV |
1455 | } |
1456 | ||
1457 | static void | |
d93859e2 | 1458 | sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
948f8e3d | 1459 | struct type *type, gdb_byte *from, gdb_byte *to) |
55ff77ac | 1460 | { |
d93859e2 | 1461 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1462 | { |
7bb11558 | 1463 | /* It is a no-op. */ |
d93859e2 | 1464 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1465 | return; |
1466 | } | |
1467 | ||
1468 | if ((regnum >= DR0_REGNUM | |
1469 | && regnum <= DR_LAST_REGNUM) | |
1470 | || (regnum >= DR0_C_REGNUM | |
1471 | && regnum <= DR_LAST_C_REGNUM)) | |
96a5a1d3 UW |
1472 | convert_typed_floating (from, sh64_littlebyte_bigword_type (gdbarch), |
1473 | to, type); | |
55ff77ac | 1474 | else |
a73c6dcd MS |
1475 | error (_("sh64_register_convert_to_virtual " |
1476 | "called with non DR register number")); | |
55ff77ac CV |
1477 | } |
1478 | ||
1479 | static void | |
d93859e2 UW |
1480 | sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
1481 | int regnum, const void *from, void *to) | |
55ff77ac | 1482 | { |
d93859e2 | 1483 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1484 | { |
7bb11558 | 1485 | /* It is a no-op. */ |
d93859e2 | 1486 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1487 | return; |
1488 | } | |
1489 | ||
1490 | if ((regnum >= DR0_REGNUM | |
1491 | && regnum <= DR_LAST_REGNUM) | |
1492 | || (regnum >= DR0_C_REGNUM | |
1493 | && regnum <= DR_LAST_C_REGNUM)) | |
96a5a1d3 UW |
1494 | convert_typed_floating (from, type, |
1495 | to, sh64_littlebyte_bigword_type (gdbarch)); | |
55ff77ac | 1496 | else |
a73c6dcd MS |
1497 | error (_("sh64_register_convert_to_raw called " |
1498 | "with non DR register number")); | |
55ff77ac CV |
1499 | } |
1500 | ||
05d1431c PA |
1501 | /* Concatenate PORTIONS contiguous raw registers starting at |
1502 | BASE_REGNUM into BUFFER. */ | |
1503 | ||
1504 | static enum register_status | |
1505 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
1506 | struct regcache *regcache, | |
1507 | int portions, | |
1508 | int base_regnum, gdb_byte *buffer) | |
1509 | { | |
1510 | int portion; | |
1511 | ||
1512 | for (portion = 0; portion < portions; portion++) | |
1513 | { | |
1514 | enum register_status status; | |
1515 | gdb_byte *b; | |
1516 | ||
1517 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
1518 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
1519 | if (status != REG_VALID) | |
1520 | return status; | |
1521 | } | |
1522 | ||
1523 | return REG_VALID; | |
1524 | } | |
1525 | ||
1526 | static enum register_status | |
55ff77ac | 1527 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1528 | int reg_nr, gdb_byte *buffer) |
55ff77ac | 1529 | { |
e17a4113 | 1530 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 1531 | int base_regnum; |
55ff77ac | 1532 | int offset = 0; |
05d1431c | 1533 | enum register_status status; |
55ff77ac CV |
1534 | |
1535 | if (reg_nr >= DR0_REGNUM | |
1536 | && reg_nr <= DR_LAST_REGNUM) | |
1537 | { | |
4a8a33c8 | 1538 | gdb_byte temp_buffer[8]; |
d93859e2 | 1539 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1540 | |
7bb11558 | 1541 | /* Build the value in the provided buffer. */ |
55ff77ac | 1542 | /* DR regs are double precision registers obtained by |
7bb11558 | 1543 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1544 | status = pseudo_register_read_portions (gdbarch, regcache, |
1545 | 2, base_regnum, temp_buffer); | |
1546 | if (status == REG_VALID) | |
1547 | { | |
1548 | /* We must pay attention to the endianness. */ | |
1549 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1550 | register_type (gdbarch, reg_nr), | |
1551 | temp_buffer, buffer); | |
1552 | } | |
55ff77ac | 1553 | |
05d1431c | 1554 | return status; |
55ff77ac CV |
1555 | } |
1556 | ||
05d1431c | 1557 | else if (reg_nr >= FPP0_REGNUM |
55ff77ac CV |
1558 | && reg_nr <= FPP_LAST_REGNUM) |
1559 | { | |
d93859e2 | 1560 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1561 | |
7bb11558 | 1562 | /* Build the value in the provided buffer. */ |
55ff77ac | 1563 | /* FPP regs are pairs of single precision registers obtained by |
7bb11558 | 1564 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1565 | return pseudo_register_read_portions (gdbarch, regcache, |
1566 | 2, base_regnum, buffer); | |
55ff77ac CV |
1567 | } |
1568 | ||
1569 | else if (reg_nr >= FV0_REGNUM | |
1570 | && reg_nr <= FV_LAST_REGNUM) | |
1571 | { | |
d93859e2 | 1572 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1573 | |
7bb11558 | 1574 | /* Build the value in the provided buffer. */ |
55ff77ac | 1575 | /* FV regs are vectors of single precision registers obtained by |
7bb11558 | 1576 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1577 | return pseudo_register_read_portions (gdbarch, regcache, |
1578 | 4, base_regnum, buffer); | |
55ff77ac CV |
1579 | } |
1580 | ||
c378eb4e | 1581 | /* sh compact pseudo registers. 1-to-1 with a shmedia register. */ |
55ff77ac CV |
1582 | else if (reg_nr >= R0_C_REGNUM |
1583 | && reg_nr <= T_C_REGNUM) | |
1584 | { | |
4a8a33c8 | 1585 | gdb_byte temp_buffer[8]; |
d93859e2 | 1586 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1587 | |
7bb11558 | 1588 | /* Build the value in the provided buffer. */ |
05d1431c PA |
1589 | status = regcache_raw_read (regcache, base_regnum, temp_buffer); |
1590 | if (status != REG_VALID) | |
1591 | return status; | |
58643501 | 1592 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1593 | offset = 4; |
c378eb4e MS |
1594 | memcpy (buffer, |
1595 | temp_buffer + offset, 4); /* get LOWER 32 bits only???? */ | |
05d1431c | 1596 | return REG_VALID; |
55ff77ac CV |
1597 | } |
1598 | ||
1599 | else if (reg_nr >= FP0_C_REGNUM | |
1600 | && reg_nr <= FP_LAST_C_REGNUM) | |
1601 | { | |
d93859e2 | 1602 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1603 | |
7bb11558 | 1604 | /* Build the value in the provided buffer. */ |
55ff77ac | 1605 | /* Floating point registers map 1-1 to the media fp regs, |
7bb11558 | 1606 | they have the same size and endianness. */ |
05d1431c | 1607 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac CV |
1608 | } |
1609 | ||
1610 | else if (reg_nr >= DR0_C_REGNUM | |
1611 | && reg_nr <= DR_LAST_C_REGNUM) | |
1612 | { | |
4a8a33c8 | 1613 | gdb_byte temp_buffer[8]; |
d93859e2 | 1614 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1615 | |
1616 | /* DR_C regs are double precision registers obtained by | |
7bb11558 | 1617 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1618 | status = pseudo_register_read_portions (gdbarch, regcache, |
1619 | 2, base_regnum, temp_buffer); | |
1620 | if (status == REG_VALID) | |
1621 | { | |
1622 | /* We must pay attention to the endianness. */ | |
1623 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1624 | register_type (gdbarch, reg_nr), | |
1625 | temp_buffer, buffer); | |
1626 | } | |
1627 | return status; | |
55ff77ac CV |
1628 | } |
1629 | ||
1630 | else if (reg_nr >= FV0_C_REGNUM | |
1631 | && reg_nr <= FV_LAST_C_REGNUM) | |
1632 | { | |
d93859e2 | 1633 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1634 | |
7bb11558 | 1635 | /* Build the value in the provided buffer. */ |
55ff77ac | 1636 | /* FV_C regs are vectors of single precision registers obtained by |
7bb11558 | 1637 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1638 | return pseudo_register_read_portions (gdbarch, regcache, |
1639 | 4, base_regnum, buffer); | |
55ff77ac CV |
1640 | } |
1641 | ||
1642 | else if (reg_nr == FPSCR_C_REGNUM) | |
1643 | { | |
1644 | int fpscr_base_regnum; | |
1645 | int sr_base_regnum; | |
4a8a33c8 AH |
1646 | ULONGEST fpscr_value; |
1647 | ULONGEST sr_value; | |
55ff77ac CV |
1648 | unsigned int fpscr_c_value; |
1649 | unsigned int fpscr_c_part1_value; | |
1650 | unsigned int fpscr_c_part2_value; | |
1651 | ||
1652 | fpscr_base_regnum = FPSCR_REGNUM; | |
1653 | sr_base_regnum = SR_REGNUM; | |
1654 | ||
7bb11558 | 1655 | /* Build the value in the provided buffer. */ |
55ff77ac CV |
1656 | /* FPSCR_C is a very weird register that contains sparse bits |
1657 | from the FPSCR and the SR architectural registers. | |
1658 | Specifically: */ | |
1659 | /* *INDENT-OFF* */ | |
1660 | /* | |
1661 | FPSRC_C bit | |
1662 | 0 Bit 0 of FPSCR | |
1663 | 1 reserved | |
1664 | 2-17 Bit 2-18 of FPSCR | |
1665 | 18-20 Bits 12,13,14 of SR | |
1666 | 21-31 reserved | |
1667 | */ | |
1668 | /* *INDENT-ON* */ | |
4a8a33c8 | 1669 | /* Get FPSCR as an int. */ |
6f98355c | 1670 | status = regcache->raw_read (fpscr_base_regnum, &fpscr_value); |
05d1431c PA |
1671 | if (status != REG_VALID) |
1672 | return status; | |
4a8a33c8 | 1673 | /* Get SR as an int. */ |
6f98355c | 1674 | status = regcache->raw_read (sr_base_regnum, &sr_value); |
05d1431c PA |
1675 | if (status != REG_VALID) |
1676 | return status; | |
7bb11558 | 1677 | /* Build the new value. */ |
55ff77ac CV |
1678 | fpscr_c_part1_value = fpscr_value & 0x3fffd; |
1679 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
1680 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
c378eb4e | 1681 | /* Store that in out buffer!!! */ |
e17a4113 | 1682 | store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value); |
7bb11558 | 1683 | /* FIXME There is surely an endianness gotcha here. */ |
05d1431c PA |
1684 | |
1685 | return REG_VALID; | |
55ff77ac CV |
1686 | } |
1687 | ||
1688 | else if (reg_nr == FPUL_C_REGNUM) | |
1689 | { | |
d93859e2 | 1690 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1691 | |
1692 | /* FPUL_C register is floating point register 32, | |
7bb11558 | 1693 | same size, same endianness. */ |
05d1431c | 1694 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac | 1695 | } |
05d1431c PA |
1696 | else |
1697 | gdb_assert_not_reached ("invalid pseudo register number"); | |
55ff77ac CV |
1698 | } |
1699 | ||
1700 | static void | |
1701 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
18cf8b5b | 1702 | int reg_nr, const gdb_byte *buffer) |
55ff77ac | 1703 | { |
e17a4113 | 1704 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1705 | int base_regnum, portion; |
1706 | int offset; | |
55ff77ac CV |
1707 | |
1708 | if (reg_nr >= DR0_REGNUM | |
1709 | && reg_nr <= DR_LAST_REGNUM) | |
1710 | { | |
4a8a33c8 | 1711 | gdb_byte temp_buffer[8]; |
d93859e2 | 1712 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1713 | /* We must pay attention to the endianness. */ |
d93859e2 | 1714 | sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
39add00a MS |
1715 | reg_nr, |
1716 | buffer, temp_buffer); | |
55ff77ac CV |
1717 | |
1718 | /* Write the real regs for which this one is an alias. */ | |
1719 | for (portion = 0; portion < 2; portion++) | |
1720 | regcache_raw_write (regcache, base_regnum + portion, | |
1721 | (temp_buffer | |
948f8e3d | 1722 | + register_size (gdbarch, |
7bb11558 | 1723 | base_regnum) * portion)); |
55ff77ac CV |
1724 | } |
1725 | ||
1726 | else if (reg_nr >= FPP0_REGNUM | |
1727 | && reg_nr <= FPP_LAST_REGNUM) | |
1728 | { | |
d93859e2 | 1729 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1730 | |
1731 | /* Write the real regs for which this one is an alias. */ | |
1732 | for (portion = 0; portion < 2; portion++) | |
1733 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d PA |
1734 | (buffer + register_size (gdbarch, |
1735 | base_regnum) * portion)); | |
55ff77ac CV |
1736 | } |
1737 | ||
1738 | else if (reg_nr >= FV0_REGNUM | |
1739 | && reg_nr <= FV_LAST_REGNUM) | |
1740 | { | |
d93859e2 | 1741 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1742 | |
1743 | /* Write the real regs for which this one is an alias. */ | |
1744 | for (portion = 0; portion < 4; portion++) | |
1745 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d PA |
1746 | (buffer + register_size (gdbarch, |
1747 | base_regnum) * portion)); | |
55ff77ac CV |
1748 | } |
1749 | ||
c378eb4e | 1750 | /* sh compact general pseudo registers. 1-to-1 with a shmedia |
55ff77ac CV |
1751 | register but only 4 bytes of it. */ |
1752 | else if (reg_nr >= R0_C_REGNUM | |
1753 | && reg_nr <= T_C_REGNUM) | |
1754 | { | |
4a8a33c8 | 1755 | gdb_byte temp_buffer[8]; |
d93859e2 | 1756 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1757 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ |
58643501 | 1758 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac CV |
1759 | offset = 4; |
1760 | else | |
1761 | offset = 0; | |
1762 | /* Let's read the value of the base register into a temporary | |
1763 | buffer, so that overwriting the last four bytes with the new | |
7bb11558 | 1764 | value of the pseudo will leave the upper 4 bytes unchanged. */ |
55ff77ac | 1765 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
c378eb4e | 1766 | /* Write as an 8 byte quantity. */ |
55ff77ac CV |
1767 | memcpy (temp_buffer + offset, buffer, 4); |
1768 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1769 | } | |
1770 | ||
c378eb4e MS |
1771 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia |
1772 | registers. Both are 4 bytes. */ | |
55ff77ac CV |
1773 | else if (reg_nr >= FP0_C_REGNUM |
1774 | && reg_nr <= FP_LAST_C_REGNUM) | |
1775 | { | |
d93859e2 | 1776 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1777 | regcache_raw_write (regcache, base_regnum, buffer); |
1778 | } | |
1779 | ||
1780 | else if (reg_nr >= DR0_C_REGNUM | |
1781 | && reg_nr <= DR_LAST_C_REGNUM) | |
1782 | { | |
4a8a33c8 | 1783 | gdb_byte temp_buffer[8]; |
d93859e2 | 1784 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1785 | for (portion = 0; portion < 2; portion++) |
1786 | { | |
7bb11558 | 1787 | /* We must pay attention to the endianness. */ |
d93859e2 UW |
1788 | sh64_register_convert_to_raw (gdbarch, |
1789 | register_type (gdbarch, reg_nr), | |
39add00a MS |
1790 | reg_nr, |
1791 | buffer, temp_buffer); | |
55ff77ac CV |
1792 | |
1793 | regcache_raw_write (regcache, base_regnum + portion, | |
1794 | (temp_buffer | |
7bb11558 MS |
1795 | + register_size (gdbarch, |
1796 | base_regnum) * portion)); | |
55ff77ac CV |
1797 | } |
1798 | } | |
1799 | ||
1800 | else if (reg_nr >= FV0_C_REGNUM | |
1801 | && reg_nr <= FV_LAST_C_REGNUM) | |
1802 | { | |
d93859e2 | 1803 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1804 | |
1805 | for (portion = 0; portion < 4; portion++) | |
1806 | { | |
1807 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d | 1808 | (buffer |
7bb11558 MS |
1809 | + register_size (gdbarch, |
1810 | base_regnum) * portion)); | |
55ff77ac CV |
1811 | } |
1812 | } | |
1813 | ||
1814 | else if (reg_nr == FPSCR_C_REGNUM) | |
1815 | { | |
1816 | int fpscr_base_regnum; | |
1817 | int sr_base_regnum; | |
4a8a33c8 AH |
1818 | ULONGEST fpscr_value; |
1819 | ULONGEST sr_value; | |
1820 | ULONGEST old_fpscr_value; | |
1821 | ULONGEST old_sr_value; | |
55ff77ac CV |
1822 | unsigned int fpscr_c_value; |
1823 | unsigned int fpscr_mask; | |
1824 | unsigned int sr_mask; | |
1825 | ||
1826 | fpscr_base_regnum = FPSCR_REGNUM; | |
1827 | sr_base_regnum = SR_REGNUM; | |
1828 | ||
1829 | /* FPSCR_C is a very weird register that contains sparse bits | |
1830 | from the FPSCR and the SR architectural registers. | |
1831 | Specifically: */ | |
1832 | /* *INDENT-OFF* */ | |
1833 | /* | |
1834 | FPSRC_C bit | |
1835 | 0 Bit 0 of FPSCR | |
1836 | 1 reserved | |
1837 | 2-17 Bit 2-18 of FPSCR | |
1838 | 18-20 Bits 12,13,14 of SR | |
1839 | 21-31 reserved | |
1840 | */ | |
1841 | /* *INDENT-ON* */ | |
7bb11558 | 1842 | /* Get value as an int. */ |
e17a4113 | 1843 | fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order); |
55ff77ac | 1844 | |
7bb11558 | 1845 | /* Build the new values. */ |
55ff77ac CV |
1846 | fpscr_mask = 0x0003fffd; |
1847 | sr_mask = 0x001c0000; | |
1848 | ||
1849 | fpscr_value = fpscr_c_value & fpscr_mask; | |
1850 | sr_value = (fpscr_value & sr_mask) >> 6; | |
1851 | ||
6f98355c | 1852 | regcache->raw_read (fpscr_base_regnum, &old_fpscr_value); |
55ff77ac CV |
1853 | old_fpscr_value &= 0xfffc0002; |
1854 | fpscr_value |= old_fpscr_value; | |
6f98355c | 1855 | regcache->raw_write (fpscr_base_regnum, fpscr_value); |
4a8a33c8 | 1856 | |
6f98355c | 1857 | regcache->raw_read (sr_base_regnum, &old_sr_value); |
55ff77ac CV |
1858 | old_sr_value &= 0xffff8fff; |
1859 | sr_value |= old_sr_value; | |
6f98355c | 1860 | regcache->raw_write (sr_base_regnum, sr_value); |
55ff77ac CV |
1861 | } |
1862 | ||
1863 | else if (reg_nr == FPUL_C_REGNUM) | |
1864 | { | |
d93859e2 | 1865 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1866 | regcache_raw_write (regcache, base_regnum, buffer); |
1867 | } | |
1868 | } | |
1869 | ||
55ff77ac | 1870 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE |
7bb11558 MS |
1871 | shmedia REGISTERS. */ |
1872 | /* Control registers, compact mode. */ | |
55ff77ac | 1873 | static void |
c30dc700 CV |
1874 | sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame, |
1875 | int cr_c_regnum) | |
55ff77ac CV |
1876 | { |
1877 | switch (cr_c_regnum) | |
1878 | { | |
c30dc700 CV |
1879 | case PC_C_REGNUM: |
1880 | fprintf_filtered (file, "pc_c\t0x%08x\n", | |
1881 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1882 | break; |
c30dc700 CV |
1883 | case GBR_C_REGNUM: |
1884 | fprintf_filtered (file, "gbr_c\t0x%08x\n", | |
1885 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1886 | break; |
c30dc700 CV |
1887 | case MACH_C_REGNUM: |
1888 | fprintf_filtered (file, "mach_c\t0x%08x\n", | |
1889 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1890 | break; |
c30dc700 CV |
1891 | case MACL_C_REGNUM: |
1892 | fprintf_filtered (file, "macl_c\t0x%08x\n", | |
1893 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1894 | break; |
c30dc700 CV |
1895 | case PR_C_REGNUM: |
1896 | fprintf_filtered (file, "pr_c\t0x%08x\n", | |
1897 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1898 | break; |
c30dc700 CV |
1899 | case T_C_REGNUM: |
1900 | fprintf_filtered (file, "t_c\t0x%08x\n", | |
1901 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1902 | break; |
c30dc700 CV |
1903 | case FPSCR_C_REGNUM: |
1904 | fprintf_filtered (file, "fpscr_c\t0x%08x\n", | |
1905 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1906 | break; |
c30dc700 CV |
1907 | case FPUL_C_REGNUM: |
1908 | fprintf_filtered (file, "fpul_c\t0x%08x\n", | |
1909 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac CV |
1910 | break; |
1911 | } | |
1912 | } | |
1913 | ||
1914 | static void | |
c30dc700 CV |
1915 | sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, |
1916 | struct frame_info *frame, int regnum) | |
c378eb4e | 1917 | { /* Do values for FP (float) regs. */ |
079c8cd0 | 1918 | unsigned char *raw_buffer; |
55ff77ac | 1919 | |
7bb11558 | 1920 | /* Allocate space for the float. */ |
c378eb4e MS |
1921 | raw_buffer = (unsigned char *) |
1922 | alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch))); | |
55ff77ac CV |
1923 | |
1924 | /* Get the data in raw format. */ | |
ca9d61b9 | 1925 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
a73c6dcd | 1926 | error (_("can't read register %d (%s)"), |
58643501 | 1927 | regnum, gdbarch_register_name (gdbarch, regnum)); |
55ff77ac | 1928 | |
7bb11558 | 1929 | /* Print the name and some spaces. */ |
58643501 | 1930 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 1931 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 1932 | (gdbarch, regnum)), file); |
55ff77ac | 1933 | |
7bb11558 | 1934 | /* Print the value. */ |
f69fdf9b UW |
1935 | const struct type *flt_type = builtin_type (gdbarch)->builtin_float; |
1936 | std::string str = target_float_to_string (raw_buffer, flt_type, "%-10.9g"); | |
8ba0dd51 | 1937 | fprintf_filtered (file, "%s", str.c_str ()); |
55ff77ac | 1938 | |
7bb11558 | 1939 | /* Print the fp register as hex. */ |
2cc762b5 AB |
1940 | fprintf_filtered (file, "\t(raw "); |
1941 | print_hex_chars (file, raw_buffer, | |
1942 | register_size (gdbarch, regnum), | |
30a25466 | 1943 | gdbarch_byte_order (gdbarch), true); |
55ff77ac CV |
1944 | fprintf_filtered (file, ")"); |
1945 | fprintf_filtered (file, "\n"); | |
1946 | } | |
1947 | ||
1948 | static void | |
c30dc700 CV |
1949 | sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
1950 | struct frame_info *frame, int regnum) | |
55ff77ac | 1951 | { |
7bb11558 | 1952 | /* All the sh64-compact mode registers are pseudo registers. */ |
55ff77ac | 1953 | |
58643501 UW |
1954 | if (regnum < gdbarch_num_regs (gdbarch) |
1955 | || regnum >= gdbarch_num_regs (gdbarch) | |
f57d151a UW |
1956 | + NUM_PSEUDO_REGS_SH_MEDIA |
1957 | + NUM_PSEUDO_REGS_SH_COMPACT) | |
55ff77ac | 1958 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1959 | _("Invalid pseudo register number %d\n"), regnum); |
55ff77ac | 1960 | |
c30dc700 CV |
1961 | else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)) |
1962 | { | |
d93859e2 | 1963 | int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1964 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM, |
1965 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1966 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
1967 | } | |
55ff77ac | 1968 | |
c30dc700 CV |
1969 | else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM)) |
1970 | { | |
d93859e2 | 1971 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1972 | fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM, |
1973 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1974 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
1975 | } | |
55ff77ac | 1976 | |
c30dc700 CV |
1977 | else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)) |
1978 | { | |
d93859e2 | 1979 | int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1980 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
1981 | regnum - FV0_REGNUM, | |
1982 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1983 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
1984 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
1985 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
1986 | } | |
55ff77ac | 1987 | |
c30dc700 CV |
1988 | else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM)) |
1989 | { | |
d93859e2 | 1990 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1991 | fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
1992 | regnum - FV0_C_REGNUM, | |
1993 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1994 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
1995 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
1996 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
1997 | } | |
1998 | ||
1999 | else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM) | |
2000 | { | |
d93859e2 | 2001 | int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2002 | fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM, |
2003 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2004 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2005 | } | |
2006 | ||
2007 | else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM) | |
2008 | { | |
d93859e2 | 2009 | int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2010 | fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM, |
2011 | (unsigned) get_frame_register_unsigned (frame, c_regnum)); | |
2012 | } | |
2013 | else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM) | |
7bb11558 | 2014 | /* This should work also for pseudoregs. */ |
c30dc700 CV |
2015 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
2016 | else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM) | |
2017 | sh64_do_cr_c_register_info (file, frame, regnum); | |
55ff77ac CV |
2018 | } |
2019 | ||
2020 | static void | |
c30dc700 CV |
2021 | sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file, |
2022 | struct frame_info *frame, int regnum) | |
55ff77ac | 2023 | { |
79a45b7d | 2024 | struct value_print_options opts; |
cc977dc7 | 2025 | struct value *val; |
55ff77ac | 2026 | |
58643501 | 2027 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 2028 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 2029 | (gdbarch, regnum)), file); |
55ff77ac CV |
2030 | |
2031 | /* Get the data in raw format. */ | |
cc977dc7 YQ |
2032 | val = get_frame_register_value (frame, regnum); |
2033 | if (value_optimized_out (val) || !value_entirely_available (val)) | |
47061676 AB |
2034 | { |
2035 | fprintf_filtered (file, "*value not available*\n"); | |
2036 | return; | |
2037 | } | |
79a45b7d TT |
2038 | |
2039 | get_formatted_print_options (&opts, 'x'); | |
2040 | opts.deref_ref = 1; | |
cc977dc7 | 2041 | val_print (register_type (gdbarch, regnum), |
e8b24d9f | 2042 | 0, 0, |
cc977dc7 | 2043 | file, 0, val, &opts, current_language); |
55ff77ac | 2044 | fprintf_filtered (file, "\t"); |
79a45b7d TT |
2045 | get_formatted_print_options (&opts, 0); |
2046 | opts.deref_ref = 1; | |
cc977dc7 | 2047 | val_print (register_type (gdbarch, regnum), |
e8b24d9f | 2048 | 0, 0, |
cc977dc7 | 2049 | file, 0, val, &opts, current_language); |
55ff77ac CV |
2050 | fprintf_filtered (file, "\n"); |
2051 | } | |
2052 | ||
2053 | static void | |
c30dc700 CV |
2054 | sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
2055 | struct frame_info *frame, int regnum) | |
55ff77ac | 2056 | { |
58643501 UW |
2057 | if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch) |
2058 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2059 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2060 | _("Invalid register number %d\n"), regnum); |
55ff77ac | 2061 | |
58643501 | 2062 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac | 2063 | { |
7b9ee6a8 | 2064 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c30dc700 | 2065 | sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */ |
55ff77ac | 2066 | else |
c30dc700 | 2067 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2068 | } |
2069 | ||
58643501 UW |
2070 | else if (regnum < gdbarch_num_regs (gdbarch) |
2071 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c30dc700 | 2072 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2073 | } |
2074 | ||
2075 | static void | |
c30dc700 CV |
2076 | sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2077 | struct frame_info *frame, int regnum, | |
2078 | int fpregs) | |
55ff77ac | 2079 | { |
c378eb4e | 2080 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2081 | { |
58643501 | 2082 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2083 | error (_("Not a valid register for the current processor type")); |
55ff77ac | 2084 | |
c30dc700 | 2085 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2086 | } |
2087 | else | |
c378eb4e | 2088 | /* Do all (or most) registers. */ |
55ff77ac CV |
2089 | { |
2090 | regnum = 0; | |
58643501 | 2091 | while (regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac CV |
2092 | { |
2093 | /* If the register name is empty, it is undefined for this | |
2094 | processor, so don't display anything. */ | |
58643501 UW |
2095 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
2096 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
55ff77ac CV |
2097 | { |
2098 | regnum++; | |
2099 | continue; | |
2100 | } | |
2101 | ||
7b9ee6a8 | 2102 | if (TYPE_CODE (register_type (gdbarch, regnum)) |
c30dc700 | 2103 | == TYPE_CODE_FLT) |
55ff77ac CV |
2104 | { |
2105 | if (fpregs) | |
2106 | { | |
c378eb4e | 2107 | /* true for "INFO ALL-REGISTERS" command. */ |
c30dc700 | 2108 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2109 | regnum ++; |
2110 | } | |
2111 | else | |
58643501 | 2112 | regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch); |
3e8c568d | 2113 | /* skip FP regs */ |
55ff77ac CV |
2114 | } |
2115 | else | |
2116 | { | |
c30dc700 | 2117 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2118 | regnum++; |
2119 | } | |
2120 | } | |
2121 | ||
2122 | if (fpregs) | |
58643501 UW |
2123 | while (regnum < gdbarch_num_regs (gdbarch) |
2124 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2125 | { |
c30dc700 | 2126 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2127 | regnum++; |
2128 | } | |
2129 | } | |
2130 | } | |
2131 | ||
2132 | static void | |
c30dc700 CV |
2133 | sh64_compact_print_registers_info (struct gdbarch *gdbarch, |
2134 | struct ui_file *file, | |
2135 | struct frame_info *frame, int regnum, | |
2136 | int fpregs) | |
55ff77ac | 2137 | { |
c378eb4e | 2138 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2139 | { |
58643501 | 2140 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2141 | error (_("Not a valid register for the current processor type")); |
55ff77ac CV |
2142 | |
2143 | if (regnum >= 0 && regnum < R0_C_REGNUM) | |
a73c6dcd | 2144 | error (_("Not a valid register for the current processor mode.")); |
55ff77ac | 2145 | |
c30dc700 | 2146 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2147 | } |
2148 | else | |
c378eb4e | 2149 | /* Do all compact registers. */ |
55ff77ac CV |
2150 | { |
2151 | regnum = R0_C_REGNUM; | |
58643501 UW |
2152 | while (regnum < gdbarch_num_regs (gdbarch) |
2153 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2154 | { |
c30dc700 | 2155 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2156 | regnum++; |
2157 | } | |
2158 | } | |
2159 | } | |
2160 | ||
2161 | static void | |
c30dc700 CV |
2162 | sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2163 | struct frame_info *frame, int regnum, int fpregs) | |
55ff77ac | 2164 | { |
c30dc700 CV |
2165 | if (pc_is_isa32 (get_frame_pc (frame))) |
2166 | sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs); | |
55ff77ac | 2167 | else |
c30dc700 | 2168 | sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs); |
55ff77ac CV |
2169 | } |
2170 | ||
c30dc700 CV |
2171 | static struct sh64_frame_cache * |
2172 | sh64_alloc_frame_cache (void) | |
2173 | { | |
2174 | struct sh64_frame_cache *cache; | |
2175 | int i; | |
2176 | ||
2177 | cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache); | |
2178 | ||
2179 | /* Base address. */ | |
2180 | cache->base = 0; | |
2181 | cache->saved_sp = 0; | |
2182 | cache->sp_offset = 0; | |
2183 | cache->pc = 0; | |
55ff77ac | 2184 | |
c30dc700 CV |
2185 | /* Frameless until proven otherwise. */ |
2186 | cache->uses_fp = 0; | |
55ff77ac | 2187 | |
c30dc700 CV |
2188 | /* Saved registers. We initialize these to -1 since zero is a valid |
2189 | offset (that's where fp is supposed to be stored). */ | |
2190 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2191 | { | |
2192 | cache->saved_regs[i] = -1; | |
2193 | } | |
2194 | ||
2195 | return cache; | |
2196 | } | |
2197 | ||
2198 | static struct sh64_frame_cache * | |
94afd7a6 | 2199 | sh64_frame_cache (struct frame_info *this_frame, void **this_cache) |
55ff77ac | 2200 | { |
58643501 | 2201 | struct gdbarch *gdbarch; |
c30dc700 CV |
2202 | struct sh64_frame_cache *cache; |
2203 | CORE_ADDR current_pc; | |
2204 | int i; | |
55ff77ac | 2205 | |
c30dc700 | 2206 | if (*this_cache) |
19ba03f4 | 2207 | return (struct sh64_frame_cache *) *this_cache; |
c30dc700 | 2208 | |
94afd7a6 | 2209 | gdbarch = get_frame_arch (this_frame); |
c30dc700 CV |
2210 | cache = sh64_alloc_frame_cache (); |
2211 | *this_cache = cache; | |
2212 | ||
94afd7a6 | 2213 | current_pc = get_frame_pc (this_frame); |
c30dc700 CV |
2214 | cache->media_mode = pc_is_isa32 (current_pc); |
2215 | ||
2216 | /* In principle, for normal frames, fp holds the frame pointer, | |
2217 | which holds the base address for the current stack frame. | |
2218 | However, for functions that don't need it, the frame pointer is | |
2219 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 2220 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 2221 | cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM); |
c30dc700 CV |
2222 | if (cache->base == 0) |
2223 | return cache; | |
2224 | ||
94afd7a6 | 2225 | cache->pc = get_frame_func (this_frame); |
c30dc700 | 2226 | if (cache->pc != 0) |
58643501 | 2227 | sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc); |
c30dc700 CV |
2228 | |
2229 | if (!cache->uses_fp) | |
55ff77ac | 2230 | { |
c30dc700 CV |
2231 | /* We didn't find a valid frame, which means that CACHE->base |
2232 | currently holds the frame pointer for our calling frame. If | |
2233 | we're at the start of a function, or somewhere half-way its | |
2234 | prologue, the function's frame probably hasn't been fully | |
2235 | setup yet. Try to reconstruct the base address for the stack | |
2236 | frame by looking at the stack pointer. For truly "frameless" | |
2237 | functions this might work too. */ | |
94afd7a6 UW |
2238 | cache->base = get_frame_register_unsigned |
2239 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
c30dc700 | 2240 | } |
55ff77ac | 2241 | |
c30dc700 CV |
2242 | /* Now that we have the base address for the stack frame we can |
2243 | calculate the value of sp in the calling frame. */ | |
2244 | cache->saved_sp = cache->base + cache->sp_offset; | |
55ff77ac | 2245 | |
c30dc700 CV |
2246 | /* Adjust all the saved registers such that they contain addresses |
2247 | instead of offsets. */ | |
2248 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2249 | if (cache->saved_regs[i] != -1) | |
2250 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i]; | |
55ff77ac | 2251 | |
c30dc700 CV |
2252 | return cache; |
2253 | } | |
55ff77ac | 2254 | |
94afd7a6 UW |
2255 | static struct value * |
2256 | sh64_frame_prev_register (struct frame_info *this_frame, | |
2257 | void **this_cache, int regnum) | |
c30dc700 | 2258 | { |
94afd7a6 UW |
2259 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
2260 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
e17a4113 | 2261 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 2262 | |
c30dc700 | 2263 | gdb_assert (regnum >= 0); |
55ff77ac | 2264 | |
58643501 | 2265 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 2266 | frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
c30dc700 CV |
2267 | |
2268 | /* The PC of the previous frame is stored in the PR register of | |
2269 | the current frame. Frob regnum so that we pull the value from | |
2270 | the correct place. */ | |
58643501 | 2271 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
c30dc700 CV |
2272 | regnum = PR_REGNUM; |
2273 | ||
2274 | if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1) | |
2275 | { | |
58643501 | 2276 | if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32 |
c30dc700 | 2277 | && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM)) |
c30dc700 | 2278 | { |
94afd7a6 | 2279 | CORE_ADDR val; |
e17a4113 UW |
2280 | val = read_memory_unsigned_integer (cache->saved_regs[regnum], |
2281 | 4, byte_order); | |
94afd7a6 | 2282 | return frame_unwind_got_constant (this_frame, regnum, val); |
c30dc700 | 2283 | } |
94afd7a6 UW |
2284 | |
2285 | return frame_unwind_got_memory (this_frame, regnum, | |
2286 | cache->saved_regs[regnum]); | |
55ff77ac CV |
2287 | } |
2288 | ||
94afd7a6 | 2289 | return frame_unwind_got_register (this_frame, regnum, regnum); |
55ff77ac | 2290 | } |
55ff77ac | 2291 | |
c30dc700 | 2292 | static void |
94afd7a6 | 2293 | sh64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
c30dc700 CV |
2294 | struct frame_id *this_id) |
2295 | { | |
94afd7a6 | 2296 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2297 | |
2298 | /* This marks the outermost frame. */ | |
2299 | if (cache->base == 0) | |
2300 | return; | |
2301 | ||
2302 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
2303 | } | |
2304 | ||
2305 | static const struct frame_unwind sh64_frame_unwind = { | |
2306 | NORMAL_FRAME, | |
8fbca658 | 2307 | default_frame_unwind_stop_reason, |
c30dc700 | 2308 | sh64_frame_this_id, |
94afd7a6 UW |
2309 | sh64_frame_prev_register, |
2310 | NULL, | |
2311 | default_frame_sniffer | |
c30dc700 CV |
2312 | }; |
2313 | ||
c30dc700 CV |
2314 | static CORE_ADDR |
2315 | sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2316 | { | |
3e8c568d | 2317 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2318 | gdbarch_sp_regnum (gdbarch)); |
c30dc700 CV |
2319 | } |
2320 | ||
2321 | static CORE_ADDR | |
2322 | sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2323 | { | |
3e8c568d | 2324 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2325 | gdbarch_pc_regnum (gdbarch)); |
c30dc700 CV |
2326 | } |
2327 | ||
2328 | static struct frame_id | |
94afd7a6 | 2329 | sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c30dc700 | 2330 | { |
94afd7a6 UW |
2331 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
2332 | gdbarch_sp_regnum (gdbarch)); | |
2333 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
c30dc700 CV |
2334 | } |
2335 | ||
2336 | static CORE_ADDR | |
94afd7a6 | 2337 | sh64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c30dc700 | 2338 | { |
94afd7a6 | 2339 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2340 | |
2341 | return cache->base; | |
2342 | } | |
2343 | ||
2344 | static const struct frame_base sh64_frame_base = { | |
2345 | &sh64_frame_unwind, | |
2346 | sh64_frame_base_address, | |
2347 | sh64_frame_base_address, | |
2348 | sh64_frame_base_address | |
2349 | }; | |
2350 | ||
55ff77ac CV |
2351 | |
2352 | struct gdbarch * | |
2353 | sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2354 | { | |
55ff77ac CV |
2355 | struct gdbarch *gdbarch; |
2356 | struct gdbarch_tdep *tdep; | |
2357 | ||
2358 | /* If there is already a candidate, use it. */ | |
2359 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2360 | if (arches != NULL) | |
2361 | return arches->gdbarch; | |
2362 | ||
2363 | /* None found, create a new architecture from the information | |
7bb11558 | 2364 | provided. */ |
cdd238da | 2365 | tdep = XCNEW (struct gdbarch_tdep); |
55ff77ac CV |
2366 | gdbarch = gdbarch_alloc (&info, tdep); |
2367 | ||
55ff77ac CV |
2368 | /* Determine the ABI */ |
2369 | if (info.abfd && bfd_get_arch_size (info.abfd) == 64) | |
2370 | { | |
7bb11558 | 2371 | /* If the ABI is the 64-bit one, it can only be sh-media. */ |
55ff77ac CV |
2372 | tdep->sh_abi = SH_ABI_64; |
2373 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2374 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2375 | } | |
2376 | else | |
2377 | { | |
2378 | /* If the ABI is the 32-bit one it could be either media or | |
7bb11558 | 2379 | compact. */ |
55ff77ac CV |
2380 | tdep->sh_abi = SH_ABI_32; |
2381 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2382 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2383 | } | |
2384 | ||
2385 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2386 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
c30dc700 | 2387 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
55ff77ac CV |
2388 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2389 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2390 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2391 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2392 | ||
c30dc700 CV |
2393 | /* The number of real registers is the same whether we are in |
2394 | ISA16(compact) or ISA32(media). */ | |
2395 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
55ff77ac | 2396 | set_gdbarch_sp_regnum (gdbarch, 15); |
c30dc700 CV |
2397 | set_gdbarch_pc_regnum (gdbarch, 64); |
2398 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
2399 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA | |
2400 | + NUM_PSEUDO_REGS_SH_COMPACT); | |
55ff77ac | 2401 | |
c30dc700 CV |
2402 | set_gdbarch_register_name (gdbarch, sh64_register_name); |
2403 | set_gdbarch_register_type (gdbarch, sh64_register_type); | |
2404 | ||
2405 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); | |
2406 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
2407 | ||
04180708 YQ |
2408 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh64_breakpoint_kind_from_pc); |
2409 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh64_sw_breakpoint_from_kind); | |
55ff77ac CV |
2410 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
2411 | ||
c30dc700 | 2412 | set_gdbarch_return_value (gdbarch, sh64_return_value); |
55ff77ac | 2413 | |
c30dc700 CV |
2414 | set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue); |
2415 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
55ff77ac | 2416 | |
c30dc700 | 2417 | set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call); |
55ff77ac | 2418 | |
c30dc700 | 2419 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
55ff77ac | 2420 | |
c30dc700 CV |
2421 | set_gdbarch_frame_align (gdbarch, sh64_frame_align); |
2422 | set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp); | |
2423 | set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc); | |
94afd7a6 | 2424 | set_gdbarch_dummy_id (gdbarch, sh64_dummy_id); |
c30dc700 | 2425 | frame_base_set_default (gdbarch, &sh64_frame_base); |
55ff77ac | 2426 | |
c30dc700 | 2427 | set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info); |
55ff77ac | 2428 | |
55ff77ac CV |
2429 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
2430 | sh64_elf_make_msymbol_special); | |
2431 | ||
2432 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
2433 | gdbarch_init_osabi (info, gdbarch); | |
2434 | ||
94afd7a6 UW |
2435 | dwarf2_append_unwinders (gdbarch); |
2436 | frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind); | |
c30dc700 | 2437 | |
55ff77ac CV |
2438 | return gdbarch; |
2439 | } |