[deliverable/binutils-gdb.git] / gdb / sparc-nat.c

/* Functions specific to running gdb native on a SPARC running SunOS4.
   Copyright 1989, 1992, 1993, 1994, 1996 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "defs.h"
#include "inferior.h"
#include "target.h"
#include "gdbcore.h"

#include <signal.h>
#include <sys/ptrace.h>
#include <sys/wait.h>
#ifdef __linux__
#include <asm/reg.h>
#else
#include <machine/reg.h>
#endif
#include <sys/user.h>

/* We don't store all registers immediately when requested, since they
   get sent over in large chunks anyway.  Instead, we accumulate most
   of the changes and send them over once.  "deferred_stores" keeps
   track of which sets of registers we have locally-changed copies of,
   so we only need send the groups that have changed.  */

#define	INT_REGS	1
#define	STACK_REGS	2
#define	FP_REGS		4

static void
fetch_core_registers PARAMS ((char *, unsigned int, int, CORE_ADDR));

/* Fetch one or more registers from the inferior.  REGNO == -1 to get
   them all.  We actually fetch more than requested, when convenient,
   marking them as valid so we won't fetch them again.  */

void
fetch_inferior_registers (regno)
     int regno;
{
  struct regs inferior_registers;
  struct fp_status inferior_fp_registers;
  int i;

  /* We should never be called with deferred stores, because a prerequisite
     for writing regs is to have fetched them all (PREPARE_TO_STORE), sigh.  */
  if (deferred_stores)
    abort ();

  DO_DEFERRED_STORES;

  /* Global and Out regs are fetched directly, as well as the control
     registers.  If we're getting one of the in or local regs,
     and the stack pointer has not yet been fetched,
     we have to do that first, since they're found in memory relative
     to the stack pointer.  */
  if (regno < O7_REGNUM		/* including -1 */
      || regno >= Y_REGNUM
      || (!register_valid[SP_REGNUM] && regno < I7_REGNUM))
    {
      if (0 != ptrace (PTRACE_GETREGS, inferior_pid,
		       (PTRACE_ARG3_TYPE) & inferior_registers, 0))
	perror ("ptrace_getregs");

      registers[REGISTER_BYTE (0)] = 0;
      memcpy (&registers[REGISTER_BYTE (1)], &inferior_registers.r_g1,
	      15 * REGISTER_RAW_SIZE (G0_REGNUM));
      *(int *) &registers[REGISTER_BYTE (PS_REGNUM)] = inferior_registers.r_ps;
      *(int *) &registers[REGISTER_BYTE (PC_REGNUM)] = inferior_registers.r_pc;
      *(int *) &registers[REGISTER_BYTE (NPC_REGNUM)] = inferior_registers.r_npc;
      *(int *) &registers[REGISTER_BYTE (Y_REGNUM)] = inferior_registers.r_y;

      for (i = G0_REGNUM; i <= O7_REGNUM; i++)
	register_valid[i] = 1;
      register_valid[Y_REGNUM] = 1;
      register_valid[PS_REGNUM] = 1;
      register_valid[PC_REGNUM] = 1;
      register_valid[NPC_REGNUM] = 1;
      /* If we don't set these valid, read_register_bytes() rereads
         all the regs every time it is called!  FIXME.  */
      register_valid[WIM_REGNUM] = 1;	/* Not true yet, FIXME */
      register_valid[TBR_REGNUM] = 1;	/* Not true yet, FIXME */
      register_valid[CPS_REGNUM] = 1;	/* Not true yet, FIXME */
    }

  /* Floating point registers */
  if (regno == -1 ||
      regno == FPS_REGNUM ||
      (regno >= FP0_REGNUM && regno <= FP0_REGNUM + 31))
    {
      if (0 != ptrace (PTRACE_GETFPREGS, inferior_pid,
		       (PTRACE_ARG3_TYPE) & inferior_fp_registers,
		       0))
	perror ("ptrace_getfpregs");
      memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], &inferior_fp_registers,
	      sizeof inferior_fp_registers.fpu_fr);
      memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)],
	      &inferior_fp_registers.Fpu_fsr,
	      sizeof (FPU_FSR_TYPE));
      for (i = FP0_REGNUM; i <= FP0_REGNUM + 31; i++)
	register_valid[i] = 1;
      register_valid[FPS_REGNUM] = 1;
    }

  /* These regs are saved on the stack by the kernel.  Only read them
     all (16 ptrace calls!) if we really need them.  */
  if (regno == -1)
    {
      target_read_memory (*(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)],
			  &registers[REGISTER_BYTE (L0_REGNUM)],
			  16 * REGISTER_RAW_SIZE (L0_REGNUM));
      for (i = L0_REGNUM; i <= I7_REGNUM; i++)
	register_valid[i] = 1;
    }
  else if (regno >= L0_REGNUM && regno <= I7_REGNUM)
    {
      CORE_ADDR sp = *(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)];
      i = REGISTER_BYTE (regno);
      if (register_valid[regno])
	printf_unfiltered ("register %d valid and read\n", regno);
      target_read_memory (sp + i - REGISTER_BYTE (L0_REGNUM),
			  &registers[i], REGISTER_RAW_SIZE (regno));
      register_valid[regno] = 1;
    }
}

/* Store our register values back into the inferior.
   If REGNO is -1, do this for all registers.
   Otherwise, REGNO specifies which register (so we can save time).  */

void
store_inferior_registers (regno)
     int regno;
{
  struct regs inferior_registers;
  struct fp_status inferior_fp_registers;
  int wanna_store = INT_REGS + STACK_REGS + FP_REGS;

  /* First decide which pieces of machine-state we need to modify.  
     Default for regno == -1 case is all pieces.  */
  if (regno >= 0)
    if (FP0_REGNUM <= regno && regno < FP0_REGNUM + 32)
      {
	wanna_store = FP_REGS;
      }
    else
      {
	if (regno == SP_REGNUM)
	  wanna_store = INT_REGS + STACK_REGS;
	else if (regno < L0_REGNUM || regno > I7_REGNUM)
	  wanna_store = INT_REGS;
	else if (regno == FPS_REGNUM)
	  wanna_store = FP_REGS;
	else
	  wanna_store = STACK_REGS;
      }

  /* See if we're forcing the stores to happen now, or deferring. */
  if (regno == -2)
    {
      wanna_store = deferred_stores;
      deferred_stores = 0;
    }
  else
    {
      if (wanna_store == STACK_REGS)
	{
	  /* Fall through and just store one stack reg.  If we deferred
	     it, we'd have to store them all, or remember more info.  */
	}
      else
	{
	  deferred_stores |= wanna_store;
	  return;
	}
    }

  if (wanna_store & STACK_REGS)
    {
      CORE_ADDR sp = *(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)];

      if (regno < 0 || regno == SP_REGNUM)
	{
	  if (!register_valid[L0_REGNUM + 5])
	    abort ();
	  target_write_memory (sp,
			       &registers[REGISTER_BYTE (L0_REGNUM)],
			       16 * REGISTER_RAW_SIZE (L0_REGNUM));
	}
      else
	{
	  if (!register_valid[regno])
	    abort ();
	  target_write_memory (sp + REGISTER_BYTE (regno) - REGISTER_BYTE (L0_REGNUM),
			       &registers[REGISTER_BYTE (regno)],
			       REGISTER_RAW_SIZE (regno));
	}

    }

  if (wanna_store & INT_REGS)
    {
      if (!register_valid[G1_REGNUM])
	abort ();

      memcpy (&inferior_registers.r_g1, &registers[REGISTER_BYTE (G1_REGNUM)],
	      15 * REGISTER_RAW_SIZE (G1_REGNUM));

      inferior_registers.r_ps =
	*(int *) &registers[REGISTER_BYTE (PS_REGNUM)];
      inferior_registers.r_pc =
	*(int *) &registers[REGISTER_BYTE (PC_REGNUM)];
      inferior_registers.r_npc =
	*(int *) &registers[REGISTER_BYTE (NPC_REGNUM)];
      inferior_registers.r_y =
	*(int *) &registers[REGISTER_BYTE (Y_REGNUM)];

      if (0 != ptrace (PTRACE_SETREGS, inferior_pid,
		       (PTRACE_ARG3_TYPE) & inferior_registers, 0))
	perror ("ptrace_setregs");
    }

  if (wanna_store & FP_REGS)
    {
      if (!register_valid[FP0_REGNUM + 9])
	abort ();
      memcpy (&inferior_fp_registers, &registers[REGISTER_BYTE (FP0_REGNUM)],
	      sizeof inferior_fp_registers.fpu_fr);
      memcpy (&inferior_fp_registers.Fpu_fsr,
	      &registers[REGISTER_BYTE (FPS_REGNUM)], sizeof (FPU_FSR_TYPE));
      if (0 !=
	  ptrace (PTRACE_SETFPREGS, inferior_pid,
		  (PTRACE_ARG3_TYPE) & inferior_fp_registers, 0))
	perror ("ptrace_setfpregs");
    }
}


static void
fetch_core_registers (core_reg_sect, core_reg_size, which, ignore)
     char *core_reg_sect;
     unsigned core_reg_size;
     int which;
     CORE_ADDR ignore;		/* reg addr, unused in this version */
{

  if (which == 0)
    {

      /* Integer registers */

#define gregs ((struct regs *)core_reg_sect)
      /* G0 *always* holds 0.  */
      *(int *) &registers[REGISTER_BYTE (0)] = 0;

      /* The globals and output registers.  */
      memcpy (&registers[REGISTER_BYTE (G1_REGNUM)], &gregs->r_g1,
	      15 * REGISTER_RAW_SIZE (G1_REGNUM));
      *(int *) &registers[REGISTER_BYTE (PS_REGNUM)] = gregs->r_ps;
      *(int *) &registers[REGISTER_BYTE (PC_REGNUM)] = gregs->r_pc;
      *(int *) &registers[REGISTER_BYTE (NPC_REGNUM)] = gregs->r_npc;
      *(int *) &registers[REGISTER_BYTE (Y_REGNUM)] = gregs->r_y;

      /* My best guess at where to get the locals and input
         registers is exactly where they usually are, right above
         the stack pointer.  If the core dump was caused by a bus error
         from blowing away the stack pointer (as is possible) then this
         won't work, but it's worth the try. */
      {
	int sp;

	sp = *(int *) &registers[REGISTER_BYTE (SP_REGNUM)];
	if (0 != target_read_memory (sp, &registers[REGISTER_BYTE (L0_REGNUM)],
				     16 * REGISTER_RAW_SIZE (L0_REGNUM)))
	  {
	    /* fprintf_unfiltered so user can still use gdb */
	    fprintf_unfiltered (gdb_stderr,
		"Couldn't read input and local registers from core file\n");
	  }
      }
    }
  else if (which == 2)
    {

      /* Floating point registers */

#define fpuregs  ((struct fpu *) core_reg_sect)
      if (core_reg_size >= sizeof (struct fpu))
	{
	  memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], fpuregs->fpu_regs,
		  sizeof (fpuregs->fpu_regs));
	  memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)], &fpuregs->fpu_fsr,
		  sizeof (FPU_FSR_TYPE));
	}
      else
	fprintf_unfiltered (gdb_stderr, "Couldn't read float regs from core file\n");
    }
}

int
kernel_u_size ()
{
  return (sizeof (struct user));
}
\f

/* Register that we are able to handle sparc core file formats.
   FIXME: is this really bfd_target_unknown_flavour? */

static struct core_fns sparc_core_fns =
{
  bfd_target_unknown_flavour,		/* core_flavour */
  default_check_format,			/* check_format */
  default_core_sniffer,			/* core_sniffer */
  fetch_core_registers,			/* core_read_registers */
  NULL					/* next */
};

void
_initialize_core_sparc ()
{
  add_core_fns (&sparc_core_fns);
}
Commit	Line	Data
c906108c SS	1	/* Functions specific to running gdb native on a SPARC running SunOS4.
	2	Copyright 1989, 1992, 1993, 1994, 1996 Free Software Foundation, Inc.
	3
c5aa993b	4	This file is part of GDB.
c906108c	5
c5aa993b JM	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
c906108c	10
c5aa993b JM	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
c906108c	15
c5aa993b JM	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330,
	19	Boston, MA 02111-1307, USA. */
c906108c SS	20
	21	#include "defs.h"
	22	#include "inferior.h"
	23	#include "target.h"
	24	#include "gdbcore.h"
	25
	26	#include <signal.h>
	27	#include <sys/ptrace.h>
	28	#include <sys/wait.h>
	29	#ifdef __linux__
	30	#include <asm/reg.h>
	31	#else
	32	#include <machine/reg.h>
	33	#endif
	34	#include <sys/user.h>
	35
	36	/* We don't store all registers immediately when requested, since they
	37	get sent over in large chunks anyway. Instead, we accumulate most
	38	of the changes and send them over once. "deferred_stores" keeps
	39	track of which sets of registers we have locally-changed copies of,
	40	so we only need send the groups that have changed. */
	41
	42	#define INT_REGS 1
	43	#define STACK_REGS 2
	44	#define FP_REGS 4
	45
	46	static void
	47	fetch_core_registers PARAMS ((char *, unsigned int, int, CORE_ADDR));
	48
	49	/* Fetch one or more registers from the inferior. REGNO == -1 to get
	50	them all. We actually fetch more than requested, when convenient,
	51	marking them as valid so we won't fetch them again. */
	52
	53	void
	54	fetch_inferior_registers (regno)
	55	int regno;
	56	{
	57	struct regs inferior_registers;
	58	struct fp_status inferior_fp_registers;
	59	int i;
	60
	61	/* We should never be called with deferred stores, because a prerequisite
	62	for writing regs is to have fetched them all (PREPARE_TO_STORE), sigh. */
c5aa993b JM	63	if (deferred_stores)
c5aa993b JM	64	abort ();
c906108c SS	65
	66	DO_DEFERRED_STORES;
	67
	68	/* Global and Out regs are fetched directly, as well as the control
	69	registers. If we're getting one of the in or local regs,
	70	and the stack pointer has not yet been fetched,
	71	we have to do that first, since they're found in memory relative
	72	to the stack pointer. */
c5aa993b	73	if (regno < O7_REGNUM /* including -1 */
c906108c SS	74	\|\| regno >= Y_REGNUM
	75	\|\| (!register_valid[SP_REGNUM] && regno < I7_REGNUM))
	76	{
	77	if (0 != ptrace (PTRACE_GETREGS, inferior_pid,
c5aa993b JM	78	(PTRACE_ARG3_TYPE) & inferior_registers, 0))
	79	perror ("ptrace_getregs");
	80
c906108c SS	81	registers[REGISTER_BYTE (0)] = 0;
	82	memcpy (&registers[REGISTER_BYTE (1)], &inferior_registers.r_g1,
	83	15 * REGISTER_RAW_SIZE (G0_REGNUM));
c5aa993b JM	84	(int ) &registers[REGISTER_BYTE (PS_REGNUM)] = inferior_registers.r_ps;
	85	(int ) &registers[REGISTER_BYTE (PC_REGNUM)] = inferior_registers.r_pc;
	86	(int ) &registers[REGISTER_BYTE (NPC_REGNUM)] = inferior_registers.r_npc;
	87	(int ) &registers[REGISTER_BYTE (Y_REGNUM)] = inferior_registers.r_y;
c906108c SS	88
	89	for (i = G0_REGNUM; i <= O7_REGNUM; i++)
	90	register_valid[i] = 1;
	91	register_valid[Y_REGNUM] = 1;
	92	register_valid[PS_REGNUM] = 1;
	93	register_valid[PC_REGNUM] = 1;
	94	register_valid[NPC_REGNUM] = 1;
	95	/* If we don't set these valid, read_register_bytes() rereads
c5aa993b	96	all the regs every time it is called! FIXME. */
c906108c SS	97	register_valid[WIM_REGNUM] = 1; /* Not true yet, FIXME */
	98	register_valid[TBR_REGNUM] = 1; /* Not true yet, FIXME */
	99	register_valid[CPS_REGNUM] = 1; /* Not true yet, FIXME */
	100	}
	101
	102	/* Floating point registers */
	103	if (regno == -1 \|\|
	104	regno == FPS_REGNUM \|\|
	105	(regno >= FP0_REGNUM && regno <= FP0_REGNUM + 31))
	106	{
	107	if (0 != ptrace (PTRACE_GETFPREGS, inferior_pid,
c5aa993b	108	(PTRACE_ARG3_TYPE) & inferior_fp_registers,
c906108c	109	0))
c5aa993b	110	perror ("ptrace_getfpregs");
c906108c SS	111	memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], &inferior_fp_registers,
	112	sizeof inferior_fp_registers.fpu_fr);
	113	memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)],
c5aa993b JM	114	&inferior_fp_registers.Fpu_fsr,
	115	sizeof (FPU_FSR_TYPE));
	116	for (i = FP0_REGNUM; i <= FP0_REGNUM + 31; i++)
c906108c SS	117	register_valid[i] = 1;
	118	register_valid[FPS_REGNUM] = 1;
	119	}
	120
	121	/* These regs are saved on the stack by the kernel. Only read them
	122	all (16 ptrace calls!) if we really need them. */
	123	if (regno == -1)
	124	{
c5aa993b JM	125	target_read_memory ((CORE_ADDR ) & registers[REGISTER_BYTE (SP_REGNUM)],
	126	&registers[REGISTER_BYTE (L0_REGNUM)],
	127	16 * REGISTER_RAW_SIZE (L0_REGNUM));
c906108c SS	128	for (i = L0_REGNUM; i <= I7_REGNUM; i++)
	129	register_valid[i] = 1;
	130	}
	131	else if (regno >= L0_REGNUM && regno <= I7_REGNUM)
	132	{
c5aa993b	133	CORE_ADDR sp = (CORE_ADDR ) & registers[REGISTER_BYTE (SP_REGNUM)];
c906108c SS	134	i = REGISTER_BYTE (regno);
c906108c SS	135	if (register_valid[regno])
c5aa993b	136	printf_unfiltered ("register %d valid and read\n", regno);
c906108c SS	137	target_read_memory (sp + i - REGISTER_BYTE (L0_REGNUM),
	138	&registers[i], REGISTER_RAW_SIZE (regno));
	139	register_valid[regno] = 1;
	140	}
	141	}
	142
	143	/* Store our register values back into the inferior.
	144	If REGNO is -1, do this for all registers.
	145	Otherwise, REGNO specifies which register (so we can save time). */
	146
	147	void
	148	store_inferior_registers (regno)
	149	int regno;
	150	{
	151	struct regs inferior_registers;
	152	struct fp_status inferior_fp_registers;
	153	int wanna_store = INT_REGS + STACK_REGS + FP_REGS;
	154
	155	/* First decide which pieces of machine-state we need to modify.
	156	Default for regno == -1 case is all pieces. */
	157	if (regno >= 0)
	158	if (FP0_REGNUM <= regno && regno < FP0_REGNUM + 32)
	159	{
	160	wanna_store = FP_REGS;
	161	}
c5aa993b	162	else
c906108c SS	163	{
	164	if (regno == SP_REGNUM)
	165	wanna_store = INT_REGS + STACK_REGS;
	166	else if (regno < L0_REGNUM \|\| regno > I7_REGNUM)
	167	wanna_store = INT_REGS;
	168	else if (regno == FPS_REGNUM)
	169	wanna_store = FP_REGS;
	170	else
	171	wanna_store = STACK_REGS;
	172	}
	173
	174	/* See if we're forcing the stores to happen now, or deferring. */
	175	if (regno == -2)
	176	{
	177	wanna_store = deferred_stores;
	178	deferred_stores = 0;
	179	}
	180	else
	181	{
	182	if (wanna_store == STACK_REGS)
	183	{
	184	/* Fall through and just store one stack reg. If we deferred
	185	it, we'd have to store them all, or remember more info. */
	186	}
	187	else
	188	{
	189	deferred_stores \|= wanna_store;
	190	return;
	191	}
	192	}
	193
	194	if (wanna_store & STACK_REGS)
	195	{
c5aa993b	196	CORE_ADDR sp = (CORE_ADDR ) & registers[REGISTER_BYTE (SP_REGNUM)];
c906108c SS	197
	198	if (regno < 0 \|\| regno == SP_REGNUM)
	199	{
c5aa993b JM	200	if (!register_valid[L0_REGNUM + 5])
	201	abort ();
	202	target_write_memory (sp,
c906108c	203	&registers[REGISTER_BYTE (L0_REGNUM)],
c5aa993b	204	16 * REGISTER_RAW_SIZE (L0_REGNUM));
c906108c SS	205	}
	206	else
	207	{
c5aa993b JM	208	if (!register_valid[regno])
c5aa993b JM	209	abort ();
c906108c SS	210	target_write_memory (sp + REGISTER_BYTE (regno) - REGISTER_BYTE (L0_REGNUM),
	211	&registers[REGISTER_BYTE (regno)],
	212	REGISTER_RAW_SIZE (regno));
	213	}
c5aa993b	214
c906108c SS	215	}
	216
	217	if (wanna_store & INT_REGS)
	218	{
c5aa993b JM	219	if (!register_valid[G1_REGNUM])
c5aa993b JM	220	abort ();
c906108c SS	221
	222	memcpy (&inferior_registers.r_g1, &registers[REGISTER_BYTE (G1_REGNUM)],
	223	15 * REGISTER_RAW_SIZE (G1_REGNUM));
	224
	225	inferior_registers.r_ps =
c5aa993b	226	(int ) &registers[REGISTER_BYTE (PS_REGNUM)];
c906108c	227	inferior_registers.r_pc =
c5aa993b	228	(int ) &registers[REGISTER_BYTE (PC_REGNUM)];
c906108c	229	inferior_registers.r_npc =
c5aa993b	230	(int ) &registers[REGISTER_BYTE (NPC_REGNUM)];
c906108c	231	inferior_registers.r_y =
c5aa993b	232	(int ) &registers[REGISTER_BYTE (Y_REGNUM)];
c906108c SS	233
c906108c SS	234	if (0 != ptrace (PTRACE_SETREGS, inferior_pid,
c5aa993b JM	235	(PTRACE_ARG3_TYPE) & inferior_registers, 0))
c5aa993b JM	236	perror ("ptrace_setregs");
c906108c SS	237	}
	238
	239	if (wanna_store & FP_REGS)
	240	{
c5aa993b JM	241	if (!register_valid[FP0_REGNUM + 9])
c5aa993b JM	242	abort ();
c906108c SS	243	memcpy (&inferior_fp_registers, &registers[REGISTER_BYTE (FP0_REGNUM)],
c906108c SS	244	sizeof inferior_fp_registers.fpu_fr);
c5aa993b	245	memcpy (&inferior_fp_registers.Fpu_fsr,
c906108c SS	246	&registers[REGISTER_BYTE (FPS_REGNUM)], sizeof (FPU_FSR_TYPE));
c906108c SS	247	if (0 !=
c5aa993b JM	248	ptrace (PTRACE_SETFPREGS, inferior_pid,
	249	(PTRACE_ARG3_TYPE) & inferior_fp_registers, 0))
	250	perror ("ptrace_setfpregs");
c906108c SS	251	}
	252	}
	253
	254
	255	static void
	256	fetch_core_registers (core_reg_sect, core_reg_size, which, ignore)
c5aa993b JM	257	char *core_reg_sect;
	258	unsigned core_reg_size;
	259	int which;
	260	CORE_ADDR ignore; /* reg addr, unused in this version */
c906108c SS	261	{
c906108c SS	262
c5aa993b JM	263	if (which == 0)
c5aa993b JM	264	{
c906108c	265
c5aa993b	266	/* Integer registers */
c906108c SS	267
c906108c SS	268	#define gregs ((struct regs *)core_reg_sect)
c5aa993b JM	269	/* G0 always holds 0. */
c5aa993b JM	270	(int ) &registers[REGISTER_BYTE (0)] = 0;
c906108c	271
c5aa993b JM	272	/* The globals and output registers. */
	273	memcpy (&registers[REGISTER_BYTE (G1_REGNUM)], &gregs->r_g1,
	274	15 * REGISTER_RAW_SIZE (G1_REGNUM));
	275	(int ) &registers[REGISTER_BYTE (PS_REGNUM)] = gregs->r_ps;
	276	(int ) &registers[REGISTER_BYTE (PC_REGNUM)] = gregs->r_pc;
	277	(int ) &registers[REGISTER_BYTE (NPC_REGNUM)] = gregs->r_npc;
	278	(int ) &registers[REGISTER_BYTE (Y_REGNUM)] = gregs->r_y;
	279
	280	/* My best guess at where to get the locals and input
	281	registers is exactly where they usually are, right above
	282	the stack pointer. If the core dump was caused by a bus error
	283	from blowing away the stack pointer (as is possible) then this
	284	won't work, but it's worth the try. */
	285	{
	286	int sp;
	287
	288	sp = (int ) &registers[REGISTER_BYTE (SP_REGNUM)];
	289	if (0 != target_read_memory (sp, &registers[REGISTER_BYTE (L0_REGNUM)],
	290	16 * REGISTER_RAW_SIZE (L0_REGNUM)))
	291	{
	292	/* fprintf_unfiltered so user can still use gdb */
	293	fprintf_unfiltered (gdb_stderr,
	294	"Couldn't read input and local registers from core file\n");
	295	}
	296	}
c906108c	297	}
c5aa993b JM	298	else if (which == 2)
c5aa993b JM	299	{
c906108c	300
c5aa993b	301	/* Floating point registers */
c906108c SS	302
c906108c SS	303	#define fpuregs ((struct fpu *) core_reg_sect)
c5aa993b JM	304	if (core_reg_size >= sizeof (struct fpu))
	305	{
	306	memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], fpuregs->fpu_regs,
	307	sizeof (fpuregs->fpu_regs));
	308	memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)], &fpuregs->fpu_fsr,
	309	sizeof (FPU_FSR_TYPE));
	310	}
	311	else
	312	fprintf_unfiltered (gdb_stderr, "Couldn't read float regs from core file\n");
	313	}
c906108c SS	314	}
	315
	316	int
	317	kernel_u_size ()
	318	{
	319	return (sizeof (struct user));
	320	}
c906108c	321	\f
c5aa993b	322
c906108c SS	323	/* Register that we are able to handle sparc core file formats.
	324	FIXME: is this really bfd_target_unknown_flavour? */
	325
	326	static struct core_fns sparc_core_fns =
	327	{
2acceee2 JM	328	bfd_target_unknown_flavour, /* core_flavour */
	329	default_check_format, /* check_format */
	330	default_core_sniffer, /* core_sniffer */
	331	fetch_core_registers, /* core_read_registers */
	332	NULL /* next */
c906108c SS	333	};
	334
	335	void
	336	_initialize_core_sparc ()
	337	{
	338	add_core_fns (&sparc_core_fns);
	339	}