Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
3666a048 | 3 | Copyright (C) 2003-2021 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
b41c5a85 | 23 | #include "dwarf2.h" |
82ca8957 | 24 | #include "dwarf2/frame.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c | 35 | #include "target.h" |
3f7b46f2 | 36 | #include "target-descriptions.h" |
c906108c | 37 | #include "value.h" |
c906108c | 38 | |
386c036b | 39 | #include "sparc-tdep.h" |
e6f9c00b | 40 | #include "sparc-ravenscar-thread.h" |
325fac50 | 41 | #include <algorithm> |
c906108c | 42 | |
a54124c5 MK |
43 | struct regset; |
44 | ||
9eb42ed1 MK |
45 | /* This file implements the SPARC 32-bit ABI as defined by the section |
46 | "Low-Level System Information" of the SPARC Compliance Definition | |
47 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 48 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 49 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
50 | |
51 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
52 | BSD-based, which is sometimes (retroactively?) referred to as | |
53 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
54 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
55 | suffering from severe version number inflation). Solaris 2.x is | |
56 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
57 | 2.x is SVR4-based. */ | |
58 | ||
59 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
60 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
61 | code that can handle both. The 64-bit specific code lives in | |
62 | sparc64-tdep.c; don't add any here. */ | |
63 | ||
64 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 65 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 66 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
67 | |
68 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
69 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
70 | hosts, so undefine it first. */ | |
71 | #undef BIAS | |
72 | #define BIAS 2047 | |
73 | ||
74 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
75 | #define X_OP(i) (((i) >> 30) & 0x3) |
76 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
77 | #define X_A(i) (((i) >> 29) & 1) | |
78 | #define X_COND(i) (((i) >> 25) & 0xf) | |
79 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
80 | #define X_IMM22(i) ((i) & 0x3fffff) | |
81 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 82 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 83 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 84 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 85 | /* Sign extension macros. */ |
c906108c | 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 88 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 89 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
90 | /* Macros to identify some instructions. */ |
91 | /* RETURN (RETT in V8) */ | |
92 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 93 | |
386c036b MK |
94 | /* Fetch the instruction at PC. Instructions are always big-endian |
95 | even if the processor operates in little-endian mode. */ | |
96 | ||
97 | unsigned long | |
98 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 99 | { |
e1613aba | 100 | gdb_byte buf[4]; |
386c036b MK |
101 | unsigned long insn; |
102 | int i; | |
103 | ||
690668cc | 104 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 105 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 106 | return 0; |
c906108c | 107 | |
386c036b MK |
108 | insn = 0; |
109 | for (i = 0; i < sizeof (buf); i++) | |
110 | insn = (insn << 8) | buf[i]; | |
111 | return insn; | |
112 | } | |
42cdca6c MK |
113 | \f |
114 | ||
5465445a JB |
115 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
116 | instruction. */ | |
117 | ||
118 | static int | |
119 | sparc_is_unimp_insn (CORE_ADDR pc) | |
120 | { | |
121 | const unsigned long insn = sparc_fetch_instruction (pc); | |
122 | ||
123 | return ((insn & 0xc1c00000) == 0); | |
124 | } | |
125 | ||
d0b5971a JM |
126 | /* Return non-zero if the instruction corresponding to PC is an |
127 | "annulled" branch, i.e. the annul bit is set. */ | |
128 | ||
129 | int | |
130 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
131 | { | |
132 | /* The branch instructions featuring an annul bit can be identified | |
133 | by the following bit patterns: | |
134 | ||
135 | OP=0 | |
136 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
137 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
138 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
139 | OP2=6: Branch on FP Condition Codes (FBcc). | |
140 | OP2=3 && Bit28=0: | |
dda83cd7 | 141 | Branch on Integer Register with Prediction (BPr). |
d0b5971a JM |
142 | |
143 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
144 | coprocessor branch instructions (Op2=7). */ | |
145 | ||
146 | const unsigned long insn = sparc_fetch_instruction (pc); | |
147 | const unsigned op2 = X_OP2 (insn); | |
148 | ||
149 | if ((X_OP (insn) == 0) | |
150 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
151 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
152 | return X_A (insn); | |
153 | else | |
154 | return 0; | |
155 | } | |
156 | ||
42cdca6c MK |
157 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
158 | website http://stackghost.cerias.purdue.edu "... transparently and | |
159 | automatically protects applications' stack frames; more | |
160 | specifically, it guards the return pointers. The protection | |
161 | mechanisms require no application source or binary modification and | |
162 | imposes only a negligible performance penalty." | |
163 | ||
164 | The same website provides the following description of how | |
165 | StackGhost works: | |
166 | ||
167 | "StackGhost interfaces with the kernel trap handler that would | |
168 | normally write out registers to the stack and the handler that | |
169 | would read them back in. By XORing a cookie into the | |
170 | return-address saved in the user stack when it is actually written | |
171 | to the stack, and then XOR it out when the return-address is pulled | |
172 | from the stack, StackGhost can cause attacker corrupted return | |
173 | pointers to behave in a manner the attacker cannot predict. | |
174 | StackGhost can also use several unused bits in the return pointer | |
175 | to detect a smashed return pointer and abort the process." | |
176 | ||
177 | For GDB this means that whenever we're reading %i7 from a stack | |
178 | frame's window save area, we'll have to XOR the cookie. | |
179 | ||
180 | More information on StackGuard can be found on in: | |
181 | ||
c378eb4e | 182 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
183 | Stack Protection." 2001. Published in USENIX Security Symposium |
184 | '01. */ | |
185 | ||
186 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
187 | ||
188 | ULONGEST | |
e17a4113 | 189 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 190 | { |
e17a4113 | 191 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
8b88a78e | 192 | struct target_ops *ops = current_top_target (); |
e1613aba | 193 | gdb_byte buf[8]; |
baf92889 MK |
194 | int len; |
195 | ||
13547ab6 | 196 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
197 | if (len == -1) |
198 | return 0; | |
42cdca6c | 199 | |
baf92889 MK |
200 | /* We should have either an 32-bit or an 64-bit cookie. */ |
201 | gdb_assert (len == 4 || len == 8); | |
202 | ||
e17a4113 | 203 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 204 | } |
386c036b | 205 | \f |
baf92889 | 206 | |
386c036b MK |
207 | /* The functions on this page are intended to be used to classify |
208 | function arguments. */ | |
c906108c | 209 | |
386c036b | 210 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 211 | |
386c036b MK |
212 | static int |
213 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 214 | { |
80ad1639 MK |
215 | int len = TYPE_LENGTH (type); |
216 | ||
78134374 | 217 | switch (type->code ()) |
c906108c | 218 | { |
386c036b MK |
219 | case TYPE_CODE_INT: |
220 | case TYPE_CODE_BOOL: | |
221 | case TYPE_CODE_CHAR: | |
222 | case TYPE_CODE_ENUM: | |
223 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
224 | /* We have byte, half-word, word and extended-word/doubleword |
225 | integral types. The doubleword is an extension to the | |
226 | original 32-bit ABI by the SCD 2.4.x. */ | |
227 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
228 | case TYPE_CODE_PTR: |
229 | case TYPE_CODE_REF: | |
aa006118 | 230 | case TYPE_CODE_RVALUE_REF: |
80ad1639 MK |
231 | /* Allow either 32-bit or 64-bit pointers. */ |
232 | return (len == 4 || len == 8); | |
386c036b MK |
233 | default: |
234 | break; | |
235 | } | |
c906108c | 236 | |
386c036b MK |
237 | return 0; |
238 | } | |
c906108c | 239 | |
386c036b | 240 | /* Check whether TYPE is "Floating". */ |
c906108c | 241 | |
386c036b MK |
242 | static int |
243 | sparc_floating_p (const struct type *type) | |
244 | { | |
78134374 | 245 | switch (type->code ()) |
c906108c | 246 | { |
386c036b MK |
247 | case TYPE_CODE_FLT: |
248 | { | |
249 | int len = TYPE_LENGTH (type); | |
250 | return (len == 4 || len == 8 || len == 16); | |
251 | } | |
252 | default: | |
253 | break; | |
254 | } | |
255 | ||
256 | return 0; | |
257 | } | |
c906108c | 258 | |
fe10a582 DM |
259 | /* Check whether TYPE is "Complex Floating". */ |
260 | ||
261 | static int | |
262 | sparc_complex_floating_p (const struct type *type) | |
263 | { | |
78134374 | 264 | switch (type->code ()) |
fe10a582 DM |
265 | { |
266 | case TYPE_CODE_COMPLEX: | |
267 | { | |
268 | int len = TYPE_LENGTH (type); | |
269 | return (len == 8 || len == 16 || len == 32); | |
270 | } | |
271 | default: | |
272 | break; | |
273 | } | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
0497f5b0 JB |
278 | /* Check whether TYPE is "Structure or Union". |
279 | ||
280 | In terms of Ada subprogram calls, arrays are treated the same as | |
281 | struct and union types. So this function also returns non-zero | |
282 | for array types. */ | |
c906108c | 283 | |
386c036b MK |
284 | static int |
285 | sparc_structure_or_union_p (const struct type *type) | |
286 | { | |
78134374 | 287 | switch (type->code ()) |
386c036b MK |
288 | { |
289 | case TYPE_CODE_STRUCT: | |
290 | case TYPE_CODE_UNION: | |
0497f5b0 | 291 | case TYPE_CODE_ARRAY: |
386c036b MK |
292 | return 1; |
293 | default: | |
294 | break; | |
c906108c | 295 | } |
386c036b MK |
296 | |
297 | return 0; | |
c906108c | 298 | } |
386c036b | 299 | |
05bc7456 JB |
300 | /* Return true if TYPE is returned by memory, false if returned by |
301 | register. */ | |
1933fd8e VM |
302 | |
303 | static bool | |
304 | sparc_structure_return_p (const struct type *type) | |
305 | { | |
bd63c870 | 306 | if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) |
1933fd8e | 307 | { |
05bc7456 JB |
308 | /* Float vectors are always returned by memory. */ |
309 | if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) | |
310 | return true; | |
311 | /* Integer vectors are returned by memory if the vector size | |
312 | is greater than 8 bytes long. */ | |
313 | return (TYPE_LENGTH (type) > 8); | |
314 | } | |
1933fd8e | 315 | |
05bc7456 JB |
316 | if (sparc_floating_p (type)) |
317 | { | |
318 | /* Floating point types are passed by register for size 4 and | |
319 | 8 bytes, and by memory for size 16 bytes. */ | |
320 | return (TYPE_LENGTH (type) == 16); | |
1933fd8e | 321 | } |
05bc7456 JB |
322 | |
323 | /* Other than that, only aggregates of all sizes get returned by | |
324 | memory. */ | |
1933fd8e VM |
325 | return sparc_structure_or_union_p (type); |
326 | } | |
327 | ||
05bc7456 JB |
328 | /* Return true if arguments of the given TYPE are passed by |
329 | memory; false if returned by register. */ | |
1933fd8e VM |
330 | |
331 | static bool | |
05bc7456 | 332 | sparc_arg_by_memory_p (const struct type *type) |
1933fd8e | 333 | { |
bd63c870 | 334 | if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) |
1933fd8e | 335 | { |
05bc7456 JB |
336 | /* Float vectors are always passed by memory. */ |
337 | if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) | |
338 | return true; | |
339 | /* Integer vectors are passed by memory if the vector size | |
340 | is greater than 8 bytes long. */ | |
341 | return (TYPE_LENGTH (type) > 8); | |
1933fd8e | 342 | } |
05bc7456 JB |
343 | |
344 | /* Floats are passed by register for size 4 and 8 bytes, and by memory | |
345 | for size 16 bytes. */ | |
346 | if (sparc_floating_p (type)) | |
347 | return (TYPE_LENGTH (type) == 16); | |
348 | ||
349 | /* Complex floats and aggregates of all sizes are passed by memory. */ | |
350 | if (sparc_complex_floating_p (type) || sparc_structure_or_union_p (type)) | |
351 | return true; | |
352 | ||
353 | /* Everything else gets passed by register. */ | |
354 | return false; | |
1933fd8e VM |
355 | } |
356 | ||
386c036b | 357 | /* Register information. */ |
7a36499a IR |
358 | #define SPARC32_FPU_REGISTERS \ |
359 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
360 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
361 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
362 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
363 | #define SPARC32_CP0_REGISTERS \ | |
364 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
386c036b | 365 | |
27087b7f TT |
366 | static const char * const sparc_core_register_names[] = { |
367 | SPARC_CORE_REGISTERS | |
368 | }; | |
369 | static const char * const sparc32_fpu_register_names[] = { | |
370 | SPARC32_FPU_REGISTERS | |
371 | }; | |
372 | static const char * const sparc32_cp0_register_names[] = { | |
373 | SPARC32_CP0_REGISTERS | |
374 | }; | |
3f7b46f2 | 375 | |
27087b7f | 376 | static const char * const sparc32_register_names[] = |
5af923b0 | 377 | { |
7a36499a IR |
378 | SPARC_CORE_REGISTERS, |
379 | SPARC32_FPU_REGISTERS, | |
380 | SPARC32_CP0_REGISTERS | |
5af923b0 MS |
381 | }; |
382 | ||
386c036b MK |
383 | /* Total number of registers. */ |
384 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 385 | |
386c036b MK |
386 | /* We provide the aliases %d0..%d30 for the floating registers as |
387 | "psuedo" registers. */ | |
388 | ||
27087b7f | 389 | static const char * const sparc32_pseudo_register_names[] = |
386c036b MK |
390 | { |
391 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
392 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
393 | }; | |
394 | ||
395 | /* Total number of pseudo registers. */ | |
396 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
397 | ||
7a36499a IR |
398 | /* Return the name of pseudo register REGNUM. */ |
399 | ||
400 | static const char * | |
401 | sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
402 | { | |
403 | regnum -= gdbarch_num_regs (gdbarch); | |
404 | ||
405 | if (regnum < SPARC32_NUM_PSEUDO_REGS) | |
406 | return sparc32_pseudo_register_names[regnum]; | |
407 | ||
408 | internal_error (__FILE__, __LINE__, | |
dda83cd7 SM |
409 | _("sparc32_pseudo_register_name: bad register number %d"), |
410 | regnum); | |
7a36499a IR |
411 | } |
412 | ||
386c036b MK |
413 | /* Return the name of register REGNUM. */ |
414 | ||
415 | static const char * | |
d93859e2 | 416 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b | 417 | { |
3f7b46f2 IR |
418 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
419 | return tdesc_register_name (gdbarch, regnum); | |
420 | ||
7a36499a | 421 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
386c036b MK |
422 | return sparc32_register_names[regnum]; |
423 | ||
7a36499a | 424 | return sparc32_pseudo_register_name (gdbarch, regnum); |
386c036b | 425 | } |
2d457077 | 426 | \f |
209bd28e | 427 | /* Construct types for ISA-specific registers. */ |
2d457077 | 428 | |
209bd28e UW |
429 | static struct type * |
430 | sparc_psr_type (struct gdbarch *gdbarch) | |
431 | { | |
432 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 433 | |
209bd28e UW |
434 | if (!tdep->sparc_psr_type) |
435 | { | |
436 | struct type *type; | |
2d457077 | 437 | |
77b7c781 | 438 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32); |
209bd28e UW |
439 | append_flags_type_flag (type, 5, "ET"); |
440 | append_flags_type_flag (type, 6, "PS"); | |
441 | append_flags_type_flag (type, 7, "S"); | |
442 | append_flags_type_flag (type, 12, "EF"); | |
443 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 444 | |
209bd28e UW |
445 | tdep->sparc_psr_type = type; |
446 | } | |
447 | ||
448 | return tdep->sparc_psr_type; | |
449 | } | |
450 | ||
451 | static struct type * | |
452 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 453 | { |
209bd28e UW |
454 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
455 | ||
456 | if (!tdep->sparc_fsr_type) | |
457 | { | |
458 | struct type *type; | |
459 | ||
77b7c781 | 460 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32); |
209bd28e UW |
461 | append_flags_type_flag (type, 0, "NXA"); |
462 | append_flags_type_flag (type, 1, "DZA"); | |
463 | append_flags_type_flag (type, 2, "UFA"); | |
464 | append_flags_type_flag (type, 3, "OFA"); | |
465 | append_flags_type_flag (type, 4, "NVA"); | |
466 | append_flags_type_flag (type, 5, "NXC"); | |
467 | append_flags_type_flag (type, 6, "DZC"); | |
468 | append_flags_type_flag (type, 7, "UFC"); | |
469 | append_flags_type_flag (type, 8, "OFC"); | |
470 | append_flags_type_flag (type, 9, "NVC"); | |
471 | append_flags_type_flag (type, 22, "NS"); | |
472 | append_flags_type_flag (type, 23, "NXM"); | |
473 | append_flags_type_flag (type, 24, "DZM"); | |
474 | append_flags_type_flag (type, 25, "UFM"); | |
475 | append_flags_type_flag (type, 26, "OFM"); | |
476 | append_flags_type_flag (type, 27, "NVM"); | |
477 | ||
478 | tdep->sparc_fsr_type = type; | |
479 | } | |
480 | ||
481 | return tdep->sparc_fsr_type; | |
2d457077 | 482 | } |
386c036b | 483 | |
7a36499a IR |
484 | /* Return the GDB type object for the "standard" data type of data in |
485 | pseudo register REGNUM. */ | |
486 | ||
487 | static struct type * | |
488 | sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
489 | { | |
490 | regnum -= gdbarch_num_regs (gdbarch); | |
491 | ||
492 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
493 | return builtin_type (gdbarch)->builtin_double; | |
494 | ||
495 | internal_error (__FILE__, __LINE__, | |
dda83cd7 SM |
496 | _("sparc32_pseudo_register_type: bad register number %d"), |
497 | regnum); | |
7a36499a IR |
498 | } |
499 | ||
386c036b | 500 | /* Return the GDB type object for the "standard" data type of data in |
c378eb4e | 501 | register REGNUM. */ |
386c036b MK |
502 | |
503 | static struct type * | |
504 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
505 | { | |
3f7b46f2 IR |
506 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
507 | return tdesc_register_type (gdbarch, regnum); | |
508 | ||
386c036b | 509 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) |
0dfff4cb | 510 | return builtin_type (gdbarch)->builtin_float; |
386c036b | 511 | |
386c036b | 512 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) |
0dfff4cb | 513 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
514 | |
515 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 516 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 517 | |
2d457077 | 518 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 519 | return sparc_psr_type (gdbarch); |
2d457077 MK |
520 | |
521 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 522 | return sparc_fsr_type (gdbarch); |
2d457077 | 523 | |
7a36499a IR |
524 | if (regnum >= gdbarch_num_regs (gdbarch)) |
525 | return sparc32_pseudo_register_type (gdbarch, regnum); | |
526 | ||
df4df182 | 527 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
528 | } |
529 | ||
05d1431c | 530 | static enum register_status |
386c036b | 531 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 532 | readable_regcache *regcache, |
e1613aba | 533 | int regnum, gdb_byte *buf) |
386c036b | 534 | { |
05d1431c PA |
535 | enum register_status status; |
536 | ||
7a36499a | 537 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
538 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
539 | ||
540 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
03f50fc8 | 541 | status = regcache->raw_read (regnum, buf); |
05d1431c | 542 | if (status == REG_VALID) |
03f50fc8 | 543 | status = regcache->raw_read (regnum + 1, buf + 4); |
05d1431c | 544 | return status; |
386c036b MK |
545 | } |
546 | ||
547 | static void | |
548 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
549 | struct regcache *regcache, | |
e1613aba | 550 | int regnum, const gdb_byte *buf) |
386c036b | 551 | { |
7a36499a | 552 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
553 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
554 | ||
555 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
10eaee5f SM |
556 | regcache->raw_write (regnum, buf); |
557 | regcache->raw_write (regnum + 1, buf + 4); | |
386c036b MK |
558 | } |
559 | \f | |
c9cf6e20 | 560 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
961842b2 JM |
561 | |
562 | int | |
c9cf6e20 | 563 | sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
961842b2 JM |
564 | { |
565 | /* This function must return true if we are one instruction after an | |
566 | instruction that destroyed the stack frame of the current | |
567 | function. The SPARC instructions used to restore the callers | |
568 | stack frame are RESTORE and RETURN/RETT. | |
569 | ||
570 | Of these RETURN/RETT is a branch instruction and thus we return | |
571 | true if we are in its delay slot. | |
572 | ||
573 | RESTORE is almost always found in the delay slot of a branch | |
574 | instruction that transfers control to the caller, such as JMPL. | |
575 | Thus the next instruction is in the caller frame and we don't | |
576 | need to do anything about it. */ | |
577 | ||
578 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
579 | ||
580 | return X_RETTURN (insn); | |
581 | } | |
582 | \f | |
386c036b | 583 | |
49a45ecf JB |
584 | static CORE_ADDR |
585 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
586 | { | |
587 | /* The ABI requires double-word alignment. */ | |
588 | return address & ~0x7; | |
589 | } | |
590 | ||
386c036b MK |
591 | static CORE_ADDR |
592 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 593 | CORE_ADDR funcaddr, |
386c036b MK |
594 | struct value **args, int nargs, |
595 | struct type *value_type, | |
e4fd649a UW |
596 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
597 | struct regcache *regcache) | |
c906108c | 598 | { |
e17a4113 UW |
599 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
600 | ||
386c036b MK |
601 | *bp_addr = sp - 4; |
602 | *real_pc = funcaddr; | |
603 | ||
d80b854b | 604 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 605 | { |
e1613aba | 606 | gdb_byte buf[4]; |
386c036b MK |
607 | |
608 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
609 | store_unsigned_integer (buf, 4, byte_order, |
610 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
611 | write_memory (sp - 8, buf, 4); |
612 | return sp - 8; | |
c906108c SS |
613 | } |
614 | ||
386c036b MK |
615 | return sp - 4; |
616 | } | |
617 | ||
618 | static CORE_ADDR | |
619 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
620 | struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
621 | function_call_return_method return_method, |
622 | CORE_ADDR struct_addr) | |
386c036b | 623 | { |
ac7936df | 624 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 625 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
626 | /* Number of words in the "parameter array". */ |
627 | int num_elements = 0; | |
628 | int element = 0; | |
629 | int i; | |
630 | ||
631 | for (i = 0; i < nargs; i++) | |
c906108c | 632 | { |
4991999e | 633 | struct type *type = value_type (args[i]); |
386c036b MK |
634 | int len = TYPE_LENGTH (type); |
635 | ||
05bc7456 | 636 | if (sparc_arg_by_memory_p (type)) |
c906108c | 637 | { |
386c036b MK |
638 | /* Structure, Union and Quad-Precision Arguments. */ |
639 | sp -= len; | |
640 | ||
641 | /* Use doubleword alignment for these values. That's always | |
dda83cd7 | 642 | correct, and wasting a few bytes shouldn't be a problem. */ |
386c036b MK |
643 | sp &= ~0x7; |
644 | ||
0fd88904 | 645 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
646 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
647 | num_elements++; | |
648 | } | |
649 | else if (sparc_floating_p (type)) | |
650 | { | |
651 | /* Floating arguments. */ | |
652 | gdb_assert (len == 4 || len == 8); | |
653 | num_elements += (len / 4); | |
c906108c | 654 | } |
c5aa993b JM |
655 | else |
656 | { | |
05bc7456 | 657 | /* Arguments passed via the General Purpose Registers. */ |
386c036b | 658 | num_elements += ((len + 3) / 4); |
c5aa993b | 659 | } |
c906108c | 660 | } |
c906108c | 661 | |
386c036b | 662 | /* Always allocate at least six words. */ |
325fac50 | 663 | sp -= std::max (6, num_elements) * 4; |
c906108c | 664 | |
386c036b MK |
665 | /* The psABI says that "Software convention requires space for the |
666 | struct/union return value pointer, even if the word is unused." */ | |
667 | sp -= 4; | |
c906108c | 668 | |
386c036b MK |
669 | /* The psABI says that "Although software convention and the |
670 | operating system require every stack frame to be doubleword | |
671 | aligned." */ | |
672 | sp &= ~0x7; | |
c906108c | 673 | |
386c036b | 674 | for (i = 0; i < nargs; i++) |
c906108c | 675 | { |
0fd88904 | 676 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 677 | struct type *type = value_type (args[i]); |
386c036b | 678 | int len = TYPE_LENGTH (type); |
1933fd8e VM |
679 | gdb_byte buf[4]; |
680 | ||
681 | if (len < 4) | |
dda83cd7 SM |
682 | { |
683 | memset (buf, 0, 4 - len); | |
684 | memcpy (buf + 4 - len, valbuf, len); | |
685 | valbuf = buf; | |
686 | len = 4; | |
687 | } | |
c906108c | 688 | |
386c036b | 689 | gdb_assert (len == 4 || len == 8); |
c906108c | 690 | |
386c036b MK |
691 | if (element < 6) |
692 | { | |
693 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 694 | |
b66f5587 | 695 | regcache->cooked_write (regnum, valbuf); |
386c036b | 696 | if (len > 4 && element < 5) |
b66f5587 | 697 | regcache->cooked_write (regnum + 1, valbuf + 4); |
386c036b | 698 | } |
5af923b0 | 699 | |
386c036b MK |
700 | /* Always store the argument in memory. */ |
701 | write_memory (sp + 4 + element * 4, valbuf, len); | |
702 | element += len / 4; | |
703 | } | |
c906108c | 704 | |
386c036b | 705 | gdb_assert (element == num_elements); |
c906108c | 706 | |
cf84fa6b | 707 | if (return_method == return_method_struct) |
c906108c | 708 | { |
e1613aba | 709 | gdb_byte buf[4]; |
c906108c | 710 | |
e17a4113 | 711 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
712 | write_memory (sp, buf, 4); |
713 | } | |
c906108c | 714 | |
386c036b | 715 | return sp; |
c906108c SS |
716 | } |
717 | ||
386c036b | 718 | static CORE_ADDR |
7d9b040b | 719 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
720 | struct regcache *regcache, CORE_ADDR bp_addr, |
721 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
722 | function_call_return_method return_method, |
723 | CORE_ADDR struct_addr) | |
c906108c | 724 | { |
cf84fa6b AH |
725 | CORE_ADDR call_pc = (return_method == return_method_struct |
726 | ? (bp_addr - 12) : (bp_addr - 8)); | |
386c036b MK |
727 | |
728 | /* Set return address. */ | |
729 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
730 | ||
731 | /* Set up function arguments. */ | |
cf84fa6b AH |
732 | sp = sparc32_store_arguments (regcache, nargs, args, sp, return_method, |
733 | struct_addr); | |
386c036b MK |
734 | |
735 | /* Allocate the 16-word window save area. */ | |
736 | sp -= 16 * 4; | |
c906108c | 737 | |
386c036b MK |
738 | /* Stack should be doubleword aligned at this point. */ |
739 | gdb_assert (sp % 8 == 0); | |
c906108c | 740 | |
386c036b MK |
741 | /* Finally, update the stack pointer. */ |
742 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
743 | ||
744 | return sp; | |
745 | } | |
746 | \f | |
c906108c | 747 | |
386c036b MK |
748 | /* Use the program counter to determine the contents and size of a |
749 | breakpoint instruction. Return a pointer to a string of bytes that | |
750 | encode a breakpoint instruction, store the length of the string in | |
751 | *LEN and optionally adjust *PC to point to the correct memory | |
752 | location for inserting the breakpoint. */ | |
04180708 | 753 | constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 754 | |
04180708 | 755 | typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; |
386c036b | 756 | \f |
c906108c | 757 | |
386c036b | 758 | /* Allocate and initialize a frame cache. */ |
c906108c | 759 | |
386c036b MK |
760 | static struct sparc_frame_cache * |
761 | sparc_alloc_frame_cache (void) | |
762 | { | |
763 | struct sparc_frame_cache *cache; | |
c906108c | 764 | |
386c036b | 765 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 766 | |
386c036b MK |
767 | /* Base address. */ |
768 | cache->base = 0; | |
769 | cache->pc = 0; | |
c906108c | 770 | |
386c036b MK |
771 | /* Frameless until proven otherwise. */ |
772 | cache->frameless_p = 1; | |
369c397b JB |
773 | cache->frame_offset = 0; |
774 | cache->saved_regs_mask = 0; | |
775 | cache->copied_regs_mask = 0; | |
386c036b MK |
776 | cache->struct_return_p = 0; |
777 | ||
778 | return cache; | |
779 | } | |
780 | ||
b0b92586 JB |
781 | /* GCC generates several well-known sequences of instructions at the begining |
782 | of each function prologue when compiling with -fstack-check. If one of | |
783 | such sequences starts at START_PC, then return the address of the | |
784 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
785 | ||
786 | static CORE_ADDR | |
787 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
788 | { | |
789 | CORE_ADDR pc = start_pc; | |
790 | unsigned long insn; | |
2067c8d4 | 791 | int probing_loop = 0; |
b0b92586 JB |
792 | |
793 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 794 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 795 | |
dda83cd7 SM |
796 | sethi <some immediate>, %g1 |
797 | sub %sp, %g1, %g1 | |
2067c8d4 JG |
798 | |
799 | or: | |
800 | ||
dda83cd7 SM |
801 | sethi <some immediate>, %g1 |
802 | sethi <some immediate>, %g4 | |
803 | sub %sp, %g1, %g1 | |
2067c8d4 JG |
804 | |
805 | or: | |
806 | ||
dda83cd7 SM |
807 | sethi <some immediate>, %g1 |
808 | sub %sp, %g1, %g1 | |
809 | sethi <some immediate>, %g4 | |
2067c8d4 JG |
810 | |
811 | If the optional instruction is found (setting g4), assume that a | |
812 | probing loop will follow. */ | |
813 | ||
814 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
815 | insn = sparc_fetch_instruction (pc); |
816 | pc = pc + 4; | |
817 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
818 | return start_pc; | |
819 | ||
2067c8d4 | 820 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
821 | insn = sparc_fetch_instruction (pc); |
822 | pc = pc + 4; | |
2067c8d4 JG |
823 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
824 | { | |
825 | probing_loop = 1; | |
826 | insn = sparc_fetch_instruction (pc); | |
827 | pc = pc + 4; | |
828 | } | |
829 | ||
830 | /* sub %sp, %g1, %g1 */ | |
b0b92586 | 831 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
dda83cd7 | 832 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) |
b0b92586 JB |
833 | return start_pc; |
834 | ||
835 | insn = sparc_fetch_instruction (pc); | |
836 | pc = pc + 4; | |
837 | ||
2067c8d4 JG |
838 | /* optional: sethi <some immediate>, %g4 */ |
839 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
840 | { | |
841 | probing_loop = 1; | |
842 | insn = sparc_fetch_instruction (pc); | |
843 | pc = pc + 4; | |
844 | } | |
845 | ||
b0b92586 | 846 | /* First possible sequence: |
dda83cd7 SM |
847 | [first two instructions above] |
848 | clr [%g1 - some immediate] */ | |
b0b92586 JB |
849 | |
850 | /* clr [%g1 - some immediate] */ | |
851 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
852 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
853 | { | |
854 | /* Valid stack-check sequence, return the new PC. */ | |
855 | return pc; | |
856 | } | |
857 | ||
858 | /* Second possible sequence: A small number of probes. | |
dda83cd7 SM |
859 | [first two instructions above] |
860 | clr [%g1] | |
861 | add %g1, -<some immediate>, %g1 | |
862 | clr [%g1] | |
863 | [repeat the two instructions above any (small) number of times] | |
864 | clr [%g1 - some immediate] */ | |
b0b92586 JB |
865 | |
866 | /* clr [%g1] */ | |
867 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
868 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
869 | { | |
870 | while (1) | |
dda83cd7 SM |
871 | { |
872 | /* add %g1, -<some immediate>, %g1 */ | |
873 | insn = sparc_fetch_instruction (pc); | |
874 | pc = pc + 4; | |
875 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
876 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
877 | break; | |
878 | ||
879 | /* clr [%g1] */ | |
880 | insn = sparc_fetch_instruction (pc); | |
881 | pc = pc + 4; | |
882 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
883 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
884 | return start_pc; | |
885 | } | |
b0b92586 JB |
886 | |
887 | /* clr [%g1 - some immediate] */ | |
888 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
dda83cd7 SM |
889 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) |
890 | return start_pc; | |
b0b92586 JB |
891 | |
892 | /* We found a valid stack-check sequence, return the new PC. */ | |
893 | return pc; | |
894 | } | |
895 | ||
896 | /* Third sequence: A probing loop. | |
dda83cd7 SM |
897 | [first three instructions above] |
898 | sub %g1, %g4, %g4 | |
899 | cmp %g1, %g4 | |
900 | be <disp> | |
901 | add %g1, -<some immediate>, %g1 | |
902 | ba <disp> | |
903 | clr [%g1] | |
2067c8d4 JG |
904 | |
905 | And an optional last probe for the remainder: | |
906 | ||
dda83cd7 | 907 | clr [%g4 - some immediate] */ |
b0b92586 | 908 | |
2067c8d4 | 909 | if (probing_loop) |
b0b92586 JB |
910 | { |
911 | /* sub %g1, %g4, %g4 */ | |
b0b92586 | 912 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
dda83cd7 SM |
913 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) |
914 | return start_pc; | |
b0b92586 JB |
915 | |
916 | /* cmp %g1, %g4 */ | |
917 | insn = sparc_fetch_instruction (pc); | |
918 | pc = pc + 4; | |
919 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
dda83cd7 SM |
920 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) |
921 | return start_pc; | |
b0b92586 JB |
922 | |
923 | /* be <disp> */ | |
924 | insn = sparc_fetch_instruction (pc); | |
925 | pc = pc + 4; | |
926 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
dda83cd7 | 927 | return start_pc; |
b0b92586 JB |
928 | |
929 | /* add %g1, -<some immediate>, %g1 */ | |
930 | insn = sparc_fetch_instruction (pc); | |
931 | pc = pc + 4; | |
932 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
dda83cd7 SM |
933 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) |
934 | return start_pc; | |
b0b92586 JB |
935 | |
936 | /* ba <disp> */ | |
937 | insn = sparc_fetch_instruction (pc); | |
938 | pc = pc + 4; | |
939 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
dda83cd7 | 940 | return start_pc; |
b0b92586 | 941 | |
2067c8d4 | 942 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
943 | insn = sparc_fetch_instruction (pc); |
944 | pc = pc + 4; | |
2067c8d4 | 945 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
dda83cd7 | 946 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 |
2067c8d4 | 947 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) |
dda83cd7 | 948 | return start_pc; |
b0b92586 | 949 | |
2067c8d4 JG |
950 | /* We found a valid stack-check sequence, return the new PC. */ |
951 | ||
952 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
953 | insn = sparc_fetch_instruction (pc); |
954 | pc = pc + 4; | |
955 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
dda83cd7 SM |
956 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) |
957 | return pc - 4; | |
2067c8d4 JG |
958 | else |
959 | return pc; | |
b0b92586 JB |
960 | } |
961 | ||
962 | /* No stack check code in our prologue, return the start_pc. */ | |
963 | return start_pc; | |
964 | } | |
965 | ||
369c397b JB |
966 | /* Record the effect of a SAVE instruction on CACHE. */ |
967 | ||
968 | void | |
969 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
970 | { | |
971 | /* The frame is set up. */ | |
972 | cache->frameless_p = 0; | |
973 | ||
974 | /* The frame pointer contains the CFA. */ | |
975 | cache->frame_offset = 0; | |
976 | ||
977 | /* The `local' and `in' registers are all saved. */ | |
978 | cache->saved_regs_mask = 0xffff; | |
979 | ||
980 | /* The `out' registers are all renamed. */ | |
981 | cache->copied_regs_mask = 0xff; | |
982 | } | |
983 | ||
984 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
985 | Bail out early if CURRENT_PC is reached. Return the address where | |
986 | the analysis stopped. | |
987 | ||
988 | We handle both the traditional register window model and the single | |
989 | register window (aka flat) model. */ | |
990 | ||
386c036b | 991 | CORE_ADDR |
be8626e0 MD |
992 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
993 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 994 | { |
be8626e0 | 995 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
996 | unsigned long insn; |
997 | int offset = 0; | |
c906108c | 998 | int dest = -1; |
c906108c | 999 | |
b0b92586 JB |
1000 | pc = sparc_skip_stack_check (pc); |
1001 | ||
386c036b MK |
1002 | if (current_pc <= pc) |
1003 | return current_pc; | |
1004 | ||
1005 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
1006 | SPARC the linker usually defines a symbol (typically | |
1007 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
1008 | This symbol makes us end up here with PC pointing at the start of | |
1009 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
1010 | would do our normal prologue analysis, we would probably conclude | |
1011 | that we've got a frame when in reality we don't, since the | |
1012 | dynamic linker patches up the first PLT with some code that | |
1013 | starts with a SAVE instruction. Patch up PC such that it points | |
1014 | at the start of our PLT entry. */ | |
3e5d3a5a | 1015 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 1016 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 1017 | |
386c036b MK |
1018 | insn = sparc_fetch_instruction (pc); |
1019 | ||
369c397b JB |
1020 | /* Recognize store insns and record their sources. */ |
1021 | while (X_OP (insn) == 3 | |
1022 | && (X_OP3 (insn) == 0x4 /* stw */ | |
1023 | || X_OP3 (insn) == 0x7 /* std */ | |
1024 | || X_OP3 (insn) == 0xe) /* stx */ | |
1025 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
1026 | { | |
1027 | int regnum = X_RD (insn); | |
1028 | ||
1029 | /* Recognize stores into the corresponding stack slots. */ | |
1030 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
1031 | && ((X_I (insn) | |
1032 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
1033 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
1034 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
1035 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
1036 | { | |
1037 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
1038 | if (X_OP3 (insn) == 0x7) | |
1039 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
1040 | } | |
1041 | ||
1042 | offset += 4; | |
1043 | ||
1044 | insn = sparc_fetch_instruction (pc + offset); | |
1045 | } | |
1046 | ||
386c036b MK |
1047 | /* Recognize a SETHI insn and record its destination. */ |
1048 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
1049 | { |
1050 | dest = X_RD (insn); | |
386c036b MK |
1051 | offset += 4; |
1052 | ||
369c397b | 1053 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
1054 | } |
1055 | ||
386c036b MK |
1056 | /* Allow for an arithmetic operation on DEST or %g1. */ |
1057 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
1058 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
1059 | { | |
386c036b | 1060 | offset += 4; |
c906108c | 1061 | |
369c397b | 1062 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 1063 | } |
c906108c | 1064 | |
386c036b MK |
1065 | /* Check for the SAVE instruction that sets up the frame. */ |
1066 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 1067 | { |
369c397b JB |
1068 | sparc_record_save_insn (cache); |
1069 | offset += 4; | |
1070 | return pc + offset; | |
1071 | } | |
1072 | ||
1073 | /* Check for an arithmetic operation on %sp. */ | |
1074 | if (X_OP (insn) == 2 | |
1075 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1076 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1077 | && X_RD (insn) == SPARC_SP_REGNUM) | |
1078 | { | |
1079 | if (X_I (insn)) | |
1080 | { | |
1081 | cache->frame_offset = X_SIMM13 (insn); | |
1082 | if (X_OP3 (insn) == 0) | |
1083 | cache->frame_offset = -cache->frame_offset; | |
1084 | } | |
1085 | offset += 4; | |
1086 | ||
1087 | insn = sparc_fetch_instruction (pc + offset); | |
1088 | ||
1089 | /* Check for an arithmetic operation that sets up the frame. */ | |
1090 | if (X_OP (insn) == 2 | |
1091 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1092 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1093 | && X_RD (insn) == SPARC_FP_REGNUM) | |
1094 | { | |
1095 | cache->frameless_p = 0; | |
1096 | cache->frame_offset = 0; | |
1097 | /* We could check that the amount subtracted to %sp above is the | |
1098 | same as the one added here, but this seems superfluous. */ | |
1099 | cache->copied_regs_mask |= 0x40; | |
1100 | offset += 4; | |
1101 | ||
1102 | insn = sparc_fetch_instruction (pc + offset); | |
1103 | } | |
1104 | ||
1105 | /* Check for a move (or) operation that copies the return register. */ | |
1106 | if (X_OP (insn) == 2 | |
1107 | && X_OP3 (insn) == 0x2 | |
1108 | && !X_I (insn) | |
1109 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1110 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1111 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1112 | { | |
1113 | cache->copied_regs_mask |= 0x80; | |
1114 | offset += 4; | |
1115 | } | |
1116 | ||
1117 | return pc + offset; | |
c906108c SS |
1118 | } |
1119 | ||
1120 | return pc; | |
1121 | } | |
1122 | ||
386c036b MK |
1123 | /* Return PC of first real instruction of the function starting at |
1124 | START_PC. */ | |
f510d44e | 1125 | |
386c036b | 1126 | static CORE_ADDR |
6093d2eb | 1127 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1128 | { |
f510d44e | 1129 | struct symtab_and_line sal; |
5dd918d9 | 1130 | CORE_ADDR func_addr; |
386c036b | 1131 | struct sparc_frame_cache cache; |
f510d44e DM |
1132 | |
1133 | /* This is the preferred method, find the end of the prologue by | |
1134 | using the debugging information. */ | |
5dd918d9 TT |
1135 | |
1136 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
f510d44e | 1137 | { |
5dd918d9 TT |
1138 | CORE_ADDR post_prologue_pc |
1139 | = skip_prologue_using_sal (gdbarch, func_addr); | |
f510d44e | 1140 | |
5dd918d9 TT |
1141 | if (post_prologue_pc != 0) |
1142 | return std::max (start_pc, post_prologue_pc); | |
f510d44e DM |
1143 | } |
1144 | ||
be8626e0 | 1145 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1146 | |
1147 | /* The psABI says that "Although the first 6 words of arguments | |
1148 | reside in registers, the standard stack frame reserves space for | |
1149 | them.". It also suggests that a function may use that space to | |
1150 | "write incoming arguments 0 to 5" into that space, and that's | |
1151 | indeed what GCC seems to be doing. In that case GCC will | |
1152 | generate debug information that points to the stack slots instead | |
1153 | of the registers, so we should consider the instructions that | |
369c397b | 1154 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1155 | |
369c397b | 1156 | while (1) |
075ccec8 MK |
1157 | { |
1158 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1159 | ||
369c397b JB |
1160 | /* Recognize instructions that store incoming arguments into the |
1161 | corresponding stack slots. */ | |
1162 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1163 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1164 | { |
369c397b JB |
1165 | int regnum = X_RD (insn); |
1166 | ||
1167 | /* Case of arguments still in %o[0..5]. */ | |
1168 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1169 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1170 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1171 | { | |
1172 | start_pc += 4; | |
1173 | continue; | |
1174 | } | |
1175 | ||
1176 | /* Case of arguments copied into %i[0..5]. */ | |
1177 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1178 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1179 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1180 | { | |
1181 | start_pc += 4; | |
1182 | continue; | |
1183 | } | |
075ccec8 MK |
1184 | } |
1185 | ||
1186 | break; | |
1187 | } | |
1188 | ||
1189 | return start_pc; | |
c906108c SS |
1190 | } |
1191 | ||
386c036b | 1192 | /* Normal frames. */ |
9319a2fe | 1193 | |
386c036b | 1194 | struct sparc_frame_cache * |
236369e7 | 1195 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1196 | { |
386c036b | 1197 | struct sparc_frame_cache *cache; |
9319a2fe | 1198 | |
386c036b | 1199 | if (*this_cache) |
19ba03f4 | 1200 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1201 | |
386c036b MK |
1202 | cache = sparc_alloc_frame_cache (); |
1203 | *this_cache = cache; | |
c906108c | 1204 | |
236369e7 | 1205 | cache->pc = get_frame_func (this_frame); |
386c036b | 1206 | if (cache->pc != 0) |
236369e7 JB |
1207 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1208 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1209 | |
1210 | if (cache->frameless_p) | |
c906108c | 1211 | { |
cbeae229 | 1212 | /* This function is frameless, so %fp (%i6) holds the frame |
dda83cd7 SM |
1213 | pointer for our calling frame. Use %sp (%o6) as this frame's |
1214 | base address. */ | |
cbeae229 | 1215 | cache->base = |
dda83cd7 | 1216 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1217 | } |
1218 | else | |
1219 | { | |
1220 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
dda83cd7 | 1221 | base address for the current stack frame. */ |
cbeae229 | 1222 | cache->base = |
236369e7 | 1223 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1224 | } |
c906108c | 1225 | |
369c397b JB |
1226 | cache->base += cache->frame_offset; |
1227 | ||
5b2d44a0 MK |
1228 | if (cache->base & 1) |
1229 | cache->base += BIAS; | |
1230 | ||
386c036b | 1231 | return cache; |
c906108c | 1232 | } |
c906108c | 1233 | |
aff37fc1 DM |
1234 | static int |
1235 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1236 | { | |
1237 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
78134374 | 1238 | enum type_code code = type->code (); |
aff37fc1 DM |
1239 | |
1240 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1241 | { | |
1242 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1243 | if (sparc_structure_or_union_p (type) | |
1244 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1245 | return 1; | |
1246 | } | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
386c036b | 1251 | struct sparc_frame_cache * |
236369e7 | 1252 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1253 | { |
386c036b MK |
1254 | struct sparc_frame_cache *cache; |
1255 | struct symbol *sym; | |
c906108c | 1256 | |
386c036b | 1257 | if (*this_cache) |
19ba03f4 | 1258 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1259 | |
236369e7 | 1260 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1261 | |
386c036b MK |
1262 | sym = find_pc_function (cache->pc); |
1263 | if (sym) | |
c906108c | 1264 | { |
aff37fc1 | 1265 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1266 | } |
5465445a JB |
1267 | else |
1268 | { | |
1269 | /* There is no debugging information for this function to | |
dda83cd7 SM |
1270 | help us determine whether this function returns a struct |
1271 | or not. So we rely on another heuristic which is to check | |
1272 | the instruction at the return address and see if this is | |
1273 | an "unimp" instruction. If it is, then it is a struct-return | |
1274 | function. */ | |
5465445a | 1275 | CORE_ADDR pc; |
369c397b JB |
1276 | int regnum = |
1277 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1278 | |
236369e7 | 1279 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a | 1280 | if (sparc_is_unimp_insn (pc)) |
dda83cd7 | 1281 | cache->struct_return_p = 1; |
5465445a | 1282 | } |
c906108c | 1283 | |
386c036b MK |
1284 | return cache; |
1285 | } | |
1286 | ||
1287 | static void | |
236369e7 | 1288 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1289 | struct frame_id *this_id) |
1290 | { | |
1291 | struct sparc_frame_cache *cache = | |
236369e7 | 1292 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1293 | |
1294 | /* This marks the outermost frame. */ | |
1295 | if (cache->base == 0) | |
1296 | return; | |
1297 | ||
1298 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1299 | } | |
c906108c | 1300 | |
236369e7 JB |
1301 | static struct value * |
1302 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1303 | void **this_cache, int regnum) | |
386c036b | 1304 | { |
e17a4113 | 1305 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1306 | struct sparc_frame_cache *cache = |
236369e7 | 1307 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1308 | |
386c036b | 1309 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1310 | { |
236369e7 | 1311 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1312 | |
236369e7 JB |
1313 | /* If this functions has a Structure, Union or Quad-Precision |
1314 | return value, we have to skip the UNIMP instruction that encodes | |
1315 | the size of the structure. */ | |
1316 | if (cache->struct_return_p) | |
1317 | pc += 4; | |
386c036b | 1318 | |
369c397b JB |
1319 | regnum = |
1320 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1321 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1322 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1323 | } |
1324 | ||
42cdca6c MK |
1325 | /* Handle StackGhost. */ |
1326 | { | |
e17a4113 | 1327 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1328 | |
1329 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1330 | { | |
dda83cd7 SM |
1331 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1332 | ULONGEST i7; | |
236369e7 | 1333 | |
dda83cd7 SM |
1334 | /* Read the value in from memory. */ |
1335 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1336 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1337 | } |
1338 | } | |
1339 | ||
369c397b | 1340 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1341 | in the register save area. */ |
369c397b JB |
1342 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1343 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1344 | { |
236369e7 | 1345 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1346 | |
236369e7 | 1347 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1348 | } |
c906108c | 1349 | |
369c397b JB |
1350 | /* The previous frame's `out' registers may be accessible as the current |
1351 | frame's `in' registers. */ | |
1352 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1353 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1354 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1355 | |
236369e7 | 1356 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1357 | } |
c906108c | 1358 | |
386c036b MK |
1359 | static const struct frame_unwind sparc32_frame_unwind = |
1360 | { | |
1361 | NORMAL_FRAME, | |
8fbca658 | 1362 | default_frame_unwind_stop_reason, |
386c036b | 1363 | sparc32_frame_this_id, |
236369e7 JB |
1364 | sparc32_frame_prev_register, |
1365 | NULL, | |
1366 | default_frame_sniffer | |
386c036b | 1367 | }; |
386c036b | 1368 | \f |
c906108c | 1369 | |
386c036b | 1370 | static CORE_ADDR |
236369e7 | 1371 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1372 | { |
1373 | struct sparc_frame_cache *cache = | |
236369e7 | 1374 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1375 | |
386c036b MK |
1376 | return cache->base; |
1377 | } | |
c906108c | 1378 | |
386c036b MK |
1379 | static const struct frame_base sparc32_frame_base = |
1380 | { | |
1381 | &sparc32_frame_unwind, | |
1382 | sparc32_frame_base_address, | |
1383 | sparc32_frame_base_address, | |
1384 | sparc32_frame_base_address | |
1385 | }; | |
c906108c | 1386 | |
386c036b | 1387 | static struct frame_id |
236369e7 | 1388 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1389 | { |
1390 | CORE_ADDR sp; | |
5af923b0 | 1391 | |
236369e7 | 1392 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1393 | if (sp & 1) |
1394 | sp += BIAS; | |
236369e7 | 1395 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1396 | } |
1397 | \f | |
c906108c | 1398 | |
3923a2b2 MK |
1399 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1400 | that into VALBUF. */ | |
5af923b0 | 1401 | |
386c036b MK |
1402 | static void |
1403 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1404 | gdb_byte *valbuf) |
386c036b MK |
1405 | { |
1406 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1407 | gdb_byte buf[32]; |
c906108c | 1408 | |
1933fd8e | 1409 | gdb_assert (!sparc_structure_return_p (type)); |
c906108c | 1410 | |
1933fd8e | 1411 | if (sparc_floating_p (type) || sparc_complex_floating_p (type) |
78134374 | 1412 | || type->code () == TYPE_CODE_ARRAY) |
5af923b0 | 1413 | { |
386c036b | 1414 | /* Floating return values. */ |
dca08e1f | 1415 | regcache->cooked_read (SPARC_F0_REGNUM, buf); |
386c036b | 1416 | if (len > 4) |
dca08e1f | 1417 | regcache->cooked_read (SPARC_F1_REGNUM, buf + 4); |
fe10a582 DM |
1418 | if (len > 8) |
1419 | { | |
dca08e1f SM |
1420 | regcache->cooked_read (SPARC_F2_REGNUM, buf + 8); |
1421 | regcache->cooked_read (SPARC_F3_REGNUM, buf + 12); | |
fe10a582 DM |
1422 | } |
1423 | if (len > 16) | |
1424 | { | |
dca08e1f SM |
1425 | regcache->cooked_read (SPARC_F4_REGNUM, buf + 16); |
1426 | regcache->cooked_read (SPARC_F5_REGNUM, buf + 20); | |
1427 | regcache->cooked_read (SPARC_F6_REGNUM, buf + 24); | |
1428 | regcache->cooked_read (SPARC_F7_REGNUM, buf + 28); | |
fe10a582 | 1429 | } |
386c036b | 1430 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1431 | } |
1432 | else | |
1433 | { | |
386c036b MK |
1434 | /* Integral and pointer return values. */ |
1435 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1436 | |
dca08e1f | 1437 | regcache->cooked_read (SPARC_O0_REGNUM, buf); |
386c036b MK |
1438 | if (len > 4) |
1439 | { | |
dca08e1f | 1440 | regcache->cooked_read (SPARC_O1_REGNUM, buf + 4); |
386c036b MK |
1441 | gdb_assert (len == 8); |
1442 | memcpy (valbuf, buf, 8); | |
1443 | } | |
1444 | else | |
1445 | { | |
1446 | /* Just stripping off any unused bytes should preserve the | |
1447 | signed-ness just fine. */ | |
1448 | memcpy (valbuf, buf + 4 - len, len); | |
1449 | } | |
1450 | } | |
1451 | } | |
c906108c | 1452 | |
3923a2b2 MK |
1453 | /* Store the function return value of type TYPE from VALBUF into |
1454 | REGCACHE. */ | |
c906108c | 1455 | |
386c036b MK |
1456 | static void |
1457 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1458 | const gdb_byte *valbuf) |
386c036b MK |
1459 | { |
1460 | int len = TYPE_LENGTH (type); | |
1933fd8e | 1461 | gdb_byte buf[32]; |
c906108c | 1462 | |
1933fd8e | 1463 | gdb_assert (!sparc_structure_return_p (type)); |
c906108c | 1464 | |
fe10a582 | 1465 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1466 | { |
1467 | /* Floating return values. */ | |
1468 | memcpy (buf, valbuf, len); | |
b66f5587 | 1469 | regcache->cooked_write (SPARC_F0_REGNUM, buf); |
386c036b | 1470 | if (len > 4) |
b66f5587 | 1471 | regcache->cooked_write (SPARC_F1_REGNUM, buf + 4); |
fe10a582 DM |
1472 | if (len > 8) |
1473 | { | |
b66f5587 SM |
1474 | regcache->cooked_write (SPARC_F2_REGNUM, buf + 8); |
1475 | regcache->cooked_write (SPARC_F3_REGNUM, buf + 12); | |
fe10a582 DM |
1476 | } |
1477 | if (len > 16) | |
1478 | { | |
b66f5587 SM |
1479 | regcache->cooked_write (SPARC_F4_REGNUM, buf + 16); |
1480 | regcache->cooked_write (SPARC_F5_REGNUM, buf + 20); | |
1481 | regcache->cooked_write (SPARC_F6_REGNUM, buf + 24); | |
1482 | regcache->cooked_write (SPARC_F7_REGNUM, buf + 28); | |
fe10a582 | 1483 | } |
386c036b MK |
1484 | } |
1485 | else | |
c906108c | 1486 | { |
386c036b MK |
1487 | /* Integral and pointer return values. */ |
1488 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1489 | ||
1490 | if (len > 4) | |
2757dd86 | 1491 | { |
386c036b MK |
1492 | gdb_assert (len == 8); |
1493 | memcpy (buf, valbuf, 8); | |
b66f5587 | 1494 | regcache->cooked_write (SPARC_O1_REGNUM, buf + 4); |
2757dd86 AC |
1495 | } |
1496 | else | |
1497 | { | |
386c036b MK |
1498 | /* ??? Do we need to do any sign-extension here? */ |
1499 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1500 | } |
b66f5587 | 1501 | regcache->cooked_write (SPARC_O0_REGNUM, buf); |
c906108c SS |
1502 | } |
1503 | } | |
1504 | ||
b9d4c5ed | 1505 | static enum return_value_convention |
6a3a010b | 1506 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1507 | struct type *type, struct regcache *regcache, |
1508 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1509 | { |
e17a4113 UW |
1510 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1511 | ||
0a8f48b9 MK |
1512 | /* The psABI says that "...every stack frame reserves the word at |
1513 | %fp+64. If a function returns a structure, union, or | |
1514 | quad-precision value, this word should hold the address of the | |
1515 | object into which the return value should be copied." This | |
1516 | guarantees that we can always find the return value, not just | |
1517 | before the function returns. */ | |
1518 | ||
1933fd8e | 1519 | if (sparc_structure_return_p (type)) |
0a8f48b9 | 1520 | { |
bbfdfe1c DM |
1521 | ULONGEST sp; |
1522 | CORE_ADDR addr; | |
1523 | ||
0a8f48b9 MK |
1524 | if (readbuf) |
1525 | { | |
0a8f48b9 | 1526 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1527 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1528 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1529 | } | |
bbfdfe1c DM |
1530 | if (writebuf) |
1531 | { | |
1532 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1533 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1534 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1535 | } | |
0a8f48b9 MK |
1536 | |
1537 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1538 | } | |
b9d4c5ed MK |
1539 | |
1540 | if (readbuf) | |
1541 | sparc32_extract_return_value (type, regcache, readbuf); | |
1542 | if (writebuf) | |
1543 | sparc32_store_return_value (type, regcache, writebuf); | |
1544 | ||
1545 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1546 | } | |
1547 | ||
386c036b MK |
1548 | static int |
1549 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1550 | { |
386c036b | 1551 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1552 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1553 | || sparc_complex_floating_p (type)); | |
386c036b | 1554 | } |
c906108c | 1555 | |
aff37fc1 | 1556 | static int |
4a4e5149 | 1557 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1558 | { |
236369e7 | 1559 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1560 | struct symbol *sym = find_pc_function (pc); |
1561 | ||
1562 | if (sym) | |
1563 | return sparc32_struct_return_from_sym (sym); | |
1564 | return 0; | |
1565 | } | |
1566 | ||
f5a9b87d DM |
1567 | static void |
1568 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1569 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1570 | struct frame_info *this_frame) |
f5a9b87d | 1571 | { |
aff37fc1 DM |
1572 | int off; |
1573 | ||
f5a9b87d DM |
1574 | switch (regnum) |
1575 | { | |
1576 | case SPARC_G0_REGNUM: | |
1577 | /* Since %g0 is always zero, there is no point in saving it, and | |
1578 | people will be inclined omit it from the CFI. Make sure we | |
1579 | don't warn about that. */ | |
1580 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1581 | break; | |
1582 | case SPARC_SP_REGNUM: | |
1583 | reg->how = DWARF2_FRAME_REG_CFA; | |
1584 | break; | |
1585 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1586 | case SPARC32_NPC_REGNUM: |
1587 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1588 | off = 8; |
4a4e5149 | 1589 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1590 | off += 4; |
1591 | if (regnum == SPARC32_NPC_REGNUM) | |
1592 | off += 4; | |
1593 | reg->loc.offset = off; | |
f5a9b87d DM |
1594 | break; |
1595 | } | |
1596 | } | |
1597 | ||
b41c5a85 JW |
1598 | /* Implement the execute_dwarf_cfa_vendor_op method. */ |
1599 | ||
1600 | static bool | |
1601 | sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, | |
1602 | struct dwarf2_frame_state *fs) | |
1603 | { | |
1604 | /* Only DW_CFA_GNU_window_save is expected on SPARC. */ | |
1605 | if (op != DW_CFA_GNU_window_save) | |
1606 | return false; | |
1607 | ||
1608 | uint64_t reg; | |
1609 | int size = register_size (gdbarch, 0); | |
1610 | ||
1c90d9f0 | 1611 | fs->regs.alloc_regs (32); |
b41c5a85 JW |
1612 | for (reg = 8; reg < 16; reg++) |
1613 | { | |
1614 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG; | |
1615 | fs->regs.reg[reg].loc.reg = reg + 16; | |
1616 | } | |
1617 | for (reg = 16; reg < 32; reg++) | |
1618 | { | |
1619 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET; | |
1620 | fs->regs.reg[reg].loc.offset = (reg - 16) * size; | |
1621 | } | |
1622 | ||
1623 | return true; | |
1624 | } | |
1625 | ||
386c036b MK |
1626 | \f |
1627 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1628 | and most operating systems don't implement it either, so we provide | |
1629 | software single-step mechanism. */ | |
c906108c | 1630 | |
386c036b | 1631 | static CORE_ADDR |
cd76b525 | 1632 | sparc_analyze_control_transfer (struct regcache *regcache, |
c893be75 | 1633 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1634 | { |
1635 | unsigned long insn = sparc_fetch_instruction (pc); | |
1636 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1637 | int branch_p = 0, fused_p = 0; |
386c036b | 1638 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1639 | |
8d1b3521 | 1640 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1641 | { |
8d1b3521 DM |
1642 | if ((insn & 0x10000000) == 0) |
1643 | { | |
1644 | /* Branch on Integer Register with Prediction (BPr). */ | |
1645 | branch_p = 1; | |
1646 | conditional_p = 1; | |
1647 | } | |
1648 | else | |
1649 | { | |
1650 | /* Compare and Branch */ | |
1651 | branch_p = 1; | |
1652 | fused_p = 1; | |
1653 | offset = 4 * X_DISP10 (insn); | |
1654 | } | |
c906108c | 1655 | } |
386c036b | 1656 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1657 | { |
386c036b MK |
1658 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1659 | branch_p = 1; | |
1660 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1661 | } |
386c036b MK |
1662 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1663 | { | |
1664 | /* Branch on Floating-Point Condition Codes with Prediction | |
dda83cd7 | 1665 | (FBPfcc). */ |
386c036b MK |
1666 | branch_p = 1; |
1667 | offset = 4 * X_DISP19 (insn); | |
1668 | } | |
1669 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1670 | { | |
1671 | /* Branch on Integer Condition Codes (Bicc). */ | |
1672 | branch_p = 1; | |
1673 | offset = 4 * X_DISP22 (insn); | |
1674 | } | |
1675 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1676 | { |
386c036b MK |
1677 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1678 | branch_p = 1; | |
1679 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1680 | } |
c893be75 MK |
1681 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1682 | { | |
cd76b525 YQ |
1683 | struct frame_info *frame = get_current_frame (); |
1684 | ||
c893be75 | 1685 | /* Trap instruction (TRAP). */ |
ac7936df | 1686 | return gdbarch_tdep (regcache->arch ())->step_trap (frame, |
cd76b525 | 1687 | insn); |
c893be75 | 1688 | } |
386c036b MK |
1689 | |
1690 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1691 | ||
386c036b | 1692 | if (branch_p) |
c906108c | 1693 | { |
8d1b3521 DM |
1694 | if (fused_p) |
1695 | { | |
1696 | /* Fused compare-and-branch instructions are non-delayed, | |
85102364 | 1697 | and do not have an annulling capability. So we need to |
8d1b3521 DM |
1698 | always set a breakpoint on both the NPC and the branch |
1699 | target address. */ | |
1700 | gdb_assert (offset != 0); | |
1701 | return pc + offset; | |
1702 | } | |
1703 | else if (conditional_p) | |
c906108c | 1704 | { |
386c036b MK |
1705 | /* For conditional branches, return nPC + 4 iff the annul |
1706 | bit is 1. */ | |
1707 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1708 | } |
1709 | else | |
1710 | { | |
386c036b MK |
1711 | /* For unconditional branches, return the target if its |
1712 | specified condition is "always" and return nPC + 4 if the | |
1713 | condition is "never". If the annul bit is 1, set *NPC to | |
1714 | zero. */ | |
1715 | if (X_COND (insn) == 0x0) | |
1716 | pc = *npc, offset = 4; | |
1717 | if (X_A (insn)) | |
1718 | *npc = 0; | |
1719 | ||
386c036b | 1720 | return pc + offset; |
c906108c SS |
1721 | } |
1722 | } | |
386c036b MK |
1723 | |
1724 | return 0; | |
c906108c SS |
1725 | } |
1726 | ||
c893be75 | 1727 | static CORE_ADDR |
0b1b3e42 | 1728 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1729 | { |
1730 | return 0; | |
1731 | } | |
1732 | ||
a0ff9e1a | 1733 | static std::vector<CORE_ADDR> |
f5ea389a | 1734 | sparc_software_single_step (struct regcache *regcache) |
386c036b | 1735 | { |
ac7936df | 1736 | struct gdbarch *arch = regcache->arch (); |
c893be75 | 1737 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1738 | CORE_ADDR npc, nnpc; |
c906108c | 1739 | |
e0cd558a | 1740 | CORE_ADDR pc, orig_npc; |
a0ff9e1a | 1741 | std::vector<CORE_ADDR> next_pcs; |
c906108c | 1742 | |
cd76b525 YQ |
1743 | pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); |
1744 | orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); | |
c906108c | 1745 | |
e0cd558a | 1746 | /* Analyze the instruction at PC. */ |
cd76b525 | 1747 | nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); |
e0cd558a | 1748 | if (npc != 0) |
a0ff9e1a | 1749 | next_pcs.push_back (npc); |
8181d85f | 1750 | |
e0cd558a | 1751 | if (nnpc != 0) |
a0ff9e1a | 1752 | next_pcs.push_back (nnpc); |
c906108c | 1753 | |
e0cd558a UW |
1754 | /* Assert that we have set at least one breakpoint, and that |
1755 | they're not set at the same spot - unless we're going | |
1756 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1757 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1758 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b | 1759 | |
93f9a11f | 1760 | return next_pcs; |
386c036b MK |
1761 | } |
1762 | ||
1763 | static void | |
61a1198a | 1764 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1765 | { |
ac7936df | 1766 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
386c036b | 1767 | |
61a1198a UW |
1768 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1769 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1770 | } |
1771 | \f | |
5af923b0 | 1772 | |
e5139de8 | 1773 | /* Iterate over core file register note sections. */ |
a54124c5 | 1774 | |
e5139de8 AA |
1775 | static void |
1776 | sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
1777 | iterate_over_regset_sections_cb *cb, | |
1778 | void *cb_data, | |
1779 | const struct regcache *regcache) | |
a54124c5 MK |
1780 | { |
1781 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1782 | ||
a616bb94 AH |
1783 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, |
1784 | cb_data); | |
1785 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, | |
1786 | NULL, cb_data); | |
a54124c5 MK |
1787 | } |
1788 | \f | |
1789 | ||
3f7b46f2 IR |
1790 | static int |
1791 | validate_tdesc_registers (const struct target_desc *tdesc, | |
dda83cd7 SM |
1792 | struct tdesc_arch_data *tdesc_data, |
1793 | const char *feature_name, | |
1794 | const char * const register_names[], | |
1795 | unsigned int registers_num, | |
1796 | unsigned int reg_start) | |
3f7b46f2 IR |
1797 | { |
1798 | int valid_p = 1; | |
1799 | const struct tdesc_feature *feature; | |
1800 | ||
1801 | feature = tdesc_find_feature (tdesc, feature_name); | |
1802 | if (feature == NULL) | |
1803 | return 0; | |
1804 | ||
1805 | for (unsigned int i = 0; i < registers_num; i++) | |
1806 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
dda83cd7 SM |
1807 | reg_start + i, |
1808 | register_names[i]); | |
3f7b46f2 IR |
1809 | |
1810 | return valid_p; | |
1811 | } | |
1812 | ||
386c036b MK |
1813 | static struct gdbarch * |
1814 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1815 | { | |
1816 | struct gdbarch_tdep *tdep; | |
3f7b46f2 | 1817 | const struct target_desc *tdesc = info.target_desc; |
386c036b | 1818 | struct gdbarch *gdbarch; |
3f7b46f2 | 1819 | int valid_p = 1; |
c906108c | 1820 | |
386c036b MK |
1821 | /* If there is already a candidate, use it. */ |
1822 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1823 | if (arches != NULL) | |
1824 | return arches->gdbarch; | |
c906108c | 1825 | |
386c036b | 1826 | /* Allocate space for the new architecture. */ |
41bf6aca | 1827 | tdep = XCNEW (struct gdbarch_tdep); |
386c036b | 1828 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1829 | |
386c036b MK |
1830 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1831 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1832 | tdep->step_trap = sparc_step_trap; |
3f7b46f2 IR |
1833 | tdep->fpu_register_names = sparc32_fpu_register_names; |
1834 | tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); | |
1835 | tdep->cp0_register_names = sparc32_cp0_register_names; | |
1836 | tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); | |
386c036b MK |
1837 | |
1838 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1839 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b | 1840 | |
53375380 PA |
1841 | set_gdbarch_wchar_bit (gdbarch, 16); |
1842 | set_gdbarch_wchar_signed (gdbarch, 1); | |
1843 | ||
386c036b MK |
1844 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); |
1845 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1846 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1847 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
3f7b46f2 IR |
1848 | set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); |
1849 | set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); | |
386c036b MK |
1850 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); |
1851 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1852 | ||
1853 | /* Register numbers of various important registers. */ | |
1854 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1855 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1856 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1857 | ||
1858 | /* Call dummy code. */ | |
49a45ecf | 1859 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1860 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1861 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1862 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1863 | ||
b9d4c5ed | 1864 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1865 | set_gdbarch_stabs_argument_has_addr |
1866 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1867 | ||
1868 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1869 | ||
1870 | /* Stack grows downward. */ | |
1871 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1872 | |
04180708 YQ |
1873 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1874 | sparc_breakpoint::kind_from_pc); | |
1875 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1876 | sparc_breakpoint::bp_from_kind); | |
c906108c | 1877 | |
386c036b | 1878 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1879 | |
386c036b MK |
1880 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1881 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1882 | |
236369e7 | 1883 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1884 | |
386c036b MK |
1885 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1886 | ||
f5a9b87d DM |
1887 | /* Hook in the DWARF CFI frame unwinder. */ |
1888 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
b41c5a85 JW |
1889 | /* Register DWARF vendor CFI handler. */ |
1890 | set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, | |
1891 | sparc_execute_dwarf_cfa_vendor_op); | |
f5a9b87d DM |
1892 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the |
1893 | StackGhost issues have been resolved. */ | |
1894 | ||
b2a0b9b2 DM |
1895 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1896 | gdbarch_init_osabi (info, gdbarch); | |
1897 | ||
236369e7 | 1898 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1899 | |
3f7b46f2 IR |
1900 | if (tdesc_has_registers (tdesc)) |
1901 | { | |
c1e1314d | 1902 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
3f7b46f2 IR |
1903 | |
1904 | /* Validate that the descriptor provides the mandatory registers | |
dda83cd7 | 1905 | and allocate their numbers. */ |
c1e1314d | 1906 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), |
dda83cd7 SM |
1907 | "org.gnu.gdb.sparc.cpu", |
1908 | sparc_core_register_names, | |
1909 | ARRAY_SIZE (sparc_core_register_names), | |
1910 | SPARC_G0_REGNUM); | |
c1e1314d | 1911 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), |
dda83cd7 SM |
1912 | "org.gnu.gdb.sparc.fpu", |
1913 | tdep->fpu_register_names, | |
1914 | tdep->fpu_registers_num, | |
1915 | SPARC_F0_REGNUM); | |
c1e1314d | 1916 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), |
dda83cd7 SM |
1917 | "org.gnu.gdb.sparc.cp0", |
1918 | tdep->cp0_register_names, | |
1919 | tdep->cp0_registers_num, | |
1920 | SPARC_F0_REGNUM | |
1921 | + tdep->fpu_registers_num); | |
3f7b46f2 | 1922 | if (!valid_p) |
c1e1314d | 1923 | return NULL; |
3f7b46f2 IR |
1924 | |
1925 | /* Target description may have changed. */ | |
c1e1314d TT |
1926 | info.tdesc_data = tdesc_data.get (); |
1927 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
3f7b46f2 IR |
1928 | } |
1929 | ||
a54124c5 | 1930 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1931 | if (tdep->gregset) |
e5139de8 AA |
1932 | set_gdbarch_iterate_over_regset_sections |
1933 | (gdbarch, sparc_iterate_over_regset_sections); | |
a54124c5 | 1934 | |
7e35103a JB |
1935 | register_sparc_ravenscar_ops (gdbarch); |
1936 | ||
386c036b MK |
1937 | return gdbarch; |
1938 | } | |
1939 | \f | |
1940 | /* Helper functions for dealing with register windows. */ | |
1941 | ||
1942 | void | |
1943 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1944 | { |
ac7936df | 1945 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1946 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b | 1947 | int offset = 0; |
e1613aba | 1948 | gdb_byte buf[8]; |
386c036b MK |
1949 | int i; |
1950 | ||
1951 | if (sp & 1) | |
1952 | { | |
1953 | /* Registers are 64-bit. */ | |
1954 | sp += BIAS; | |
c906108c | 1955 | |
386c036b MK |
1956 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1957 | { | |
1958 | if (regnum == i || regnum == -1) | |
1959 | { | |
1960 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1961 | |
1962 | /* Handle StackGhost. */ | |
1963 | if (i == SPARC_I7_REGNUM) | |
1964 | { | |
e17a4113 UW |
1965 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1966 | ULONGEST i7; | |
f700a364 | 1967 | |
e17a4113 UW |
1968 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1969 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1970 | i7 ^ wcookie); | |
f700a364 MK |
1971 | } |
1972 | ||
73e1c03f | 1973 | regcache->raw_supply (i, buf); |
386c036b MK |
1974 | } |
1975 | } | |
1976 | } | |
1977 | else | |
c906108c | 1978 | { |
386c036b MK |
1979 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1980 | pointer. */ | |
1981 | sp &= 0xffffffffUL; | |
c906108c | 1982 | |
386c036b MK |
1983 | /* Clear out the top half of the temporary buffer, and put the |
1984 | register value in the bottom half if we're in 64-bit mode. */ | |
ac7936df | 1985 | if (gdbarch_ptr_bit (regcache->arch ()) == 64) |
c906108c | 1986 | { |
386c036b MK |
1987 | memset (buf, 0, 4); |
1988 | offset = 4; | |
1989 | } | |
c906108c | 1990 | |
386c036b MK |
1991 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1992 | { | |
1993 | if (regnum == i || regnum == -1) | |
1994 | { | |
1995 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1996 | buf + offset, 4); | |
42cdca6c MK |
1997 | |
1998 | /* Handle StackGhost. */ | |
1999 | if (i == SPARC_I7_REGNUM) | |
2000 | { | |
e17a4113 UW |
2001 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2002 | ULONGEST i7; | |
42cdca6c | 2003 | |
e17a4113 UW |
2004 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
2005 | store_unsigned_integer (buf + offset, 4, byte_order, | |
2006 | i7 ^ wcookie); | |
42cdca6c MK |
2007 | } |
2008 | ||
73e1c03f | 2009 | regcache->raw_supply (i, buf); |
386c036b | 2010 | } |
c906108c SS |
2011 | } |
2012 | } | |
c906108c | 2013 | } |
c906108c SS |
2014 | |
2015 | void | |
386c036b MK |
2016 | sparc_collect_rwindow (const struct regcache *regcache, |
2017 | CORE_ADDR sp, int regnum) | |
c906108c | 2018 | { |
ac7936df | 2019 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2020 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b | 2021 | int offset = 0; |
e1613aba | 2022 | gdb_byte buf[8]; |
386c036b | 2023 | int i; |
5af923b0 | 2024 | |
386c036b | 2025 | if (sp & 1) |
5af923b0 | 2026 | { |
386c036b MK |
2027 | /* Registers are 64-bit. */ |
2028 | sp += BIAS; | |
c906108c | 2029 | |
386c036b MK |
2030 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
2031 | { | |
2032 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
2033 | { | |
34a79281 | 2034 | regcache->raw_collect (i, buf); |
f700a364 MK |
2035 | |
2036 | /* Handle StackGhost. */ | |
2037 | if (i == SPARC_I7_REGNUM) | |
2038 | { | |
e17a4113 UW |
2039 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2040 | ULONGEST i7; | |
f700a364 | 2041 | |
e17a4113 UW |
2042 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
2043 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
2044 | } |
2045 | ||
386c036b MK |
2046 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
2047 | } | |
2048 | } | |
5af923b0 MS |
2049 | } |
2050 | else | |
2051 | { | |
386c036b MK |
2052 | /* Registers are 32-bit. Toss any sign-extension of the stack |
2053 | pointer. */ | |
2054 | sp &= 0xffffffffUL; | |
2055 | ||
2056 | /* Only use the bottom half if we're in 64-bit mode. */ | |
ac7936df | 2057 | if (gdbarch_ptr_bit (regcache->arch ()) == 64) |
386c036b MK |
2058 | offset = 4; |
2059 | ||
2060 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2061 | { | |
2062 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
2063 | { | |
34a79281 | 2064 | regcache->raw_collect (i, buf); |
42cdca6c MK |
2065 | |
2066 | /* Handle StackGhost. */ | |
2067 | if (i == SPARC_I7_REGNUM) | |
2068 | { | |
e17a4113 UW |
2069 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2070 | ULONGEST i7; | |
42cdca6c | 2071 | |
e17a4113 UW |
2072 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
2073 | store_unsigned_integer (buf + offset, 4, byte_order, | |
2074 | i7 ^ wcookie); | |
42cdca6c MK |
2075 | } |
2076 | ||
386c036b MK |
2077 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
2078 | buf + offset, 4); | |
2079 | } | |
2080 | } | |
5af923b0 | 2081 | } |
c906108c SS |
2082 | } |
2083 | ||
386c036b MK |
2084 | /* Helper functions for dealing with register sets. */ |
2085 | ||
c906108c | 2086 | void |
b4fd25c9 | 2087 | sparc32_supply_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2088 | struct regcache *regcache, |
2089 | int regnum, const void *gregs) | |
c906108c | 2090 | { |
19ba03f4 | 2091 | const gdb_byte *regs = (const gdb_byte *) gregs; |
22e74ef9 | 2092 | gdb_byte zero[4] = { 0 }; |
386c036b | 2093 | int i; |
5af923b0 | 2094 | |
386c036b | 2095 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
73e1c03f | 2096 | regcache->raw_supply (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); |
c906108c | 2097 | |
386c036b | 2098 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
73e1c03f | 2099 | regcache->raw_supply (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); |
5af923b0 | 2100 | |
386c036b | 2101 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
73e1c03f | 2102 | regcache->raw_supply (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); |
5af923b0 | 2103 | |
386c036b | 2104 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
73e1c03f | 2105 | regcache->raw_supply (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); |
5af923b0 | 2106 | |
386c036b | 2107 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
73e1c03f | 2108 | regcache->raw_supply (SPARC_G0_REGNUM, &zero); |
5af923b0 | 2109 | |
386c036b | 2110 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 2111 | { |
b4fd25c9 | 2112 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2113 | |
2114 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2115 | { | |
2116 | if (regnum == i || regnum == -1) | |
73e1c03f | 2117 | regcache->raw_supply (i, regs + offset); |
386c036b MK |
2118 | offset += 4; |
2119 | } | |
c906108c | 2120 | } |
386c036b MK |
2121 | |
2122 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 2123 | { |
386c036b | 2124 | /* Not all of the register set variants include Locals and |
dda83cd7 | 2125 | Inputs. For those that don't, we read them off the stack. */ |
b4fd25c9 | 2126 | if (gregmap->r_l0_offset == -1) |
386c036b MK |
2127 | { |
2128 | ULONGEST sp; | |
2129 | ||
2130 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
2131 | sparc_supply_rwindow (regcache, sp, regnum); | |
2132 | } | |
2133 | else | |
2134 | { | |
b4fd25c9 | 2135 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2136 | |
2137 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2138 | { | |
2139 | if (regnum == i || regnum == -1) | |
73e1c03f | 2140 | regcache->raw_supply (i, regs + offset); |
386c036b MK |
2141 | offset += 4; |
2142 | } | |
2143 | } | |
c906108c SS |
2144 | } |
2145 | } | |
2146 | ||
c5aa993b | 2147 | void |
b4fd25c9 | 2148 | sparc32_collect_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2149 | const struct regcache *regcache, |
2150 | int regnum, void *gregs) | |
c906108c | 2151 | { |
19ba03f4 | 2152 | gdb_byte *regs = (gdb_byte *) gregs; |
386c036b | 2153 | int i; |
c5aa993b | 2154 | |
386c036b | 2155 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
34a79281 | 2156 | regcache->raw_collect (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); |
60054393 | 2157 | |
386c036b | 2158 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
34a79281 | 2159 | regcache->raw_collect (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); |
386c036b MK |
2160 | |
2161 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
34a79281 | 2162 | regcache->raw_collect (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); |
5af923b0 | 2163 | |
386c036b | 2164 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
34a79281 | 2165 | regcache->raw_collect (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); |
386c036b MK |
2166 | |
2167 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 2168 | { |
b4fd25c9 | 2169 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2170 | |
2171 | /* %g0 is always zero. */ | |
2172 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2173 | { | |
2174 | if (regnum == i || regnum == -1) | |
34a79281 | 2175 | regcache->raw_collect (i, regs + offset); |
386c036b MK |
2176 | offset += 4; |
2177 | } | |
5af923b0 | 2178 | } |
386c036b MK |
2179 | |
2180 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2181 | { |
386c036b | 2182 | /* Not all of the register set variants include Locals and |
dda83cd7 | 2183 | Inputs. For those that don't, we read them off the stack. */ |
b4fd25c9 | 2184 | if (gregmap->r_l0_offset != -1) |
386c036b | 2185 | { |
b4fd25c9 | 2186 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2187 | |
2188 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2189 | { | |
2190 | if (regnum == i || regnum == -1) | |
34a79281 | 2191 | regcache->raw_collect (i, regs + offset); |
386c036b MK |
2192 | offset += 4; |
2193 | } | |
2194 | } | |
5af923b0 | 2195 | } |
c906108c SS |
2196 | } |
2197 | ||
c906108c | 2198 | void |
b4fd25c9 | 2199 | sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2200 | struct regcache *regcache, |
386c036b | 2201 | int regnum, const void *fpregs) |
c906108c | 2202 | { |
19ba03f4 | 2203 | const gdb_byte *regs = (const gdb_byte *) fpregs; |
386c036b | 2204 | int i; |
60054393 | 2205 | |
386c036b | 2206 | for (i = 0; i < 32; i++) |
c906108c | 2207 | { |
386c036b | 2208 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
73e1c03f SM |
2209 | regcache->raw_supply (SPARC_F0_REGNUM + i, |
2210 | regs + fpregmap->r_f0_offset + (i * 4)); | |
c906108c | 2211 | } |
5af923b0 | 2212 | |
386c036b | 2213 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
73e1c03f | 2214 | regcache->raw_supply (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset); |
c906108c SS |
2215 | } |
2216 | ||
386c036b | 2217 | void |
b4fd25c9 | 2218 | sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2219 | const struct regcache *regcache, |
386c036b | 2220 | int regnum, void *fpregs) |
c906108c | 2221 | { |
19ba03f4 | 2222 | gdb_byte *regs = (gdb_byte *) fpregs; |
386c036b | 2223 | int i; |
c906108c | 2224 | |
386c036b MK |
2225 | for (i = 0; i < 32; i++) |
2226 | { | |
2227 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
34a79281 SM |
2228 | regcache->raw_collect (SPARC_F0_REGNUM + i, |
2229 | regs + fpregmap->r_f0_offset + (i * 4)); | |
386c036b | 2230 | } |
c906108c | 2231 | |
386c036b | 2232 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
34a79281 SM |
2233 | regcache->raw_collect (SPARC32_FSR_REGNUM, |
2234 | regs + fpregmap->r_fsr_offset); | |
c906108c | 2235 | } |
c906108c | 2236 | \f |
c906108c | 2237 | |
386c036b | 2238 | /* SunOS 4. */ |
c906108c | 2239 | |
386c036b | 2240 | /* From <machine/reg.h>. */ |
b4fd25c9 | 2241 | const struct sparc_gregmap sparc32_sunos4_gregmap = |
c906108c | 2242 | { |
386c036b MK |
2243 | 0 * 4, /* %psr */ |
2244 | 1 * 4, /* %pc */ | |
2245 | 2 * 4, /* %npc */ | |
2246 | 3 * 4, /* %y */ | |
2247 | -1, /* %wim */ | |
2248 | -1, /* %tbr */ | |
2249 | 4 * 4, /* %g1 */ | |
2250 | -1 /* %l0 */ | |
2251 | }; | |
db75c717 | 2252 | |
b4fd25c9 | 2253 | const struct sparc_fpregmap sparc32_sunos4_fpregmap = |
db75c717 DM |
2254 | { |
2255 | 0 * 4, /* %f0 */ | |
2256 | 33 * 4, /* %fsr */ | |
2257 | }; | |
2258 | ||
b4fd25c9 | 2259 | const struct sparc_fpregmap sparc32_bsd_fpregmap = |
db75c717 DM |
2260 | { |
2261 | 0 * 4, /* %f0 */ | |
2262 | 32 * 4, /* %fsr */ | |
2263 | }; | |
c906108c | 2264 | |
6c265988 | 2265 | void _initialize_sparc_tdep (); |
c906108c | 2266 | void |
6c265988 | 2267 | _initialize_sparc_tdep () |
c906108c | 2268 | { |
386c036b | 2269 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2270 | } |