Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
7b6bb8da | 3 | Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
9b254dd1 | 4 | Free Software Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 11 | (at your option) any later version. |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b | 18 | You should have received a copy of the GNU General Public License |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 20 | |
c906108c | 21 | #include "defs.h" |
5af923b0 | 22 | #include "arch-utils.h" |
386c036b | 23 | #include "dis-asm.h" |
f5a9b87d | 24 | #include "dwarf2-frame.h" |
386c036b | 25 | #include "floatformat.h" |
c906108c | 26 | #include "frame.h" |
386c036b MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbtypes.h" | |
c906108c | 31 | #include "inferior.h" |
386c036b MK |
32 | #include "symtab.h" |
33 | #include "objfiles.h" | |
34 | #include "osabi.h" | |
35 | #include "regcache.h" | |
c906108c SS |
36 | #include "target.h" |
37 | #include "value.h" | |
c906108c | 38 | |
43bd9a9e | 39 | #include "gdb_assert.h" |
386c036b | 40 | #include "gdb_string.h" |
c906108c | 41 | |
386c036b | 42 | #include "sparc-tdep.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
9eb42ed1 MK |
46 | /* This file implements the SPARC 32-bit ABI as defined by the section |
47 | "Low-Level System Information" of the SPARC Compliance Definition | |
48 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 49 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 50 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
51 | |
52 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
53 | BSD-based, which is sometimes (retroactively?) referred to as | |
54 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
55 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
56 | suffering from severe version number inflation). Solaris 2.x is | |
57 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
58 | 2.x is SVR4-based. */ | |
59 | ||
60 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
61 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
62 | code that can handle both. The 64-bit specific code lives in | |
63 | sparc64-tdep.c; don't add any here. */ | |
64 | ||
65 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 66 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 67 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
68 | |
69 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
70 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
71 | hosts, so undefine it first. */ | |
72 | #undef BIAS | |
73 | #define BIAS 2047 | |
74 | ||
75 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
76 | #define X_OP(i) (((i) >> 30) & 0x3) |
77 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
78 | #define X_A(i) (((i) >> 29) & 1) | |
79 | #define X_COND(i) (((i) >> 25) & 0xf) | |
80 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
81 | #define X_IMM22(i) ((i) & 0x3fffff) | |
82 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 83 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 84 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 89 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 90 | |
386c036b MK |
91 | /* Fetch the instruction at PC. Instructions are always big-endian |
92 | even if the processor operates in little-endian mode. */ | |
93 | ||
94 | unsigned long | |
95 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 96 | { |
e1613aba | 97 | gdb_byte buf[4]; |
386c036b MK |
98 | unsigned long insn; |
99 | int i; | |
100 | ||
690668cc | 101 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 102 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 103 | return 0; |
c906108c | 104 | |
386c036b MK |
105 | insn = 0; |
106 | for (i = 0; i < sizeof (buf); i++) | |
107 | insn = (insn << 8) | buf[i]; | |
108 | return insn; | |
109 | } | |
42cdca6c MK |
110 | \f |
111 | ||
5465445a JB |
112 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
113 | instruction. */ | |
114 | ||
115 | static int | |
116 | sparc_is_unimp_insn (CORE_ADDR pc) | |
117 | { | |
118 | const unsigned long insn = sparc_fetch_instruction (pc); | |
119 | ||
120 | return ((insn & 0xc1c00000) == 0); | |
121 | } | |
122 | ||
42cdca6c MK |
123 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
124 | website http://stackghost.cerias.purdue.edu "... transparently and | |
125 | automatically protects applications' stack frames; more | |
126 | specifically, it guards the return pointers. The protection | |
127 | mechanisms require no application source or binary modification and | |
128 | imposes only a negligible performance penalty." | |
129 | ||
130 | The same website provides the following description of how | |
131 | StackGhost works: | |
132 | ||
133 | "StackGhost interfaces with the kernel trap handler that would | |
134 | normally write out registers to the stack and the handler that | |
135 | would read them back in. By XORing a cookie into the | |
136 | return-address saved in the user stack when it is actually written | |
137 | to the stack, and then XOR it out when the return-address is pulled | |
138 | from the stack, StackGhost can cause attacker corrupted return | |
139 | pointers to behave in a manner the attacker cannot predict. | |
140 | StackGhost can also use several unused bits in the return pointer | |
141 | to detect a smashed return pointer and abort the process." | |
142 | ||
143 | For GDB this means that whenever we're reading %i7 from a stack | |
144 | frame's window save area, we'll have to XOR the cookie. | |
145 | ||
146 | More information on StackGuard can be found on in: | |
147 | ||
c378eb4e | 148 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
149 | Stack Protection." 2001. Published in USENIX Security Symposium |
150 | '01. */ | |
151 | ||
152 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
153 | ||
154 | ULONGEST | |
e17a4113 | 155 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 156 | { |
e17a4113 | 157 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 158 | struct target_ops *ops = ¤t_target; |
e1613aba | 159 | gdb_byte buf[8]; |
baf92889 MK |
160 | int len; |
161 | ||
13547ab6 | 162 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
163 | if (len == -1) |
164 | return 0; | |
42cdca6c | 165 | |
baf92889 MK |
166 | /* We should have either an 32-bit or an 64-bit cookie. */ |
167 | gdb_assert (len == 4 || len == 8); | |
168 | ||
e17a4113 | 169 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 170 | } |
386c036b | 171 | \f |
baf92889 | 172 | |
386c036b MK |
173 | /* The functions on this page are intended to be used to classify |
174 | function arguments. */ | |
c906108c | 175 | |
386c036b | 176 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 177 | |
386c036b MK |
178 | static int |
179 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 180 | { |
80ad1639 MK |
181 | int len = TYPE_LENGTH (type); |
182 | ||
386c036b | 183 | switch (TYPE_CODE (type)) |
c906108c | 184 | { |
386c036b MK |
185 | case TYPE_CODE_INT: |
186 | case TYPE_CODE_BOOL: | |
187 | case TYPE_CODE_CHAR: | |
188 | case TYPE_CODE_ENUM: | |
189 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
190 | /* We have byte, half-word, word and extended-word/doubleword |
191 | integral types. The doubleword is an extension to the | |
192 | original 32-bit ABI by the SCD 2.4.x. */ | |
193 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
194 | case TYPE_CODE_PTR: |
195 | case TYPE_CODE_REF: | |
80ad1639 MK |
196 | /* Allow either 32-bit or 64-bit pointers. */ |
197 | return (len == 4 || len == 8); | |
386c036b MK |
198 | default: |
199 | break; | |
200 | } | |
c906108c | 201 | |
386c036b MK |
202 | return 0; |
203 | } | |
c906108c | 204 | |
386c036b | 205 | /* Check whether TYPE is "Floating". */ |
c906108c | 206 | |
386c036b MK |
207 | static int |
208 | sparc_floating_p (const struct type *type) | |
209 | { | |
210 | switch (TYPE_CODE (type)) | |
c906108c | 211 | { |
386c036b MK |
212 | case TYPE_CODE_FLT: |
213 | { | |
214 | int len = TYPE_LENGTH (type); | |
215 | return (len == 4 || len == 8 || len == 16); | |
216 | } | |
217 | default: | |
218 | break; | |
219 | } | |
220 | ||
221 | return 0; | |
222 | } | |
c906108c | 223 | |
0497f5b0 JB |
224 | /* Check whether TYPE is "Structure or Union". |
225 | ||
226 | In terms of Ada subprogram calls, arrays are treated the same as | |
227 | struct and union types. So this function also returns non-zero | |
228 | for array types. */ | |
c906108c | 229 | |
386c036b MK |
230 | static int |
231 | sparc_structure_or_union_p (const struct type *type) | |
232 | { | |
233 | switch (TYPE_CODE (type)) | |
234 | { | |
235 | case TYPE_CODE_STRUCT: | |
236 | case TYPE_CODE_UNION: | |
0497f5b0 | 237 | case TYPE_CODE_ARRAY: |
386c036b MK |
238 | return 1; |
239 | default: | |
240 | break; | |
c906108c | 241 | } |
386c036b MK |
242 | |
243 | return 0; | |
c906108c | 244 | } |
386c036b MK |
245 | |
246 | /* Register information. */ | |
247 | ||
248 | static const char *sparc32_register_names[] = | |
5af923b0 | 249 | { |
386c036b MK |
250 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
251 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
252 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
253 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
254 | ||
255 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
256 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
257 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
258 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
259 | ||
260 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
261 | }; |
262 | ||
386c036b MK |
263 | /* Total number of registers. */ |
264 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 265 | |
386c036b MK |
266 | /* We provide the aliases %d0..%d30 for the floating registers as |
267 | "psuedo" registers. */ | |
268 | ||
269 | static const char *sparc32_pseudo_register_names[] = | |
270 | { | |
271 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
272 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
273 | }; | |
274 | ||
275 | /* Total number of pseudo registers. */ | |
276 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
277 | ||
278 | /* Return the name of register REGNUM. */ | |
279 | ||
280 | static const char * | |
d93859e2 | 281 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
282 | { |
283 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
284 | return sparc32_register_names[regnum]; | |
285 | ||
286 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
287 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
288 | ||
289 | return NULL; | |
290 | } | |
2d457077 | 291 | \f |
209bd28e | 292 | /* Construct types for ISA-specific registers. */ |
2d457077 | 293 | |
209bd28e UW |
294 | static struct type * |
295 | sparc_psr_type (struct gdbarch *gdbarch) | |
296 | { | |
297 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 298 | |
209bd28e UW |
299 | if (!tdep->sparc_psr_type) |
300 | { | |
301 | struct type *type; | |
2d457077 | 302 | |
e9bb382b | 303 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
304 | append_flags_type_flag (type, 5, "ET"); |
305 | append_flags_type_flag (type, 6, "PS"); | |
306 | append_flags_type_flag (type, 7, "S"); | |
307 | append_flags_type_flag (type, 12, "EF"); | |
308 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 309 | |
209bd28e UW |
310 | tdep->sparc_psr_type = type; |
311 | } | |
312 | ||
313 | return tdep->sparc_psr_type; | |
314 | } | |
315 | ||
316 | static struct type * | |
317 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 318 | { |
209bd28e UW |
319 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
320 | ||
321 | if (!tdep->sparc_fsr_type) | |
322 | { | |
323 | struct type *type; | |
324 | ||
e9bb382b | 325 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
326 | append_flags_type_flag (type, 0, "NXA"); |
327 | append_flags_type_flag (type, 1, "DZA"); | |
328 | append_flags_type_flag (type, 2, "UFA"); | |
329 | append_flags_type_flag (type, 3, "OFA"); | |
330 | append_flags_type_flag (type, 4, "NVA"); | |
331 | append_flags_type_flag (type, 5, "NXC"); | |
332 | append_flags_type_flag (type, 6, "DZC"); | |
333 | append_flags_type_flag (type, 7, "UFC"); | |
334 | append_flags_type_flag (type, 8, "OFC"); | |
335 | append_flags_type_flag (type, 9, "NVC"); | |
336 | append_flags_type_flag (type, 22, "NS"); | |
337 | append_flags_type_flag (type, 23, "NXM"); | |
338 | append_flags_type_flag (type, 24, "DZM"); | |
339 | append_flags_type_flag (type, 25, "UFM"); | |
340 | append_flags_type_flag (type, 26, "OFM"); | |
341 | append_flags_type_flag (type, 27, "NVM"); | |
342 | ||
343 | tdep->sparc_fsr_type = type; | |
344 | } | |
345 | ||
346 | return tdep->sparc_fsr_type; | |
2d457077 | 347 | } |
386c036b MK |
348 | |
349 | /* Return the GDB type object for the "standard" data type of data in | |
c378eb4e | 350 | register REGNUM. */ |
386c036b MK |
351 | |
352 | static struct type * | |
353 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
354 | { | |
355 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 356 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
357 | |
358 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 359 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
360 | |
361 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 362 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
363 | |
364 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 365 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 366 | |
2d457077 | 367 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 368 | return sparc_psr_type (gdbarch); |
2d457077 MK |
369 | |
370 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 371 | return sparc_fsr_type (gdbarch); |
2d457077 | 372 | |
df4df182 | 373 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
374 | } |
375 | ||
05d1431c | 376 | static enum register_status |
386c036b MK |
377 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
378 | struct regcache *regcache, | |
e1613aba | 379 | int regnum, gdb_byte *buf) |
386c036b | 380 | { |
05d1431c PA |
381 | enum register_status status; |
382 | ||
386c036b MK |
383 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
384 | ||
385 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
386 | status = regcache_raw_read (regcache, regnum, buf); |
387 | if (status == REG_VALID) | |
388 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
389 | return status; | |
386c036b MK |
390 | } |
391 | ||
392 | static void | |
393 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
394 | struct regcache *regcache, | |
e1613aba | 395 | int regnum, const gdb_byte *buf) |
386c036b MK |
396 | { |
397 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
398 | ||
399 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
400 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 401 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
402 | } |
403 | \f | |
404 | ||
49a45ecf JB |
405 | static CORE_ADDR |
406 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
407 | { | |
408 | /* The ABI requires double-word alignment. */ | |
409 | return address & ~0x7; | |
410 | } | |
411 | ||
386c036b MK |
412 | static CORE_ADDR |
413 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 414 | CORE_ADDR funcaddr, |
386c036b MK |
415 | struct value **args, int nargs, |
416 | struct type *value_type, | |
e4fd649a UW |
417 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
418 | struct regcache *regcache) | |
c906108c | 419 | { |
e17a4113 UW |
420 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
421 | ||
386c036b MK |
422 | *bp_addr = sp - 4; |
423 | *real_pc = funcaddr; | |
424 | ||
d80b854b | 425 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 426 | { |
e1613aba | 427 | gdb_byte buf[4]; |
386c036b MK |
428 | |
429 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
430 | store_unsigned_integer (buf, 4, byte_order, |
431 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
432 | write_memory (sp - 8, buf, 4); |
433 | return sp - 8; | |
c906108c SS |
434 | } |
435 | ||
386c036b MK |
436 | return sp - 4; |
437 | } | |
438 | ||
439 | static CORE_ADDR | |
440 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
441 | struct value **args, CORE_ADDR sp, | |
442 | int struct_return, CORE_ADDR struct_addr) | |
443 | { | |
df4df182 | 444 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 445 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
446 | /* Number of words in the "parameter array". */ |
447 | int num_elements = 0; | |
448 | int element = 0; | |
449 | int i; | |
450 | ||
451 | for (i = 0; i < nargs; i++) | |
c906108c | 452 | { |
4991999e | 453 | struct type *type = value_type (args[i]); |
386c036b MK |
454 | int len = TYPE_LENGTH (type); |
455 | ||
456 | if (sparc_structure_or_union_p (type) | |
457 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 458 | { |
386c036b MK |
459 | /* Structure, Union and Quad-Precision Arguments. */ |
460 | sp -= len; | |
461 | ||
462 | /* Use doubleword alignment for these values. That's always | |
463 | correct, and wasting a few bytes shouldn't be a problem. */ | |
464 | sp &= ~0x7; | |
465 | ||
0fd88904 | 466 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
467 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
468 | num_elements++; | |
469 | } | |
470 | else if (sparc_floating_p (type)) | |
471 | { | |
472 | /* Floating arguments. */ | |
473 | gdb_assert (len == 4 || len == 8); | |
474 | num_elements += (len / 4); | |
c906108c | 475 | } |
c5aa993b JM |
476 | else |
477 | { | |
386c036b MK |
478 | /* Integral and pointer arguments. */ |
479 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
480 | ||
481 | if (len < 4) | |
df4df182 UW |
482 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
483 | args[i]); | |
386c036b | 484 | num_elements += ((len + 3) / 4); |
c5aa993b | 485 | } |
c906108c | 486 | } |
c906108c | 487 | |
386c036b MK |
488 | /* Always allocate at least six words. */ |
489 | sp -= max (6, num_elements) * 4; | |
c906108c | 490 | |
386c036b MK |
491 | /* The psABI says that "Software convention requires space for the |
492 | struct/union return value pointer, even if the word is unused." */ | |
493 | sp -= 4; | |
c906108c | 494 | |
386c036b MK |
495 | /* The psABI says that "Although software convention and the |
496 | operating system require every stack frame to be doubleword | |
497 | aligned." */ | |
498 | sp &= ~0x7; | |
c906108c | 499 | |
386c036b | 500 | for (i = 0; i < nargs; i++) |
c906108c | 501 | { |
0fd88904 | 502 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 503 | struct type *type = value_type (args[i]); |
386c036b | 504 | int len = TYPE_LENGTH (type); |
c906108c | 505 | |
386c036b | 506 | gdb_assert (len == 4 || len == 8); |
c906108c | 507 | |
386c036b MK |
508 | if (element < 6) |
509 | { | |
510 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 511 | |
386c036b MK |
512 | regcache_cooked_write (regcache, regnum, valbuf); |
513 | if (len > 4 && element < 5) | |
514 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
515 | } | |
5af923b0 | 516 | |
386c036b MK |
517 | /* Always store the argument in memory. */ |
518 | write_memory (sp + 4 + element * 4, valbuf, len); | |
519 | element += len / 4; | |
520 | } | |
c906108c | 521 | |
386c036b | 522 | gdb_assert (element == num_elements); |
c906108c | 523 | |
386c036b | 524 | if (struct_return) |
c906108c | 525 | { |
e1613aba | 526 | gdb_byte buf[4]; |
c906108c | 527 | |
e17a4113 | 528 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
529 | write_memory (sp, buf, 4); |
530 | } | |
c906108c | 531 | |
386c036b | 532 | return sp; |
c906108c SS |
533 | } |
534 | ||
386c036b | 535 | static CORE_ADDR |
7d9b040b | 536 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
537 | struct regcache *regcache, CORE_ADDR bp_addr, |
538 | int nargs, struct value **args, CORE_ADDR sp, | |
539 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 540 | { |
386c036b MK |
541 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
542 | ||
543 | /* Set return address. */ | |
544 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
545 | ||
546 | /* Set up function arguments. */ | |
547 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
548 | struct_return, struct_addr); | |
549 | ||
550 | /* Allocate the 16-word window save area. */ | |
551 | sp -= 16 * 4; | |
c906108c | 552 | |
386c036b MK |
553 | /* Stack should be doubleword aligned at this point. */ |
554 | gdb_assert (sp % 8 == 0); | |
c906108c | 555 | |
386c036b MK |
556 | /* Finally, update the stack pointer. */ |
557 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
558 | ||
559 | return sp; | |
560 | } | |
561 | \f | |
c906108c | 562 | |
386c036b MK |
563 | /* Use the program counter to determine the contents and size of a |
564 | breakpoint instruction. Return a pointer to a string of bytes that | |
565 | encode a breakpoint instruction, store the length of the string in | |
566 | *LEN and optionally adjust *PC to point to the correct memory | |
567 | location for inserting the breakpoint. */ | |
568 | ||
e1613aba | 569 | static const gdb_byte * |
67d57894 | 570 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 571 | { |
864a1a37 | 572 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 573 | |
386c036b MK |
574 | *len = sizeof (break_insn); |
575 | return break_insn; | |
c906108c | 576 | } |
386c036b | 577 | \f |
c906108c | 578 | |
386c036b | 579 | /* Allocate and initialize a frame cache. */ |
c906108c | 580 | |
386c036b MK |
581 | static struct sparc_frame_cache * |
582 | sparc_alloc_frame_cache (void) | |
583 | { | |
584 | struct sparc_frame_cache *cache; | |
585 | int i; | |
c906108c | 586 | |
386c036b | 587 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 588 | |
386c036b MK |
589 | /* Base address. */ |
590 | cache->base = 0; | |
591 | cache->pc = 0; | |
c906108c | 592 | |
386c036b MK |
593 | /* Frameless until proven otherwise. */ |
594 | cache->frameless_p = 1; | |
369c397b JB |
595 | cache->frame_offset = 0; |
596 | cache->saved_regs_mask = 0; | |
597 | cache->copied_regs_mask = 0; | |
386c036b MK |
598 | cache->struct_return_p = 0; |
599 | ||
600 | return cache; | |
601 | } | |
602 | ||
b0b92586 JB |
603 | /* GCC generates several well-known sequences of instructions at the begining |
604 | of each function prologue when compiling with -fstack-check. If one of | |
605 | such sequences starts at START_PC, then return the address of the | |
606 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
607 | ||
608 | static CORE_ADDR | |
609 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
610 | { | |
611 | CORE_ADDR pc = start_pc; | |
612 | unsigned long insn; | |
613 | int offset_stack_checking_sequence = 0; | |
2067c8d4 | 614 | int probing_loop = 0; |
b0b92586 JB |
615 | |
616 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 617 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 618 | |
2067c8d4 JG |
619 | sethi <some immediate>, %g1 |
620 | sub %sp, %g1, %g1 | |
621 | ||
622 | or: | |
623 | ||
624 | sethi <some immediate>, %g1 | |
625 | sethi <some immediate>, %g4 | |
626 | sub %sp, %g1, %g1 | |
627 | ||
628 | or: | |
629 | ||
630 | sethi <some immediate>, %g1 | |
631 | sub %sp, %g1, %g1 | |
632 | sethi <some immediate>, %g4 | |
633 | ||
634 | If the optional instruction is found (setting g4), assume that a | |
635 | probing loop will follow. */ | |
636 | ||
637 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
638 | insn = sparc_fetch_instruction (pc); |
639 | pc = pc + 4; | |
640 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
641 | return start_pc; | |
642 | ||
2067c8d4 | 643 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
644 | insn = sparc_fetch_instruction (pc); |
645 | pc = pc + 4; | |
2067c8d4 JG |
646 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
647 | { | |
648 | probing_loop = 1; | |
649 | insn = sparc_fetch_instruction (pc); | |
650 | pc = pc + 4; | |
651 | } | |
652 | ||
653 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
654 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
655 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
656 | return start_pc; | |
657 | ||
658 | insn = sparc_fetch_instruction (pc); | |
659 | pc = pc + 4; | |
660 | ||
2067c8d4 JG |
661 | /* optional: sethi <some immediate>, %g4 */ |
662 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
663 | { | |
664 | probing_loop = 1; | |
665 | insn = sparc_fetch_instruction (pc); | |
666 | pc = pc + 4; | |
667 | } | |
668 | ||
b0b92586 JB |
669 | /* First possible sequence: |
670 | [first two instructions above] | |
671 | clr [%g1 - some immediate] */ | |
672 | ||
673 | /* clr [%g1 - some immediate] */ | |
674 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
675 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
676 | { | |
677 | /* Valid stack-check sequence, return the new PC. */ | |
678 | return pc; | |
679 | } | |
680 | ||
681 | /* Second possible sequence: A small number of probes. | |
682 | [first two instructions above] | |
683 | clr [%g1] | |
684 | add %g1, -<some immediate>, %g1 | |
685 | clr [%g1] | |
686 | [repeat the two instructions above any (small) number of times] | |
687 | clr [%g1 - some immediate] */ | |
688 | ||
689 | /* clr [%g1] */ | |
690 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
691 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
692 | { | |
693 | while (1) | |
694 | { | |
695 | /* add %g1, -<some immediate>, %g1 */ | |
696 | insn = sparc_fetch_instruction (pc); | |
697 | pc = pc + 4; | |
698 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
699 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
700 | break; | |
701 | ||
702 | /* clr [%g1] */ | |
703 | insn = sparc_fetch_instruction (pc); | |
704 | pc = pc + 4; | |
705 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
706 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
707 | return start_pc; | |
708 | } | |
709 | ||
710 | /* clr [%g1 - some immediate] */ | |
711 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
712 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
713 | return start_pc; | |
714 | ||
715 | /* We found a valid stack-check sequence, return the new PC. */ | |
716 | return pc; | |
717 | } | |
718 | ||
719 | /* Third sequence: A probing loop. | |
2067c8d4 | 720 | [first three instructions above] |
b0b92586 JB |
721 | sub %g1, %g4, %g4 |
722 | cmp %g1, %g4 | |
723 | be <disp> | |
724 | add %g1, -<some immediate>, %g1 | |
725 | ba <disp> | |
726 | clr [%g1] | |
2067c8d4 JG |
727 | |
728 | And an optional last probe for the remainder: | |
729 | ||
b0b92586 JB |
730 | clr [%g4 - some immediate] */ |
731 | ||
2067c8d4 | 732 | if (probing_loop) |
b0b92586 JB |
733 | { |
734 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
735 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
736 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
737 | return start_pc; | |
738 | ||
739 | /* cmp %g1, %g4 */ | |
740 | insn = sparc_fetch_instruction (pc); | |
741 | pc = pc + 4; | |
742 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
743 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
744 | return start_pc; | |
745 | ||
746 | /* be <disp> */ | |
747 | insn = sparc_fetch_instruction (pc); | |
748 | pc = pc + 4; | |
749 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
750 | return start_pc; | |
751 | ||
752 | /* add %g1, -<some immediate>, %g1 */ | |
753 | insn = sparc_fetch_instruction (pc); | |
754 | pc = pc + 4; | |
755 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
756 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
757 | return start_pc; | |
758 | ||
759 | /* ba <disp> */ | |
760 | insn = sparc_fetch_instruction (pc); | |
761 | pc = pc + 4; | |
762 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
763 | return start_pc; | |
764 | ||
2067c8d4 | 765 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
766 | insn = sparc_fetch_instruction (pc); |
767 | pc = pc + 4; | |
2067c8d4 JG |
768 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
769 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
770 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
771 | return start_pc; |
772 | ||
2067c8d4 JG |
773 | /* We found a valid stack-check sequence, return the new PC. */ |
774 | ||
775 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
776 | insn = sparc_fetch_instruction (pc); |
777 | pc = pc + 4; | |
778 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
779 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
780 | return pc - 4; |
781 | else | |
782 | return pc; | |
b0b92586 JB |
783 | } |
784 | ||
785 | /* No stack check code in our prologue, return the start_pc. */ | |
786 | return start_pc; | |
787 | } | |
788 | ||
369c397b JB |
789 | /* Record the effect of a SAVE instruction on CACHE. */ |
790 | ||
791 | void | |
792 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
793 | { | |
794 | /* The frame is set up. */ | |
795 | cache->frameless_p = 0; | |
796 | ||
797 | /* The frame pointer contains the CFA. */ | |
798 | cache->frame_offset = 0; | |
799 | ||
800 | /* The `local' and `in' registers are all saved. */ | |
801 | cache->saved_regs_mask = 0xffff; | |
802 | ||
803 | /* The `out' registers are all renamed. */ | |
804 | cache->copied_regs_mask = 0xff; | |
805 | } | |
806 | ||
807 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
808 | Bail out early if CURRENT_PC is reached. Return the address where | |
809 | the analysis stopped. | |
810 | ||
811 | We handle both the traditional register window model and the single | |
812 | register window (aka flat) model. */ | |
813 | ||
386c036b | 814 | CORE_ADDR |
be8626e0 MD |
815 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
816 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 817 | { |
be8626e0 | 818 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
819 | unsigned long insn; |
820 | int offset = 0; | |
c906108c | 821 | int dest = -1; |
c906108c | 822 | |
b0b92586 JB |
823 | pc = sparc_skip_stack_check (pc); |
824 | ||
386c036b MK |
825 | if (current_pc <= pc) |
826 | return current_pc; | |
827 | ||
828 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
829 | SPARC the linker usually defines a symbol (typically | |
830 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
831 | This symbol makes us end up here with PC pointing at the start of | |
832 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
833 | would do our normal prologue analysis, we would probably conclude | |
834 | that we've got a frame when in reality we don't, since the | |
835 | dynamic linker patches up the first PLT with some code that | |
836 | starts with a SAVE instruction. Patch up PC such that it points | |
837 | at the start of our PLT entry. */ | |
838 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
839 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 840 | |
386c036b MK |
841 | insn = sparc_fetch_instruction (pc); |
842 | ||
369c397b JB |
843 | /* Recognize store insns and record their sources. */ |
844 | while (X_OP (insn) == 3 | |
845 | && (X_OP3 (insn) == 0x4 /* stw */ | |
846 | || X_OP3 (insn) == 0x7 /* std */ | |
847 | || X_OP3 (insn) == 0xe) /* stx */ | |
848 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
849 | { | |
850 | int regnum = X_RD (insn); | |
851 | ||
852 | /* Recognize stores into the corresponding stack slots. */ | |
853 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
854 | && ((X_I (insn) | |
855 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
856 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
857 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
858 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
859 | { | |
860 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
861 | if (X_OP3 (insn) == 0x7) | |
862 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
863 | } | |
864 | ||
865 | offset += 4; | |
866 | ||
867 | insn = sparc_fetch_instruction (pc + offset); | |
868 | } | |
869 | ||
386c036b MK |
870 | /* Recognize a SETHI insn and record its destination. */ |
871 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
872 | { |
873 | dest = X_RD (insn); | |
386c036b MK |
874 | offset += 4; |
875 | ||
369c397b | 876 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
877 | } |
878 | ||
386c036b MK |
879 | /* Allow for an arithmetic operation on DEST or %g1. */ |
880 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
881 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
882 | { | |
386c036b | 883 | offset += 4; |
c906108c | 884 | |
369c397b | 885 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 886 | } |
c906108c | 887 | |
386c036b MK |
888 | /* Check for the SAVE instruction that sets up the frame. */ |
889 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 890 | { |
369c397b JB |
891 | sparc_record_save_insn (cache); |
892 | offset += 4; | |
893 | return pc + offset; | |
894 | } | |
895 | ||
896 | /* Check for an arithmetic operation on %sp. */ | |
897 | if (X_OP (insn) == 2 | |
898 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
899 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
900 | && X_RD (insn) == SPARC_SP_REGNUM) | |
901 | { | |
902 | if (X_I (insn)) | |
903 | { | |
904 | cache->frame_offset = X_SIMM13 (insn); | |
905 | if (X_OP3 (insn) == 0) | |
906 | cache->frame_offset = -cache->frame_offset; | |
907 | } | |
908 | offset += 4; | |
909 | ||
910 | insn = sparc_fetch_instruction (pc + offset); | |
911 | ||
912 | /* Check for an arithmetic operation that sets up the frame. */ | |
913 | if (X_OP (insn) == 2 | |
914 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
915 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
916 | && X_RD (insn) == SPARC_FP_REGNUM) | |
917 | { | |
918 | cache->frameless_p = 0; | |
919 | cache->frame_offset = 0; | |
920 | /* We could check that the amount subtracted to %sp above is the | |
921 | same as the one added here, but this seems superfluous. */ | |
922 | cache->copied_regs_mask |= 0x40; | |
923 | offset += 4; | |
924 | ||
925 | insn = sparc_fetch_instruction (pc + offset); | |
926 | } | |
927 | ||
928 | /* Check for a move (or) operation that copies the return register. */ | |
929 | if (X_OP (insn) == 2 | |
930 | && X_OP3 (insn) == 0x2 | |
931 | && !X_I (insn) | |
932 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
933 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
934 | && X_RD (insn) == SPARC_I7_REGNUM) | |
935 | { | |
936 | cache->copied_regs_mask |= 0x80; | |
937 | offset += 4; | |
938 | } | |
939 | ||
940 | return pc + offset; | |
c906108c SS |
941 | } |
942 | ||
943 | return pc; | |
944 | } | |
945 | ||
386c036b | 946 | static CORE_ADDR |
236369e7 | 947 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
948 | { |
949 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 950 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
951 | } |
952 | ||
953 | /* Return PC of first real instruction of the function starting at | |
954 | START_PC. */ | |
f510d44e | 955 | |
386c036b | 956 | static CORE_ADDR |
6093d2eb | 957 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 958 | { |
f510d44e DM |
959 | struct symtab_and_line sal; |
960 | CORE_ADDR func_start, func_end; | |
386c036b | 961 | struct sparc_frame_cache cache; |
f510d44e DM |
962 | |
963 | /* This is the preferred method, find the end of the prologue by | |
964 | using the debugging information. */ | |
965 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
966 | { | |
967 | sal = find_pc_line (func_start, 0); | |
968 | ||
969 | if (sal.end < func_end | |
970 | && start_pc <= sal.end) | |
971 | return sal.end; | |
972 | } | |
973 | ||
be8626e0 | 974 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
975 | |
976 | /* The psABI says that "Although the first 6 words of arguments | |
977 | reside in registers, the standard stack frame reserves space for | |
978 | them.". It also suggests that a function may use that space to | |
979 | "write incoming arguments 0 to 5" into that space, and that's | |
980 | indeed what GCC seems to be doing. In that case GCC will | |
981 | generate debug information that points to the stack slots instead | |
982 | of the registers, so we should consider the instructions that | |
369c397b | 983 | write out these incoming arguments onto the stack. */ |
075ccec8 | 984 | |
369c397b | 985 | while (1) |
075ccec8 MK |
986 | { |
987 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
988 | ||
369c397b JB |
989 | /* Recognize instructions that store incoming arguments into the |
990 | corresponding stack slots. */ | |
991 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
992 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 993 | { |
369c397b JB |
994 | int regnum = X_RD (insn); |
995 | ||
996 | /* Case of arguments still in %o[0..5]. */ | |
997 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
998 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
999 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1000 | { | |
1001 | start_pc += 4; | |
1002 | continue; | |
1003 | } | |
1004 | ||
1005 | /* Case of arguments copied into %i[0..5]. */ | |
1006 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1007 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1008 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1009 | { | |
1010 | start_pc += 4; | |
1011 | continue; | |
1012 | } | |
075ccec8 MK |
1013 | } |
1014 | ||
1015 | break; | |
1016 | } | |
1017 | ||
1018 | return start_pc; | |
c906108c SS |
1019 | } |
1020 | ||
386c036b | 1021 | /* Normal frames. */ |
9319a2fe | 1022 | |
386c036b | 1023 | struct sparc_frame_cache * |
236369e7 | 1024 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1025 | { |
386c036b | 1026 | struct sparc_frame_cache *cache; |
9319a2fe | 1027 | |
386c036b MK |
1028 | if (*this_cache) |
1029 | return *this_cache; | |
c906108c | 1030 | |
386c036b MK |
1031 | cache = sparc_alloc_frame_cache (); |
1032 | *this_cache = cache; | |
c906108c | 1033 | |
236369e7 | 1034 | cache->pc = get_frame_func (this_frame); |
386c036b | 1035 | if (cache->pc != 0) |
236369e7 JB |
1036 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1037 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1038 | |
1039 | if (cache->frameless_p) | |
c906108c | 1040 | { |
cbeae229 MK |
1041 | /* This function is frameless, so %fp (%i6) holds the frame |
1042 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1043 | base address. */ | |
1044 | cache->base = | |
236369e7 | 1045 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1046 | } |
1047 | else | |
1048 | { | |
1049 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1050 | base address for the current stack frame. */ | |
1051 | cache->base = | |
236369e7 | 1052 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1053 | } |
c906108c | 1054 | |
369c397b JB |
1055 | cache->base += cache->frame_offset; |
1056 | ||
5b2d44a0 MK |
1057 | if (cache->base & 1) |
1058 | cache->base += BIAS; | |
1059 | ||
386c036b | 1060 | return cache; |
c906108c | 1061 | } |
c906108c | 1062 | |
aff37fc1 DM |
1063 | static int |
1064 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1065 | { | |
1066 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1067 | enum type_code code = TYPE_CODE (type); | |
1068 | ||
1069 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1070 | { | |
1071 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1072 | if (sparc_structure_or_union_p (type) | |
1073 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1074 | return 1; | |
1075 | } | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
386c036b | 1080 | struct sparc_frame_cache * |
236369e7 | 1081 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1082 | { |
386c036b MK |
1083 | struct sparc_frame_cache *cache; |
1084 | struct symbol *sym; | |
c906108c | 1085 | |
386c036b MK |
1086 | if (*this_cache) |
1087 | return *this_cache; | |
c906108c | 1088 | |
236369e7 | 1089 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1090 | |
386c036b MK |
1091 | sym = find_pc_function (cache->pc); |
1092 | if (sym) | |
c906108c | 1093 | { |
aff37fc1 | 1094 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1095 | } |
5465445a JB |
1096 | else |
1097 | { | |
1098 | /* There is no debugging information for this function to | |
1099 | help us determine whether this function returns a struct | |
1100 | or not. So we rely on another heuristic which is to check | |
1101 | the instruction at the return address and see if this is | |
1102 | an "unimp" instruction. If it is, then it is a struct-return | |
1103 | function. */ | |
1104 | CORE_ADDR pc; | |
369c397b JB |
1105 | int regnum = |
1106 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1107 | |
236369e7 | 1108 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1109 | if (sparc_is_unimp_insn (pc)) |
1110 | cache->struct_return_p = 1; | |
1111 | } | |
c906108c | 1112 | |
386c036b MK |
1113 | return cache; |
1114 | } | |
1115 | ||
1116 | static void | |
236369e7 | 1117 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1118 | struct frame_id *this_id) |
1119 | { | |
1120 | struct sparc_frame_cache *cache = | |
236369e7 | 1121 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1122 | |
1123 | /* This marks the outermost frame. */ | |
1124 | if (cache->base == 0) | |
1125 | return; | |
1126 | ||
1127 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1128 | } | |
c906108c | 1129 | |
236369e7 JB |
1130 | static struct value * |
1131 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1132 | void **this_cache, int regnum) | |
386c036b | 1133 | { |
e17a4113 | 1134 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1135 | struct sparc_frame_cache *cache = |
236369e7 | 1136 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1137 | |
386c036b | 1138 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1139 | { |
236369e7 | 1140 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1141 | |
236369e7 JB |
1142 | /* If this functions has a Structure, Union or Quad-Precision |
1143 | return value, we have to skip the UNIMP instruction that encodes | |
1144 | the size of the structure. */ | |
1145 | if (cache->struct_return_p) | |
1146 | pc += 4; | |
386c036b | 1147 | |
369c397b JB |
1148 | regnum = |
1149 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1150 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1151 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1152 | } |
1153 | ||
42cdca6c MK |
1154 | /* Handle StackGhost. */ |
1155 | { | |
e17a4113 | 1156 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1157 | |
1158 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1159 | { | |
236369e7 JB |
1160 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1161 | ULONGEST i7; | |
1162 | ||
1163 | /* Read the value in from memory. */ | |
1164 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1165 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1166 | } |
1167 | } | |
1168 | ||
369c397b | 1169 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1170 | in the register save area. */ |
369c397b JB |
1171 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1172 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1173 | { |
236369e7 | 1174 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1175 | |
236369e7 | 1176 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1177 | } |
c906108c | 1178 | |
369c397b JB |
1179 | /* The previous frame's `out' registers may be accessible as the current |
1180 | frame's `in' registers. */ | |
1181 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1182 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1183 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1184 | |
236369e7 | 1185 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1186 | } |
c906108c | 1187 | |
386c036b MK |
1188 | static const struct frame_unwind sparc32_frame_unwind = |
1189 | { | |
1190 | NORMAL_FRAME, | |
8fbca658 | 1191 | default_frame_unwind_stop_reason, |
386c036b | 1192 | sparc32_frame_this_id, |
236369e7 JB |
1193 | sparc32_frame_prev_register, |
1194 | NULL, | |
1195 | default_frame_sniffer | |
386c036b | 1196 | }; |
386c036b | 1197 | \f |
c906108c | 1198 | |
386c036b | 1199 | static CORE_ADDR |
236369e7 | 1200 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1201 | { |
1202 | struct sparc_frame_cache *cache = | |
236369e7 | 1203 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1204 | |
386c036b MK |
1205 | return cache->base; |
1206 | } | |
c906108c | 1207 | |
386c036b MK |
1208 | static const struct frame_base sparc32_frame_base = |
1209 | { | |
1210 | &sparc32_frame_unwind, | |
1211 | sparc32_frame_base_address, | |
1212 | sparc32_frame_base_address, | |
1213 | sparc32_frame_base_address | |
1214 | }; | |
c906108c | 1215 | |
386c036b | 1216 | static struct frame_id |
236369e7 | 1217 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1218 | { |
1219 | CORE_ADDR sp; | |
5af923b0 | 1220 | |
236369e7 | 1221 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1222 | if (sp & 1) |
1223 | sp += BIAS; | |
236369e7 | 1224 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1225 | } |
1226 | \f | |
c906108c | 1227 | |
3923a2b2 MK |
1228 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1229 | that into VALBUF. */ | |
5af923b0 | 1230 | |
386c036b MK |
1231 | static void |
1232 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1233 | gdb_byte *valbuf) |
386c036b MK |
1234 | { |
1235 | int len = TYPE_LENGTH (type); | |
e1613aba | 1236 | gdb_byte buf[8]; |
c906108c | 1237 | |
386c036b MK |
1238 | gdb_assert (!sparc_structure_or_union_p (type)); |
1239 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1240 | |
386c036b | 1241 | if (sparc_floating_p (type)) |
5af923b0 | 1242 | { |
386c036b MK |
1243 | /* Floating return values. */ |
1244 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1245 | if (len > 4) | |
1246 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
1247 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
1248 | } |
1249 | else | |
1250 | { | |
386c036b MK |
1251 | /* Integral and pointer return values. */ |
1252 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1253 | |
386c036b MK |
1254 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1255 | if (len > 4) | |
1256 | { | |
1257 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1258 | gdb_assert (len == 8); | |
1259 | memcpy (valbuf, buf, 8); | |
1260 | } | |
1261 | else | |
1262 | { | |
1263 | /* Just stripping off any unused bytes should preserve the | |
1264 | signed-ness just fine. */ | |
1265 | memcpy (valbuf, buf + 4 - len, len); | |
1266 | } | |
1267 | } | |
1268 | } | |
c906108c | 1269 | |
3923a2b2 MK |
1270 | /* Store the function return value of type TYPE from VALBUF into |
1271 | REGCACHE. */ | |
c906108c | 1272 | |
386c036b MK |
1273 | static void |
1274 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1275 | const gdb_byte *valbuf) |
386c036b MK |
1276 | { |
1277 | int len = TYPE_LENGTH (type); | |
e1613aba | 1278 | gdb_byte buf[8]; |
c906108c | 1279 | |
386c036b MK |
1280 | gdb_assert (!sparc_structure_or_union_p (type)); |
1281 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1282 | gdb_assert (len <= 8); |
c906108c | 1283 | |
386c036b MK |
1284 | if (sparc_floating_p (type)) |
1285 | { | |
1286 | /* Floating return values. */ | |
1287 | memcpy (buf, valbuf, len); | |
1288 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1289 | if (len > 4) | |
1290 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
1291 | } | |
1292 | else | |
c906108c | 1293 | { |
386c036b MK |
1294 | /* Integral and pointer return values. */ |
1295 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1296 | ||
1297 | if (len > 4) | |
2757dd86 | 1298 | { |
386c036b MK |
1299 | gdb_assert (len == 8); |
1300 | memcpy (buf, valbuf, 8); | |
1301 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1302 | } |
1303 | else | |
1304 | { | |
386c036b MK |
1305 | /* ??? Do we need to do any sign-extension here? */ |
1306 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1307 | } |
386c036b | 1308 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1309 | } |
1310 | } | |
1311 | ||
b9d4c5ed | 1312 | static enum return_value_convention |
c055b101 CV |
1313 | sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1314 | struct type *type, struct regcache *regcache, | |
1315 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1316 | { |
e17a4113 UW |
1317 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1318 | ||
0a8f48b9 MK |
1319 | /* The psABI says that "...every stack frame reserves the word at |
1320 | %fp+64. If a function returns a structure, union, or | |
1321 | quad-precision value, this word should hold the address of the | |
1322 | object into which the return value should be copied." This | |
1323 | guarantees that we can always find the return value, not just | |
1324 | before the function returns. */ | |
1325 | ||
b9d4c5ed MK |
1326 | if (sparc_structure_or_union_p (type) |
1327 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1328 | { |
1329 | if (readbuf) | |
1330 | { | |
1331 | ULONGEST sp; | |
1332 | CORE_ADDR addr; | |
1333 | ||
1334 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
e17a4113 | 1335 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1336 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1337 | } | |
1338 | ||
1339 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1340 | } | |
b9d4c5ed MK |
1341 | |
1342 | if (readbuf) | |
1343 | sparc32_extract_return_value (type, regcache, readbuf); | |
1344 | if (writebuf) | |
1345 | sparc32_store_return_value (type, regcache, writebuf); | |
1346 | ||
1347 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1348 | } | |
1349 | ||
386c036b MK |
1350 | static int |
1351 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1352 | { |
386c036b MK |
1353 | return (sparc_structure_or_union_p (type) |
1354 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
1355 | } | |
c906108c | 1356 | |
aff37fc1 | 1357 | static int |
4a4e5149 | 1358 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1359 | { |
236369e7 | 1360 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1361 | struct symbol *sym = find_pc_function (pc); |
1362 | ||
1363 | if (sym) | |
1364 | return sparc32_struct_return_from_sym (sym); | |
1365 | return 0; | |
1366 | } | |
1367 | ||
f5a9b87d DM |
1368 | static void |
1369 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1370 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1371 | struct frame_info *this_frame) |
f5a9b87d | 1372 | { |
aff37fc1 DM |
1373 | int off; |
1374 | ||
f5a9b87d DM |
1375 | switch (regnum) |
1376 | { | |
1377 | case SPARC_G0_REGNUM: | |
1378 | /* Since %g0 is always zero, there is no point in saving it, and | |
1379 | people will be inclined omit it from the CFI. Make sure we | |
1380 | don't warn about that. */ | |
1381 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1382 | break; | |
1383 | case SPARC_SP_REGNUM: | |
1384 | reg->how = DWARF2_FRAME_REG_CFA; | |
1385 | break; | |
1386 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1387 | case SPARC32_NPC_REGNUM: |
1388 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1389 | off = 8; |
4a4e5149 | 1390 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1391 | off += 4; |
1392 | if (regnum == SPARC32_NPC_REGNUM) | |
1393 | off += 4; | |
1394 | reg->loc.offset = off; | |
f5a9b87d DM |
1395 | break; |
1396 | } | |
1397 | } | |
1398 | ||
386c036b MK |
1399 | \f |
1400 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1401 | and most operating systems don't implement it either, so we provide | |
1402 | software single-step mechanism. */ | |
c906108c | 1403 | |
386c036b | 1404 | static CORE_ADDR |
0b1b3e42 | 1405 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1406 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1407 | { |
1408 | unsigned long insn = sparc_fetch_instruction (pc); | |
1409 | int conditional_p = X_COND (insn) & 0x7; | |
1410 | int branch_p = 0; | |
1411 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1412 | |
386c036b | 1413 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1414 | { |
386c036b MK |
1415 | /* Branch on Integer Register with Prediction (BPr). */ |
1416 | branch_p = 1; | |
1417 | conditional_p = 1; | |
c906108c | 1418 | } |
386c036b | 1419 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1420 | { |
386c036b MK |
1421 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1422 | branch_p = 1; | |
1423 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1424 | } |
386c036b MK |
1425 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1426 | { | |
1427 | /* Branch on Floating-Point Condition Codes with Prediction | |
1428 | (FBPfcc). */ | |
1429 | branch_p = 1; | |
1430 | offset = 4 * X_DISP19 (insn); | |
1431 | } | |
1432 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1433 | { | |
1434 | /* Branch on Integer Condition Codes (Bicc). */ | |
1435 | branch_p = 1; | |
1436 | offset = 4 * X_DISP22 (insn); | |
1437 | } | |
1438 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1439 | { |
386c036b MK |
1440 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1441 | branch_p = 1; | |
1442 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1443 | } |
c893be75 MK |
1444 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1445 | { | |
1446 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1447 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1448 | } |
386c036b MK |
1449 | |
1450 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1451 | ||
386c036b | 1452 | if (branch_p) |
c906108c | 1453 | { |
386c036b | 1454 | if (conditional_p) |
c906108c | 1455 | { |
386c036b MK |
1456 | /* For conditional branches, return nPC + 4 iff the annul |
1457 | bit is 1. */ | |
1458 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1459 | } |
1460 | else | |
1461 | { | |
386c036b MK |
1462 | /* For unconditional branches, return the target if its |
1463 | specified condition is "always" and return nPC + 4 if the | |
1464 | condition is "never". If the annul bit is 1, set *NPC to | |
1465 | zero. */ | |
1466 | if (X_COND (insn) == 0x0) | |
1467 | pc = *npc, offset = 4; | |
1468 | if (X_A (insn)) | |
1469 | *npc = 0; | |
1470 | ||
1471 | gdb_assert (offset != 0); | |
1472 | return pc + offset; | |
c906108c SS |
1473 | } |
1474 | } | |
386c036b MK |
1475 | |
1476 | return 0; | |
c906108c SS |
1477 | } |
1478 | ||
c893be75 | 1479 | static CORE_ADDR |
0b1b3e42 | 1480 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1481 | { |
1482 | return 0; | |
1483 | } | |
1484 | ||
e6590a1b | 1485 | int |
0b1b3e42 | 1486 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1487 | { |
0b1b3e42 | 1488 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1489 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
6c95b8df | 1490 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 1491 | CORE_ADDR npc, nnpc; |
c906108c | 1492 | |
e0cd558a | 1493 | CORE_ADDR pc, orig_npc; |
c906108c | 1494 | |
0b1b3e42 UW |
1495 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1496 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1497 | |
e0cd558a | 1498 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1499 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1500 | if (npc != 0) |
6c95b8df | 1501 | insert_single_step_breakpoint (arch, aspace, npc); |
8181d85f | 1502 | |
e0cd558a | 1503 | if (nnpc != 0) |
6c95b8df | 1504 | insert_single_step_breakpoint (arch, aspace, nnpc); |
c906108c | 1505 | |
e0cd558a UW |
1506 | /* Assert that we have set at least one breakpoint, and that |
1507 | they're not set at the same spot - unless we're going | |
1508 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1509 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1510 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1511 | |
1512 | return 1; | |
386c036b MK |
1513 | } |
1514 | ||
1515 | static void | |
61a1198a | 1516 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1517 | { |
61a1198a | 1518 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1519 | |
61a1198a UW |
1520 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1521 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1522 | } |
1523 | \f | |
5af923b0 | 1524 | |
a54124c5 MK |
1525 | /* Return the appropriate register set for the core section identified |
1526 | by SECT_NAME and SECT_SIZE. */ | |
1527 | ||
63807e1d | 1528 | static const struct regset * |
a54124c5 MK |
1529 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1530 | const char *sect_name, size_t sect_size) | |
1531 | { | |
1532 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1533 | ||
c558d81a | 1534 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1535 | return tdep->gregset; |
1536 | ||
c558d81a | 1537 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1538 | return tdep->fpregset; |
1539 | ||
1540 | return NULL; | |
1541 | } | |
1542 | \f | |
1543 | ||
386c036b MK |
1544 | static struct gdbarch * |
1545 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1546 | { | |
1547 | struct gdbarch_tdep *tdep; | |
1548 | struct gdbarch *gdbarch; | |
c906108c | 1549 | |
386c036b MK |
1550 | /* If there is already a candidate, use it. */ |
1551 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1552 | if (arches != NULL) | |
1553 | return arches->gdbarch; | |
c906108c | 1554 | |
386c036b | 1555 | /* Allocate space for the new architecture. */ |
1390fcc2 | 1556 | tdep = XZALLOC (struct gdbarch_tdep); |
386c036b | 1557 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1558 | |
386c036b MK |
1559 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1560 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1561 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1562 | |
1563 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1564 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1565 | |
1566 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1567 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1568 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1569 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1570 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1571 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1572 | ||
1573 | /* Register numbers of various important registers. */ | |
1574 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1575 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1576 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1577 | ||
1578 | /* Call dummy code. */ | |
49a45ecf | 1579 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1580 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1581 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1582 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1583 | ||
b9d4c5ed | 1584 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1585 | set_gdbarch_stabs_argument_has_addr |
1586 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1587 | ||
1588 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1589 | ||
1590 | /* Stack grows downward. */ | |
1591 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1592 | |
386c036b | 1593 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1594 | |
386c036b | 1595 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1596 | |
386c036b | 1597 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1598 | |
386c036b MK |
1599 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1600 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1601 | |
236369e7 | 1602 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1603 | |
386c036b | 1604 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1605 | |
386c036b MK |
1606 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1607 | ||
f5a9b87d DM |
1608 | /* Hook in the DWARF CFI frame unwinder. */ |
1609 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1610 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1611 | StackGhost issues have been resolved. */ | |
1612 | ||
b2a0b9b2 DM |
1613 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1614 | gdbarch_init_osabi (info, gdbarch); | |
1615 | ||
236369e7 | 1616 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1617 | |
a54124c5 | 1618 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1619 | if (tdep->gregset) |
a54124c5 MK |
1620 | set_gdbarch_regset_from_core_section (gdbarch, |
1621 | sparc_regset_from_core_section); | |
1622 | ||
386c036b MK |
1623 | return gdbarch; |
1624 | } | |
1625 | \f | |
1626 | /* Helper functions for dealing with register windows. */ | |
1627 | ||
1628 | void | |
1629 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1630 | { |
e17a4113 UW |
1631 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1632 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1633 | int offset = 0; |
e1613aba | 1634 | gdb_byte buf[8]; |
386c036b MK |
1635 | int i; |
1636 | ||
1637 | if (sp & 1) | |
1638 | { | |
1639 | /* Registers are 64-bit. */ | |
1640 | sp += BIAS; | |
c906108c | 1641 | |
386c036b MK |
1642 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1643 | { | |
1644 | if (regnum == i || regnum == -1) | |
1645 | { | |
1646 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1647 | |
1648 | /* Handle StackGhost. */ | |
1649 | if (i == SPARC_I7_REGNUM) | |
1650 | { | |
e17a4113 UW |
1651 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1652 | ULONGEST i7; | |
f700a364 | 1653 | |
e17a4113 UW |
1654 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1655 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1656 | i7 ^ wcookie); | |
f700a364 MK |
1657 | } |
1658 | ||
386c036b MK |
1659 | regcache_raw_supply (regcache, i, buf); |
1660 | } | |
1661 | } | |
1662 | } | |
1663 | else | |
c906108c | 1664 | { |
386c036b MK |
1665 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1666 | pointer. */ | |
1667 | sp &= 0xffffffffUL; | |
c906108c | 1668 | |
386c036b MK |
1669 | /* Clear out the top half of the temporary buffer, and put the |
1670 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1671 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1672 | { |
386c036b MK |
1673 | memset (buf, 0, 4); |
1674 | offset = 4; | |
1675 | } | |
c906108c | 1676 | |
386c036b MK |
1677 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1678 | { | |
1679 | if (regnum == i || regnum == -1) | |
1680 | { | |
1681 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1682 | buf + offset, 4); | |
42cdca6c MK |
1683 | |
1684 | /* Handle StackGhost. */ | |
1685 | if (i == SPARC_I7_REGNUM) | |
1686 | { | |
e17a4113 UW |
1687 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1688 | ULONGEST i7; | |
42cdca6c | 1689 | |
e17a4113 UW |
1690 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1691 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1692 | i7 ^ wcookie); | |
42cdca6c MK |
1693 | } |
1694 | ||
386c036b MK |
1695 | regcache_raw_supply (regcache, i, buf); |
1696 | } | |
c906108c SS |
1697 | } |
1698 | } | |
c906108c | 1699 | } |
c906108c SS |
1700 | |
1701 | void | |
386c036b MK |
1702 | sparc_collect_rwindow (const struct regcache *regcache, |
1703 | CORE_ADDR sp, int regnum) | |
c906108c | 1704 | { |
e17a4113 UW |
1705 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1706 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1707 | int offset = 0; |
e1613aba | 1708 | gdb_byte buf[8]; |
386c036b | 1709 | int i; |
5af923b0 | 1710 | |
386c036b | 1711 | if (sp & 1) |
5af923b0 | 1712 | { |
386c036b MK |
1713 | /* Registers are 64-bit. */ |
1714 | sp += BIAS; | |
c906108c | 1715 | |
386c036b MK |
1716 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1717 | { | |
1718 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1719 | { | |
1720 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1721 | |
1722 | /* Handle StackGhost. */ | |
1723 | if (i == SPARC_I7_REGNUM) | |
1724 | { | |
e17a4113 UW |
1725 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1726 | ULONGEST i7; | |
f700a364 | 1727 | |
e17a4113 UW |
1728 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1729 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1730 | } |
1731 | ||
386c036b MK |
1732 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1733 | } | |
1734 | } | |
5af923b0 MS |
1735 | } |
1736 | else | |
1737 | { | |
386c036b MK |
1738 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1739 | pointer. */ | |
1740 | sp &= 0xffffffffUL; | |
1741 | ||
1742 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1743 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1744 | offset = 4; |
1745 | ||
1746 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1747 | { | |
1748 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1749 | { | |
1750 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1751 | |
1752 | /* Handle StackGhost. */ | |
1753 | if (i == SPARC_I7_REGNUM) | |
1754 | { | |
e17a4113 UW |
1755 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1756 | ULONGEST i7; | |
42cdca6c | 1757 | |
e17a4113 UW |
1758 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1759 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1760 | i7 ^ wcookie); | |
42cdca6c MK |
1761 | } |
1762 | ||
386c036b MK |
1763 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1764 | buf + offset, 4); | |
1765 | } | |
1766 | } | |
5af923b0 | 1767 | } |
c906108c SS |
1768 | } |
1769 | ||
386c036b MK |
1770 | /* Helper functions for dealing with register sets. */ |
1771 | ||
c906108c | 1772 | void |
386c036b MK |
1773 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1774 | struct regcache *regcache, | |
1775 | int regnum, const void *gregs) | |
c906108c | 1776 | { |
e1613aba | 1777 | const gdb_byte *regs = gregs; |
22e74ef9 | 1778 | gdb_byte zero[4] = { 0 }; |
386c036b | 1779 | int i; |
5af923b0 | 1780 | |
386c036b MK |
1781 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1782 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1783 | regs + gregset->r_psr_offset); | |
c906108c | 1784 | |
386c036b MK |
1785 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1786 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1787 | regs + gregset->r_pc_offset); | |
5af923b0 | 1788 | |
386c036b MK |
1789 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1790 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1791 | regs + gregset->r_npc_offset); | |
5af923b0 | 1792 | |
386c036b MK |
1793 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1794 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1795 | regs + gregset->r_y_offset); | |
5af923b0 | 1796 | |
386c036b | 1797 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 1798 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 1799 | |
386c036b | 1800 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1801 | { |
386c036b MK |
1802 | int offset = gregset->r_g1_offset; |
1803 | ||
1804 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1805 | { | |
1806 | if (regnum == i || regnum == -1) | |
1807 | regcache_raw_supply (regcache, i, regs + offset); | |
1808 | offset += 4; | |
1809 | } | |
c906108c | 1810 | } |
386c036b MK |
1811 | |
1812 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1813 | { |
386c036b MK |
1814 | /* Not all of the register set variants include Locals and |
1815 | Inputs. For those that don't, we read them off the stack. */ | |
1816 | if (gregset->r_l0_offset == -1) | |
1817 | { | |
1818 | ULONGEST sp; | |
1819 | ||
1820 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1821 | sparc_supply_rwindow (regcache, sp, regnum); | |
1822 | } | |
1823 | else | |
1824 | { | |
1825 | int offset = gregset->r_l0_offset; | |
1826 | ||
1827 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1828 | { | |
1829 | if (regnum == i || regnum == -1) | |
1830 | regcache_raw_supply (regcache, i, regs + offset); | |
1831 | offset += 4; | |
1832 | } | |
1833 | } | |
c906108c SS |
1834 | } |
1835 | } | |
1836 | ||
c5aa993b | 1837 | void |
386c036b MK |
1838 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1839 | const struct regcache *regcache, | |
1840 | int regnum, void *gregs) | |
c906108c | 1841 | { |
e1613aba | 1842 | gdb_byte *regs = gregs; |
386c036b | 1843 | int i; |
c5aa993b | 1844 | |
386c036b MK |
1845 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1846 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1847 | regs + gregset->r_psr_offset); | |
60054393 | 1848 | |
386c036b MK |
1849 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1850 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1851 | regs + gregset->r_pc_offset); | |
1852 | ||
1853 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1854 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1855 | regs + gregset->r_npc_offset); | |
5af923b0 | 1856 | |
386c036b MK |
1857 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1858 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1859 | regs + gregset->r_y_offset); | |
1860 | ||
1861 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1862 | { |
386c036b MK |
1863 | int offset = gregset->r_g1_offset; |
1864 | ||
1865 | /* %g0 is always zero. */ | |
1866 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1867 | { | |
1868 | if (regnum == i || regnum == -1) | |
1869 | regcache_raw_collect (regcache, i, regs + offset); | |
1870 | offset += 4; | |
1871 | } | |
5af923b0 | 1872 | } |
386c036b MK |
1873 | |
1874 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1875 | { |
386c036b MK |
1876 | /* Not all of the register set variants include Locals and |
1877 | Inputs. For those that don't, we read them off the stack. */ | |
1878 | if (gregset->r_l0_offset != -1) | |
1879 | { | |
1880 | int offset = gregset->r_l0_offset; | |
1881 | ||
1882 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1883 | { | |
1884 | if (regnum == i || regnum == -1) | |
1885 | regcache_raw_collect (regcache, i, regs + offset); | |
1886 | offset += 4; | |
1887 | } | |
1888 | } | |
5af923b0 | 1889 | } |
c906108c SS |
1890 | } |
1891 | ||
c906108c | 1892 | void |
386c036b MK |
1893 | sparc32_supply_fpregset (struct regcache *regcache, |
1894 | int regnum, const void *fpregs) | |
c906108c | 1895 | { |
e1613aba | 1896 | const gdb_byte *regs = fpregs; |
386c036b | 1897 | int i; |
60054393 | 1898 | |
386c036b | 1899 | for (i = 0; i < 32; i++) |
c906108c | 1900 | { |
386c036b MK |
1901 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1902 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1903 | } |
5af923b0 | 1904 | |
386c036b MK |
1905 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1906 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1907 | } |
1908 | ||
386c036b MK |
1909 | void |
1910 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1911 | int regnum, void *fpregs) | |
c906108c | 1912 | { |
e1613aba | 1913 | gdb_byte *regs = fpregs; |
386c036b | 1914 | int i; |
c906108c | 1915 | |
386c036b MK |
1916 | for (i = 0; i < 32; i++) |
1917 | { | |
1918 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1919 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1920 | } | |
c906108c | 1921 | |
386c036b MK |
1922 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1923 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1924 | } |
c906108c | 1925 | \f |
c906108c | 1926 | |
386c036b | 1927 | /* SunOS 4. */ |
c906108c | 1928 | |
386c036b MK |
1929 | /* From <machine/reg.h>. */ |
1930 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1931 | { |
386c036b MK |
1932 | 0 * 4, /* %psr */ |
1933 | 1 * 4, /* %pc */ | |
1934 | 2 * 4, /* %npc */ | |
1935 | 3 * 4, /* %y */ | |
1936 | -1, /* %wim */ | |
1937 | -1, /* %tbr */ | |
1938 | 4 * 4, /* %g1 */ | |
1939 | -1 /* %l0 */ | |
1940 | }; | |
1941 | \f | |
c906108c | 1942 | |
386c036b MK |
1943 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1944 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1945 | |
1946 | void | |
386c036b | 1947 | _initialize_sparc_tdep (void) |
c906108c | 1948 | { |
386c036b | 1949 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 1950 | } |