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[deliverable/binutils-gdb.git] / gdb / sparc-tdep.c
CommitLineData
386c036b 1/* Target-dependent code for SPARC.
cda5a58a 2
386c036b 3 Copyright 2003, 2004 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c 21
c906108c 22#include "defs.h"
5af923b0 23#include "arch-utils.h"
386c036b
MK
24#include "dis-asm.h"
25#include "floatformat.h"
c906108c 26#include "frame.h"
386c036b
MK
27#include "frame-base.h"
28#include "frame-unwind.h"
29#include "gdbcore.h"
30#include "gdbtypes.h"
c906108c 31#include "inferior.h"
386c036b
MK
32#include "symtab.h"
33#include "objfiles.h"
34#include "osabi.h"
35#include "regcache.h"
c906108c
SS
36#include "target.h"
37#include "value.h"
c906108c 38
43bd9a9e 39#include "gdb_assert.h"
386c036b 40#include "gdb_string.h"
c906108c 41
386c036b 42#include "sparc-tdep.h"
c906108c 43
a54124c5
MK
44struct regset;
45
9eb42ed1
MK
46/* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
f2e7c15d 49 lists changes with respect to the original 32-bit psABI as defined
9eb42ed1 50 in the "System V ABI, SPARC Processor Supplement".
386c036b
MK
51
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
58 2.x is SVR4-based. */
59
60/* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
64
65/* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-recision format. */
67#define floatformat_sparc_quad floatformat_ia64_quad_big
68
69/* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
72#undef BIAS
73#define BIAS 2047
74
75/* Macros to extract fields from SPARC instructions. */
c906108c
SS
76#define X_OP(i) (((i) >> 30) & 0x3)
77#define X_RD(i) (((i) >> 25) & 0x1f)
78#define X_A(i) (((i) >> 29) & 1)
79#define X_COND(i) (((i) >> 25) & 0xf)
80#define X_OP2(i) (((i) >> 22) & 0x7)
81#define X_IMM22(i) ((i) & 0x3fffff)
82#define X_OP3(i) (((i) >> 19) & 0x3f)
c906108c 83#define X_I(i) (((i) >> 13) & 1)
c906108c 84/* Sign extension macros. */
c906108c 85#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
c906108c 86#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
c906108c 87
386c036b
MK
88/* Fetch the instruction at PC. Instructions are always big-endian
89 even if the processor operates in little-endian mode. */
90
91unsigned long
92sparc_fetch_instruction (CORE_ADDR pc)
c906108c 93{
386c036b
MK
94 unsigned char buf[4];
95 unsigned long insn;
96 int i;
97
690668cc
MK
98 /* If we can't read the instruction at PC, return zero. */
99 if (target_read_memory (pc, buf, sizeof (buf)))
100 return 0;
c906108c 101
386c036b
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102 insn = 0;
103 for (i = 0; i < sizeof (buf); i++)
104 insn = (insn << 8) | buf[i];
105 return insn;
106}
42cdca6c
MK
107\f
108
109/* OpenBSD/sparc includes StackGhost, which according to the author's
110 website http://stackghost.cerias.purdue.edu "... transparently and
111 automatically protects applications' stack frames; more
112 specifically, it guards the return pointers. The protection
113 mechanisms require no application source or binary modification and
114 imposes only a negligible performance penalty."
115
116 The same website provides the following description of how
117 StackGhost works:
118
119 "StackGhost interfaces with the kernel trap handler that would
120 normally write out registers to the stack and the handler that
121 would read them back in. By XORing a cookie into the
122 return-address saved in the user stack when it is actually written
123 to the stack, and then XOR it out when the return-address is pulled
124 from the stack, StackGhost can cause attacker corrupted return
125 pointers to behave in a manner the attacker cannot predict.
126 StackGhost can also use several unused bits in the return pointer
127 to detect a smashed return pointer and abort the process."
128
129 For GDB this means that whenever we're reading %i7 from a stack
130 frame's window save area, we'll have to XOR the cookie.
131
132 More information on StackGuard can be found on in:
133
134 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
135 Stack Protection." 2001. Published in USENIX Security Symposium
136 '01. */
137
138/* Fetch StackGhost Per-Process XOR cookie. */
139
140ULONGEST
141sparc_fetch_wcookie (void)
142{
baf92889
MK
143 struct target_ops *ops = &current_target;
144 char buf[8];
145 int len;
146
147 len = target_read_partial (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
148 if (len == -1)
149 return 0;
42cdca6c 150
baf92889
MK
151 /* We should have either an 32-bit or an 64-bit cookie. */
152 gdb_assert (len == 4 || len == 8);
153
154 return extract_unsigned_integer (buf, len);
155}
386c036b 156\f
baf92889 157
386c036b 158/* Return the contents if register REGNUM as an address. */
c906108c 159
386c036b
MK
160static CORE_ADDR
161sparc_address_from_register (int regnum)
162{
163 ULONGEST addr;
c906108c 164
386c036b
MK
165 regcache_cooked_read_unsigned (current_regcache, regnum, &addr);
166 return addr;
167}
168\f
c906108c 169
386c036b
MK
170/* The functions on this page are intended to be used to classify
171 function arguments. */
c906108c 172
386c036b 173/* Check whether TYPE is "Integral or Pointer". */
c906108c 174
386c036b
MK
175static int
176sparc_integral_or_pointer_p (const struct type *type)
c906108c 177{
386c036b 178 switch (TYPE_CODE (type))
c906108c 179 {
386c036b
MK
180 case TYPE_CODE_INT:
181 case TYPE_CODE_BOOL:
182 case TYPE_CODE_CHAR:
183 case TYPE_CODE_ENUM:
184 case TYPE_CODE_RANGE:
185 {
186 /* We have byte, half-word, word and extended-word/doubleword
187 integral types. The doubleword is an extension to the
f2e7c15d 188 original 32-bit ABI by the SCD 2.4.x. */
386c036b
MK
189 int len = TYPE_LENGTH (type);
190 return (len == 1 || len == 2 || len == 4 || len == 8);
191 }
192 return 1;
193 case TYPE_CODE_PTR:
194 case TYPE_CODE_REF:
195 {
196 /* Allow either 32-bit or 64-bit pointers. */
197 int len = TYPE_LENGTH (type);
198 return (len == 4 || len == 8);
199 }
200 return 1;
201 default:
202 break;
203 }
c906108c 204
386c036b
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205 return 0;
206}
c906108c 207
386c036b 208/* Check whether TYPE is "Floating". */
c906108c 209
386c036b
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210static int
211sparc_floating_p (const struct type *type)
212{
213 switch (TYPE_CODE (type))
c906108c 214 {
386c036b
MK
215 case TYPE_CODE_FLT:
216 {
217 int len = TYPE_LENGTH (type);
218 return (len == 4 || len == 8 || len == 16);
219 }
220 default:
221 break;
222 }
223
224 return 0;
225}
c906108c 226
386c036b 227/* Check whether TYPE is "Structure or Union". */
c906108c 228
386c036b
MK
229static int
230sparc_structure_or_union_p (const struct type *type)
231{
232 switch (TYPE_CODE (type))
233 {
234 case TYPE_CODE_STRUCT:
235 case TYPE_CODE_UNION:
236 return 1;
237 default:
238 break;
c906108c 239 }
386c036b
MK
240
241 return 0;
c906108c 242}
386c036b
MK
243
244/* Register information. */
245
246static const char *sparc32_register_names[] =
5af923b0 247{
386c036b
MK
248 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
249 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
250 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
251 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
252
253 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
254 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
255 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
256 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
257
258 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
5af923b0
MS
259};
260
386c036b
MK
261/* Total number of registers. */
262#define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
c906108c 263
386c036b
MK
264/* We provide the aliases %d0..%d30 for the floating registers as
265 "psuedo" registers. */
266
267static const char *sparc32_pseudo_register_names[] =
268{
269 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
270 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
271};
272
273/* Total number of pseudo registers. */
274#define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
275
276/* Return the name of register REGNUM. */
277
278static const char *
279sparc32_register_name (int regnum)
280{
281 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
282 return sparc32_register_names[regnum];
283
284 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
285 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
286
287 return NULL;
288}
289
290/* Return the GDB type object for the "standard" data type of data in
291 register REGNUM. */
292
293static struct type *
294sparc32_register_type (struct gdbarch *gdbarch, int regnum)
295{
296 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
297 return builtin_type_float;
298
299 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
300 return builtin_type_double;
301
302 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
303 return builtin_type_void_data_ptr;
304
305 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
306 return builtin_type_void_func_ptr;
307
308 return builtin_type_int32;
309}
310
311static void
312sparc32_pseudo_register_read (struct gdbarch *gdbarch,
313 struct regcache *regcache,
314 int regnum, void *buf)
315{
316 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
317
318 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
319 regcache_raw_read (regcache, regnum, buf);
320 regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4);
321}
322
323static void
324sparc32_pseudo_register_write (struct gdbarch *gdbarch,
325 struct regcache *regcache,
326 int regnum, const void *buf)
327{
328 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
329
330 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
331 regcache_raw_write (regcache, regnum, buf);
332 regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4);
333}
334\f
335
336static CORE_ADDR
337sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
338 CORE_ADDR funcaddr, int using_gcc,
339 struct value **args, int nargs,
340 struct type *value_type,
341 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
c906108c 342{
386c036b
MK
343 *bp_addr = sp - 4;
344 *real_pc = funcaddr;
345
346 if (using_struct_return (value_type, using_gcc))
c906108c 347 {
386c036b
MK
348 char buf[4];
349
350 /* This is an UNIMP instruction. */
351 store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
352 write_memory (sp - 8, buf, 4);
353 return sp - 8;
c906108c
SS
354 }
355
386c036b
MK
356 return sp - 4;
357}
358
359static CORE_ADDR
360sparc32_store_arguments (struct regcache *regcache, int nargs,
361 struct value **args, CORE_ADDR sp,
362 int struct_return, CORE_ADDR struct_addr)
363{
364 /* Number of words in the "parameter array". */
365 int num_elements = 0;
366 int element = 0;
367 int i;
368
369 for (i = 0; i < nargs; i++)
c906108c 370 {
386c036b
MK
371 struct type *type = VALUE_TYPE (args[i]);
372 int len = TYPE_LENGTH (type);
373
374 if (sparc_structure_or_union_p (type)
375 || (sparc_floating_p (type) && len == 16))
c906108c 376 {
386c036b
MK
377 /* Structure, Union and Quad-Precision Arguments. */
378 sp -= len;
379
380 /* Use doubleword alignment for these values. That's always
381 correct, and wasting a few bytes shouldn't be a problem. */
382 sp &= ~0x7;
383
384 write_memory (sp, VALUE_CONTENTS (args[i]), len);
385 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
386 num_elements++;
387 }
388 else if (sparc_floating_p (type))
389 {
390 /* Floating arguments. */
391 gdb_assert (len == 4 || len == 8);
392 num_elements += (len / 4);
c906108c 393 }
c5aa993b
JM
394 else
395 {
386c036b
MK
396 /* Integral and pointer arguments. */
397 gdb_assert (sparc_integral_or_pointer_p (type));
398
399 if (len < 4)
400 args[i] = value_cast (builtin_type_int32, args[i]);
401 num_elements += ((len + 3) / 4);
c5aa993b 402 }
c906108c 403 }
c906108c 404
386c036b
MK
405 /* Always allocate at least six words. */
406 sp -= max (6, num_elements) * 4;
c906108c 407
386c036b
MK
408 /* The psABI says that "Software convention requires space for the
409 struct/union return value pointer, even if the word is unused." */
410 sp -= 4;
c906108c 411
386c036b
MK
412 /* The psABI says that "Although software convention and the
413 operating system require every stack frame to be doubleword
414 aligned." */
415 sp &= ~0x7;
c906108c 416
386c036b 417 for (i = 0; i < nargs; i++)
c906108c 418 {
386c036b
MK
419 char *valbuf = VALUE_CONTENTS (args[i]);
420 struct type *type = VALUE_TYPE (args[i]);
421 int len = TYPE_LENGTH (type);
c906108c 422
386c036b 423 gdb_assert (len == 4 || len == 8);
c906108c 424
386c036b
MK
425 if (element < 6)
426 {
427 int regnum = SPARC_O0_REGNUM + element;
c906108c 428
386c036b
MK
429 regcache_cooked_write (regcache, regnum, valbuf);
430 if (len > 4 && element < 5)
431 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
432 }
5af923b0 433
386c036b
MK
434 /* Always store the argument in memory. */
435 write_memory (sp + 4 + element * 4, valbuf, len);
436 element += len / 4;
437 }
c906108c 438
386c036b 439 gdb_assert (element == num_elements);
c906108c 440
386c036b 441 if (struct_return)
c906108c 442 {
386c036b 443 char buf[4];
c906108c 444
386c036b
MK
445 store_unsigned_integer (buf, 4, struct_addr);
446 write_memory (sp, buf, 4);
447 }
c906108c 448
386c036b 449 return sp;
c906108c
SS
450}
451
386c036b
MK
452static CORE_ADDR
453sparc32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
454 struct regcache *regcache, CORE_ADDR bp_addr,
455 int nargs, struct value **args, CORE_ADDR sp,
456 int struct_return, CORE_ADDR struct_addr)
c906108c 457{
386c036b
MK
458 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
459
460 /* Set return address. */
461 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
462
463 /* Set up function arguments. */
464 sp = sparc32_store_arguments (regcache, nargs, args, sp,
465 struct_return, struct_addr);
466
467 /* Allocate the 16-word window save area. */
468 sp -= 16 * 4;
c906108c 469
386c036b
MK
470 /* Stack should be doubleword aligned at this point. */
471 gdb_assert (sp % 8 == 0);
c906108c 472
386c036b
MK
473 /* Finally, update the stack pointer. */
474 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
475
476 return sp;
477}
478\f
c906108c 479
386c036b
MK
480/* Use the program counter to determine the contents and size of a
481 breakpoint instruction. Return a pointer to a string of bytes that
482 encode a breakpoint instruction, store the length of the string in
483 *LEN and optionally adjust *PC to point to the correct memory
484 location for inserting the breakpoint. */
485
486static const unsigned char *
487sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len)
488{
489 static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
c5aa993b 490
386c036b
MK
491 *len = sizeof (break_insn);
492 return break_insn;
c906108c 493}
386c036b 494\f
c906108c 495
386c036b 496/* Allocate and initialize a frame cache. */
c906108c 497
386c036b
MK
498static struct sparc_frame_cache *
499sparc_alloc_frame_cache (void)
500{
501 struct sparc_frame_cache *cache;
502 int i;
c906108c 503
386c036b 504 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
c906108c 505
386c036b
MK
506 /* Base address. */
507 cache->base = 0;
508 cache->pc = 0;
c906108c 509
386c036b
MK
510 /* Frameless until proven otherwise. */
511 cache->frameless_p = 1;
512
513 cache->struct_return_p = 0;
514
515 return cache;
516}
517
518CORE_ADDR
519sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
520 struct sparc_frame_cache *cache)
c906108c 521{
386c036b
MK
522 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
523 unsigned long insn;
524 int offset = 0;
c906108c 525 int dest = -1;
c906108c 526
386c036b
MK
527 if (current_pc <= pc)
528 return current_pc;
529
530 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
531 SPARC the linker usually defines a symbol (typically
532 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
533 This symbol makes us end up here with PC pointing at the start of
534 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
535 would do our normal prologue analysis, we would probably conclude
536 that we've got a frame when in reality we don't, since the
537 dynamic linker patches up the first PLT with some code that
538 starts with a SAVE instruction. Patch up PC such that it points
539 at the start of our PLT entry. */
540 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
541 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
c906108c 542
386c036b
MK
543 insn = sparc_fetch_instruction (pc);
544
545 /* Recognize a SETHI insn and record its destination. */
546 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
c906108c
SS
547 {
548 dest = X_RD (insn);
386c036b
MK
549 offset += 4;
550
551 insn = sparc_fetch_instruction (pc + 4);
c906108c
SS
552 }
553
386c036b
MK
554 /* Allow for an arithmetic operation on DEST or %g1. */
555 if (X_OP (insn) == 2 && X_I (insn)
c906108c
SS
556 && (X_RD (insn) == 1 || X_RD (insn) == dest))
557 {
386c036b 558 offset += 4;
c906108c 559
386c036b 560 insn = sparc_fetch_instruction (pc + 8);
c906108c 561 }
c906108c 562
386c036b
MK
563 /* Check for the SAVE instruction that sets up the frame. */
564 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
c906108c 565 {
386c036b
MK
566 cache->frameless_p = 0;
567 return pc + offset + 4;
c906108c
SS
568 }
569
570 return pc;
571}
572
386c036b
MK
573static CORE_ADDR
574sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
575{
576 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
577 return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
578}
579
580/* Return PC of first real instruction of the function starting at
581 START_PC. */
f510d44e 582
386c036b
MK
583static CORE_ADDR
584sparc32_skip_prologue (CORE_ADDR start_pc)
c906108c 585{
f510d44e
DM
586 struct symtab_and_line sal;
587 CORE_ADDR func_start, func_end;
386c036b 588 struct sparc_frame_cache cache;
f510d44e
DM
589
590 /* This is the preferred method, find the end of the prologue by
591 using the debugging information. */
592 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
593 {
594 sal = find_pc_line (func_start, 0);
595
596 if (sal.end < func_end
597 && start_pc <= sal.end)
598 return sal.end;
599 }
600
386c036b 601 return sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache);
c906108c
SS
602}
603
386c036b 604/* Normal frames. */
9319a2fe 605
386c036b
MK
606struct sparc_frame_cache *
607sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
9319a2fe 608{
386c036b 609 struct sparc_frame_cache *cache;
9319a2fe 610
386c036b
MK
611 if (*this_cache)
612 return *this_cache;
c906108c 613
386c036b
MK
614 cache = sparc_alloc_frame_cache ();
615 *this_cache = cache;
c906108c 616
386c036b
MK
617 cache->pc = frame_func_unwind (next_frame);
618 if (cache->pc != 0)
c906108c 619 {
386c036b
MK
620 CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame);
621 sparc_analyze_prologue (cache->pc, addr_in_block, cache);
c906108c 622 }
386c036b
MK
623
624 if (cache->frameless_p)
c906108c 625 {
cbeae229
MK
626 /* This function is frameless, so %fp (%i6) holds the frame
627 pointer for our calling frame. Use %sp (%o6) as this frame's
628 base address. */
629 cache->base =
630 frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
631 }
632 else
633 {
634 /* For normal frames, %fp (%i6) holds the frame pointer, the
635 base address for the current stack frame. */
636 cache->base =
637 frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
c906108c 638 }
c906108c 639
386c036b 640 return cache;
c906108c 641}
c906108c 642
386c036b
MK
643struct sparc_frame_cache *
644sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
c906108c 645{
386c036b
MK
646 struct sparc_frame_cache *cache;
647 struct symbol *sym;
c906108c 648
386c036b
MK
649 if (*this_cache)
650 return *this_cache;
c906108c 651
386c036b 652 cache = sparc_frame_cache (next_frame, this_cache);
c906108c 653
386c036b
MK
654 sym = find_pc_function (cache->pc);
655 if (sym)
c906108c 656 {
386c036b
MK
657 struct type *type = check_typedef (SYMBOL_TYPE (sym));
658 enum type_code code = TYPE_CODE (type);
659
660 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
661 {
662 type = check_typedef (TYPE_TARGET_TYPE (type));
663 if (sparc_structure_or_union_p (type)
664 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
665 cache->struct_return_p = 1;
666 }
c906108c
SS
667 }
668
386c036b
MK
669 return cache;
670}
671
672static void
673sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
674 struct frame_id *this_id)
675{
676 struct sparc_frame_cache *cache =
677 sparc32_frame_cache (next_frame, this_cache);
678
679 /* This marks the outermost frame. */
680 if (cache->base == 0)
681 return;
682
683 (*this_id) = frame_id_build (cache->base, cache->pc);
684}
c906108c 685
386c036b
MK
686static void
687sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
688 int regnum, int *optimizedp,
689 enum lval_type *lvalp, CORE_ADDR *addrp,
690 int *realnump, void *valuep)
691{
692 struct sparc_frame_cache *cache =
693 sparc32_frame_cache (next_frame, this_cache);
c906108c 694
386c036b 695 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
c906108c 696 {
386c036b
MK
697 *optimizedp = 0;
698 *lvalp = not_lval;
699 *addrp = 0;
700 *realnump = -1;
701 if (valuep)
c906108c 702 {
386c036b
MK
703 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
704
705 /* If this functions has a Structure, Union or
706 Quad-Precision return value, we have to skip the UNIMP
707 instruction that encodes the size of the structure. */
708 if (cache->struct_return_p)
709 pc += 4;
710
711 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
712 pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
713 store_unsigned_integer (valuep, 4, pc);
c906108c 714 }
c906108c
SS
715 return;
716 }
717
42cdca6c
MK
718 /* Handle StackGhost. */
719 {
720 ULONGEST wcookie = sparc_fetch_wcookie ();
721
722 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
723 {
724 *optimizedp = 0;
725 *lvalp = not_lval;
726 *addrp = 0;
727 *realnump = -1;
728 if (valuep)
729 {
730 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
7d34766b 731 ULONGEST i7;
42cdca6c
MK
732
733 /* Read the value in from memory. */
7d34766b
MK
734 i7 = get_frame_memory_unsigned (next_frame, addr, 4);
735 store_unsigned_integer (valuep, 4, i7 ^ wcookie);
42cdca6c
MK
736 }
737 return;
738 }
739 }
740
386c036b
MK
741 /* The previous frame's `local' and `in' registers have been saved
742 in the register save area. */
743 if (!cache->frameless_p
744 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
c906108c 745 {
386c036b
MK
746 *optimizedp = 0;
747 *lvalp = lval_memory;
748 *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
749 *realnump = -1;
750 if (valuep)
c906108c 751 {
386c036b
MK
752 struct gdbarch *gdbarch = get_frame_arch (next_frame);
753
754 /* Read the value in from memory. */
755 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
c906108c 756 }
386c036b
MK
757 return;
758 }
c906108c 759
386c036b
MK
760 /* The previous frame's `out' registers are accessable as the
761 current frame's `in' registers. */
762 if (!cache->frameless_p
763 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
764 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
5af923b0 765
386c036b
MK
766 frame_register_unwind (next_frame, regnum,
767 optimizedp, lvalp, addrp, realnump, valuep);
768}
c906108c 769
386c036b
MK
770static const struct frame_unwind sparc32_frame_unwind =
771{
772 NORMAL_FRAME,
773 sparc32_frame_this_id,
774 sparc32_frame_prev_register
775};
776
777static const struct frame_unwind *
778sparc32_frame_sniffer (struct frame_info *next_frame)
779{
780 return &sparc32_frame_unwind;
c906108c 781}
386c036b 782\f
c906108c 783
386c036b
MK
784static CORE_ADDR
785sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
786{
787 struct sparc_frame_cache *cache =
788 sparc32_frame_cache (next_frame, this_cache);
c906108c 789
386c036b
MK
790 return cache->base;
791}
c906108c 792
386c036b
MK
793static const struct frame_base sparc32_frame_base =
794{
795 &sparc32_frame_unwind,
796 sparc32_frame_base_address,
797 sparc32_frame_base_address,
798 sparc32_frame_base_address
799};
c906108c 800
386c036b
MK
801static struct frame_id
802sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
803{
804 CORE_ADDR sp;
5af923b0 805
386c036b
MK
806 sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
807 return frame_id_build (sp, frame_pc_unwind (next_frame));
808}
809\f
c906108c 810
386c036b
MK
811/* Extract from an array REGBUF containing the (raw) register state, a
812 function return value of TYPE, and copy that into VALBUF. */
5af923b0 813
386c036b
MK
814static void
815sparc32_extract_return_value (struct type *type, struct regcache *regcache,
816 void *valbuf)
817{
818 int len = TYPE_LENGTH (type);
819 char buf[8];
c906108c 820
386c036b
MK
821 gdb_assert (!sparc_structure_or_union_p (type));
822 gdb_assert (!(sparc_floating_p (type) && len == 16));
c906108c 823
386c036b 824 if (sparc_floating_p (type))
5af923b0 825 {
386c036b
MK
826 /* Floating return values. */
827 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
828 if (len > 4)
829 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
830 memcpy (valbuf, buf, len);
5af923b0
MS
831 }
832 else
833 {
386c036b
MK
834 /* Integral and pointer return values. */
835 gdb_assert (sparc_integral_or_pointer_p (type));
c906108c 836
386c036b
MK
837 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
838 if (len > 4)
839 {
840 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
841 gdb_assert (len == 8);
842 memcpy (valbuf, buf, 8);
843 }
844 else
845 {
846 /* Just stripping off any unused bytes should preserve the
847 signed-ness just fine. */
848 memcpy (valbuf, buf + 4 - len, len);
849 }
850 }
851}
c906108c 852
386c036b
MK
853/* Write into the appropriate registers a function return value stored
854 in VALBUF of type TYPE. */
c906108c 855
386c036b
MK
856static void
857sparc32_store_return_value (struct type *type, struct regcache *regcache,
858 const void *valbuf)
859{
860 int len = TYPE_LENGTH (type);
861 char buf[8];
c906108c 862
386c036b
MK
863 gdb_assert (!sparc_structure_or_union_p (type));
864 gdb_assert (!(sparc_floating_p (type) && len == 16));
c906108c 865
386c036b
MK
866 if (sparc_floating_p (type))
867 {
868 /* Floating return values. */
869 memcpy (buf, valbuf, len);
870 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
871 if (len > 4)
872 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
873 }
874 else
c906108c 875 {
386c036b
MK
876 /* Integral and pointer return values. */
877 gdb_assert (sparc_integral_or_pointer_p (type));
878
879 if (len > 4)
2757dd86 880 {
386c036b
MK
881 gdb_assert (len == 8);
882 memcpy (buf, valbuf, 8);
883 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
2757dd86
AC
884 }
885 else
886 {
386c036b
MK
887 /* ??? Do we need to do any sign-extension here? */
888 memcpy (buf + 4 - len, valbuf, len);
2757dd86 889 }
386c036b 890 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
c906108c
SS
891 }
892}
893
b9d4c5ed
MK
894static enum return_value_convention
895sparc32_return_value (struct gdbarch *gdbarch, struct type *type,
896 struct regcache *regcache, void *readbuf,
897 const void *writebuf)
898{
899 if (sparc_structure_or_union_p (type)
900 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
901 return RETURN_VALUE_STRUCT_CONVENTION;
902
903 if (readbuf)
904 sparc32_extract_return_value (type, regcache, readbuf);
905 if (writebuf)
906 sparc32_store_return_value (type, regcache, writebuf);
907
908 return RETURN_VALUE_REGISTER_CONVENTION;
909}
910
931aecf5
AC
911#if 0
912/* NOTE: cagney/2004-01-17: For the moment disable this method. The
913 architecture and CORE-gdb will need new code (and a replacement for
74055713
AC
914 DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS) before this can be made to
915 work robustly. Here is a possible function signature: */
931aecf5
AC
916/* NOTE: cagney/2004-01-17: So far only the 32-bit SPARC ABI has been
917 identifed as having a way to robustly recover the address of a
918 struct-convention return-value (after the function has returned).
919 For all other ABIs so far examined, the calling convention makes no
920 guarenteed that the register containing the return-value will be
921 preserved and hence that the return-value's address can be
922 recovered. */
386c036b
MK
923/* Extract from REGCACHE, which contains the (raw) register state, the
924 address in which a function should return its structure value, as a
925 CORE_ADDR. */
c906108c 926
386c036b 927static CORE_ADDR
ca9d58e9 928sparc32_extract_struct_value_address (struct regcache *regcache)
386c036b 929{
9515395e 930 ULONGEST sp;
c906108c 931
9515395e
MK
932 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
933 return read_memory_unsigned_integer (sp + 64, 4);
386c036b 934}
931aecf5 935#endif
c906108c 936
386c036b
MK
937static int
938sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
c906108c 939{
386c036b
MK
940 return (sparc_structure_or_union_p (type)
941 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
942}
c906108c 943
386c036b
MK
944\f
945/* The SPARC Architecture doesn't have hardware single-step support,
946 and most operating systems don't implement it either, so we provide
947 software single-step mechanism. */
c906108c 948
386c036b
MK
949static CORE_ADDR
950sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc)
951{
952 unsigned long insn = sparc_fetch_instruction (pc);
953 int conditional_p = X_COND (insn) & 0x7;
954 int branch_p = 0;
955 long offset = 0; /* Must be signed for sign-extend. */
c906108c 956
386c036b 957 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
c906108c 958 {
386c036b
MK
959 /* Branch on Integer Register with Prediction (BPr). */
960 branch_p = 1;
961 conditional_p = 1;
c906108c 962 }
386c036b 963 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
c906108c 964 {
386c036b
MK
965 /* Branch on Floating-Point Condition Codes (FBfcc). */
966 branch_p = 1;
967 offset = 4 * X_DISP22 (insn);
c906108c 968 }
386c036b
MK
969 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
970 {
971 /* Branch on Floating-Point Condition Codes with Prediction
972 (FBPfcc). */
973 branch_p = 1;
974 offset = 4 * X_DISP19 (insn);
975 }
976 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
977 {
978 /* Branch on Integer Condition Codes (Bicc). */
979 branch_p = 1;
980 offset = 4 * X_DISP22 (insn);
981 }
982 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
c906108c 983 {
386c036b
MK
984 /* Branch on Integer Condition Codes with Prediction (BPcc). */
985 branch_p = 1;
986 offset = 4 * X_DISP19 (insn);
c906108c 987 }
386c036b
MK
988
989 /* FIXME: Handle DONE and RETRY instructions. */
990
991 /* FIXME: Handle the Trap instruction. */
992
993 if (branch_p)
c906108c 994 {
386c036b 995 if (conditional_p)
c906108c 996 {
386c036b
MK
997 /* For conditional branches, return nPC + 4 iff the annul
998 bit is 1. */
999 return (X_A (insn) ? *npc + 4 : 0);
c906108c
SS
1000 }
1001 else
1002 {
386c036b
MK
1003 /* For unconditional branches, return the target if its
1004 specified condition is "always" and return nPC + 4 if the
1005 condition is "never". If the annul bit is 1, set *NPC to
1006 zero. */
1007 if (X_COND (insn) == 0x0)
1008 pc = *npc, offset = 4;
1009 if (X_A (insn))
1010 *npc = 0;
1011
1012 gdb_assert (offset != 0);
1013 return pc + offset;
c906108c
SS
1014 }
1015 }
386c036b
MK
1016
1017 return 0;
c906108c
SS
1018}
1019
386c036b
MK
1020void
1021sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1022{
1023 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1024 static CORE_ADDR npc, nnpc;
1025 static char npc_save[4], nnpc_save[4];
c906108c 1026
386c036b
MK
1027 if (insert_breakpoints_p)
1028 {
1029 CORE_ADDR pc;
c906108c 1030
386c036b
MK
1031 pc = sparc_address_from_register (tdep->pc_regnum);
1032 npc = sparc_address_from_register (tdep->npc_regnum);
c906108c 1033
386c036b
MK
1034 /* Analyze the instruction at PC. */
1035 nnpc = sparc_analyze_control_transfer (pc, &npc);
1036 if (npc != 0)
1037 target_insert_breakpoint (npc, npc_save);
1038 if (nnpc != 0)
1039 target_insert_breakpoint (nnpc, nnpc_save);
c906108c 1040
386c036b
MK
1041 /* Assert that we have set at least one breakpoint, and that
1042 they're not set at the same spot. */
1043 gdb_assert (npc != 0 || nnpc != 0);
1044 gdb_assert (nnpc != npc);
60054393 1045 }
386c036b 1046 else
c906108c 1047 {
386c036b
MK
1048 if (npc != 0)
1049 target_remove_breakpoint (npc, npc_save);
1050 if (nnpc != 0)
1051 target_remove_breakpoint (nnpc, nnpc_save);
c906108c 1052 }
386c036b
MK
1053}
1054
1055static void
1056sparc_write_pc (CORE_ADDR pc, ptid_t ptid)
1057{
1058 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1059
1060 write_register_pid (tdep->pc_regnum, pc, ptid);
1061 write_register_pid (tdep->npc_regnum, pc + 4, ptid);
1062}
1063\f
1064/* Unglobalize NAME. */
1065
1066char *
1067sparc_stabs_unglobalize_name (char *name)
1068{
1069 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1070 SunPRO) convert file static variables into global values, a
1071 process known as globalization. In order to do this, the
1072 compiler will create a unique prefix and prepend it to each file
1073 static variable. For static variables within a function, this
1074 globalization prefix is followed by the function name (nested
1075 static variables within a function are supposed to generate a
1076 warning message, and are left alone). The procedure is
1077 documented in the Stabs Interface Manual, which is distrubuted
1078 with the compilers, although version 4.0 of the manual seems to
1079 be incorrect in some places, at least for SPARC. The
1080 globalization prefix is encoded into an N_OPT stab, with the form
1081 "G=<prefix>". The globalization prefix always seems to start
1082 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1083 simply strip everything up until the last dot. */
c906108c 1084
386c036b 1085 if (name[0] == '$')
c906108c 1086 {
386c036b
MK
1087 char *p = strrchr (name, '.');
1088 if (p)
1089 return p + 1;
c906108c 1090 }
c906108c 1091
386c036b
MK
1092 return name;
1093}
1094\f
5af923b0 1095
a54124c5
MK
1096/* Return the appropriate register set for the core section identified
1097 by SECT_NAME and SECT_SIZE. */
1098
1099const struct regset *
1100sparc_regset_from_core_section (struct gdbarch *gdbarch,
1101 const char *sect_name, size_t sect_size)
1102{
1103 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1104
c558d81a 1105 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
a54124c5
MK
1106 return tdep->gregset;
1107
c558d81a 1108 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
a54124c5
MK
1109 return tdep->fpregset;
1110
1111 return NULL;
1112}
1113\f
1114
386c036b
MK
1115static struct gdbarch *
1116sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1117{
1118 struct gdbarch_tdep *tdep;
1119 struct gdbarch *gdbarch;
c906108c 1120
386c036b
MK
1121 /* If there is already a candidate, use it. */
1122 arches = gdbarch_list_lookup_by_info (arches, &info);
1123 if (arches != NULL)
1124 return arches->gdbarch;
c906108c 1125
386c036b
MK
1126 /* Allocate space for the new architecture. */
1127 tdep = XMALLOC (struct gdbarch_tdep);
1128 gdbarch = gdbarch_alloc (&info, tdep);
5af923b0 1129
386c036b
MK
1130 tdep->pc_regnum = SPARC32_PC_REGNUM;
1131 tdep->npc_regnum = SPARC32_NPC_REGNUM;
a54124c5 1132 tdep->gregset = NULL;
c558d81a 1133 tdep->sizeof_gregset = 0;
a54124c5 1134 tdep->fpregset = NULL;
c558d81a 1135 tdep->sizeof_fpregset = 0;
386c036b
MK
1136 tdep->plt_entry_size = 0;
1137
1138 set_gdbarch_long_double_bit (gdbarch, 128);
1139 set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad);
1140
1141 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1142 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1143 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1144 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1145 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1146 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1147
1148 /* Register numbers of various important registers. */
1149 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1150 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1151 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1152
1153 /* Call dummy code. */
1154 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1155 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1156 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1157
b9d4c5ed 1158 set_gdbarch_return_value (gdbarch, sparc32_return_value);
386c036b
MK
1159 set_gdbarch_stabs_argument_has_addr
1160 (gdbarch, sparc32_stabs_argument_has_addr);
1161
1162 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1163
1164 /* Stack grows downward. */
1165 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
c906108c 1166
386c036b 1167 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
c906108c 1168
386c036b 1169 set_gdbarch_frame_args_skip (gdbarch, 8);
5af923b0 1170
386c036b 1171 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
c906108c 1172
386c036b
MK
1173 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1174 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
c906108c 1175
386c036b 1176 set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
c906108c 1177
386c036b 1178 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
c906108c 1179
386c036b
MK
1180 frame_base_set_default (gdbarch, &sparc32_frame_base);
1181
1182 /* Hook in ABI-specific overrides, if they have been registered. */
1183 gdbarch_init_osabi (info, gdbarch);
c906108c 1184
386c036b 1185 frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
c906108c 1186
a54124c5 1187 /* If we have register sets, enable the generic core file support. */
4c72d57a 1188 if (tdep->gregset)
a54124c5
MK
1189 set_gdbarch_regset_from_core_section (gdbarch,
1190 sparc_regset_from_core_section);
1191
386c036b
MK
1192 return gdbarch;
1193}
1194\f
1195/* Helper functions for dealing with register windows. */
1196
1197void
1198sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
c906108c 1199{
386c036b
MK
1200 int offset = 0;
1201 char buf[8];
1202 int i;
1203
1204 if (sp & 1)
1205 {
1206 /* Registers are 64-bit. */
1207 sp += BIAS;
c906108c 1208
386c036b
MK
1209 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1210 {
1211 if (regnum == i || regnum == -1)
1212 {
1213 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1214 regcache_raw_supply (regcache, i, buf);
1215 }
1216 }
1217 }
1218 else
c906108c 1219 {
386c036b
MK
1220 /* Registers are 32-bit. Toss any sign-extension of the stack
1221 pointer. */
1222 sp &= 0xffffffffUL;
c906108c 1223
386c036b
MK
1224 /* Clear out the top half of the temporary buffer, and put the
1225 register value in the bottom half if we're in 64-bit mode. */
1226 if (gdbarch_ptr_bit (current_gdbarch) == 64)
c906108c 1227 {
386c036b
MK
1228 memset (buf, 0, 4);
1229 offset = 4;
1230 }
c906108c 1231
386c036b
MK
1232 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1233 {
1234 if (regnum == i || regnum == -1)
1235 {
1236 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1237 buf + offset, 4);
42cdca6c
MK
1238
1239 /* Handle StackGhost. */
1240 if (i == SPARC_I7_REGNUM)
1241 {
1242 ULONGEST wcookie = sparc_fetch_wcookie ();
7d34766b 1243 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
42cdca6c 1244
7d34766b 1245 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
42cdca6c
MK
1246 }
1247
386c036b
MK
1248 regcache_raw_supply (regcache, i, buf);
1249 }
c906108c
SS
1250 }
1251 }
c906108c 1252}
c906108c
SS
1253
1254void
386c036b
MK
1255sparc_collect_rwindow (const struct regcache *regcache,
1256 CORE_ADDR sp, int regnum)
c906108c 1257{
386c036b
MK
1258 int offset = 0;
1259 char buf[8];
1260 int i;
5af923b0 1261
386c036b 1262 if (sp & 1)
5af923b0 1263 {
386c036b
MK
1264 /* Registers are 64-bit. */
1265 sp += BIAS;
c906108c 1266
386c036b
MK
1267 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1268 {
1269 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1270 {
1271 regcache_raw_collect (regcache, i, buf);
1272 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1273 }
1274 }
5af923b0
MS
1275 }
1276 else
1277 {
386c036b
MK
1278 /* Registers are 32-bit. Toss any sign-extension of the stack
1279 pointer. */
1280 sp &= 0xffffffffUL;
1281
1282 /* Only use the bottom half if we're in 64-bit mode. */
1283 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1284 offset = 4;
1285
1286 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1287 {
1288 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1289 {
1290 regcache_raw_collect (regcache, i, buf);
42cdca6c
MK
1291
1292 /* Handle StackGhost. */
1293 if (i == SPARC_I7_REGNUM)
1294 {
1295 ULONGEST wcookie = sparc_fetch_wcookie ();
7d34766b 1296 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
42cdca6c 1297
7d34766b 1298 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
42cdca6c
MK
1299 }
1300
386c036b
MK
1301 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1302 buf + offset, 4);
1303 }
1304 }
5af923b0 1305 }
c906108c
SS
1306}
1307
386c036b
MK
1308/* Helper functions for dealing with register sets. */
1309
c906108c 1310void
386c036b
MK
1311sparc32_supply_gregset (const struct sparc_gregset *gregset,
1312 struct regcache *regcache,
1313 int regnum, const void *gregs)
c906108c 1314{
386c036b
MK
1315 const char *regs = gregs;
1316 int i;
5af923b0 1317
386c036b
MK
1318 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1319 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1320 regs + gregset->r_psr_offset);
c906108c 1321
386c036b
MK
1322 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1323 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1324 regs + gregset->r_pc_offset);
5af923b0 1325
386c036b
MK
1326 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1327 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1328 regs + gregset->r_npc_offset);
5af923b0 1329
386c036b
MK
1330 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1331 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1332 regs + gregset->r_y_offset);
5af923b0 1333
386c036b
MK
1334 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1335 regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
5af923b0 1336
386c036b 1337 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
c906108c 1338 {
386c036b
MK
1339 int offset = gregset->r_g1_offset;
1340
1341 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1342 {
1343 if (regnum == i || regnum == -1)
1344 regcache_raw_supply (regcache, i, regs + offset);
1345 offset += 4;
1346 }
c906108c 1347 }
386c036b
MK
1348
1349 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
c906108c 1350 {
386c036b
MK
1351 /* Not all of the register set variants include Locals and
1352 Inputs. For those that don't, we read them off the stack. */
1353 if (gregset->r_l0_offset == -1)
1354 {
1355 ULONGEST sp;
1356
1357 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1358 sparc_supply_rwindow (regcache, sp, regnum);
1359 }
1360 else
1361 {
1362 int offset = gregset->r_l0_offset;
1363
1364 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1365 {
1366 if (regnum == i || regnum == -1)
1367 regcache_raw_supply (regcache, i, regs + offset);
1368 offset += 4;
1369 }
1370 }
c906108c
SS
1371 }
1372}
1373
c5aa993b 1374void
386c036b
MK
1375sparc32_collect_gregset (const struct sparc_gregset *gregset,
1376 const struct regcache *regcache,
1377 int regnum, void *gregs)
c906108c 1378{
386c036b
MK
1379 char *regs = gregs;
1380 int i;
c5aa993b 1381
386c036b
MK
1382 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1383 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1384 regs + gregset->r_psr_offset);
60054393 1385
386c036b
MK
1386 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1387 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1388 regs + gregset->r_pc_offset);
1389
1390 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1391 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1392 regs + gregset->r_npc_offset);
5af923b0 1393
386c036b
MK
1394 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1395 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1396 regs + gregset->r_y_offset);
1397
1398 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
5af923b0 1399 {
386c036b
MK
1400 int offset = gregset->r_g1_offset;
1401
1402 /* %g0 is always zero. */
1403 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1404 {
1405 if (regnum == i || regnum == -1)
1406 regcache_raw_collect (regcache, i, regs + offset);
1407 offset += 4;
1408 }
5af923b0 1409 }
386c036b
MK
1410
1411 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
5af923b0 1412 {
386c036b
MK
1413 /* Not all of the register set variants include Locals and
1414 Inputs. For those that don't, we read them off the stack. */
1415 if (gregset->r_l0_offset != -1)
1416 {
1417 int offset = gregset->r_l0_offset;
1418
1419 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1420 {
1421 if (regnum == i || regnum == -1)
1422 regcache_raw_collect (regcache, i, regs + offset);
1423 offset += 4;
1424 }
1425 }
5af923b0 1426 }
c906108c
SS
1427}
1428
c906108c 1429void
386c036b
MK
1430sparc32_supply_fpregset (struct regcache *regcache,
1431 int regnum, const void *fpregs)
c906108c 1432{
386c036b
MK
1433 const char *regs = fpregs;
1434 int i;
60054393 1435
386c036b 1436 for (i = 0; i < 32; i++)
c906108c 1437 {
386c036b
MK
1438 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1439 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
c906108c 1440 }
5af923b0 1441
386c036b
MK
1442 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1443 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
c906108c
SS
1444}
1445
386c036b
MK
1446void
1447sparc32_collect_fpregset (const struct regcache *regcache,
1448 int regnum, void *fpregs)
c906108c 1449{
386c036b
MK
1450 char *regs = fpregs;
1451 int i;
c906108c 1452
386c036b
MK
1453 for (i = 0; i < 32; i++)
1454 {
1455 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1456 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1457 }
c906108c 1458
386c036b
MK
1459 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1460 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
c906108c 1461}
c906108c 1462\f
c906108c 1463
386c036b 1464/* SunOS 4. */
c906108c 1465
386c036b
MK
1466/* From <machine/reg.h>. */
1467const struct sparc_gregset sparc32_sunos4_gregset =
c906108c 1468{
386c036b
MK
1469 0 * 4, /* %psr */
1470 1 * 4, /* %pc */
1471 2 * 4, /* %npc */
1472 3 * 4, /* %y */
1473 -1, /* %wim */
1474 -1, /* %tbr */
1475 4 * 4, /* %g1 */
1476 -1 /* %l0 */
1477};
1478\f
c906108c 1479
386c036b
MK
1480/* Provide a prototype to silence -Wmissing-prototypes. */
1481void _initialize_sparc_tdep (void);
c906108c
SS
1482
1483void
386c036b 1484_initialize_sparc_tdep (void)
c906108c 1485{
386c036b 1486 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
ef3cf062 1487}
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