Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
386c036b | 3 | Copyright 2003, 2004 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
c906108c | 22 | #include "defs.h" |
5af923b0 | 23 | #include "arch-utils.h" |
386c036b MK |
24 | #include "dis-asm.h" |
25 | #include "floatformat.h" | |
c906108c | 26 | #include "frame.h" |
386c036b MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbtypes.h" | |
c906108c | 31 | #include "inferior.h" |
386c036b MK |
32 | #include "symtab.h" |
33 | #include "objfiles.h" | |
34 | #include "osabi.h" | |
35 | #include "regcache.h" | |
c906108c SS |
36 | #include "target.h" |
37 | #include "value.h" | |
c906108c | 38 | |
43bd9a9e | 39 | #include "gdb_assert.h" |
386c036b | 40 | #include "gdb_string.h" |
c906108c | 41 | |
386c036b | 42 | #include "sparc-tdep.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
386c036b MK |
46 | /* This file implements the The SPARC 32-bit ABI as defined by the |
47 | section "Low-Level System Information" of the SPARC Compliance | |
48 | Definition (SCD) 2.4.1, which is the 32-bit System V psABI for | |
49 | SPARC. The SCD lists changes with respect to the origional 32-bit | |
50 | psABI as defined in the "System V ABI, SPARC Processor | |
51 | Supplement". | |
52 | ||
53 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
54 | BSD-based, which is sometimes (retroactively?) referred to as | |
55 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
56 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
57 | suffering from severe version number inflation). Solaris 2.x is | |
58 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
59 | 2.x is SVR4-based. */ | |
60 | ||
61 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
62 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
63 | code that can handle both. The 64-bit specific code lives in | |
64 | sparc64-tdep.c; don't add any here. */ | |
65 | ||
66 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
67 | big-endian IA-64 Quad-recision format. */ | |
68 | #define floatformat_sparc_quad floatformat_ia64_quad_big | |
69 | ||
70 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
71 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
72 | hosts, so undefine it first. */ | |
73 | #undef BIAS | |
74 | #define BIAS 2047 | |
75 | ||
76 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
77 | #define X_OP(i) (((i) >> 30) & 0x3) |
78 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
79 | #define X_A(i) (((i) >> 29) & 1) | |
80 | #define X_COND(i) (((i) >> 25) & 0xf) | |
81 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
82 | #define X_IMM22(i) ((i) & 0x3fffff) | |
83 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
c906108c | 84 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 85 | /* Sign extension macros. */ |
c906108c | 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
c906108c | 88 | |
386c036b MK |
89 | /* Fetch the instruction at PC. Instructions are always big-endian |
90 | even if the processor operates in little-endian mode. */ | |
91 | ||
92 | unsigned long | |
93 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 94 | { |
386c036b MK |
95 | unsigned char buf[4]; |
96 | unsigned long insn; | |
97 | int i; | |
98 | ||
690668cc MK |
99 | /* If we can't read the instruction at PC, return zero. */ |
100 | if (target_read_memory (pc, buf, sizeof (buf))) | |
101 | return 0; | |
c906108c | 102 | |
386c036b MK |
103 | insn = 0; |
104 | for (i = 0; i < sizeof (buf); i++) | |
105 | insn = (insn << 8) | buf[i]; | |
106 | return insn; | |
107 | } | |
108 | \f | |
109 | /* Return the contents if register REGNUM as an address. */ | |
c906108c | 110 | |
386c036b MK |
111 | static CORE_ADDR |
112 | sparc_address_from_register (int regnum) | |
113 | { | |
114 | ULONGEST addr; | |
c906108c | 115 | |
386c036b MK |
116 | regcache_cooked_read_unsigned (current_regcache, regnum, &addr); |
117 | return addr; | |
118 | } | |
119 | \f | |
c906108c | 120 | |
386c036b MK |
121 | /* The functions on this page are intended to be used to classify |
122 | function arguments. */ | |
c906108c | 123 | |
386c036b | 124 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 125 | |
386c036b MK |
126 | static int |
127 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 128 | { |
386c036b | 129 | switch (TYPE_CODE (type)) |
c906108c | 130 | { |
386c036b MK |
131 | case TYPE_CODE_INT: |
132 | case TYPE_CODE_BOOL: | |
133 | case TYPE_CODE_CHAR: | |
134 | case TYPE_CODE_ENUM: | |
135 | case TYPE_CODE_RANGE: | |
136 | { | |
137 | /* We have byte, half-word, word and extended-word/doubleword | |
138 | integral types. The doubleword is an extension to the | |
139 | origional 32-bit ABI by the SCD 2.4.x. */ | |
140 | int len = TYPE_LENGTH (type); | |
141 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
142 | } | |
143 | return 1; | |
144 | case TYPE_CODE_PTR: | |
145 | case TYPE_CODE_REF: | |
146 | { | |
147 | /* Allow either 32-bit or 64-bit pointers. */ | |
148 | int len = TYPE_LENGTH (type); | |
149 | return (len == 4 || len == 8); | |
150 | } | |
151 | return 1; | |
152 | default: | |
153 | break; | |
154 | } | |
c906108c | 155 | |
386c036b MK |
156 | return 0; |
157 | } | |
c906108c | 158 | |
386c036b | 159 | /* Check whether TYPE is "Floating". */ |
c906108c | 160 | |
386c036b MK |
161 | static int |
162 | sparc_floating_p (const struct type *type) | |
163 | { | |
164 | switch (TYPE_CODE (type)) | |
c906108c | 165 | { |
386c036b MK |
166 | case TYPE_CODE_FLT: |
167 | { | |
168 | int len = TYPE_LENGTH (type); | |
169 | return (len == 4 || len == 8 || len == 16); | |
170 | } | |
171 | default: | |
172 | break; | |
173 | } | |
174 | ||
175 | return 0; | |
176 | } | |
c906108c | 177 | |
386c036b | 178 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 179 | |
386c036b MK |
180 | static int |
181 | sparc_structure_or_union_p (const struct type *type) | |
182 | { | |
183 | switch (TYPE_CODE (type)) | |
184 | { | |
185 | case TYPE_CODE_STRUCT: | |
186 | case TYPE_CODE_UNION: | |
187 | return 1; | |
188 | default: | |
189 | break; | |
c906108c | 190 | } |
386c036b MK |
191 | |
192 | return 0; | |
c906108c | 193 | } |
386c036b MK |
194 | |
195 | /* Register information. */ | |
196 | ||
197 | static const char *sparc32_register_names[] = | |
5af923b0 | 198 | { |
386c036b MK |
199 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
200 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
201 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
202 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
203 | ||
204 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
205 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
206 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
207 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
208 | ||
209 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
210 | }; |
211 | ||
386c036b MK |
212 | /* Total number of registers. */ |
213 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 214 | |
386c036b MK |
215 | /* We provide the aliases %d0..%d30 for the floating registers as |
216 | "psuedo" registers. */ | |
217 | ||
218 | static const char *sparc32_pseudo_register_names[] = | |
219 | { | |
220 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
221 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
222 | }; | |
223 | ||
224 | /* Total number of pseudo registers. */ | |
225 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
226 | ||
227 | /* Return the name of register REGNUM. */ | |
228 | ||
229 | static const char * | |
230 | sparc32_register_name (int regnum) | |
231 | { | |
232 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
233 | return sparc32_register_names[regnum]; | |
234 | ||
235 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
236 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
237 | ||
238 | return NULL; | |
239 | } | |
240 | ||
241 | /* Return the GDB type object for the "standard" data type of data in | |
242 | register REGNUM. */ | |
243 | ||
244 | static struct type * | |
245 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
246 | { | |
247 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
248 | return builtin_type_float; | |
249 | ||
250 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
251 | return builtin_type_double; | |
252 | ||
253 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
254 | return builtin_type_void_data_ptr; | |
255 | ||
256 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
257 | return builtin_type_void_func_ptr; | |
258 | ||
259 | return builtin_type_int32; | |
260 | } | |
261 | ||
262 | static void | |
263 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
264 | struct regcache *regcache, | |
265 | int regnum, void *buf) | |
266 | { | |
267 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
268 | ||
269 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
270 | regcache_raw_read (regcache, regnum, buf); | |
271 | regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); | |
272 | } | |
273 | ||
274 | static void | |
275 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
276 | struct regcache *regcache, | |
277 | int regnum, const void *buf) | |
278 | { | |
279 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
280 | ||
281 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
282 | regcache_raw_write (regcache, regnum, buf); | |
283 | regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); | |
284 | } | |
285 | \f | |
286 | ||
287 | static CORE_ADDR | |
288 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
289 | CORE_ADDR funcaddr, int using_gcc, | |
290 | struct value **args, int nargs, | |
291 | struct type *value_type, | |
292 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
c906108c | 293 | { |
386c036b MK |
294 | *bp_addr = sp - 4; |
295 | *real_pc = funcaddr; | |
296 | ||
297 | if (using_struct_return (value_type, using_gcc)) | |
c906108c | 298 | { |
386c036b MK |
299 | char buf[4]; |
300 | ||
301 | /* This is an UNIMP instruction. */ | |
302 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
303 | write_memory (sp - 8, buf, 4); | |
304 | return sp - 8; | |
c906108c SS |
305 | } |
306 | ||
386c036b MK |
307 | return sp - 4; |
308 | } | |
309 | ||
310 | static CORE_ADDR | |
311 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
312 | struct value **args, CORE_ADDR sp, | |
313 | int struct_return, CORE_ADDR struct_addr) | |
314 | { | |
315 | /* Number of words in the "parameter array". */ | |
316 | int num_elements = 0; | |
317 | int element = 0; | |
318 | int i; | |
319 | ||
320 | for (i = 0; i < nargs; i++) | |
c906108c | 321 | { |
386c036b MK |
322 | struct type *type = VALUE_TYPE (args[i]); |
323 | int len = TYPE_LENGTH (type); | |
324 | ||
325 | if (sparc_structure_or_union_p (type) | |
326 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 327 | { |
386c036b MK |
328 | /* Structure, Union and Quad-Precision Arguments. */ |
329 | sp -= len; | |
330 | ||
331 | /* Use doubleword alignment for these values. That's always | |
332 | correct, and wasting a few bytes shouldn't be a problem. */ | |
333 | sp &= ~0x7; | |
334 | ||
335 | write_memory (sp, VALUE_CONTENTS (args[i]), len); | |
336 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); | |
337 | num_elements++; | |
338 | } | |
339 | else if (sparc_floating_p (type)) | |
340 | { | |
341 | /* Floating arguments. */ | |
342 | gdb_assert (len == 4 || len == 8); | |
343 | num_elements += (len / 4); | |
c906108c | 344 | } |
c5aa993b JM |
345 | else |
346 | { | |
386c036b MK |
347 | /* Integral and pointer arguments. */ |
348 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
349 | ||
350 | if (len < 4) | |
351 | args[i] = value_cast (builtin_type_int32, args[i]); | |
352 | num_elements += ((len + 3) / 4); | |
c5aa993b | 353 | } |
c906108c | 354 | } |
c906108c | 355 | |
386c036b MK |
356 | /* Always allocate at least six words. */ |
357 | sp -= max (6, num_elements) * 4; | |
c906108c | 358 | |
386c036b MK |
359 | /* The psABI says that "Software convention requires space for the |
360 | struct/union return value pointer, even if the word is unused." */ | |
361 | sp -= 4; | |
c906108c | 362 | |
386c036b MK |
363 | /* The psABI says that "Although software convention and the |
364 | operating system require every stack frame to be doubleword | |
365 | aligned." */ | |
366 | sp &= ~0x7; | |
c906108c | 367 | |
386c036b | 368 | for (i = 0; i < nargs; i++) |
c906108c | 369 | { |
386c036b MK |
370 | char *valbuf = VALUE_CONTENTS (args[i]); |
371 | struct type *type = VALUE_TYPE (args[i]); | |
372 | int len = TYPE_LENGTH (type); | |
c906108c | 373 | |
386c036b | 374 | gdb_assert (len == 4 || len == 8); |
c906108c | 375 | |
386c036b MK |
376 | if (element < 6) |
377 | { | |
378 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 379 | |
386c036b MK |
380 | regcache_cooked_write (regcache, regnum, valbuf); |
381 | if (len > 4 && element < 5) | |
382 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
383 | } | |
5af923b0 | 384 | |
386c036b MK |
385 | /* Always store the argument in memory. */ |
386 | write_memory (sp + 4 + element * 4, valbuf, len); | |
387 | element += len / 4; | |
388 | } | |
c906108c | 389 | |
386c036b | 390 | gdb_assert (element == num_elements); |
c906108c | 391 | |
386c036b | 392 | if (struct_return) |
c906108c | 393 | { |
386c036b | 394 | char buf[4]; |
c906108c | 395 | |
386c036b MK |
396 | store_unsigned_integer (buf, 4, struct_addr); |
397 | write_memory (sp, buf, 4); | |
398 | } | |
c906108c | 399 | |
386c036b | 400 | return sp; |
c906108c SS |
401 | } |
402 | ||
386c036b MK |
403 | static CORE_ADDR |
404 | sparc32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
405 | struct regcache *regcache, CORE_ADDR bp_addr, | |
406 | int nargs, struct value **args, CORE_ADDR sp, | |
407 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 408 | { |
386c036b MK |
409 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
410 | ||
411 | /* Set return address. */ | |
412 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
413 | ||
414 | /* Set up function arguments. */ | |
415 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
416 | struct_return, struct_addr); | |
417 | ||
418 | /* Allocate the 16-word window save area. */ | |
419 | sp -= 16 * 4; | |
c906108c | 420 | |
386c036b MK |
421 | /* Stack should be doubleword aligned at this point. */ |
422 | gdb_assert (sp % 8 == 0); | |
c906108c | 423 | |
386c036b MK |
424 | /* Finally, update the stack pointer. */ |
425 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
426 | ||
427 | return sp; | |
428 | } | |
429 | \f | |
c906108c | 430 | |
386c036b MK |
431 | /* Use the program counter to determine the contents and size of a |
432 | breakpoint instruction. Return a pointer to a string of bytes that | |
433 | encode a breakpoint instruction, store the length of the string in | |
434 | *LEN and optionally adjust *PC to point to the correct memory | |
435 | location for inserting the breakpoint. */ | |
436 | ||
437 | static const unsigned char * | |
438 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) | |
439 | { | |
440 | static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; | |
c5aa993b | 441 | |
386c036b MK |
442 | *len = sizeof (break_insn); |
443 | return break_insn; | |
c906108c | 444 | } |
386c036b | 445 | \f |
c906108c | 446 | |
386c036b | 447 | /* Allocate and initialize a frame cache. */ |
c906108c | 448 | |
386c036b MK |
449 | static struct sparc_frame_cache * |
450 | sparc_alloc_frame_cache (void) | |
451 | { | |
452 | struct sparc_frame_cache *cache; | |
453 | int i; | |
c906108c | 454 | |
386c036b | 455 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 456 | |
386c036b MK |
457 | /* Base address. */ |
458 | cache->base = 0; | |
459 | cache->pc = 0; | |
c906108c | 460 | |
386c036b MK |
461 | /* Frameless until proven otherwise. */ |
462 | cache->frameless_p = 1; | |
463 | ||
464 | cache->struct_return_p = 0; | |
465 | ||
466 | return cache; | |
467 | } | |
468 | ||
469 | CORE_ADDR | |
470 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
471 | struct sparc_frame_cache *cache) | |
c906108c | 472 | { |
386c036b MK |
473 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
474 | unsigned long insn; | |
475 | int offset = 0; | |
c906108c | 476 | int dest = -1; |
c906108c | 477 | |
386c036b MK |
478 | if (current_pc <= pc) |
479 | return current_pc; | |
480 | ||
481 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
482 | SPARC the linker usually defines a symbol (typically | |
483 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
484 | This symbol makes us end up here with PC pointing at the start of | |
485 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
486 | would do our normal prologue analysis, we would probably conclude | |
487 | that we've got a frame when in reality we don't, since the | |
488 | dynamic linker patches up the first PLT with some code that | |
489 | starts with a SAVE instruction. Patch up PC such that it points | |
490 | at the start of our PLT entry. */ | |
491 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
492 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 493 | |
386c036b MK |
494 | insn = sparc_fetch_instruction (pc); |
495 | ||
496 | /* Recognize a SETHI insn and record its destination. */ | |
497 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
498 | { |
499 | dest = X_RD (insn); | |
386c036b MK |
500 | offset += 4; |
501 | ||
502 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
503 | } |
504 | ||
386c036b MK |
505 | /* Allow for an arithmetic operation on DEST or %g1. */ |
506 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
507 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
508 | { | |
386c036b | 509 | offset += 4; |
c906108c | 510 | |
386c036b | 511 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 512 | } |
c906108c | 513 | |
386c036b MK |
514 | /* Check for the SAVE instruction that sets up the frame. */ |
515 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 516 | { |
386c036b MK |
517 | cache->frameless_p = 0; |
518 | return pc + offset + 4; | |
c906108c SS |
519 | } |
520 | ||
521 | return pc; | |
522 | } | |
523 | ||
386c036b MK |
524 | static CORE_ADDR |
525 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
526 | { | |
527 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
528 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); | |
529 | } | |
530 | ||
531 | /* Return PC of first real instruction of the function starting at | |
532 | START_PC. */ | |
f510d44e | 533 | |
386c036b MK |
534 | static CORE_ADDR |
535 | sparc32_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 536 | { |
f510d44e DM |
537 | struct symtab_and_line sal; |
538 | CORE_ADDR func_start, func_end; | |
386c036b | 539 | struct sparc_frame_cache cache; |
f510d44e DM |
540 | |
541 | /* This is the preferred method, find the end of the prologue by | |
542 | using the debugging information. */ | |
543 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
544 | { | |
545 | sal = find_pc_line (func_start, 0); | |
546 | ||
547 | if (sal.end < func_end | |
548 | && start_pc <= sal.end) | |
549 | return sal.end; | |
550 | } | |
551 | ||
386c036b | 552 | return sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
c906108c SS |
553 | } |
554 | ||
386c036b | 555 | /* Normal frames. */ |
9319a2fe | 556 | |
386c036b MK |
557 | struct sparc_frame_cache * |
558 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) | |
9319a2fe | 559 | { |
386c036b | 560 | struct sparc_frame_cache *cache; |
9319a2fe | 561 | |
386c036b MK |
562 | if (*this_cache) |
563 | return *this_cache; | |
c906108c | 564 | |
386c036b MK |
565 | cache = sparc_alloc_frame_cache (); |
566 | *this_cache = cache; | |
c906108c | 567 | |
386c036b MK |
568 | /* In priciple, for normal frames, %fp (%i6) holds the frame |
569 | pointer, which holds the base address for the current stack | |
570 | frame. */ | |
571 | ||
572 | cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
573 | if (cache->base == 0) | |
574 | return cache; | |
575 | ||
576 | cache->pc = frame_func_unwind (next_frame); | |
577 | if (cache->pc != 0) | |
c906108c | 578 | { |
386c036b MK |
579 | CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame); |
580 | sparc_analyze_prologue (cache->pc, addr_in_block, cache); | |
c906108c | 581 | } |
386c036b MK |
582 | |
583 | if (cache->frameless_p) | |
c906108c | 584 | { |
386c036b MK |
585 | /* We didn't find a valid frame, which means that CACHE->base |
586 | currently holds the frame pointer for our calling frame. */ | |
587 | cache->base = frame_unwind_register_unsigned (next_frame, | |
588 | SPARC_SP_REGNUM); | |
c906108c | 589 | } |
c906108c | 590 | |
386c036b | 591 | return cache; |
c906108c | 592 | } |
c906108c | 593 | |
386c036b MK |
594 | struct sparc_frame_cache * |
595 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 596 | { |
386c036b MK |
597 | struct sparc_frame_cache *cache; |
598 | struct symbol *sym; | |
c906108c | 599 | |
386c036b MK |
600 | if (*this_cache) |
601 | return *this_cache; | |
c906108c | 602 | |
386c036b | 603 | cache = sparc_frame_cache (next_frame, this_cache); |
c906108c | 604 | |
386c036b MK |
605 | sym = find_pc_function (cache->pc); |
606 | if (sym) | |
c906108c | 607 | { |
386c036b MK |
608 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); |
609 | enum type_code code = TYPE_CODE (type); | |
610 | ||
611 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
612 | { | |
613 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
614 | if (sparc_structure_or_union_p (type) | |
615 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
616 | cache->struct_return_p = 1; | |
617 | } | |
c906108c SS |
618 | } |
619 | ||
386c036b MK |
620 | return cache; |
621 | } | |
622 | ||
623 | static void | |
624 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
625 | struct frame_id *this_id) | |
626 | { | |
627 | struct sparc_frame_cache *cache = | |
628 | sparc32_frame_cache (next_frame, this_cache); | |
629 | ||
630 | /* This marks the outermost frame. */ | |
631 | if (cache->base == 0) | |
632 | return; | |
633 | ||
634 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
635 | } | |
c906108c | 636 | |
386c036b MK |
637 | static void |
638 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
639 | int regnum, int *optimizedp, | |
640 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
641 | int *realnump, void *valuep) | |
642 | { | |
643 | struct sparc_frame_cache *cache = | |
644 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 645 | |
386c036b | 646 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 647 | { |
386c036b MK |
648 | *optimizedp = 0; |
649 | *lvalp = not_lval; | |
650 | *addrp = 0; | |
651 | *realnump = -1; | |
652 | if (valuep) | |
c906108c | 653 | { |
386c036b MK |
654 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
655 | ||
656 | /* If this functions has a Structure, Union or | |
657 | Quad-Precision return value, we have to skip the UNIMP | |
658 | instruction that encodes the size of the structure. */ | |
659 | if (cache->struct_return_p) | |
660 | pc += 4; | |
661 | ||
662 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
663 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
664 | store_unsigned_integer (valuep, 4, pc); | |
c906108c | 665 | } |
c906108c SS |
666 | return; |
667 | } | |
668 | ||
386c036b MK |
669 | /* The previous frame's `local' and `in' registers have been saved |
670 | in the register save area. */ | |
671 | if (!cache->frameless_p | |
672 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 673 | { |
386c036b MK |
674 | *optimizedp = 0; |
675 | *lvalp = lval_memory; | |
676 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
677 | *realnump = -1; | |
678 | if (valuep) | |
c906108c | 679 | { |
386c036b MK |
680 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
681 | ||
682 | /* Read the value in from memory. */ | |
683 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
c906108c | 684 | } |
386c036b MK |
685 | return; |
686 | } | |
c906108c | 687 | |
386c036b MK |
688 | /* The previous frame's `out' registers are accessable as the |
689 | current frame's `in' registers. */ | |
690 | if (!cache->frameless_p | |
691 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
692 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 693 | |
386c036b MK |
694 | frame_register_unwind (next_frame, regnum, |
695 | optimizedp, lvalp, addrp, realnump, valuep); | |
696 | } | |
c906108c | 697 | |
386c036b MK |
698 | static const struct frame_unwind sparc32_frame_unwind = |
699 | { | |
700 | NORMAL_FRAME, | |
701 | sparc32_frame_this_id, | |
702 | sparc32_frame_prev_register | |
703 | }; | |
704 | ||
705 | static const struct frame_unwind * | |
706 | sparc32_frame_sniffer (struct frame_info *next_frame) | |
707 | { | |
708 | return &sparc32_frame_unwind; | |
c906108c | 709 | } |
386c036b | 710 | \f |
c906108c | 711 | |
386c036b MK |
712 | static CORE_ADDR |
713 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
714 | { | |
715 | struct sparc_frame_cache *cache = | |
716 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 717 | |
386c036b MK |
718 | return cache->base; |
719 | } | |
c906108c | 720 | |
386c036b MK |
721 | static const struct frame_base sparc32_frame_base = |
722 | { | |
723 | &sparc32_frame_unwind, | |
724 | sparc32_frame_base_address, | |
725 | sparc32_frame_base_address, | |
726 | sparc32_frame_base_address | |
727 | }; | |
c906108c | 728 | |
386c036b MK |
729 | static struct frame_id |
730 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
731 | { | |
732 | CORE_ADDR sp; | |
5af923b0 | 733 | |
386c036b MK |
734 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
735 | return frame_id_build (sp, frame_pc_unwind (next_frame)); | |
736 | } | |
737 | \f | |
c906108c | 738 | |
386c036b MK |
739 | /* Extract from an array REGBUF containing the (raw) register state, a |
740 | function return value of TYPE, and copy that into VALBUF. */ | |
5af923b0 | 741 | |
386c036b MK |
742 | static void |
743 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
744 | void *valbuf) | |
745 | { | |
746 | int len = TYPE_LENGTH (type); | |
747 | char buf[8]; | |
c906108c | 748 | |
386c036b MK |
749 | gdb_assert (!sparc_structure_or_union_p (type)); |
750 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 751 | |
386c036b | 752 | if (sparc_floating_p (type)) |
5af923b0 | 753 | { |
386c036b MK |
754 | /* Floating return values. */ |
755 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
756 | if (len > 4) | |
757 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
758 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
759 | } |
760 | else | |
761 | { | |
386c036b MK |
762 | /* Integral and pointer return values. */ |
763 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 764 | |
386c036b MK |
765 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
766 | if (len > 4) | |
767 | { | |
768 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
769 | gdb_assert (len == 8); | |
770 | memcpy (valbuf, buf, 8); | |
771 | } | |
772 | else | |
773 | { | |
774 | /* Just stripping off any unused bytes should preserve the | |
775 | signed-ness just fine. */ | |
776 | memcpy (valbuf, buf + 4 - len, len); | |
777 | } | |
778 | } | |
779 | } | |
c906108c | 780 | |
386c036b MK |
781 | /* Write into the appropriate registers a function return value stored |
782 | in VALBUF of type TYPE. */ | |
c906108c | 783 | |
386c036b MK |
784 | static void |
785 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
786 | const void *valbuf) | |
787 | { | |
788 | int len = TYPE_LENGTH (type); | |
789 | char buf[8]; | |
c906108c | 790 | |
386c036b MK |
791 | gdb_assert (!sparc_structure_or_union_p (type)); |
792 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 793 | |
386c036b MK |
794 | if (sparc_floating_p (type)) |
795 | { | |
796 | /* Floating return values. */ | |
797 | memcpy (buf, valbuf, len); | |
798 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
799 | if (len > 4) | |
800 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
801 | } | |
802 | else | |
c906108c | 803 | { |
386c036b MK |
804 | /* Integral and pointer return values. */ |
805 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
806 | ||
807 | if (len > 4) | |
2757dd86 | 808 | { |
386c036b MK |
809 | gdb_assert (len == 8); |
810 | memcpy (buf, valbuf, 8); | |
811 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
812 | } |
813 | else | |
814 | { | |
386c036b MK |
815 | /* ??? Do we need to do any sign-extension here? */ |
816 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 817 | } |
386c036b | 818 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
819 | } |
820 | } | |
821 | ||
b9d4c5ed MK |
822 | static enum return_value_convention |
823 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, | |
824 | struct regcache *regcache, void *readbuf, | |
825 | const void *writebuf) | |
826 | { | |
827 | if (sparc_structure_or_union_p (type) | |
828 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
829 | return RETURN_VALUE_STRUCT_CONVENTION; | |
830 | ||
831 | if (readbuf) | |
832 | sparc32_extract_return_value (type, regcache, readbuf); | |
833 | if (writebuf) | |
834 | sparc32_store_return_value (type, regcache, writebuf); | |
835 | ||
836 | return RETURN_VALUE_REGISTER_CONVENTION; | |
837 | } | |
838 | ||
931aecf5 AC |
839 | #if 0 |
840 | /* NOTE: cagney/2004-01-17: For the moment disable this method. The | |
841 | architecture and CORE-gdb will need new code (and a replacement for | |
74055713 AC |
842 | DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS) before this can be made to |
843 | work robustly. Here is a possible function signature: */ | |
931aecf5 AC |
844 | /* NOTE: cagney/2004-01-17: So far only the 32-bit SPARC ABI has been |
845 | identifed as having a way to robustly recover the address of a | |
846 | struct-convention return-value (after the function has returned). | |
847 | For all other ABIs so far examined, the calling convention makes no | |
848 | guarenteed that the register containing the return-value will be | |
849 | preserved and hence that the return-value's address can be | |
850 | recovered. */ | |
386c036b MK |
851 | /* Extract from REGCACHE, which contains the (raw) register state, the |
852 | address in which a function should return its structure value, as a | |
853 | CORE_ADDR. */ | |
c906108c | 854 | |
386c036b | 855 | static CORE_ADDR |
ca9d58e9 | 856 | sparc32_extract_struct_value_address (struct regcache *regcache) |
386c036b | 857 | { |
9515395e | 858 | ULONGEST sp; |
c906108c | 859 | |
9515395e MK |
860 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
861 | return read_memory_unsigned_integer (sp + 64, 4); | |
386c036b | 862 | } |
931aecf5 | 863 | #endif |
c906108c | 864 | |
386c036b MK |
865 | static int |
866 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 867 | { |
386c036b MK |
868 | return (sparc_structure_or_union_p (type) |
869 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
870 | } | |
c906108c | 871 | |
386c036b MK |
872 | \f |
873 | /* The SPARC Architecture doesn't have hardware single-step support, | |
874 | and most operating systems don't implement it either, so we provide | |
875 | software single-step mechanism. */ | |
c906108c | 876 | |
386c036b MK |
877 | static CORE_ADDR |
878 | sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc) | |
879 | { | |
880 | unsigned long insn = sparc_fetch_instruction (pc); | |
881 | int conditional_p = X_COND (insn) & 0x7; | |
882 | int branch_p = 0; | |
883 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 884 | |
386c036b | 885 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 886 | { |
386c036b MK |
887 | /* Branch on Integer Register with Prediction (BPr). */ |
888 | branch_p = 1; | |
889 | conditional_p = 1; | |
c906108c | 890 | } |
386c036b | 891 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 892 | { |
386c036b MK |
893 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
894 | branch_p = 1; | |
895 | offset = 4 * X_DISP22 (insn); | |
c906108c | 896 | } |
386c036b MK |
897 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
898 | { | |
899 | /* Branch on Floating-Point Condition Codes with Prediction | |
900 | (FBPfcc). */ | |
901 | branch_p = 1; | |
902 | offset = 4 * X_DISP19 (insn); | |
903 | } | |
904 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
905 | { | |
906 | /* Branch on Integer Condition Codes (Bicc). */ | |
907 | branch_p = 1; | |
908 | offset = 4 * X_DISP22 (insn); | |
909 | } | |
910 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 911 | { |
386c036b MK |
912 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
913 | branch_p = 1; | |
914 | offset = 4 * X_DISP19 (insn); | |
c906108c | 915 | } |
386c036b MK |
916 | |
917 | /* FIXME: Handle DONE and RETRY instructions. */ | |
918 | ||
919 | /* FIXME: Handle the Trap instruction. */ | |
920 | ||
921 | if (branch_p) | |
c906108c | 922 | { |
386c036b | 923 | if (conditional_p) |
c906108c | 924 | { |
386c036b MK |
925 | /* For conditional branches, return nPC + 4 iff the annul |
926 | bit is 1. */ | |
927 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
928 | } |
929 | else | |
930 | { | |
386c036b MK |
931 | /* For unconditional branches, return the target if its |
932 | specified condition is "always" and return nPC + 4 if the | |
933 | condition is "never". If the annul bit is 1, set *NPC to | |
934 | zero. */ | |
935 | if (X_COND (insn) == 0x0) | |
936 | pc = *npc, offset = 4; | |
937 | if (X_A (insn)) | |
938 | *npc = 0; | |
939 | ||
940 | gdb_assert (offset != 0); | |
941 | return pc + offset; | |
c906108c SS |
942 | } |
943 | } | |
386c036b MK |
944 | |
945 | return 0; | |
c906108c SS |
946 | } |
947 | ||
386c036b MK |
948 | void |
949 | sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
950 | { | |
951 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
952 | static CORE_ADDR npc, nnpc; | |
953 | static char npc_save[4], nnpc_save[4]; | |
c906108c | 954 | |
386c036b MK |
955 | if (insert_breakpoints_p) |
956 | { | |
957 | CORE_ADDR pc; | |
c906108c | 958 | |
386c036b MK |
959 | pc = sparc_address_from_register (tdep->pc_regnum); |
960 | npc = sparc_address_from_register (tdep->npc_regnum); | |
c906108c | 961 | |
386c036b MK |
962 | /* Analyze the instruction at PC. */ |
963 | nnpc = sparc_analyze_control_transfer (pc, &npc); | |
964 | if (npc != 0) | |
965 | target_insert_breakpoint (npc, npc_save); | |
966 | if (nnpc != 0) | |
967 | target_insert_breakpoint (nnpc, nnpc_save); | |
c906108c | 968 | |
386c036b MK |
969 | /* Assert that we have set at least one breakpoint, and that |
970 | they're not set at the same spot. */ | |
971 | gdb_assert (npc != 0 || nnpc != 0); | |
972 | gdb_assert (nnpc != npc); | |
60054393 | 973 | } |
386c036b | 974 | else |
c906108c | 975 | { |
386c036b MK |
976 | if (npc != 0) |
977 | target_remove_breakpoint (npc, npc_save); | |
978 | if (nnpc != 0) | |
979 | target_remove_breakpoint (nnpc, nnpc_save); | |
c906108c | 980 | } |
386c036b MK |
981 | } |
982 | ||
983 | static void | |
984 | sparc_write_pc (CORE_ADDR pc, ptid_t ptid) | |
985 | { | |
986 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
987 | ||
988 | write_register_pid (tdep->pc_regnum, pc, ptid); | |
989 | write_register_pid (tdep->npc_regnum, pc + 4, ptid); | |
990 | } | |
991 | \f | |
992 | /* Unglobalize NAME. */ | |
993 | ||
994 | char * | |
995 | sparc_stabs_unglobalize_name (char *name) | |
996 | { | |
997 | /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop, | |
998 | SunPRO) convert file static variables into global values, a | |
999 | process known as globalization. In order to do this, the | |
1000 | compiler will create a unique prefix and prepend it to each file | |
1001 | static variable. For static variables within a function, this | |
1002 | globalization prefix is followed by the function name (nested | |
1003 | static variables within a function are supposed to generate a | |
1004 | warning message, and are left alone). The procedure is | |
1005 | documented in the Stabs Interface Manual, which is distrubuted | |
1006 | with the compilers, although version 4.0 of the manual seems to | |
1007 | be incorrect in some places, at least for SPARC. The | |
1008 | globalization prefix is encoded into an N_OPT stab, with the form | |
1009 | "G=<prefix>". The globalization prefix always seems to start | |
1010 | with a dollar sign '$'; a dot '.' is used as a seperator. So we | |
1011 | simply strip everything up until the last dot. */ | |
c906108c | 1012 | |
386c036b | 1013 | if (name[0] == '$') |
c906108c | 1014 | { |
386c036b MK |
1015 | char *p = strrchr (name, '.'); |
1016 | if (p) | |
1017 | return p + 1; | |
c906108c | 1018 | } |
c906108c | 1019 | |
386c036b MK |
1020 | return name; |
1021 | } | |
1022 | \f | |
5af923b0 | 1023 | |
a54124c5 MK |
1024 | /* Return the appropriate register set for the core section identified |
1025 | by SECT_NAME and SECT_SIZE. */ | |
1026 | ||
1027 | const struct regset * | |
1028 | sparc_regset_from_core_section (struct gdbarch *gdbarch, | |
1029 | const char *sect_name, size_t sect_size) | |
1030 | { | |
1031 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1032 | ||
c558d81a | 1033 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1034 | return tdep->gregset; |
1035 | ||
c558d81a | 1036 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1037 | return tdep->fpregset; |
1038 | ||
1039 | return NULL; | |
1040 | } | |
1041 | \f | |
1042 | ||
386c036b MK |
1043 | static struct gdbarch * |
1044 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1045 | { | |
1046 | struct gdbarch_tdep *tdep; | |
1047 | struct gdbarch *gdbarch; | |
c906108c | 1048 | |
386c036b MK |
1049 | /* If there is already a candidate, use it. */ |
1050 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1051 | if (arches != NULL) | |
1052 | return arches->gdbarch; | |
c906108c | 1053 | |
386c036b MK |
1054 | /* Allocate space for the new architecture. */ |
1055 | tdep = XMALLOC (struct gdbarch_tdep); | |
1056 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1057 | |
386c036b MK |
1058 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1059 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
a54124c5 | 1060 | tdep->gregset = NULL; |
c558d81a | 1061 | tdep->sizeof_gregset = 0; |
a54124c5 | 1062 | tdep->fpregset = NULL; |
c558d81a | 1063 | tdep->sizeof_fpregset = 0; |
386c036b MK |
1064 | tdep->plt_entry_size = 0; |
1065 | ||
1066 | set_gdbarch_long_double_bit (gdbarch, 128); | |
1067 | set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad); | |
1068 | ||
1069 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1070 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1071 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1072 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1073 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1074 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1075 | ||
1076 | /* Register numbers of various important registers. */ | |
1077 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1078 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1079 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1080 | ||
1081 | /* Call dummy code. */ | |
1082 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1083 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1084 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1085 | ||
b9d4c5ed | 1086 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1087 | set_gdbarch_stabs_argument_has_addr |
1088 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1089 | ||
1090 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1091 | ||
1092 | /* Stack grows downward. */ | |
1093 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1094 | |
386c036b | 1095 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1096 | |
386c036b | 1097 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1098 | |
386c036b | 1099 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1100 | |
386c036b MK |
1101 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1102 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1103 | |
386c036b | 1104 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
c906108c | 1105 | |
386c036b | 1106 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1107 | |
386c036b MK |
1108 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1109 | ||
1110 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
1111 | gdbarch_init_osabi (info, gdbarch); | |
c906108c | 1112 | |
386c036b | 1113 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
c906108c | 1114 | |
a54124c5 | 1115 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1116 | if (tdep->gregset) |
a54124c5 MK |
1117 | set_gdbarch_regset_from_core_section (gdbarch, |
1118 | sparc_regset_from_core_section); | |
1119 | ||
386c036b MK |
1120 | return gdbarch; |
1121 | } | |
1122 | \f | |
1123 | /* Helper functions for dealing with register windows. */ | |
1124 | ||
1125 | void | |
1126 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1127 | { |
386c036b MK |
1128 | int offset = 0; |
1129 | char buf[8]; | |
1130 | int i; | |
1131 | ||
1132 | if (sp & 1) | |
1133 | { | |
1134 | /* Registers are 64-bit. */ | |
1135 | sp += BIAS; | |
c906108c | 1136 | |
386c036b MK |
1137 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1138 | { | |
1139 | if (regnum == i || regnum == -1) | |
1140 | { | |
1141 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
1142 | regcache_raw_supply (regcache, i, buf); | |
1143 | } | |
1144 | } | |
1145 | } | |
1146 | else | |
c906108c | 1147 | { |
386c036b MK |
1148 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1149 | pointer. */ | |
1150 | sp &= 0xffffffffUL; | |
c906108c | 1151 | |
386c036b MK |
1152 | /* Clear out the top half of the temporary buffer, and put the |
1153 | register value in the bottom half if we're in 64-bit mode. */ | |
1154 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
c906108c | 1155 | { |
386c036b MK |
1156 | memset (buf, 0, 4); |
1157 | offset = 4; | |
1158 | } | |
c906108c | 1159 | |
386c036b MK |
1160 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1161 | { | |
1162 | if (regnum == i || regnum == -1) | |
1163 | { | |
1164 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1165 | buf + offset, 4); | |
1166 | regcache_raw_supply (regcache, i, buf); | |
1167 | } | |
c906108c SS |
1168 | } |
1169 | } | |
c906108c | 1170 | } |
c906108c SS |
1171 | |
1172 | void | |
386c036b MK |
1173 | sparc_collect_rwindow (const struct regcache *regcache, |
1174 | CORE_ADDR sp, int regnum) | |
c906108c | 1175 | { |
386c036b MK |
1176 | int offset = 0; |
1177 | char buf[8]; | |
1178 | int i; | |
5af923b0 | 1179 | |
386c036b | 1180 | if (sp & 1) |
5af923b0 | 1181 | { |
386c036b MK |
1182 | /* Registers are 64-bit. */ |
1183 | sp += BIAS; | |
c906108c | 1184 | |
386c036b MK |
1185 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1186 | { | |
1187 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1188 | { | |
1189 | regcache_raw_collect (regcache, i, buf); | |
1190 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
1191 | } | |
1192 | } | |
5af923b0 MS |
1193 | } |
1194 | else | |
1195 | { | |
386c036b MK |
1196 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1197 | pointer. */ | |
1198 | sp &= 0xffffffffUL; | |
1199 | ||
1200 | /* Only use the bottom half if we're in 64-bit mode. */ | |
1201 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1202 | offset = 4; | |
1203 | ||
1204 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1205 | { | |
1206 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1207 | { | |
1208 | regcache_raw_collect (regcache, i, buf); | |
1209 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1210 | buf + offset, 4); | |
1211 | } | |
1212 | } | |
5af923b0 | 1213 | } |
c906108c SS |
1214 | } |
1215 | ||
386c036b MK |
1216 | /* Helper functions for dealing with register sets. */ |
1217 | ||
c906108c | 1218 | void |
386c036b MK |
1219 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1220 | struct regcache *regcache, | |
1221 | int regnum, const void *gregs) | |
c906108c | 1222 | { |
386c036b MK |
1223 | const char *regs = gregs; |
1224 | int i; | |
5af923b0 | 1225 | |
386c036b MK |
1226 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1227 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1228 | regs + gregset->r_psr_offset); | |
c906108c | 1229 | |
386c036b MK |
1230 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1231 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1232 | regs + gregset->r_pc_offset); | |
5af923b0 | 1233 | |
386c036b MK |
1234 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1235 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1236 | regs + gregset->r_npc_offset); | |
5af923b0 | 1237 | |
386c036b MK |
1238 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1239 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1240 | regs + gregset->r_y_offset); | |
5af923b0 | 1241 | |
386c036b MK |
1242 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1243 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1244 | |
386c036b | 1245 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1246 | { |
386c036b MK |
1247 | int offset = gregset->r_g1_offset; |
1248 | ||
1249 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1250 | { | |
1251 | if (regnum == i || regnum == -1) | |
1252 | regcache_raw_supply (regcache, i, regs + offset); | |
1253 | offset += 4; | |
1254 | } | |
c906108c | 1255 | } |
386c036b MK |
1256 | |
1257 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1258 | { |
386c036b MK |
1259 | /* Not all of the register set variants include Locals and |
1260 | Inputs. For those that don't, we read them off the stack. */ | |
1261 | if (gregset->r_l0_offset == -1) | |
1262 | { | |
1263 | ULONGEST sp; | |
1264 | ||
1265 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1266 | sparc_supply_rwindow (regcache, sp, regnum); | |
1267 | } | |
1268 | else | |
1269 | { | |
1270 | int offset = gregset->r_l0_offset; | |
1271 | ||
1272 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1273 | { | |
1274 | if (regnum == i || regnum == -1) | |
1275 | regcache_raw_supply (regcache, i, regs + offset); | |
1276 | offset += 4; | |
1277 | } | |
1278 | } | |
c906108c SS |
1279 | } |
1280 | } | |
1281 | ||
c5aa993b | 1282 | void |
386c036b MK |
1283 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1284 | const struct regcache *regcache, | |
1285 | int regnum, void *gregs) | |
c906108c | 1286 | { |
386c036b MK |
1287 | char *regs = gregs; |
1288 | int i; | |
c5aa993b | 1289 | |
386c036b MK |
1290 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1291 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1292 | regs + gregset->r_psr_offset); | |
60054393 | 1293 | |
386c036b MK |
1294 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1295 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1296 | regs + gregset->r_pc_offset); | |
1297 | ||
1298 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1299 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1300 | regs + gregset->r_npc_offset); | |
5af923b0 | 1301 | |
386c036b MK |
1302 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1303 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1304 | regs + gregset->r_y_offset); | |
1305 | ||
1306 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1307 | { |
386c036b MK |
1308 | int offset = gregset->r_g1_offset; |
1309 | ||
1310 | /* %g0 is always zero. */ | |
1311 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1312 | { | |
1313 | if (regnum == i || regnum == -1) | |
1314 | regcache_raw_collect (regcache, i, regs + offset); | |
1315 | offset += 4; | |
1316 | } | |
5af923b0 | 1317 | } |
386c036b MK |
1318 | |
1319 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1320 | { |
386c036b MK |
1321 | /* Not all of the register set variants include Locals and |
1322 | Inputs. For those that don't, we read them off the stack. */ | |
1323 | if (gregset->r_l0_offset != -1) | |
1324 | { | |
1325 | int offset = gregset->r_l0_offset; | |
1326 | ||
1327 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1328 | { | |
1329 | if (regnum == i || regnum == -1) | |
1330 | regcache_raw_collect (regcache, i, regs + offset); | |
1331 | offset += 4; | |
1332 | } | |
1333 | } | |
5af923b0 | 1334 | } |
c906108c SS |
1335 | } |
1336 | ||
c906108c | 1337 | void |
386c036b MK |
1338 | sparc32_supply_fpregset (struct regcache *regcache, |
1339 | int regnum, const void *fpregs) | |
c906108c | 1340 | { |
386c036b MK |
1341 | const char *regs = fpregs; |
1342 | int i; | |
60054393 | 1343 | |
386c036b | 1344 | for (i = 0; i < 32; i++) |
c906108c | 1345 | { |
386c036b MK |
1346 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1347 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1348 | } |
5af923b0 | 1349 | |
386c036b MK |
1350 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1351 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1352 | } |
1353 | ||
386c036b MK |
1354 | void |
1355 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1356 | int regnum, void *fpregs) | |
c906108c | 1357 | { |
386c036b MK |
1358 | char *regs = fpregs; |
1359 | int i; | |
c906108c | 1360 | |
386c036b MK |
1361 | for (i = 0; i < 32; i++) |
1362 | { | |
1363 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1364 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1365 | } | |
c906108c | 1366 | |
386c036b MK |
1367 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1368 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1369 | } |
c906108c | 1370 | \f |
c906108c | 1371 | |
386c036b | 1372 | /* SunOS 4. */ |
c906108c | 1373 | |
386c036b MK |
1374 | /* From <machine/reg.h>. */ |
1375 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1376 | { |
386c036b MK |
1377 | 0 * 4, /* %psr */ |
1378 | 1 * 4, /* %pc */ | |
1379 | 2 * 4, /* %npc */ | |
1380 | 3 * 4, /* %y */ | |
1381 | -1, /* %wim */ | |
1382 | -1, /* %tbr */ | |
1383 | 4 * 4, /* %g1 */ | |
1384 | -1 /* %l0 */ | |
1385 | }; | |
1386 | \f | |
c906108c | 1387 | |
386c036b MK |
1388 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1389 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1390 | |
1391 | void | |
386c036b | 1392 | _initialize_sparc_tdep (void) |
c906108c | 1393 | { |
386c036b | 1394 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 1395 | } |