Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
61baf725 | 3 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
b41c5a85 | 23 | #include "dwarf2.h" |
f5a9b87d | 24 | #include "dwarf2-frame.h" |
386c036b | 25 | #include "floatformat.h" |
c906108c | 26 | #include "frame.h" |
386c036b MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbtypes.h" | |
c906108c | 31 | #include "inferior.h" |
386c036b MK |
32 | #include "symtab.h" |
33 | #include "objfiles.h" | |
34 | #include "osabi.h" | |
35 | #include "regcache.h" | |
c906108c | 36 | #include "target.h" |
3f7b46f2 | 37 | #include "target-descriptions.h" |
c906108c | 38 | #include "value.h" |
c906108c | 39 | |
386c036b | 40 | #include "sparc-tdep.h" |
e6f9c00b | 41 | #include "sparc-ravenscar-thread.h" |
325fac50 | 42 | #include <algorithm> |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
9eb42ed1 MK |
46 | /* This file implements the SPARC 32-bit ABI as defined by the section |
47 | "Low-Level System Information" of the SPARC Compliance Definition | |
48 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 49 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 50 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
51 | |
52 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
53 | BSD-based, which is sometimes (retroactively?) referred to as | |
54 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
55 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
56 | suffering from severe version number inflation). Solaris 2.x is | |
57 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
58 | 2.x is SVR4-based. */ | |
59 | ||
60 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
61 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
62 | code that can handle both. The 64-bit specific code lives in | |
63 | sparc64-tdep.c; don't add any here. */ | |
64 | ||
65 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 66 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 67 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
68 | |
69 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
70 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
71 | hosts, so undefine it first. */ | |
72 | #undef BIAS | |
73 | #define BIAS 2047 | |
74 | ||
75 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
76 | #define X_OP(i) (((i) >> 30) & 0x3) |
77 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
78 | #define X_A(i) (((i) >> 29) & 1) | |
79 | #define X_COND(i) (((i) >> 25) & 0xf) | |
80 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
81 | #define X_IMM22(i) ((i) & 0x3fffff) | |
82 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 83 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 84 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 89 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 90 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
91 | /* Macros to identify some instructions. */ |
92 | /* RETURN (RETT in V8) */ | |
93 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 94 | |
386c036b MK |
95 | /* Fetch the instruction at PC. Instructions are always big-endian |
96 | even if the processor operates in little-endian mode. */ | |
97 | ||
98 | unsigned long | |
99 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 100 | { |
e1613aba | 101 | gdb_byte buf[4]; |
386c036b MK |
102 | unsigned long insn; |
103 | int i; | |
104 | ||
690668cc | 105 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 106 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 107 | return 0; |
c906108c | 108 | |
386c036b MK |
109 | insn = 0; |
110 | for (i = 0; i < sizeof (buf); i++) | |
111 | insn = (insn << 8) | buf[i]; | |
112 | return insn; | |
113 | } | |
42cdca6c MK |
114 | \f |
115 | ||
5465445a JB |
116 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
117 | instruction. */ | |
118 | ||
119 | static int | |
120 | sparc_is_unimp_insn (CORE_ADDR pc) | |
121 | { | |
122 | const unsigned long insn = sparc_fetch_instruction (pc); | |
123 | ||
124 | return ((insn & 0xc1c00000) == 0); | |
125 | } | |
126 | ||
d0b5971a JM |
127 | /* Return non-zero if the instruction corresponding to PC is an |
128 | "annulled" branch, i.e. the annul bit is set. */ | |
129 | ||
130 | int | |
131 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
132 | { | |
133 | /* The branch instructions featuring an annul bit can be identified | |
134 | by the following bit patterns: | |
135 | ||
136 | OP=0 | |
137 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
138 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
139 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
140 | OP2=6: Branch on FP Condition Codes (FBcc). | |
141 | OP2=3 && Bit28=0: | |
142 | Branch on Integer Register with Prediction (BPr). | |
143 | ||
144 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
145 | coprocessor branch instructions (Op2=7). */ | |
146 | ||
147 | const unsigned long insn = sparc_fetch_instruction (pc); | |
148 | const unsigned op2 = X_OP2 (insn); | |
149 | ||
150 | if ((X_OP (insn) == 0) | |
151 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
152 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
153 | return X_A (insn); | |
154 | else | |
155 | return 0; | |
156 | } | |
157 | ||
42cdca6c MK |
158 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
159 | website http://stackghost.cerias.purdue.edu "... transparently and | |
160 | automatically protects applications' stack frames; more | |
161 | specifically, it guards the return pointers. The protection | |
162 | mechanisms require no application source or binary modification and | |
163 | imposes only a negligible performance penalty." | |
164 | ||
165 | The same website provides the following description of how | |
166 | StackGhost works: | |
167 | ||
168 | "StackGhost interfaces with the kernel trap handler that would | |
169 | normally write out registers to the stack and the handler that | |
170 | would read them back in. By XORing a cookie into the | |
171 | return-address saved in the user stack when it is actually written | |
172 | to the stack, and then XOR it out when the return-address is pulled | |
173 | from the stack, StackGhost can cause attacker corrupted return | |
174 | pointers to behave in a manner the attacker cannot predict. | |
175 | StackGhost can also use several unused bits in the return pointer | |
176 | to detect a smashed return pointer and abort the process." | |
177 | ||
178 | For GDB this means that whenever we're reading %i7 from a stack | |
179 | frame's window save area, we'll have to XOR the cookie. | |
180 | ||
181 | More information on StackGuard can be found on in: | |
182 | ||
c378eb4e | 183 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
184 | Stack Protection." 2001. Published in USENIX Security Symposium |
185 | '01. */ | |
186 | ||
187 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
188 | ||
189 | ULONGEST | |
e17a4113 | 190 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 191 | { |
e17a4113 | 192 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 193 | struct target_ops *ops = ¤t_target; |
e1613aba | 194 | gdb_byte buf[8]; |
baf92889 MK |
195 | int len; |
196 | ||
13547ab6 | 197 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
198 | if (len == -1) |
199 | return 0; | |
42cdca6c | 200 | |
baf92889 MK |
201 | /* We should have either an 32-bit or an 64-bit cookie. */ |
202 | gdb_assert (len == 4 || len == 8); | |
203 | ||
e17a4113 | 204 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 205 | } |
386c036b | 206 | \f |
baf92889 | 207 | |
386c036b MK |
208 | /* The functions on this page are intended to be used to classify |
209 | function arguments. */ | |
c906108c | 210 | |
386c036b | 211 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 212 | |
386c036b MK |
213 | static int |
214 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 215 | { |
80ad1639 MK |
216 | int len = TYPE_LENGTH (type); |
217 | ||
386c036b | 218 | switch (TYPE_CODE (type)) |
c906108c | 219 | { |
386c036b MK |
220 | case TYPE_CODE_INT: |
221 | case TYPE_CODE_BOOL: | |
222 | case TYPE_CODE_CHAR: | |
223 | case TYPE_CODE_ENUM: | |
224 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
225 | /* We have byte, half-word, word and extended-word/doubleword |
226 | integral types. The doubleword is an extension to the | |
227 | original 32-bit ABI by the SCD 2.4.x. */ | |
228 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
229 | case TYPE_CODE_PTR: |
230 | case TYPE_CODE_REF: | |
aa006118 | 231 | case TYPE_CODE_RVALUE_REF: |
80ad1639 MK |
232 | /* Allow either 32-bit or 64-bit pointers. */ |
233 | return (len == 4 || len == 8); | |
386c036b MK |
234 | default: |
235 | break; | |
236 | } | |
c906108c | 237 | |
386c036b MK |
238 | return 0; |
239 | } | |
c906108c | 240 | |
386c036b | 241 | /* Check whether TYPE is "Floating". */ |
c906108c | 242 | |
386c036b MK |
243 | static int |
244 | sparc_floating_p (const struct type *type) | |
245 | { | |
246 | switch (TYPE_CODE (type)) | |
c906108c | 247 | { |
386c036b MK |
248 | case TYPE_CODE_FLT: |
249 | { | |
250 | int len = TYPE_LENGTH (type); | |
251 | return (len == 4 || len == 8 || len == 16); | |
252 | } | |
253 | default: | |
254 | break; | |
255 | } | |
256 | ||
257 | return 0; | |
258 | } | |
c906108c | 259 | |
fe10a582 DM |
260 | /* Check whether TYPE is "Complex Floating". */ |
261 | ||
262 | static int | |
263 | sparc_complex_floating_p (const struct type *type) | |
264 | { | |
265 | switch (TYPE_CODE (type)) | |
266 | { | |
267 | case TYPE_CODE_COMPLEX: | |
268 | { | |
269 | int len = TYPE_LENGTH (type); | |
270 | return (len == 8 || len == 16 || len == 32); | |
271 | } | |
272 | default: | |
273 | break; | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
0497f5b0 JB |
279 | /* Check whether TYPE is "Structure or Union". |
280 | ||
281 | In terms of Ada subprogram calls, arrays are treated the same as | |
282 | struct and union types. So this function also returns non-zero | |
283 | for array types. */ | |
c906108c | 284 | |
386c036b MK |
285 | static int |
286 | sparc_structure_or_union_p (const struct type *type) | |
287 | { | |
288 | switch (TYPE_CODE (type)) | |
289 | { | |
290 | case TYPE_CODE_STRUCT: | |
291 | case TYPE_CODE_UNION: | |
0497f5b0 | 292 | case TYPE_CODE_ARRAY: |
386c036b MK |
293 | return 1; |
294 | default: | |
295 | break; | |
c906108c | 296 | } |
386c036b MK |
297 | |
298 | return 0; | |
c906108c | 299 | } |
386c036b MK |
300 | |
301 | /* Register information. */ | |
7a36499a IR |
302 | #define SPARC32_FPU_REGISTERS \ |
303 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
304 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
305 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
306 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
307 | #define SPARC32_CP0_REGISTERS \ | |
308 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
386c036b | 309 | |
3f7b46f2 IR |
310 | static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS }; |
311 | static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS }; | |
312 | static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS }; | |
313 | ||
386c036b | 314 | static const char *sparc32_register_names[] = |
5af923b0 | 315 | { |
7a36499a IR |
316 | SPARC_CORE_REGISTERS, |
317 | SPARC32_FPU_REGISTERS, | |
318 | SPARC32_CP0_REGISTERS | |
5af923b0 MS |
319 | }; |
320 | ||
386c036b MK |
321 | /* Total number of registers. */ |
322 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 323 | |
386c036b MK |
324 | /* We provide the aliases %d0..%d30 for the floating registers as |
325 | "psuedo" registers. */ | |
326 | ||
327 | static const char *sparc32_pseudo_register_names[] = | |
328 | { | |
329 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
330 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
331 | }; | |
332 | ||
333 | /* Total number of pseudo registers. */ | |
334 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
335 | ||
7a36499a IR |
336 | /* Return the name of pseudo register REGNUM. */ |
337 | ||
338 | static const char * | |
339 | sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
340 | { | |
341 | regnum -= gdbarch_num_regs (gdbarch); | |
342 | ||
343 | if (regnum < SPARC32_NUM_PSEUDO_REGS) | |
344 | return sparc32_pseudo_register_names[regnum]; | |
345 | ||
346 | internal_error (__FILE__, __LINE__, | |
347 | _("sparc32_pseudo_register_name: bad register number %d"), | |
348 | regnum); | |
349 | } | |
350 | ||
386c036b MK |
351 | /* Return the name of register REGNUM. */ |
352 | ||
353 | static const char * | |
d93859e2 | 354 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b | 355 | { |
3f7b46f2 IR |
356 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
357 | return tdesc_register_name (gdbarch, regnum); | |
358 | ||
7a36499a | 359 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
386c036b MK |
360 | return sparc32_register_names[regnum]; |
361 | ||
7a36499a | 362 | return sparc32_pseudo_register_name (gdbarch, regnum); |
386c036b | 363 | } |
2d457077 | 364 | \f |
209bd28e | 365 | /* Construct types for ISA-specific registers. */ |
2d457077 | 366 | |
209bd28e UW |
367 | static struct type * |
368 | sparc_psr_type (struct gdbarch *gdbarch) | |
369 | { | |
370 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 371 | |
209bd28e UW |
372 | if (!tdep->sparc_psr_type) |
373 | { | |
374 | struct type *type; | |
2d457077 | 375 | |
e9bb382b | 376 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
377 | append_flags_type_flag (type, 5, "ET"); |
378 | append_flags_type_flag (type, 6, "PS"); | |
379 | append_flags_type_flag (type, 7, "S"); | |
380 | append_flags_type_flag (type, 12, "EF"); | |
381 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 382 | |
209bd28e UW |
383 | tdep->sparc_psr_type = type; |
384 | } | |
385 | ||
386 | return tdep->sparc_psr_type; | |
387 | } | |
388 | ||
389 | static struct type * | |
390 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 391 | { |
209bd28e UW |
392 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
393 | ||
394 | if (!tdep->sparc_fsr_type) | |
395 | { | |
396 | struct type *type; | |
397 | ||
e9bb382b | 398 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
399 | append_flags_type_flag (type, 0, "NXA"); |
400 | append_flags_type_flag (type, 1, "DZA"); | |
401 | append_flags_type_flag (type, 2, "UFA"); | |
402 | append_flags_type_flag (type, 3, "OFA"); | |
403 | append_flags_type_flag (type, 4, "NVA"); | |
404 | append_flags_type_flag (type, 5, "NXC"); | |
405 | append_flags_type_flag (type, 6, "DZC"); | |
406 | append_flags_type_flag (type, 7, "UFC"); | |
407 | append_flags_type_flag (type, 8, "OFC"); | |
408 | append_flags_type_flag (type, 9, "NVC"); | |
409 | append_flags_type_flag (type, 22, "NS"); | |
410 | append_flags_type_flag (type, 23, "NXM"); | |
411 | append_flags_type_flag (type, 24, "DZM"); | |
412 | append_flags_type_flag (type, 25, "UFM"); | |
413 | append_flags_type_flag (type, 26, "OFM"); | |
414 | append_flags_type_flag (type, 27, "NVM"); | |
415 | ||
416 | tdep->sparc_fsr_type = type; | |
417 | } | |
418 | ||
419 | return tdep->sparc_fsr_type; | |
2d457077 | 420 | } |
386c036b | 421 | |
7a36499a IR |
422 | /* Return the GDB type object for the "standard" data type of data in |
423 | pseudo register REGNUM. */ | |
424 | ||
425 | static struct type * | |
426 | sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
427 | { | |
428 | regnum -= gdbarch_num_regs (gdbarch); | |
429 | ||
430 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
431 | return builtin_type (gdbarch)->builtin_double; | |
432 | ||
433 | internal_error (__FILE__, __LINE__, | |
434 | _("sparc32_pseudo_register_type: bad register number %d"), | |
435 | regnum); | |
436 | } | |
437 | ||
386c036b | 438 | /* Return the GDB type object for the "standard" data type of data in |
c378eb4e | 439 | register REGNUM. */ |
386c036b MK |
440 | |
441 | static struct type * | |
442 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
443 | { | |
3f7b46f2 IR |
444 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
445 | return tdesc_register_type (gdbarch, regnum); | |
446 | ||
386c036b | 447 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) |
0dfff4cb | 448 | return builtin_type (gdbarch)->builtin_float; |
386c036b | 449 | |
386c036b | 450 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) |
0dfff4cb | 451 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
452 | |
453 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 454 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 455 | |
2d457077 | 456 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 457 | return sparc_psr_type (gdbarch); |
2d457077 MK |
458 | |
459 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 460 | return sparc_fsr_type (gdbarch); |
2d457077 | 461 | |
7a36499a IR |
462 | if (regnum >= gdbarch_num_regs (gdbarch)) |
463 | return sparc32_pseudo_register_type (gdbarch, regnum); | |
464 | ||
df4df182 | 465 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
466 | } |
467 | ||
05d1431c | 468 | static enum register_status |
386c036b MK |
469 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
470 | struct regcache *regcache, | |
e1613aba | 471 | int regnum, gdb_byte *buf) |
386c036b | 472 | { |
05d1431c PA |
473 | enum register_status status; |
474 | ||
7a36499a | 475 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
476 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
477 | ||
478 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
479 | status = regcache_raw_read (regcache, regnum, buf); |
480 | if (status == REG_VALID) | |
481 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
482 | return status; | |
386c036b MK |
483 | } |
484 | ||
485 | static void | |
486 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
487 | struct regcache *regcache, | |
e1613aba | 488 | int regnum, const gdb_byte *buf) |
386c036b | 489 | { |
7a36499a | 490 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
491 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
492 | ||
493 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
494 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 495 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
496 | } |
497 | \f | |
c9cf6e20 | 498 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
961842b2 JM |
499 | |
500 | int | |
c9cf6e20 | 501 | sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
961842b2 JM |
502 | { |
503 | /* This function must return true if we are one instruction after an | |
504 | instruction that destroyed the stack frame of the current | |
505 | function. The SPARC instructions used to restore the callers | |
506 | stack frame are RESTORE and RETURN/RETT. | |
507 | ||
508 | Of these RETURN/RETT is a branch instruction and thus we return | |
509 | true if we are in its delay slot. | |
510 | ||
511 | RESTORE is almost always found in the delay slot of a branch | |
512 | instruction that transfers control to the caller, such as JMPL. | |
513 | Thus the next instruction is in the caller frame and we don't | |
514 | need to do anything about it. */ | |
515 | ||
516 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
517 | ||
518 | return X_RETTURN (insn); | |
519 | } | |
520 | \f | |
386c036b | 521 | |
49a45ecf JB |
522 | static CORE_ADDR |
523 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
524 | { | |
525 | /* The ABI requires double-word alignment. */ | |
526 | return address & ~0x7; | |
527 | } | |
528 | ||
386c036b MK |
529 | static CORE_ADDR |
530 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 531 | CORE_ADDR funcaddr, |
386c036b MK |
532 | struct value **args, int nargs, |
533 | struct type *value_type, | |
e4fd649a UW |
534 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
535 | struct regcache *regcache) | |
c906108c | 536 | { |
e17a4113 UW |
537 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
538 | ||
386c036b MK |
539 | *bp_addr = sp - 4; |
540 | *real_pc = funcaddr; | |
541 | ||
d80b854b | 542 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 543 | { |
e1613aba | 544 | gdb_byte buf[4]; |
386c036b MK |
545 | |
546 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
547 | store_unsigned_integer (buf, 4, byte_order, |
548 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
549 | write_memory (sp - 8, buf, 4); |
550 | return sp - 8; | |
c906108c SS |
551 | } |
552 | ||
386c036b MK |
553 | return sp - 4; |
554 | } | |
555 | ||
556 | static CORE_ADDR | |
557 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
558 | struct value **args, CORE_ADDR sp, | |
559 | int struct_return, CORE_ADDR struct_addr) | |
560 | { | |
df4df182 | 561 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 562 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
563 | /* Number of words in the "parameter array". */ |
564 | int num_elements = 0; | |
565 | int element = 0; | |
566 | int i; | |
567 | ||
568 | for (i = 0; i < nargs; i++) | |
c906108c | 569 | { |
4991999e | 570 | struct type *type = value_type (args[i]); |
386c036b MK |
571 | int len = TYPE_LENGTH (type); |
572 | ||
573 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
574 | || (sparc_floating_p (type) && len == 16) |
575 | || sparc_complex_floating_p (type)) | |
c906108c | 576 | { |
386c036b MK |
577 | /* Structure, Union and Quad-Precision Arguments. */ |
578 | sp -= len; | |
579 | ||
580 | /* Use doubleword alignment for these values. That's always | |
581 | correct, and wasting a few bytes shouldn't be a problem. */ | |
582 | sp &= ~0x7; | |
583 | ||
0fd88904 | 584 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
585 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
586 | num_elements++; | |
587 | } | |
588 | else if (sparc_floating_p (type)) | |
589 | { | |
590 | /* Floating arguments. */ | |
591 | gdb_assert (len == 4 || len == 8); | |
592 | num_elements += (len / 4); | |
c906108c | 593 | } |
c5aa993b JM |
594 | else |
595 | { | |
386c036b MK |
596 | /* Integral and pointer arguments. */ |
597 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
598 | ||
599 | if (len < 4) | |
df4df182 UW |
600 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
601 | args[i]); | |
386c036b | 602 | num_elements += ((len + 3) / 4); |
c5aa993b | 603 | } |
c906108c | 604 | } |
c906108c | 605 | |
386c036b | 606 | /* Always allocate at least six words. */ |
325fac50 | 607 | sp -= std::max (6, num_elements) * 4; |
c906108c | 608 | |
386c036b MK |
609 | /* The psABI says that "Software convention requires space for the |
610 | struct/union return value pointer, even if the word is unused." */ | |
611 | sp -= 4; | |
c906108c | 612 | |
386c036b MK |
613 | /* The psABI says that "Although software convention and the |
614 | operating system require every stack frame to be doubleword | |
615 | aligned." */ | |
616 | sp &= ~0x7; | |
c906108c | 617 | |
386c036b | 618 | for (i = 0; i < nargs; i++) |
c906108c | 619 | { |
0fd88904 | 620 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 621 | struct type *type = value_type (args[i]); |
386c036b | 622 | int len = TYPE_LENGTH (type); |
c906108c | 623 | |
386c036b | 624 | gdb_assert (len == 4 || len == 8); |
c906108c | 625 | |
386c036b MK |
626 | if (element < 6) |
627 | { | |
628 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 629 | |
386c036b MK |
630 | regcache_cooked_write (regcache, regnum, valbuf); |
631 | if (len > 4 && element < 5) | |
632 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
633 | } | |
5af923b0 | 634 | |
386c036b MK |
635 | /* Always store the argument in memory. */ |
636 | write_memory (sp + 4 + element * 4, valbuf, len); | |
637 | element += len / 4; | |
638 | } | |
c906108c | 639 | |
386c036b | 640 | gdb_assert (element == num_elements); |
c906108c | 641 | |
386c036b | 642 | if (struct_return) |
c906108c | 643 | { |
e1613aba | 644 | gdb_byte buf[4]; |
c906108c | 645 | |
e17a4113 | 646 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
647 | write_memory (sp, buf, 4); |
648 | } | |
c906108c | 649 | |
386c036b | 650 | return sp; |
c906108c SS |
651 | } |
652 | ||
386c036b | 653 | static CORE_ADDR |
7d9b040b | 654 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
655 | struct regcache *regcache, CORE_ADDR bp_addr, |
656 | int nargs, struct value **args, CORE_ADDR sp, | |
657 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 658 | { |
386c036b MK |
659 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
660 | ||
661 | /* Set return address. */ | |
662 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
663 | ||
664 | /* Set up function arguments. */ | |
665 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
666 | struct_return, struct_addr); | |
667 | ||
668 | /* Allocate the 16-word window save area. */ | |
669 | sp -= 16 * 4; | |
c906108c | 670 | |
386c036b MK |
671 | /* Stack should be doubleword aligned at this point. */ |
672 | gdb_assert (sp % 8 == 0); | |
c906108c | 673 | |
386c036b MK |
674 | /* Finally, update the stack pointer. */ |
675 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
676 | ||
677 | return sp; | |
678 | } | |
679 | \f | |
c906108c | 680 | |
386c036b MK |
681 | /* Use the program counter to determine the contents and size of a |
682 | breakpoint instruction. Return a pointer to a string of bytes that | |
683 | encode a breakpoint instruction, store the length of the string in | |
684 | *LEN and optionally adjust *PC to point to the correct memory | |
685 | location for inserting the breakpoint. */ | |
04180708 | 686 | constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 687 | |
04180708 | 688 | typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; |
386c036b | 689 | \f |
c906108c | 690 | |
386c036b | 691 | /* Allocate and initialize a frame cache. */ |
c906108c | 692 | |
386c036b MK |
693 | static struct sparc_frame_cache * |
694 | sparc_alloc_frame_cache (void) | |
695 | { | |
696 | struct sparc_frame_cache *cache; | |
c906108c | 697 | |
386c036b | 698 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 699 | |
386c036b MK |
700 | /* Base address. */ |
701 | cache->base = 0; | |
702 | cache->pc = 0; | |
c906108c | 703 | |
386c036b MK |
704 | /* Frameless until proven otherwise. */ |
705 | cache->frameless_p = 1; | |
369c397b JB |
706 | cache->frame_offset = 0; |
707 | cache->saved_regs_mask = 0; | |
708 | cache->copied_regs_mask = 0; | |
386c036b MK |
709 | cache->struct_return_p = 0; |
710 | ||
711 | return cache; | |
712 | } | |
713 | ||
b0b92586 JB |
714 | /* GCC generates several well-known sequences of instructions at the begining |
715 | of each function prologue when compiling with -fstack-check. If one of | |
716 | such sequences starts at START_PC, then return the address of the | |
717 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
718 | ||
719 | static CORE_ADDR | |
720 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
721 | { | |
722 | CORE_ADDR pc = start_pc; | |
723 | unsigned long insn; | |
2067c8d4 | 724 | int probing_loop = 0; |
b0b92586 JB |
725 | |
726 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 727 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 728 | |
2067c8d4 JG |
729 | sethi <some immediate>, %g1 |
730 | sub %sp, %g1, %g1 | |
731 | ||
732 | or: | |
733 | ||
734 | sethi <some immediate>, %g1 | |
735 | sethi <some immediate>, %g4 | |
736 | sub %sp, %g1, %g1 | |
737 | ||
738 | or: | |
739 | ||
740 | sethi <some immediate>, %g1 | |
741 | sub %sp, %g1, %g1 | |
742 | sethi <some immediate>, %g4 | |
743 | ||
744 | If the optional instruction is found (setting g4), assume that a | |
745 | probing loop will follow. */ | |
746 | ||
747 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
748 | insn = sparc_fetch_instruction (pc); |
749 | pc = pc + 4; | |
750 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
751 | return start_pc; | |
752 | ||
2067c8d4 | 753 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
754 | insn = sparc_fetch_instruction (pc); |
755 | pc = pc + 4; | |
2067c8d4 JG |
756 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
757 | { | |
758 | probing_loop = 1; | |
759 | insn = sparc_fetch_instruction (pc); | |
760 | pc = pc + 4; | |
761 | } | |
762 | ||
763 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
764 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
765 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
766 | return start_pc; | |
767 | ||
768 | insn = sparc_fetch_instruction (pc); | |
769 | pc = pc + 4; | |
770 | ||
2067c8d4 JG |
771 | /* optional: sethi <some immediate>, %g4 */ |
772 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
773 | { | |
774 | probing_loop = 1; | |
775 | insn = sparc_fetch_instruction (pc); | |
776 | pc = pc + 4; | |
777 | } | |
778 | ||
b0b92586 JB |
779 | /* First possible sequence: |
780 | [first two instructions above] | |
781 | clr [%g1 - some immediate] */ | |
782 | ||
783 | /* clr [%g1 - some immediate] */ | |
784 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
785 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
786 | { | |
787 | /* Valid stack-check sequence, return the new PC. */ | |
788 | return pc; | |
789 | } | |
790 | ||
791 | /* Second possible sequence: A small number of probes. | |
792 | [first two instructions above] | |
793 | clr [%g1] | |
794 | add %g1, -<some immediate>, %g1 | |
795 | clr [%g1] | |
796 | [repeat the two instructions above any (small) number of times] | |
797 | clr [%g1 - some immediate] */ | |
798 | ||
799 | /* clr [%g1] */ | |
800 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
801 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
802 | { | |
803 | while (1) | |
804 | { | |
805 | /* add %g1, -<some immediate>, %g1 */ | |
806 | insn = sparc_fetch_instruction (pc); | |
807 | pc = pc + 4; | |
808 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
809 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
810 | break; | |
811 | ||
812 | /* clr [%g1] */ | |
813 | insn = sparc_fetch_instruction (pc); | |
814 | pc = pc + 4; | |
815 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
816 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
817 | return start_pc; | |
818 | } | |
819 | ||
820 | /* clr [%g1 - some immediate] */ | |
821 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
822 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
823 | return start_pc; | |
824 | ||
825 | /* We found a valid stack-check sequence, return the new PC. */ | |
826 | return pc; | |
827 | } | |
828 | ||
829 | /* Third sequence: A probing loop. | |
2067c8d4 | 830 | [first three instructions above] |
b0b92586 JB |
831 | sub %g1, %g4, %g4 |
832 | cmp %g1, %g4 | |
833 | be <disp> | |
834 | add %g1, -<some immediate>, %g1 | |
835 | ba <disp> | |
836 | clr [%g1] | |
2067c8d4 JG |
837 | |
838 | And an optional last probe for the remainder: | |
839 | ||
b0b92586 JB |
840 | clr [%g4 - some immediate] */ |
841 | ||
2067c8d4 | 842 | if (probing_loop) |
b0b92586 JB |
843 | { |
844 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
845 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
846 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
847 | return start_pc; | |
848 | ||
849 | /* cmp %g1, %g4 */ | |
850 | insn = sparc_fetch_instruction (pc); | |
851 | pc = pc + 4; | |
852 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
853 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
854 | return start_pc; | |
855 | ||
856 | /* be <disp> */ | |
857 | insn = sparc_fetch_instruction (pc); | |
858 | pc = pc + 4; | |
859 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
860 | return start_pc; | |
861 | ||
862 | /* add %g1, -<some immediate>, %g1 */ | |
863 | insn = sparc_fetch_instruction (pc); | |
864 | pc = pc + 4; | |
865 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
866 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
867 | return start_pc; | |
868 | ||
869 | /* ba <disp> */ | |
870 | insn = sparc_fetch_instruction (pc); | |
871 | pc = pc + 4; | |
872 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
873 | return start_pc; | |
874 | ||
2067c8d4 | 875 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
876 | insn = sparc_fetch_instruction (pc); |
877 | pc = pc + 4; | |
2067c8d4 JG |
878 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
879 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
880 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
881 | return start_pc; |
882 | ||
2067c8d4 JG |
883 | /* We found a valid stack-check sequence, return the new PC. */ |
884 | ||
885 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
886 | insn = sparc_fetch_instruction (pc); |
887 | pc = pc + 4; | |
888 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
889 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
890 | return pc - 4; |
891 | else | |
892 | return pc; | |
b0b92586 JB |
893 | } |
894 | ||
895 | /* No stack check code in our prologue, return the start_pc. */ | |
896 | return start_pc; | |
897 | } | |
898 | ||
369c397b JB |
899 | /* Record the effect of a SAVE instruction on CACHE. */ |
900 | ||
901 | void | |
902 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
903 | { | |
904 | /* The frame is set up. */ | |
905 | cache->frameless_p = 0; | |
906 | ||
907 | /* The frame pointer contains the CFA. */ | |
908 | cache->frame_offset = 0; | |
909 | ||
910 | /* The `local' and `in' registers are all saved. */ | |
911 | cache->saved_regs_mask = 0xffff; | |
912 | ||
913 | /* The `out' registers are all renamed. */ | |
914 | cache->copied_regs_mask = 0xff; | |
915 | } | |
916 | ||
917 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
918 | Bail out early if CURRENT_PC is reached. Return the address where | |
919 | the analysis stopped. | |
920 | ||
921 | We handle both the traditional register window model and the single | |
922 | register window (aka flat) model. */ | |
923 | ||
386c036b | 924 | CORE_ADDR |
be8626e0 MD |
925 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
926 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 927 | { |
be8626e0 | 928 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
929 | unsigned long insn; |
930 | int offset = 0; | |
c906108c | 931 | int dest = -1; |
c906108c | 932 | |
b0b92586 JB |
933 | pc = sparc_skip_stack_check (pc); |
934 | ||
386c036b MK |
935 | if (current_pc <= pc) |
936 | return current_pc; | |
937 | ||
938 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
939 | SPARC the linker usually defines a symbol (typically | |
940 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
941 | This symbol makes us end up here with PC pointing at the start of | |
942 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
943 | would do our normal prologue analysis, we would probably conclude | |
944 | that we've got a frame when in reality we don't, since the | |
945 | dynamic linker patches up the first PLT with some code that | |
946 | starts with a SAVE instruction. Patch up PC such that it points | |
947 | at the start of our PLT entry. */ | |
3e5d3a5a | 948 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 949 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 950 | |
386c036b MK |
951 | insn = sparc_fetch_instruction (pc); |
952 | ||
369c397b JB |
953 | /* Recognize store insns and record their sources. */ |
954 | while (X_OP (insn) == 3 | |
955 | && (X_OP3 (insn) == 0x4 /* stw */ | |
956 | || X_OP3 (insn) == 0x7 /* std */ | |
957 | || X_OP3 (insn) == 0xe) /* stx */ | |
958 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
959 | { | |
960 | int regnum = X_RD (insn); | |
961 | ||
962 | /* Recognize stores into the corresponding stack slots. */ | |
963 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
964 | && ((X_I (insn) | |
965 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
966 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
967 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
968 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
969 | { | |
970 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
971 | if (X_OP3 (insn) == 0x7) | |
972 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
973 | } | |
974 | ||
975 | offset += 4; | |
976 | ||
977 | insn = sparc_fetch_instruction (pc + offset); | |
978 | } | |
979 | ||
386c036b MK |
980 | /* Recognize a SETHI insn and record its destination. */ |
981 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
982 | { |
983 | dest = X_RD (insn); | |
386c036b MK |
984 | offset += 4; |
985 | ||
369c397b | 986 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
987 | } |
988 | ||
386c036b MK |
989 | /* Allow for an arithmetic operation on DEST or %g1. */ |
990 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
991 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
992 | { | |
386c036b | 993 | offset += 4; |
c906108c | 994 | |
369c397b | 995 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 996 | } |
c906108c | 997 | |
386c036b MK |
998 | /* Check for the SAVE instruction that sets up the frame. */ |
999 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 1000 | { |
369c397b JB |
1001 | sparc_record_save_insn (cache); |
1002 | offset += 4; | |
1003 | return pc + offset; | |
1004 | } | |
1005 | ||
1006 | /* Check for an arithmetic operation on %sp. */ | |
1007 | if (X_OP (insn) == 2 | |
1008 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1009 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1010 | && X_RD (insn) == SPARC_SP_REGNUM) | |
1011 | { | |
1012 | if (X_I (insn)) | |
1013 | { | |
1014 | cache->frame_offset = X_SIMM13 (insn); | |
1015 | if (X_OP3 (insn) == 0) | |
1016 | cache->frame_offset = -cache->frame_offset; | |
1017 | } | |
1018 | offset += 4; | |
1019 | ||
1020 | insn = sparc_fetch_instruction (pc + offset); | |
1021 | ||
1022 | /* Check for an arithmetic operation that sets up the frame. */ | |
1023 | if (X_OP (insn) == 2 | |
1024 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1025 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1026 | && X_RD (insn) == SPARC_FP_REGNUM) | |
1027 | { | |
1028 | cache->frameless_p = 0; | |
1029 | cache->frame_offset = 0; | |
1030 | /* We could check that the amount subtracted to %sp above is the | |
1031 | same as the one added here, but this seems superfluous. */ | |
1032 | cache->copied_regs_mask |= 0x40; | |
1033 | offset += 4; | |
1034 | ||
1035 | insn = sparc_fetch_instruction (pc + offset); | |
1036 | } | |
1037 | ||
1038 | /* Check for a move (or) operation that copies the return register. */ | |
1039 | if (X_OP (insn) == 2 | |
1040 | && X_OP3 (insn) == 0x2 | |
1041 | && !X_I (insn) | |
1042 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1043 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1044 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1045 | { | |
1046 | cache->copied_regs_mask |= 0x80; | |
1047 | offset += 4; | |
1048 | } | |
1049 | ||
1050 | return pc + offset; | |
c906108c SS |
1051 | } |
1052 | ||
1053 | return pc; | |
1054 | } | |
1055 | ||
386c036b | 1056 | static CORE_ADDR |
236369e7 | 1057 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1058 | { |
1059 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 1060 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
1061 | } |
1062 | ||
1063 | /* Return PC of first real instruction of the function starting at | |
1064 | START_PC. */ | |
f510d44e | 1065 | |
386c036b | 1066 | static CORE_ADDR |
6093d2eb | 1067 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1068 | { |
f510d44e DM |
1069 | struct symtab_and_line sal; |
1070 | CORE_ADDR func_start, func_end; | |
386c036b | 1071 | struct sparc_frame_cache cache; |
f510d44e DM |
1072 | |
1073 | /* This is the preferred method, find the end of the prologue by | |
1074 | using the debugging information. */ | |
1075 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
1076 | { | |
1077 | sal = find_pc_line (func_start, 0); | |
1078 | ||
1079 | if (sal.end < func_end | |
1080 | && start_pc <= sal.end) | |
1081 | return sal.end; | |
1082 | } | |
1083 | ||
be8626e0 | 1084 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1085 | |
1086 | /* The psABI says that "Although the first 6 words of arguments | |
1087 | reside in registers, the standard stack frame reserves space for | |
1088 | them.". It also suggests that a function may use that space to | |
1089 | "write incoming arguments 0 to 5" into that space, and that's | |
1090 | indeed what GCC seems to be doing. In that case GCC will | |
1091 | generate debug information that points to the stack slots instead | |
1092 | of the registers, so we should consider the instructions that | |
369c397b | 1093 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1094 | |
369c397b | 1095 | while (1) |
075ccec8 MK |
1096 | { |
1097 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1098 | ||
369c397b JB |
1099 | /* Recognize instructions that store incoming arguments into the |
1100 | corresponding stack slots. */ | |
1101 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1102 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1103 | { |
369c397b JB |
1104 | int regnum = X_RD (insn); |
1105 | ||
1106 | /* Case of arguments still in %o[0..5]. */ | |
1107 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1108 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1109 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1110 | { | |
1111 | start_pc += 4; | |
1112 | continue; | |
1113 | } | |
1114 | ||
1115 | /* Case of arguments copied into %i[0..5]. */ | |
1116 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1117 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1118 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1119 | { | |
1120 | start_pc += 4; | |
1121 | continue; | |
1122 | } | |
075ccec8 MK |
1123 | } |
1124 | ||
1125 | break; | |
1126 | } | |
1127 | ||
1128 | return start_pc; | |
c906108c SS |
1129 | } |
1130 | ||
386c036b | 1131 | /* Normal frames. */ |
9319a2fe | 1132 | |
386c036b | 1133 | struct sparc_frame_cache * |
236369e7 | 1134 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1135 | { |
386c036b | 1136 | struct sparc_frame_cache *cache; |
9319a2fe | 1137 | |
386c036b | 1138 | if (*this_cache) |
19ba03f4 | 1139 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1140 | |
386c036b MK |
1141 | cache = sparc_alloc_frame_cache (); |
1142 | *this_cache = cache; | |
c906108c | 1143 | |
236369e7 | 1144 | cache->pc = get_frame_func (this_frame); |
386c036b | 1145 | if (cache->pc != 0) |
236369e7 JB |
1146 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1147 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1148 | |
1149 | if (cache->frameless_p) | |
c906108c | 1150 | { |
cbeae229 MK |
1151 | /* This function is frameless, so %fp (%i6) holds the frame |
1152 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1153 | base address. */ | |
1154 | cache->base = | |
236369e7 | 1155 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1156 | } |
1157 | else | |
1158 | { | |
1159 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1160 | base address for the current stack frame. */ | |
1161 | cache->base = | |
236369e7 | 1162 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1163 | } |
c906108c | 1164 | |
369c397b JB |
1165 | cache->base += cache->frame_offset; |
1166 | ||
5b2d44a0 MK |
1167 | if (cache->base & 1) |
1168 | cache->base += BIAS; | |
1169 | ||
386c036b | 1170 | return cache; |
c906108c | 1171 | } |
c906108c | 1172 | |
aff37fc1 DM |
1173 | static int |
1174 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1175 | { | |
1176 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1177 | enum type_code code = TYPE_CODE (type); | |
1178 | ||
1179 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1180 | { | |
1181 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1182 | if (sparc_structure_or_union_p (type) | |
1183 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1184 | return 1; | |
1185 | } | |
1186 | ||
1187 | return 0; | |
1188 | } | |
1189 | ||
386c036b | 1190 | struct sparc_frame_cache * |
236369e7 | 1191 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1192 | { |
386c036b MK |
1193 | struct sparc_frame_cache *cache; |
1194 | struct symbol *sym; | |
c906108c | 1195 | |
386c036b | 1196 | if (*this_cache) |
19ba03f4 | 1197 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1198 | |
236369e7 | 1199 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1200 | |
386c036b MK |
1201 | sym = find_pc_function (cache->pc); |
1202 | if (sym) | |
c906108c | 1203 | { |
aff37fc1 | 1204 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1205 | } |
5465445a JB |
1206 | else |
1207 | { | |
1208 | /* There is no debugging information for this function to | |
1209 | help us determine whether this function returns a struct | |
1210 | or not. So we rely on another heuristic which is to check | |
1211 | the instruction at the return address and see if this is | |
1212 | an "unimp" instruction. If it is, then it is a struct-return | |
1213 | function. */ | |
1214 | CORE_ADDR pc; | |
369c397b JB |
1215 | int regnum = |
1216 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1217 | |
236369e7 | 1218 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1219 | if (sparc_is_unimp_insn (pc)) |
1220 | cache->struct_return_p = 1; | |
1221 | } | |
c906108c | 1222 | |
386c036b MK |
1223 | return cache; |
1224 | } | |
1225 | ||
1226 | static void | |
236369e7 | 1227 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1228 | struct frame_id *this_id) |
1229 | { | |
1230 | struct sparc_frame_cache *cache = | |
236369e7 | 1231 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1232 | |
1233 | /* This marks the outermost frame. */ | |
1234 | if (cache->base == 0) | |
1235 | return; | |
1236 | ||
1237 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1238 | } | |
c906108c | 1239 | |
236369e7 JB |
1240 | static struct value * |
1241 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1242 | void **this_cache, int regnum) | |
386c036b | 1243 | { |
e17a4113 | 1244 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1245 | struct sparc_frame_cache *cache = |
236369e7 | 1246 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1247 | |
386c036b | 1248 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1249 | { |
236369e7 | 1250 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1251 | |
236369e7 JB |
1252 | /* If this functions has a Structure, Union or Quad-Precision |
1253 | return value, we have to skip the UNIMP instruction that encodes | |
1254 | the size of the structure. */ | |
1255 | if (cache->struct_return_p) | |
1256 | pc += 4; | |
386c036b | 1257 | |
369c397b JB |
1258 | regnum = |
1259 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1260 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1261 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1262 | } |
1263 | ||
42cdca6c MK |
1264 | /* Handle StackGhost. */ |
1265 | { | |
e17a4113 | 1266 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1267 | |
1268 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1269 | { | |
236369e7 JB |
1270 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1271 | ULONGEST i7; | |
1272 | ||
1273 | /* Read the value in from memory. */ | |
1274 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1275 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1276 | } |
1277 | } | |
1278 | ||
369c397b | 1279 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1280 | in the register save area. */ |
369c397b JB |
1281 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1282 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1283 | { |
236369e7 | 1284 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1285 | |
236369e7 | 1286 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1287 | } |
c906108c | 1288 | |
369c397b JB |
1289 | /* The previous frame's `out' registers may be accessible as the current |
1290 | frame's `in' registers. */ | |
1291 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1292 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1293 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1294 | |
236369e7 | 1295 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1296 | } |
c906108c | 1297 | |
386c036b MK |
1298 | static const struct frame_unwind sparc32_frame_unwind = |
1299 | { | |
1300 | NORMAL_FRAME, | |
8fbca658 | 1301 | default_frame_unwind_stop_reason, |
386c036b | 1302 | sparc32_frame_this_id, |
236369e7 JB |
1303 | sparc32_frame_prev_register, |
1304 | NULL, | |
1305 | default_frame_sniffer | |
386c036b | 1306 | }; |
386c036b | 1307 | \f |
c906108c | 1308 | |
386c036b | 1309 | static CORE_ADDR |
236369e7 | 1310 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1311 | { |
1312 | struct sparc_frame_cache *cache = | |
236369e7 | 1313 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1314 | |
386c036b MK |
1315 | return cache->base; |
1316 | } | |
c906108c | 1317 | |
386c036b MK |
1318 | static const struct frame_base sparc32_frame_base = |
1319 | { | |
1320 | &sparc32_frame_unwind, | |
1321 | sparc32_frame_base_address, | |
1322 | sparc32_frame_base_address, | |
1323 | sparc32_frame_base_address | |
1324 | }; | |
c906108c | 1325 | |
386c036b | 1326 | static struct frame_id |
236369e7 | 1327 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1328 | { |
1329 | CORE_ADDR sp; | |
5af923b0 | 1330 | |
236369e7 | 1331 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1332 | if (sp & 1) |
1333 | sp += BIAS; | |
236369e7 | 1334 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1335 | } |
1336 | \f | |
c906108c | 1337 | |
3923a2b2 MK |
1338 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1339 | that into VALBUF. */ | |
5af923b0 | 1340 | |
386c036b MK |
1341 | static void |
1342 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1343 | gdb_byte *valbuf) |
386c036b MK |
1344 | { |
1345 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1346 | gdb_byte buf[32]; |
c906108c | 1347 | |
386c036b MK |
1348 | gdb_assert (!sparc_structure_or_union_p (type)); |
1349 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1350 | |
fe10a582 | 1351 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1352 | { |
386c036b MK |
1353 | /* Floating return values. */ |
1354 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1355 | if (len > 4) | |
1356 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1357 | if (len > 8) |
1358 | { | |
1359 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1360 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1361 | } | |
1362 | if (len > 16) | |
1363 | { | |
1364 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1365 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1366 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1367 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1368 | } | |
386c036b | 1369 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1370 | } |
1371 | else | |
1372 | { | |
386c036b MK |
1373 | /* Integral and pointer return values. */ |
1374 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1375 | |
386c036b MK |
1376 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1377 | if (len > 4) | |
1378 | { | |
1379 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1380 | gdb_assert (len == 8); | |
1381 | memcpy (valbuf, buf, 8); | |
1382 | } | |
1383 | else | |
1384 | { | |
1385 | /* Just stripping off any unused bytes should preserve the | |
1386 | signed-ness just fine. */ | |
1387 | memcpy (valbuf, buf + 4 - len, len); | |
1388 | } | |
1389 | } | |
1390 | } | |
c906108c | 1391 | |
3923a2b2 MK |
1392 | /* Store the function return value of type TYPE from VALBUF into |
1393 | REGCACHE. */ | |
c906108c | 1394 | |
386c036b MK |
1395 | static void |
1396 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1397 | const gdb_byte *valbuf) |
386c036b MK |
1398 | { |
1399 | int len = TYPE_LENGTH (type); | |
e1613aba | 1400 | gdb_byte buf[8]; |
c906108c | 1401 | |
386c036b MK |
1402 | gdb_assert (!sparc_structure_or_union_p (type)); |
1403 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1404 | gdb_assert (len <= 8); |
c906108c | 1405 | |
fe10a582 | 1406 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1407 | { |
1408 | /* Floating return values. */ | |
1409 | memcpy (buf, valbuf, len); | |
1410 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1411 | if (len > 4) | |
1412 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1413 | if (len > 8) |
1414 | { | |
1415 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1416 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1417 | } | |
1418 | if (len > 16) | |
1419 | { | |
1420 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1421 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1422 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1423 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1424 | } | |
386c036b MK |
1425 | } |
1426 | else | |
c906108c | 1427 | { |
386c036b MK |
1428 | /* Integral and pointer return values. */ |
1429 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1430 | ||
1431 | if (len > 4) | |
2757dd86 | 1432 | { |
386c036b MK |
1433 | gdb_assert (len == 8); |
1434 | memcpy (buf, valbuf, 8); | |
1435 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1436 | } |
1437 | else | |
1438 | { | |
386c036b MK |
1439 | /* ??? Do we need to do any sign-extension here? */ |
1440 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1441 | } |
386c036b | 1442 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1443 | } |
1444 | } | |
1445 | ||
b9d4c5ed | 1446 | static enum return_value_convention |
6a3a010b | 1447 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1448 | struct type *type, struct regcache *regcache, |
1449 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1450 | { |
e17a4113 UW |
1451 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1452 | ||
0a8f48b9 MK |
1453 | /* The psABI says that "...every stack frame reserves the word at |
1454 | %fp+64. If a function returns a structure, union, or | |
1455 | quad-precision value, this word should hold the address of the | |
1456 | object into which the return value should be copied." This | |
1457 | guarantees that we can always find the return value, not just | |
1458 | before the function returns. */ | |
1459 | ||
b9d4c5ed MK |
1460 | if (sparc_structure_or_union_p (type) |
1461 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 | 1462 | { |
bbfdfe1c DM |
1463 | ULONGEST sp; |
1464 | CORE_ADDR addr; | |
1465 | ||
0a8f48b9 MK |
1466 | if (readbuf) |
1467 | { | |
0a8f48b9 | 1468 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1469 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1470 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1471 | } | |
bbfdfe1c DM |
1472 | if (writebuf) |
1473 | { | |
1474 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1475 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1476 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1477 | } | |
0a8f48b9 MK |
1478 | |
1479 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1480 | } | |
b9d4c5ed MK |
1481 | |
1482 | if (readbuf) | |
1483 | sparc32_extract_return_value (type, regcache, readbuf); | |
1484 | if (writebuf) | |
1485 | sparc32_store_return_value (type, regcache, writebuf); | |
1486 | ||
1487 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1488 | } | |
1489 | ||
386c036b MK |
1490 | static int |
1491 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1492 | { |
386c036b | 1493 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1494 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1495 | || sparc_complex_floating_p (type)); | |
386c036b | 1496 | } |
c906108c | 1497 | |
aff37fc1 | 1498 | static int |
4a4e5149 | 1499 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1500 | { |
236369e7 | 1501 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1502 | struct symbol *sym = find_pc_function (pc); |
1503 | ||
1504 | if (sym) | |
1505 | return sparc32_struct_return_from_sym (sym); | |
1506 | return 0; | |
1507 | } | |
1508 | ||
f5a9b87d DM |
1509 | static void |
1510 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1511 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1512 | struct frame_info *this_frame) |
f5a9b87d | 1513 | { |
aff37fc1 DM |
1514 | int off; |
1515 | ||
f5a9b87d DM |
1516 | switch (regnum) |
1517 | { | |
1518 | case SPARC_G0_REGNUM: | |
1519 | /* Since %g0 is always zero, there is no point in saving it, and | |
1520 | people will be inclined omit it from the CFI. Make sure we | |
1521 | don't warn about that. */ | |
1522 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1523 | break; | |
1524 | case SPARC_SP_REGNUM: | |
1525 | reg->how = DWARF2_FRAME_REG_CFA; | |
1526 | break; | |
1527 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1528 | case SPARC32_NPC_REGNUM: |
1529 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1530 | off = 8; |
4a4e5149 | 1531 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1532 | off += 4; |
1533 | if (regnum == SPARC32_NPC_REGNUM) | |
1534 | off += 4; | |
1535 | reg->loc.offset = off; | |
f5a9b87d DM |
1536 | break; |
1537 | } | |
1538 | } | |
1539 | ||
b41c5a85 JW |
1540 | /* Implement the execute_dwarf_cfa_vendor_op method. */ |
1541 | ||
1542 | static bool | |
1543 | sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, | |
1544 | struct dwarf2_frame_state *fs) | |
1545 | { | |
1546 | /* Only DW_CFA_GNU_window_save is expected on SPARC. */ | |
1547 | if (op != DW_CFA_GNU_window_save) | |
1548 | return false; | |
1549 | ||
1550 | uint64_t reg; | |
1551 | int size = register_size (gdbarch, 0); | |
1552 | ||
1553 | dwarf2_frame_state_alloc_regs (&fs->regs, 32); | |
1554 | for (reg = 8; reg < 16; reg++) | |
1555 | { | |
1556 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG; | |
1557 | fs->regs.reg[reg].loc.reg = reg + 16; | |
1558 | } | |
1559 | for (reg = 16; reg < 32; reg++) | |
1560 | { | |
1561 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET; | |
1562 | fs->regs.reg[reg].loc.offset = (reg - 16) * size; | |
1563 | } | |
1564 | ||
1565 | return true; | |
1566 | } | |
1567 | ||
386c036b MK |
1568 | \f |
1569 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1570 | and most operating systems don't implement it either, so we provide | |
1571 | software single-step mechanism. */ | |
c906108c | 1572 | |
386c036b | 1573 | static CORE_ADDR |
cd76b525 | 1574 | sparc_analyze_control_transfer (struct regcache *regcache, |
c893be75 | 1575 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1576 | { |
1577 | unsigned long insn = sparc_fetch_instruction (pc); | |
1578 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1579 | int branch_p = 0, fused_p = 0; |
386c036b | 1580 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1581 | |
8d1b3521 | 1582 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1583 | { |
8d1b3521 DM |
1584 | if ((insn & 0x10000000) == 0) |
1585 | { | |
1586 | /* Branch on Integer Register with Prediction (BPr). */ | |
1587 | branch_p = 1; | |
1588 | conditional_p = 1; | |
1589 | } | |
1590 | else | |
1591 | { | |
1592 | /* Compare and Branch */ | |
1593 | branch_p = 1; | |
1594 | fused_p = 1; | |
1595 | offset = 4 * X_DISP10 (insn); | |
1596 | } | |
c906108c | 1597 | } |
386c036b | 1598 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1599 | { |
386c036b MK |
1600 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1601 | branch_p = 1; | |
1602 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1603 | } |
386c036b MK |
1604 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1605 | { | |
1606 | /* Branch on Floating-Point Condition Codes with Prediction | |
1607 | (FBPfcc). */ | |
1608 | branch_p = 1; | |
1609 | offset = 4 * X_DISP19 (insn); | |
1610 | } | |
1611 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1612 | { | |
1613 | /* Branch on Integer Condition Codes (Bicc). */ | |
1614 | branch_p = 1; | |
1615 | offset = 4 * X_DISP22 (insn); | |
1616 | } | |
1617 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1618 | { |
386c036b MK |
1619 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1620 | branch_p = 1; | |
1621 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1622 | } |
c893be75 MK |
1623 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1624 | { | |
cd76b525 YQ |
1625 | struct frame_info *frame = get_current_frame (); |
1626 | ||
c893be75 | 1627 | /* Trap instruction (TRAP). */ |
cd76b525 YQ |
1628 | return gdbarch_tdep (get_regcache_arch (regcache))->step_trap (frame, |
1629 | insn); | |
c893be75 | 1630 | } |
386c036b MK |
1631 | |
1632 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1633 | ||
386c036b | 1634 | if (branch_p) |
c906108c | 1635 | { |
8d1b3521 DM |
1636 | if (fused_p) |
1637 | { | |
1638 | /* Fused compare-and-branch instructions are non-delayed, | |
1639 | and do not have an annuling capability. So we need to | |
1640 | always set a breakpoint on both the NPC and the branch | |
1641 | target address. */ | |
1642 | gdb_assert (offset != 0); | |
1643 | return pc + offset; | |
1644 | } | |
1645 | else if (conditional_p) | |
c906108c | 1646 | { |
386c036b MK |
1647 | /* For conditional branches, return nPC + 4 iff the annul |
1648 | bit is 1. */ | |
1649 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1650 | } |
1651 | else | |
1652 | { | |
386c036b MK |
1653 | /* For unconditional branches, return the target if its |
1654 | specified condition is "always" and return nPC + 4 if the | |
1655 | condition is "never". If the annul bit is 1, set *NPC to | |
1656 | zero. */ | |
1657 | if (X_COND (insn) == 0x0) | |
1658 | pc = *npc, offset = 4; | |
1659 | if (X_A (insn)) | |
1660 | *npc = 0; | |
1661 | ||
386c036b | 1662 | return pc + offset; |
c906108c SS |
1663 | } |
1664 | } | |
386c036b MK |
1665 | |
1666 | return 0; | |
c906108c SS |
1667 | } |
1668 | ||
c893be75 | 1669 | static CORE_ADDR |
0b1b3e42 | 1670 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1671 | { |
1672 | return 0; | |
1673 | } | |
1674 | ||
a0ff9e1a | 1675 | static std::vector<CORE_ADDR> |
f5ea389a | 1676 | sparc_software_single_step (struct regcache *regcache) |
386c036b | 1677 | { |
cd76b525 | 1678 | struct gdbarch *arch = get_regcache_arch (regcache); |
c893be75 | 1679 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1680 | CORE_ADDR npc, nnpc; |
c906108c | 1681 | |
e0cd558a | 1682 | CORE_ADDR pc, orig_npc; |
a0ff9e1a | 1683 | std::vector<CORE_ADDR> next_pcs; |
c906108c | 1684 | |
cd76b525 YQ |
1685 | pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); |
1686 | orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); | |
c906108c | 1687 | |
e0cd558a | 1688 | /* Analyze the instruction at PC. */ |
cd76b525 | 1689 | nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); |
e0cd558a | 1690 | if (npc != 0) |
a0ff9e1a | 1691 | next_pcs.push_back (npc); |
8181d85f | 1692 | |
e0cd558a | 1693 | if (nnpc != 0) |
a0ff9e1a | 1694 | next_pcs.push_back (nnpc); |
c906108c | 1695 | |
e0cd558a UW |
1696 | /* Assert that we have set at least one breakpoint, and that |
1697 | they're not set at the same spot - unless we're going | |
1698 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1699 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1700 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b | 1701 | |
93f9a11f | 1702 | return next_pcs; |
386c036b MK |
1703 | } |
1704 | ||
1705 | static void | |
61a1198a | 1706 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1707 | { |
61a1198a | 1708 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1709 | |
61a1198a UW |
1710 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1711 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1712 | } |
1713 | \f | |
5af923b0 | 1714 | |
e5139de8 | 1715 | /* Iterate over core file register note sections. */ |
a54124c5 | 1716 | |
e5139de8 AA |
1717 | static void |
1718 | sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
1719 | iterate_over_regset_sections_cb *cb, | |
1720 | void *cb_data, | |
1721 | const struct regcache *regcache) | |
a54124c5 MK |
1722 | { |
1723 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1724 | ||
e5139de8 AA |
1725 | cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); |
1726 | cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); | |
a54124c5 MK |
1727 | } |
1728 | \f | |
1729 | ||
3f7b46f2 IR |
1730 | static int |
1731 | validate_tdesc_registers (const struct target_desc *tdesc, | |
1732 | struct tdesc_arch_data *tdesc_data, | |
1733 | const char *feature_name, | |
1734 | const char *register_names[], | |
1735 | unsigned int registers_num, | |
1736 | unsigned int reg_start) | |
1737 | { | |
1738 | int valid_p = 1; | |
1739 | const struct tdesc_feature *feature; | |
1740 | ||
1741 | feature = tdesc_find_feature (tdesc, feature_name); | |
1742 | if (feature == NULL) | |
1743 | return 0; | |
1744 | ||
1745 | for (unsigned int i = 0; i < registers_num; i++) | |
1746 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1747 | reg_start + i, | |
1748 | register_names[i]); | |
1749 | ||
1750 | return valid_p; | |
1751 | } | |
1752 | ||
386c036b MK |
1753 | static struct gdbarch * |
1754 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1755 | { | |
1756 | struct gdbarch_tdep *tdep; | |
3f7b46f2 | 1757 | const struct target_desc *tdesc = info.target_desc; |
386c036b | 1758 | struct gdbarch *gdbarch; |
3f7b46f2 | 1759 | int valid_p = 1; |
c906108c | 1760 | |
386c036b MK |
1761 | /* If there is already a candidate, use it. */ |
1762 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1763 | if (arches != NULL) | |
1764 | return arches->gdbarch; | |
c906108c | 1765 | |
386c036b | 1766 | /* Allocate space for the new architecture. */ |
41bf6aca | 1767 | tdep = XCNEW (struct gdbarch_tdep); |
386c036b | 1768 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1769 | |
386c036b MK |
1770 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1771 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1772 | tdep->step_trap = sparc_step_trap; |
3f7b46f2 IR |
1773 | tdep->fpu_register_names = sparc32_fpu_register_names; |
1774 | tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); | |
1775 | tdep->cp0_register_names = sparc32_cp0_register_names; | |
1776 | tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); | |
386c036b MK |
1777 | |
1778 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1779 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b | 1780 | |
53375380 PA |
1781 | set_gdbarch_wchar_bit (gdbarch, 16); |
1782 | set_gdbarch_wchar_signed (gdbarch, 1); | |
1783 | ||
386c036b MK |
1784 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); |
1785 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1786 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1787 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
3f7b46f2 IR |
1788 | set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); |
1789 | set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); | |
386c036b MK |
1790 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); |
1791 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1792 | ||
1793 | /* Register numbers of various important registers. */ | |
1794 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1795 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1796 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1797 | ||
1798 | /* Call dummy code. */ | |
49a45ecf | 1799 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1800 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1801 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1802 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1803 | ||
b9d4c5ed | 1804 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1805 | set_gdbarch_stabs_argument_has_addr |
1806 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1807 | ||
1808 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1809 | ||
1810 | /* Stack grows downward. */ | |
1811 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1812 | |
04180708 YQ |
1813 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1814 | sparc_breakpoint::kind_from_pc); | |
1815 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1816 | sparc_breakpoint::bp_from_kind); | |
c906108c | 1817 | |
386c036b | 1818 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1819 | |
386c036b | 1820 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1821 | |
386c036b MK |
1822 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1823 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1824 | |
236369e7 | 1825 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1826 | |
386c036b | 1827 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1828 | |
386c036b MK |
1829 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1830 | ||
f5a9b87d DM |
1831 | /* Hook in the DWARF CFI frame unwinder. */ |
1832 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
b41c5a85 JW |
1833 | /* Register DWARF vendor CFI handler. */ |
1834 | set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, | |
1835 | sparc_execute_dwarf_cfa_vendor_op); | |
f5a9b87d DM |
1836 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the |
1837 | StackGhost issues have been resolved. */ | |
1838 | ||
b2a0b9b2 DM |
1839 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1840 | gdbarch_init_osabi (info, gdbarch); | |
1841 | ||
236369e7 | 1842 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1843 | |
3f7b46f2 IR |
1844 | if (tdesc_has_registers (tdesc)) |
1845 | { | |
1846 | struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); | |
1847 | ||
1848 | /* Validate that the descriptor provides the mandatory registers | |
1849 | and allocate their numbers. */ | |
1850 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1851 | "org.gnu.gdb.sparc.cpu", | |
1852 | sparc_core_register_names, | |
1853 | ARRAY_SIZE (sparc_core_register_names), | |
1854 | SPARC_G0_REGNUM); | |
1855 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1856 | "org.gnu.gdb.sparc.fpu", | |
1857 | tdep->fpu_register_names, | |
1858 | tdep->fpu_registers_num, | |
1859 | SPARC_F0_REGNUM); | |
1860 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1861 | "org.gnu.gdb.sparc.cp0", | |
1862 | tdep->cp0_register_names, | |
1863 | tdep->cp0_registers_num, | |
1291063d JM |
1864 | SPARC_F0_REGNUM |
1865 | + tdep->fpu_registers_num); | |
3f7b46f2 IR |
1866 | if (!valid_p) |
1867 | { | |
1868 | tdesc_data_cleanup (tdesc_data); | |
1869 | return NULL; | |
1870 | } | |
1871 | ||
1872 | /* Target description may have changed. */ | |
1873 | info.tdep_info = tdesc_data; | |
1874 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
1875 | } | |
1876 | ||
a54124c5 | 1877 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1878 | if (tdep->gregset) |
e5139de8 AA |
1879 | set_gdbarch_iterate_over_regset_sections |
1880 | (gdbarch, sparc_iterate_over_regset_sections); | |
a54124c5 | 1881 | |
7e35103a JB |
1882 | register_sparc_ravenscar_ops (gdbarch); |
1883 | ||
386c036b MK |
1884 | return gdbarch; |
1885 | } | |
1886 | \f | |
1887 | /* Helper functions for dealing with register windows. */ | |
1888 | ||
1889 | void | |
1890 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1891 | { |
e17a4113 UW |
1892 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1893 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1894 | int offset = 0; |
e1613aba | 1895 | gdb_byte buf[8]; |
386c036b MK |
1896 | int i; |
1897 | ||
1898 | if (sp & 1) | |
1899 | { | |
1900 | /* Registers are 64-bit. */ | |
1901 | sp += BIAS; | |
c906108c | 1902 | |
386c036b MK |
1903 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1904 | { | |
1905 | if (regnum == i || regnum == -1) | |
1906 | { | |
1907 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1908 | |
1909 | /* Handle StackGhost. */ | |
1910 | if (i == SPARC_I7_REGNUM) | |
1911 | { | |
e17a4113 UW |
1912 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1913 | ULONGEST i7; | |
f700a364 | 1914 | |
e17a4113 UW |
1915 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1916 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1917 | i7 ^ wcookie); | |
f700a364 MK |
1918 | } |
1919 | ||
386c036b MK |
1920 | regcache_raw_supply (regcache, i, buf); |
1921 | } | |
1922 | } | |
1923 | } | |
1924 | else | |
c906108c | 1925 | { |
386c036b MK |
1926 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1927 | pointer. */ | |
1928 | sp &= 0xffffffffUL; | |
c906108c | 1929 | |
386c036b MK |
1930 | /* Clear out the top half of the temporary buffer, and put the |
1931 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1932 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1933 | { |
386c036b MK |
1934 | memset (buf, 0, 4); |
1935 | offset = 4; | |
1936 | } | |
c906108c | 1937 | |
386c036b MK |
1938 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1939 | { | |
1940 | if (regnum == i || regnum == -1) | |
1941 | { | |
1942 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1943 | buf + offset, 4); | |
42cdca6c MK |
1944 | |
1945 | /* Handle StackGhost. */ | |
1946 | if (i == SPARC_I7_REGNUM) | |
1947 | { | |
e17a4113 UW |
1948 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1949 | ULONGEST i7; | |
42cdca6c | 1950 | |
e17a4113 UW |
1951 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1952 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1953 | i7 ^ wcookie); | |
42cdca6c MK |
1954 | } |
1955 | ||
386c036b MK |
1956 | regcache_raw_supply (regcache, i, buf); |
1957 | } | |
c906108c SS |
1958 | } |
1959 | } | |
c906108c | 1960 | } |
c906108c SS |
1961 | |
1962 | void | |
386c036b MK |
1963 | sparc_collect_rwindow (const struct regcache *regcache, |
1964 | CORE_ADDR sp, int regnum) | |
c906108c | 1965 | { |
e17a4113 UW |
1966 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1967 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1968 | int offset = 0; |
e1613aba | 1969 | gdb_byte buf[8]; |
386c036b | 1970 | int i; |
5af923b0 | 1971 | |
386c036b | 1972 | if (sp & 1) |
5af923b0 | 1973 | { |
386c036b MK |
1974 | /* Registers are 64-bit. */ |
1975 | sp += BIAS; | |
c906108c | 1976 | |
386c036b MK |
1977 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1978 | { | |
1979 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1980 | { | |
1981 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1982 | |
1983 | /* Handle StackGhost. */ | |
1984 | if (i == SPARC_I7_REGNUM) | |
1985 | { | |
e17a4113 UW |
1986 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1987 | ULONGEST i7; | |
f700a364 | 1988 | |
e17a4113 UW |
1989 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1990 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1991 | } |
1992 | ||
386c036b MK |
1993 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1994 | } | |
1995 | } | |
5af923b0 MS |
1996 | } |
1997 | else | |
1998 | { | |
386c036b MK |
1999 | /* Registers are 32-bit. Toss any sign-extension of the stack |
2000 | pointer. */ | |
2001 | sp &= 0xffffffffUL; | |
2002 | ||
2003 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 2004 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
2005 | offset = 4; |
2006 | ||
2007 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2008 | { | |
2009 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
2010 | { | |
2011 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
2012 | |
2013 | /* Handle StackGhost. */ | |
2014 | if (i == SPARC_I7_REGNUM) | |
2015 | { | |
e17a4113 UW |
2016 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2017 | ULONGEST i7; | |
42cdca6c | 2018 | |
e17a4113 UW |
2019 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
2020 | store_unsigned_integer (buf + offset, 4, byte_order, | |
2021 | i7 ^ wcookie); | |
42cdca6c MK |
2022 | } |
2023 | ||
386c036b MK |
2024 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
2025 | buf + offset, 4); | |
2026 | } | |
2027 | } | |
5af923b0 | 2028 | } |
c906108c SS |
2029 | } |
2030 | ||
386c036b MK |
2031 | /* Helper functions for dealing with register sets. */ |
2032 | ||
c906108c | 2033 | void |
b4fd25c9 | 2034 | sparc32_supply_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2035 | struct regcache *regcache, |
2036 | int regnum, const void *gregs) | |
c906108c | 2037 | { |
19ba03f4 | 2038 | const gdb_byte *regs = (const gdb_byte *) gregs; |
22e74ef9 | 2039 | gdb_byte zero[4] = { 0 }; |
386c036b | 2040 | int i; |
5af923b0 | 2041 | |
386c036b MK |
2042 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
2043 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 2044 | regs + gregmap->r_psr_offset); |
c906108c | 2045 | |
386c036b MK |
2046 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
2047 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 2048 | regs + gregmap->r_pc_offset); |
5af923b0 | 2049 | |
386c036b MK |
2050 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
2051 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 2052 | regs + gregmap->r_npc_offset); |
5af923b0 | 2053 | |
386c036b MK |
2054 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
2055 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 2056 | regs + gregmap->r_y_offset); |
5af923b0 | 2057 | |
386c036b | 2058 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 2059 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 2060 | |
386c036b | 2061 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 2062 | { |
b4fd25c9 | 2063 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2064 | |
2065 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2066 | { | |
2067 | if (regnum == i || regnum == -1) | |
2068 | regcache_raw_supply (regcache, i, regs + offset); | |
2069 | offset += 4; | |
2070 | } | |
c906108c | 2071 | } |
386c036b MK |
2072 | |
2073 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 2074 | { |
386c036b MK |
2075 | /* Not all of the register set variants include Locals and |
2076 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2077 | if (gregmap->r_l0_offset == -1) |
386c036b MK |
2078 | { |
2079 | ULONGEST sp; | |
2080 | ||
2081 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
2082 | sparc_supply_rwindow (regcache, sp, regnum); | |
2083 | } | |
2084 | else | |
2085 | { | |
b4fd25c9 | 2086 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2087 | |
2088 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2089 | { | |
2090 | if (regnum == i || regnum == -1) | |
2091 | regcache_raw_supply (regcache, i, regs + offset); | |
2092 | offset += 4; | |
2093 | } | |
2094 | } | |
c906108c SS |
2095 | } |
2096 | } | |
2097 | ||
c5aa993b | 2098 | void |
b4fd25c9 | 2099 | sparc32_collect_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2100 | const struct regcache *regcache, |
2101 | int regnum, void *gregs) | |
c906108c | 2102 | { |
19ba03f4 | 2103 | gdb_byte *regs = (gdb_byte *) gregs; |
386c036b | 2104 | int i; |
c5aa993b | 2105 | |
386c036b MK |
2106 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
2107 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 2108 | regs + gregmap->r_psr_offset); |
60054393 | 2109 | |
386c036b MK |
2110 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
2111 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 2112 | regs + gregmap->r_pc_offset); |
386c036b MK |
2113 | |
2114 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
2115 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 2116 | regs + gregmap->r_npc_offset); |
5af923b0 | 2117 | |
386c036b MK |
2118 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
2119 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 2120 | regs + gregmap->r_y_offset); |
386c036b MK |
2121 | |
2122 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 2123 | { |
b4fd25c9 | 2124 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2125 | |
2126 | /* %g0 is always zero. */ | |
2127 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2128 | { | |
2129 | if (regnum == i || regnum == -1) | |
2130 | regcache_raw_collect (regcache, i, regs + offset); | |
2131 | offset += 4; | |
2132 | } | |
5af923b0 | 2133 | } |
386c036b MK |
2134 | |
2135 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2136 | { |
386c036b MK |
2137 | /* Not all of the register set variants include Locals and |
2138 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2139 | if (gregmap->r_l0_offset != -1) |
386c036b | 2140 | { |
b4fd25c9 | 2141 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2142 | |
2143 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2144 | { | |
2145 | if (regnum == i || regnum == -1) | |
2146 | regcache_raw_collect (regcache, i, regs + offset); | |
2147 | offset += 4; | |
2148 | } | |
2149 | } | |
5af923b0 | 2150 | } |
c906108c SS |
2151 | } |
2152 | ||
c906108c | 2153 | void |
b4fd25c9 | 2154 | sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2155 | struct regcache *regcache, |
386c036b | 2156 | int regnum, const void *fpregs) |
c906108c | 2157 | { |
19ba03f4 | 2158 | const gdb_byte *regs = (const gdb_byte *) fpregs; |
386c036b | 2159 | int i; |
60054393 | 2160 | |
386c036b | 2161 | for (i = 0; i < 32; i++) |
c906108c | 2162 | { |
386c036b | 2163 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
db75c717 | 2164 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2165 | regs + fpregmap->r_f0_offset + (i * 4)); |
c906108c | 2166 | } |
5af923b0 | 2167 | |
386c036b | 2168 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2169 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2170 | regs + fpregmap->r_fsr_offset); |
c906108c SS |
2171 | } |
2172 | ||
386c036b | 2173 | void |
b4fd25c9 | 2174 | sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2175 | const struct regcache *regcache, |
386c036b | 2176 | int regnum, void *fpregs) |
c906108c | 2177 | { |
19ba03f4 | 2178 | gdb_byte *regs = (gdb_byte *) fpregs; |
386c036b | 2179 | int i; |
c906108c | 2180 | |
386c036b MK |
2181 | for (i = 0; i < 32; i++) |
2182 | { | |
2183 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
db75c717 | 2184 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2185 | regs + fpregmap->r_f0_offset + (i * 4)); |
386c036b | 2186 | } |
c906108c | 2187 | |
386c036b | 2188 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2189 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2190 | regs + fpregmap->r_fsr_offset); |
c906108c | 2191 | } |
c906108c | 2192 | \f |
c906108c | 2193 | |
386c036b | 2194 | /* SunOS 4. */ |
c906108c | 2195 | |
386c036b | 2196 | /* From <machine/reg.h>. */ |
b4fd25c9 | 2197 | const struct sparc_gregmap sparc32_sunos4_gregmap = |
c906108c | 2198 | { |
386c036b MK |
2199 | 0 * 4, /* %psr */ |
2200 | 1 * 4, /* %pc */ | |
2201 | 2 * 4, /* %npc */ | |
2202 | 3 * 4, /* %y */ | |
2203 | -1, /* %wim */ | |
2204 | -1, /* %tbr */ | |
2205 | 4 * 4, /* %g1 */ | |
2206 | -1 /* %l0 */ | |
2207 | }; | |
db75c717 | 2208 | |
b4fd25c9 | 2209 | const struct sparc_fpregmap sparc32_sunos4_fpregmap = |
db75c717 DM |
2210 | { |
2211 | 0 * 4, /* %f0 */ | |
2212 | 33 * 4, /* %fsr */ | |
2213 | }; | |
2214 | ||
b4fd25c9 | 2215 | const struct sparc_fpregmap sparc32_bsd_fpregmap = |
db75c717 DM |
2216 | { |
2217 | 0 * 4, /* %f0 */ | |
2218 | 32 * 4, /* %fsr */ | |
2219 | }; | |
386c036b | 2220 | \f |
c906108c | 2221 | |
386c036b MK |
2222 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2223 | void _initialize_sparc_tdep (void); | |
c906108c SS |
2224 | |
2225 | void | |
386c036b | 2226 | _initialize_sparc_tdep (void) |
c906108c | 2227 | { |
386c036b | 2228 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2229 | } |