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8b39fe56 MK |
1 | /* Target-dependent code for UltraSPARC. |
2 | ||
3 | Copyright 2003 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include "defs.h" | |
23 | #include "arch-utils.h" | |
24 | #include "floatformat.h" | |
25 | #include "frame.h" | |
26 | #include "frame-base.h" | |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "osabi.h" | |
31 | #include "regcache.h" | |
32 | #include "target.h" | |
33 | #include "value.h" | |
34 | ||
35 | #include "gdb_assert.h" | |
36 | #include "gdb_string.h" | |
37 | ||
38 | #include "sparc64-tdep.h" | |
39 | ||
40 | /* This file implements the The SPARC 64-bit ABI as defined by the | |
41 | section "Low-Level System Information" of the SPARC Compliance | |
42 | Definition (SCD) 2.4.1, which is the 64-bit System V psABI for | |
43 | SPARC. */ | |
44 | ||
45 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
46 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
47 | code can handle both. */ | |
48 | ||
49 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
50 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
51 | hosts, so undefine it first. */ | |
52 | #undef BIAS | |
53 | #define BIAS 2047 | |
54 | ||
55 | /* Macros to extract fields from SPARC instructions. */ | |
56 | #define X_OP(i) (((i) >> 30) & 0x3) | |
57 | #define X_A(i) (((i) >> 29) & 1) | |
58 | #define X_COND(i) (((i) >> 25) & 0xf) | |
59 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
60 | #define X_IMM22(i) ((i) & 0x3fffff) | |
61 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
62 | /* Sign extension macros. */ | |
63 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) | |
64 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) | |
65 | ||
66 | /* Fetch the instruction at PC. Instructions are always big-endian | |
67 | even if the processor operates in little-endian mode. */ | |
68 | ||
69 | static unsigned long | |
70 | sparc_fetch_instruction (CORE_ADDR pc) | |
71 | { | |
72 | unsigned char buf[4]; | |
73 | unsigned long insn; | |
74 | int i; | |
75 | ||
76 | read_memory (pc, buf, sizeof (buf)); | |
77 | ||
78 | insn = 0; | |
79 | for (i = 0; i < sizeof (buf); i++) | |
80 | insn = (insn << 8) | buf[i]; | |
81 | return insn; | |
82 | } | |
83 | \f | |
84 | /* The functions on this page are intended to be used to classify | |
85 | function arguments. */ | |
86 | ||
87 | /* Return the contents if register REGNUM as an address. */ | |
88 | ||
89 | static CORE_ADDR | |
90 | sparc_address_from_register (int regnum) | |
91 | { | |
92 | ULONGEST addr; | |
93 | ||
94 | regcache_cooked_read_unsigned (current_regcache, regnum, &addr); | |
95 | return addr; | |
96 | } | |
97 | ||
98 | /* Check whether TYPE is "Integral or Pointer". */ | |
99 | ||
100 | static int | |
101 | sparc64_integral_or_pointer_p (const struct type *type) | |
102 | { | |
103 | switch (TYPE_CODE (type)) | |
104 | { | |
105 | case TYPE_CODE_INT: | |
106 | case TYPE_CODE_BOOL: | |
107 | case TYPE_CODE_CHAR: | |
108 | case TYPE_CODE_ENUM: | |
109 | case TYPE_CODE_RANGE: | |
110 | { | |
111 | int len = TYPE_LENGTH (type); | |
112 | gdb_assert (len == 1 || len == 2 || len == 4 || len == 8); | |
113 | } | |
114 | return 1; | |
115 | case TYPE_CODE_PTR: | |
116 | case TYPE_CODE_REF: | |
117 | { | |
118 | int len = TYPE_LENGTH (type); | |
119 | gdb_assert (len == 8); | |
120 | } | |
121 | return 1; | |
122 | default: | |
123 | break; | |
124 | } | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
129 | /* Check whether TYPE is "Floating". */ | |
130 | ||
131 | static int | |
132 | sparc64_floating_p (const struct type *type) | |
133 | { | |
134 | switch (TYPE_CODE (type)) | |
135 | { | |
136 | case TYPE_CODE_FLT: | |
137 | { | |
138 | int len = TYPE_LENGTH (type); | |
139 | gdb_assert (len == 4 || len == 8 || len == 16); | |
140 | } | |
141 | return 1; | |
142 | default: | |
143 | break; | |
144 | } | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | /* Check whether TYPE is "Structure or Union". */ | |
150 | ||
151 | static int | |
152 | sparc64_structure_or_union_p (const struct type *type) | |
153 | { | |
154 | switch (TYPE_CODE (type)) | |
155 | { | |
156 | case TYPE_CODE_STRUCT: | |
157 | case TYPE_CODE_UNION: | |
158 | return 1; | |
159 | default: | |
160 | break; | |
161 | } | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | /* UltraSPARC architecture specific information. */ | |
167 | ||
168 | struct gdbarch_tdep | |
169 | { | |
170 | /* Offset of saved PC in jmp_buf. */ | |
171 | int jb_pc_offset; | |
172 | }; | |
173 | ||
174 | /* Register information. */ | |
175 | ||
176 | struct sparc64_register_info | |
177 | { | |
178 | char *name; | |
179 | struct type **type; | |
180 | }; | |
181 | ||
182 | static struct sparc64_register_info sparc64_register_info[] = | |
183 | { | |
184 | { "g0", &builtin_type_int64 }, | |
185 | { "g1", &builtin_type_int64 }, | |
186 | { "g2", &builtin_type_int64 }, | |
187 | { "g3", &builtin_type_int64 }, | |
188 | { "g4", &builtin_type_int64 }, | |
189 | { "g5", &builtin_type_int64 }, | |
190 | { "g6", &builtin_type_int64 }, | |
191 | { "g7", &builtin_type_int64 }, | |
192 | ||
193 | { "o0", &builtin_type_int64 }, | |
194 | { "o1", &builtin_type_int64 }, | |
195 | { "o2", &builtin_type_int64 }, | |
196 | { "o3", &builtin_type_int64 }, | |
197 | { "o4", &builtin_type_int64 }, | |
198 | { "o5", &builtin_type_int64 }, | |
199 | { "sp", &builtin_type_void_data_ptr }, | |
200 | { "o7", &builtin_type_int64 }, | |
201 | ||
202 | { "l0", &builtin_type_int64 }, | |
203 | { "l1", &builtin_type_int64 }, | |
204 | { "l2", &builtin_type_int64 }, | |
205 | { "l3", &builtin_type_int64 }, | |
206 | { "l4", &builtin_type_int64 }, | |
207 | { "l5", &builtin_type_int64 }, | |
208 | { "l6", &builtin_type_int64 }, | |
209 | { "l7", &builtin_type_int64 }, | |
210 | ||
211 | { "i0", &builtin_type_int64 }, | |
212 | { "i1", &builtin_type_int64 }, | |
213 | { "i2", &builtin_type_int64 }, | |
214 | { "i3", &builtin_type_int64 }, | |
215 | { "i4", &builtin_type_int64 }, | |
216 | { "i5", &builtin_type_int64 }, | |
217 | { "fp", &builtin_type_void_data_ptr }, | |
218 | { "i7", &builtin_type_int64 }, | |
219 | ||
220 | { "f0", &builtin_type_float }, | |
221 | { "f1", &builtin_type_float }, | |
222 | { "f2", &builtin_type_float }, | |
223 | { "f3", &builtin_type_float }, | |
224 | { "f4", &builtin_type_float }, | |
225 | { "f5", &builtin_type_float }, | |
226 | { "f6", &builtin_type_float }, | |
227 | { "f7", &builtin_type_float }, | |
228 | { "f8", &builtin_type_float }, | |
229 | { "f9", &builtin_type_float }, | |
230 | { "f10", &builtin_type_float }, | |
231 | { "f11", &builtin_type_float }, | |
232 | { "f12", &builtin_type_float }, | |
233 | { "f13", &builtin_type_float }, | |
234 | { "f14", &builtin_type_float }, | |
235 | { "f15", &builtin_type_float }, | |
236 | { "f16", &builtin_type_float }, | |
237 | { "f17", &builtin_type_float }, | |
238 | { "f18", &builtin_type_float }, | |
239 | { "f19", &builtin_type_float }, | |
240 | { "f20", &builtin_type_float }, | |
241 | { "f21", &builtin_type_float }, | |
242 | { "f22", &builtin_type_float }, | |
243 | { "f23", &builtin_type_float }, | |
244 | { "f24", &builtin_type_float }, | |
245 | { "f25", &builtin_type_float }, | |
246 | { "f26", &builtin_type_float }, | |
247 | { "f27", &builtin_type_float }, | |
248 | { "f28", &builtin_type_float }, | |
249 | { "f29", &builtin_type_float }, | |
250 | { "f30", &builtin_type_float }, | |
251 | { "f31", &builtin_type_float }, | |
252 | { "f32", &builtin_type_double }, | |
253 | { "f34", &builtin_type_double }, | |
254 | { "f36", &builtin_type_double }, | |
255 | { "f38", &builtin_type_double }, | |
256 | { "f40", &builtin_type_double }, | |
257 | { "f42", &builtin_type_double }, | |
258 | { "f44", &builtin_type_double }, | |
259 | { "f46", &builtin_type_double }, | |
260 | { "f48", &builtin_type_double }, | |
261 | { "f50", &builtin_type_double }, | |
262 | { "f52", &builtin_type_double }, | |
263 | { "f54", &builtin_type_double }, | |
264 | { "f56", &builtin_type_double }, | |
265 | { "f58", &builtin_type_double }, | |
266 | { "f60", &builtin_type_double }, | |
267 | { "f62", &builtin_type_double }, | |
268 | ||
269 | { "pc", &builtin_type_void_func_ptr }, | |
270 | { "npc", &builtin_type_void_func_ptr }, | |
271 | ||
272 | /* This raw register contains the contents of %cwp, %pstate, %asi | |
273 | and %ccr as laid out in a %tstate register. */ | |
274 | { NULL, &builtin_type_int64 }, | |
275 | ||
276 | { "fsr", &builtin_type_int64 }, | |
277 | { "fprs", &builtin_type_int64 }, | |
278 | ||
279 | /* "Although Y is a 64-bit register, its high-order 32 bits are | |
280 | reserved and always read as 0." */ | |
281 | { "y", &builtin_type_int64 } | |
282 | }; | |
283 | ||
284 | /* Total number of registers. */ | |
285 | #define SPARC64_NUM_REGS \ | |
286 | (sizeof (sparc64_register_info) / sizeof (sparc64_register_info[0])) | |
287 | ||
288 | /* We provide the aliases %d0..%d62 and %q0..%q60 for the floating | |
289 | registers as "psuedo" registers. */ | |
290 | ||
291 | static struct sparc64_register_info sparc64_pseudo_register_info[] = | |
292 | { | |
293 | { "cwp", &builtin_type_int64 }, | |
294 | { "pstate", &builtin_type_int64 }, | |
295 | { "asi", &builtin_type_int64 }, | |
296 | { "ccr", &builtin_type_int64 }, | |
297 | ||
298 | { "d0", &builtin_type_double }, | |
299 | { "d2", &builtin_type_double }, | |
300 | { "d4", &builtin_type_double }, | |
301 | { "d6", &builtin_type_double }, | |
302 | { "d8", &builtin_type_double }, | |
303 | { "d10", &builtin_type_double }, | |
304 | { "d12", &builtin_type_double }, | |
305 | { "d14", &builtin_type_double }, | |
306 | { "d16", &builtin_type_double }, | |
307 | { "d18", &builtin_type_double }, | |
308 | { "d20", &builtin_type_double }, | |
309 | { "d22", &builtin_type_double }, | |
310 | { "d24", &builtin_type_double }, | |
311 | { "d26", &builtin_type_double }, | |
312 | { "d28", &builtin_type_double }, | |
313 | { "d30", &builtin_type_double }, | |
314 | { "d32", &builtin_type_double }, | |
315 | { "d34", &builtin_type_double }, | |
316 | { "d36", &builtin_type_double }, | |
317 | { "d38", &builtin_type_double }, | |
318 | { "d40", &builtin_type_double }, | |
319 | { "d42", &builtin_type_double }, | |
320 | { "d44", &builtin_type_double }, | |
321 | { "d46", &builtin_type_double }, | |
322 | { "d48", &builtin_type_double }, | |
323 | { "d50", &builtin_type_double }, | |
324 | { "d52", &builtin_type_double }, | |
325 | { "d54", &builtin_type_double }, | |
326 | { "d56", &builtin_type_double }, | |
327 | { "d58", &builtin_type_double }, | |
328 | { "d60", &builtin_type_double }, | |
329 | { "d62", &builtin_type_double }, | |
330 | ||
331 | { "q0", &builtin_type_long_double }, | |
332 | { "q4", &builtin_type_long_double }, | |
333 | { "q8", &builtin_type_long_double }, | |
334 | { "q12", &builtin_type_long_double }, | |
335 | { "q16", &builtin_type_long_double }, | |
336 | { "q20", &builtin_type_long_double }, | |
337 | { "q24", &builtin_type_long_double }, | |
338 | { "q28", &builtin_type_long_double }, | |
339 | { "q32", &builtin_type_long_double }, | |
340 | { "q36", &builtin_type_long_double }, | |
341 | { "q40", &builtin_type_long_double }, | |
342 | { "q44", &builtin_type_long_double }, | |
343 | { "q48", &builtin_type_long_double }, | |
344 | { "q52", &builtin_type_long_double }, | |
345 | { "q56", &builtin_type_long_double }, | |
346 | { "q60", &builtin_type_long_double } | |
347 | }; | |
348 | ||
349 | /* Total number of pseudo registers. */ | |
350 | #define SPARC64_NUM_PSEUDO_REGS \ | |
351 | (sizeof (sparc64_pseudo_register_info) \ | |
352 | / sizeof (sparc64_pseudo_register_info[0])) | |
353 | ||
354 | /* Return the name of register REGNUM. */ | |
355 | ||
356 | static const char * | |
357 | sparc64_register_name (int regnum) | |
358 | { | |
359 | if (regnum >= 0 && regnum < SPARC64_NUM_REGS) | |
360 | return sparc64_register_info[regnum].name; | |
361 | ||
362 | if (regnum >= SPARC64_NUM_REGS | |
363 | && regnum < SPARC64_NUM_REGS + SPARC64_NUM_PSEUDO_REGS) | |
364 | return sparc64_pseudo_register_info[regnum - SPARC64_NUM_REGS].name; | |
365 | ||
366 | return NULL; | |
367 | } | |
368 | ||
369 | /* Return the GDB type object for the "standard" data type of data in | |
370 | register REGNUM. */ | |
371 | ||
372 | static struct type * | |
373 | sparc64_register_type (struct gdbarch *gdbarch, int regnum) | |
374 | { | |
375 | if (regnum >= SPARC64_NUM_REGS | |
376 | && regnum < SPARC64_NUM_REGS + SPARC64_NUM_PSEUDO_REGS) | |
377 | return *sparc64_pseudo_register_info[regnum - SPARC64_NUM_REGS].type; | |
378 | ||
379 | gdb_assert (regnum >= 0 && regnum < SPARC64_NUM_REGS); | |
380 | return *sparc64_register_info[regnum].type; | |
381 | } | |
382 | ||
383 | static void | |
384 | sparc64_pseudo_register_read (struct gdbarch *gdbarch, | |
385 | struct regcache *regcache, | |
386 | int regnum, void *buf) | |
387 | { | |
388 | gdb_assert (regnum >= SPARC64_NUM_REGS); | |
389 | ||
390 | if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM) | |
391 | { | |
392 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC64_D0_REGNUM); | |
393 | regcache_raw_read (regcache, regnum, buf); | |
394 | regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); | |
395 | } | |
396 | else if (regnum >= SPARC64_D32_REGNUM && regnum <= SPARC64_D62_REGNUM) | |
397 | { | |
398 | regnum = SPARC64_F32_REGNUM + (regnum - SPARC64_D32_REGNUM); | |
399 | regcache_raw_read (regcache, regnum, buf); | |
400 | } | |
401 | else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q28_REGNUM) | |
402 | { | |
403 | regnum = SPARC_F0_REGNUM + 4 * (regnum - SPARC64_Q0_REGNUM); | |
404 | regcache_raw_read (regcache, regnum, buf); | |
405 | regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); | |
406 | regcache_raw_read (regcache, regnum + 2, ((char *)buf) + 8); | |
407 | regcache_raw_read (regcache, regnum + 3, ((char *)buf) + 12); | |
408 | } | |
409 | else if (regnum >= SPARC64_Q32_REGNUM && regnum <= SPARC64_Q60_REGNUM) | |
410 | { | |
411 | regnum = SPARC64_F32_REGNUM + 2 * (regnum - SPARC64_Q32_REGNUM); | |
412 | regcache_raw_read (regcache, regnum, buf); | |
413 | regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 8); | |
414 | } | |
415 | else if (regnum == SPARC64_CWP_REGNUM | |
416 | || regnum == SPARC64_PSTATE_REGNUM | |
417 | || regnum == SPARC64_ASI_REGNUM | |
418 | || regnum == SPARC64_CCR_REGNUM) | |
419 | { | |
420 | ULONGEST state; | |
421 | ||
422 | regcache_raw_read_unsigned (regcache, SPARC64_STATE_REGNUM, &state); | |
423 | switch (regnum) | |
424 | { | |
425 | SPARC64_CWP_REGNUM: | |
426 | state = (state >> 0) & ((1 << 5) - 1); | |
427 | break; | |
428 | SPARC64_PSTATE_REGNUM: | |
429 | state = (state >> 8) & ((1 << 12) - 1); | |
430 | break; | |
431 | SPARC64_ASI_REGNUM: | |
432 | state = (state >> 24) & ((1 << 8) - 1); | |
433 | break; | |
434 | SPARC64_CCR_REGNUM: | |
435 | state = (state >> 32) & ((1 << 8) - 1); | |
436 | break; | |
437 | } | |
438 | store_unsigned_integer (buf, 8, state); | |
439 | } | |
440 | } | |
441 | ||
442 | static void | |
443 | sparc64_pseudo_register_write (struct gdbarch *gdbarch, | |
444 | struct regcache *regcache, | |
445 | int regnum, const void *buf) | |
446 | { | |
447 | gdb_assert (regnum >= SPARC64_NUM_REGS); | |
448 | ||
449 | if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM) | |
450 | { | |
451 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC64_D0_REGNUM); | |
452 | regcache_raw_write (regcache, regnum, buf); | |
453 | regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); | |
454 | } | |
455 | else if (regnum >= SPARC64_D32_REGNUM && regnum <= SPARC64_D62_REGNUM) | |
456 | { | |
457 | regnum = SPARC64_F32_REGNUM + (regnum - SPARC64_D32_REGNUM); | |
458 | regcache_raw_write (regcache, regnum, buf); | |
459 | } | |
460 | else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q28_REGNUM) | |
461 | { | |
462 | regnum = SPARC_F0_REGNUM + 4 * (regnum - SPARC64_Q0_REGNUM); | |
463 | regcache_raw_write (regcache, regnum, buf); | |
464 | regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); | |
465 | regcache_raw_write (regcache, regnum + 2, ((const char *)buf) + 8); | |
466 | regcache_raw_write (regcache, regnum + 3, ((const char *)buf) + 12); | |
467 | } | |
468 | else if (regnum >= SPARC64_Q32_REGNUM && regnum <= SPARC64_Q60_REGNUM) | |
469 | { | |
470 | regnum = SPARC64_F32_REGNUM + 2 * (regnum - SPARC64_Q32_REGNUM); | |
471 | regcache_raw_write (regcache, regnum, buf); | |
472 | regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 8); | |
473 | } | |
474 | } | |
475 | ||
476 | /* Use the program counter to determine the contents and size of a | |
477 | breakpoint instruction. Return a pointer to a string of bytes that | |
478 | encode a breakpoint instruction, store the length of the string in | |
479 | *LEN and optionally adjust *PC to point to the correct memory | |
480 | location for inserting the breakpoint. */ | |
481 | ||
482 | static const unsigned char * | |
483 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) | |
484 | { | |
485 | static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; | |
486 | ||
487 | *len = sizeof (break_insn); | |
488 | return break_insn; | |
489 | } | |
490 | \f | |
491 | ||
492 | struct sparc64_frame_cache | |
493 | { | |
494 | /* Base address. */ | |
495 | CORE_ADDR base; | |
496 | CORE_ADDR pc; | |
497 | ||
498 | /* Do we have a frame? */ | |
499 | int frameless_p; | |
500 | }; | |
501 | ||
502 | /* Allocate and initialize a frame cache. */ | |
503 | ||
504 | static struct sparc64_frame_cache * | |
505 | sparc64_alloc_frame_cache (void) | |
506 | { | |
507 | struct sparc64_frame_cache *cache; | |
508 | int i; | |
509 | ||
510 | cache = FRAME_OBSTACK_ZALLOC (struct sparc64_frame_cache); | |
511 | ||
512 | /* Base address. */ | |
513 | cache->base = 0; | |
514 | cache->pc = 0; | |
515 | ||
516 | /* Frameless until proven otherwise. */ | |
517 | cache->frameless_p = 1; | |
518 | ||
519 | return cache; | |
520 | } | |
521 | ||
522 | static CORE_ADDR | |
523 | sparc64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
524 | struct sparc64_frame_cache *cache) | |
525 | { | |
526 | unsigned long insn; | |
527 | ||
528 | if (current_pc <= pc) | |
529 | return current_pc; | |
530 | ||
531 | /* Check whether the function starts with a SAVE instruction. */ | |
532 | insn = sparc_fetch_instruction (pc); | |
533 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
534 | { | |
535 | cache->frameless_p = 0; | |
536 | return pc + 4; | |
537 | } | |
538 | ||
539 | return pc; | |
540 | } | |
541 | ||
542 | static CORE_ADDR | |
543 | sparc64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
544 | { | |
545 | return frame_unwind_register_unsigned (next_frame, SPARC64_PC_REGNUM); | |
546 | } | |
547 | ||
548 | /* Return PC of first real instruction of the function starting at | |
549 | START_PC. */ | |
550 | ||
551 | static CORE_ADDR | |
552 | sparc64_skip_prologue (CORE_ADDR start_pc) | |
553 | { | |
554 | struct symtab_and_line sal; | |
555 | CORE_ADDR func_start, func_end; | |
556 | struct sparc64_frame_cache cache; | |
557 | ||
558 | /* This is the preferred method, find the end of the prologue by | |
559 | using the debugging information. */ | |
560 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
561 | { | |
562 | sal = find_pc_line (func_start, 0); | |
563 | ||
564 | if (sal.end < func_end | |
565 | && start_pc <= sal.end) | |
566 | return sal.end; | |
567 | } | |
568 | ||
569 | return sparc64_analyze_prologue (start_pc, 0xffffffffffffffffUL, &cache); | |
570 | } | |
571 | ||
572 | /* Normal frames. */ | |
573 | ||
574 | static struct sparc64_frame_cache * | |
575 | sparc64_frame_cache (struct frame_info *next_frame, void **this_cache) | |
576 | { | |
577 | struct sparc64_frame_cache *cache; | |
578 | ||
579 | if (*this_cache) | |
580 | return *this_cache; | |
581 | ||
582 | cache = sparc64_alloc_frame_cache (); | |
583 | *this_cache = cache; | |
584 | ||
585 | /* In priciple, for normal frames, %fp (%i6) holds the frame | |
586 | pointer, which holds the base address for the current stack | |
587 | frame. */ | |
588 | ||
589 | cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
590 | if (cache->base == 0) | |
591 | return cache; | |
592 | ||
593 | cache->pc = frame_func_unwind (next_frame); | |
594 | if (cache->pc != 0) | |
595 | sparc64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); | |
596 | ||
597 | if (cache->frameless_p) | |
598 | { | |
599 | /* We didn't find a valid frame, which means that CACHE->base | |
600 | currently holds the frame pointer for our calling frame. */ | |
601 | cache->base = frame_unwind_register_unsigned (next_frame, | |
602 | SPARC_SP_REGNUM); | |
603 | } | |
604 | ||
605 | return cache; | |
606 | } | |
607 | ||
608 | static void | |
609 | sparc64_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
610 | struct frame_id *this_id) | |
611 | { | |
612 | struct sparc64_frame_cache *cache = | |
613 | sparc64_frame_cache (next_frame, this_cache); | |
614 | ||
615 | /* This marks the outermost frame. */ | |
616 | if (cache->base == 0) | |
617 | return; | |
618 | ||
619 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
620 | } | |
621 | ||
622 | static void | |
623 | sparc64_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
624 | int regnum, int *optimizedp, | |
625 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
626 | int *realnump, void *valuep) | |
627 | { | |
628 | struct sparc64_frame_cache *cache = | |
629 | sparc64_frame_cache (next_frame, this_cache); | |
630 | ||
631 | if (regnum == SPARC64_PC_REGNUM || regnum == SPARC64_NPC_REGNUM) | |
632 | { | |
633 | *optimizedp = 0; | |
634 | *lvalp = not_lval; | |
635 | *addrp = 0; | |
636 | *realnump = -1; | |
637 | if (valuep) | |
638 | { | |
639 | CORE_ADDR pc = (regnum == SPARC64_NPC_REGNUM) ? 4 : 0; | |
640 | ||
641 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
642 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
643 | store_unsigned_integer (valuep, 8, pc); | |
644 | } | |
645 | return; | |
646 | } | |
647 | ||
648 | /* The previous frame's `local' and `in' registers have been saved | |
649 | in the register save area. */ | |
650 | if (!cache->frameless_p | |
651 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
652 | { | |
653 | *optimizedp = 0; | |
654 | *lvalp = lval_memory; | |
655 | *addrp = cache->base + BIAS + (regnum - SPARC_L0_REGNUM) * 8; | |
656 | *realnump = -1; | |
657 | if (valuep) | |
658 | { | |
659 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
660 | ||
661 | /* Read the value in from memory. */ | |
662 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
663 | } | |
664 | return; | |
665 | } | |
666 | ||
667 | /* The previous frame's `out' registers are accessable as the | |
668 | current frame's `in' registers. */ | |
669 | if (!cache->frameless_p | |
670 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
671 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
672 | ||
673 | frame_register_unwind (next_frame, regnum, | |
674 | optimizedp, lvalp, addrp, realnump, valuep); | |
675 | } | |
676 | ||
677 | static const struct frame_unwind sparc64_frame_unwind = | |
678 | { | |
679 | NORMAL_FRAME, | |
680 | sparc64_frame_this_id, | |
681 | sparc64_frame_prev_register | |
682 | }; | |
683 | ||
684 | static const struct frame_unwind * | |
685 | sparc64_frame_sniffer (struct frame_info *next_frame) | |
686 | { | |
687 | return &sparc64_frame_unwind; | |
688 | } | |
689 | \f | |
690 | ||
691 | static CORE_ADDR | |
692 | sparc64_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
693 | { | |
694 | struct sparc64_frame_cache *cache = | |
695 | sparc64_frame_cache (next_frame, this_cache); | |
696 | ||
697 | /* ??? Should we take BIAS into account here? */ | |
698 | return cache->base; | |
699 | } | |
700 | ||
701 | static const struct frame_base sparc64_frame_base = | |
702 | { | |
703 | &sparc64_frame_unwind, | |
704 | sparc64_frame_base_address, | |
705 | sparc64_frame_base_address, | |
706 | sparc64_frame_base_address | |
707 | }; | |
708 | ||
709 | static struct frame_id | |
710 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
711 | { | |
712 | CORE_ADDR sp; | |
713 | ||
714 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); | |
715 | return frame_id_build (sp, frame_pc_unwind (next_frame)); | |
716 | } | |
717 | \f | |
718 | /* Check whether TYPE must be 16-byte aligned. */ | |
719 | ||
720 | static int | |
721 | sparc64_16_byte_align_p (struct type *type) | |
722 | { | |
723 | if (sparc64_floating_p (type) && TYPE_LENGTH (type) == 16) | |
724 | return 1; | |
725 | ||
726 | if (sparc64_structure_or_union_p (type)) | |
727 | { | |
728 | int i; | |
729 | ||
730 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
731 | if (sparc64_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
732 | return 1; | |
733 | } | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
738 | /* Store floating fields of element ELEMENT of an "parameter array" | |
739 | that has type TYPE and is stored at BITPOS in VALBUF in the | |
740 | apropriate registers of REGCACHE. This function can be called | |
741 | recursively and therefore handles floating types in addition to | |
742 | structures. */ | |
743 | ||
744 | static void | |
745 | sparc64_store_floating_fields (struct regcache *regcache, struct type *type, | |
746 | char *valbuf, int element, int bitpos) | |
747 | { | |
748 | gdb_assert (element < 16); | |
749 | ||
750 | if (sparc64_floating_p (type)) | |
751 | { | |
752 | int len = TYPE_LENGTH (type); | |
753 | int regnum; | |
754 | ||
755 | if (len == 16) | |
756 | { | |
757 | gdb_assert (bitpos == 0); | |
758 | gdb_assert ((element % 2) == 0); | |
759 | ||
760 | regnum = SPARC64_Q0_REGNUM + element / 2; | |
761 | regcache_cooked_write (regcache, regnum, valbuf); | |
762 | } | |
763 | else if (len == 8) | |
764 | { | |
765 | gdb_assert (bitpos == 0 || bitpos == 64); | |
766 | ||
767 | regnum = SPARC64_D0_REGNUM + element + bitpos / 64; | |
768 | regcache_cooked_write (regcache, regnum, valbuf + (bitpos / 8)); | |
769 | } | |
770 | else | |
771 | { | |
772 | gdb_assert (len == 4); | |
773 | gdb_assert (bitpos % 32 == 0 && bitpos >= 0 && bitpos < 128); | |
774 | ||
775 | regnum = SPARC_F0_REGNUM + element * 2 + bitpos / 32; | |
776 | regcache_cooked_write (regcache, regnum, valbuf + (bitpos / 8)); | |
777 | } | |
778 | } | |
779 | else if (sparc64_structure_or_union_p (type)) | |
780 | { | |
781 | int i; | |
782 | ||
783 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
784 | sparc64_store_floating_fields (regcache, TYPE_FIELD_TYPE (type, i), | |
785 | valbuf, element, | |
786 | bitpos + TYPE_FIELD_BITPOS (type, i)); | |
787 | } | |
788 | } | |
789 | ||
790 | /* Fetch floating fields from a variable of type TYPE from the | |
791 | appropriate registers for BITPOS in REGCACHE and store it at BITPOS | |
792 | in VALBUF. This function can be called recursively and therefore | |
793 | handles floating types in addition to structures. */ | |
794 | ||
795 | static void | |
796 | sparc64_extract_floating_fields (struct regcache *regcache, struct type *type, | |
797 | char *valbuf, int bitpos) | |
798 | { | |
799 | if (sparc64_floating_p (type)) | |
800 | { | |
801 | int len = TYPE_LENGTH (type); | |
802 | int regnum; | |
803 | ||
804 | if (len == 16) | |
805 | { | |
806 | gdb_assert (bitpos == 0 || bitpos == 128); | |
807 | ||
808 | regnum = SPARC64_Q0_REGNUM + bitpos / 128; | |
809 | regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); | |
810 | } | |
811 | else if (len == 8) | |
812 | { | |
813 | gdb_assert (bitpos % 64 == 0 && bitpos >= 0 && bitpos < 256); | |
814 | ||
815 | regnum = SPARC64_D0_REGNUM + bitpos / 64; | |
816 | regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); | |
817 | } | |
818 | else | |
819 | { | |
820 | gdb_assert (len == 4); | |
821 | gdb_assert (bitpos % 32 == 0 && bitpos >= 0 && bitpos < 256); | |
822 | ||
823 | regnum = SPARC_F0_REGNUM + bitpos / 32; | |
824 | regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); | |
825 | } | |
826 | } | |
827 | else if (sparc64_structure_or_union_p (type)) | |
828 | { | |
829 | int i; | |
830 | ||
831 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
832 | sparc64_extract_floating_fields (regcache, TYPE_FIELD_TYPE (type, i), | |
833 | valbuf, | |
834 | bitpos + TYPE_FIELD_BITPOS (type, i)); | |
835 | } | |
836 | } | |
837 | ||
838 | /* Store the NARGS arguments ARGS and STRUCT_ADDR (if STRUCT_RETURN is | |
839 | non-zero) in REGCACHE and on the stack (starting from address SP). */ | |
840 | ||
841 | static CORE_ADDR | |
842 | sparc64_store_arguments (struct regcache *regcache, int nargs, | |
843 | struct value **args, CORE_ADDR sp, | |
844 | int struct_return, CORE_ADDR struct_addr) | |
845 | { | |
846 | /* Number of extended words in the "parameter array". */ | |
847 | int num_elements = 0; | |
848 | int element = 0; | |
849 | int i; | |
850 | ||
851 | /* Take BIAS into account. */ | |
852 | sp += BIAS; | |
853 | ||
854 | /* First we calculate the number of extended words in the "parameter | |
855 | array". While doing so we also convert some of the arguments. */ | |
856 | ||
857 | if (struct_return) | |
858 | num_elements++; | |
859 | ||
860 | for (i = 0; i < nargs; i++) | |
861 | { | |
862 | struct type *type = VALUE_TYPE (args[i]); | |
863 | int len = TYPE_LENGTH (type); | |
864 | ||
865 | if (sparc64_structure_or_union_p (type)) | |
866 | { | |
867 | /* Structure or Union arguments. */ | |
868 | if (len <= 16) | |
869 | { | |
870 | if (num_elements % 2 && sparc64_16_byte_align_p (type)) | |
871 | num_elements++; | |
872 | num_elements += ((len + 7) / 8); | |
873 | } | |
874 | else | |
875 | { | |
876 | /* The psABI says that "Structures or unions larger than | |
877 | sixteen bytes are copied by the caller and passed | |
878 | indirectly; the caller will pass the address of a | |
879 | correctly aligned structure value. This sixty-four | |
880 | bit address will occupy one word in the parameter | |
881 | array, and may be promoted to an %o register like any | |
882 | other pointer value." Allocate memory for these | |
883 | values on the stack. */ | |
884 | sp -= len; | |
885 | ||
886 | /* Use 16-byte alignment for these values. That's | |
887 | always correct, and wasting a few bytes shouldn't be | |
888 | a problem. */ | |
889 | sp &= ~0xf; | |
890 | ||
891 | write_memory (sp, VALUE_CONTENTS (args[i]), len); | |
892 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); | |
893 | num_elements++; | |
894 | } | |
895 | } | |
896 | else if (sparc64_floating_p (type)) | |
897 | { | |
898 | /* Floating arguments. */ | |
899 | ||
900 | if (len == 16) | |
901 | { | |
902 | /* The psABI says that "Each quad-precision parameter | |
903 | value will be assigned to two extended words in the | |
904 | parameter array. */ | |
905 | num_elements += 2; | |
906 | ||
907 | /* The psABI says that "Long doubles must be | |
908 | quad-aligned, and thus a hole might be introduced | |
909 | into the parameter array to force alignment." Skip | |
910 | an element if necessary. */ | |
911 | if (num_elements % 2) | |
912 | num_elements++; | |
913 | } | |
914 | else | |
915 | num_elements++; | |
916 | } | |
917 | else | |
918 | { | |
919 | /* Integral and pointer arguments. */ | |
920 | gdb_assert (sparc64_integral_or_pointer_p (type)); | |
921 | ||
922 | /* The psABI says that "Each argument value of integral type | |
923 | smaller than an extended word will be widened by the | |
924 | caller to an extended word according to the signed-ness | |
925 | of the argument type." */ | |
926 | if (len < 8) | |
927 | args[i] = value_cast (builtin_type_int64, args[i]); | |
928 | num_elements++; | |
929 | } | |
930 | } | |
931 | ||
932 | /* Allocate the "parameter array". */ | |
933 | sp -= num_elements * 8; | |
934 | ||
935 | /* The psABI says that "Every stack frame must be 16-byte aligned." */ | |
936 | sp &= ~0xf; | |
937 | ||
938 | /* Now we store the arguments in to the "paramater array". Some | |
939 | Integer or Pointer arguments and Structure or Union arguments | |
940 | will be passed in %o registers. Some Floating arguments and | |
941 | floating members of structures are passed in floating-point | |
942 | registers. However, for functions with variable arguments, | |
943 | floating arguments are stored in an %0 register, and for | |
944 | functions without a prototype floating arguments are stored in | |
945 | both a floating-point and an %o registers, or a floating-point | |
946 | register and memory. To simplify the logic here we always pass | |
947 | arguments in memory, an %o register, and a floating-point | |
948 | register if appropriate. This should be no problem since the | |
949 | contents of any unused memory or registers in the "parameter | |
950 | array" are undefined. */ | |
951 | ||
952 | if (struct_return) | |
953 | { | |
954 | regcache_cooked_write_unsigned (regcache, SPARC_O0_REGNUM, struct_addr); | |
955 | element++; | |
956 | } | |
957 | ||
958 | for (i = 0; i < nargs; i++) | |
959 | { | |
960 | char *valbuf = VALUE_CONTENTS (args[i]); | |
961 | struct type *type = VALUE_TYPE (args[i]); | |
962 | int len = TYPE_LENGTH (type); | |
963 | int regnum = -1; | |
964 | char buf[16]; | |
965 | ||
966 | if (sparc64_structure_or_union_p (type)) | |
967 | { | |
968 | /* Structure or Union arguments. */ | |
969 | gdb_assert (len <= 16); | |
970 | memset (buf, 0, sizeof (buf)); | |
971 | valbuf = memcpy (buf, valbuf, len); | |
972 | ||
973 | if (element % 2 && sparc64_16_byte_align_p (type)) | |
974 | element++; | |
975 | ||
976 | if (element < 6) | |
977 | { | |
978 | regnum = SPARC_O0_REGNUM + element; | |
979 | if (len > 8 && element < 5) | |
980 | regcache_cooked_write (regcache, regnum + 1, valbuf + 8); | |
981 | } | |
982 | ||
983 | if (element < 16) | |
984 | sparc64_store_floating_fields (regcache, type, valbuf, element, 0); | |
985 | } | |
986 | else if (sparc64_floating_p (type)) | |
987 | { | |
988 | /* Floating arguments. */ | |
989 | if (len == 16) | |
990 | { | |
991 | if (element % 2) | |
992 | element++; | |
993 | if (element < 16) | |
994 | regnum = SPARC64_Q0_REGNUM + element / 2; | |
995 | } | |
996 | else if (len == 8) | |
997 | { | |
998 | if (element < 16) | |
999 | regnum = SPARC64_D0_REGNUM + element; | |
1000 | } | |
1001 | else | |
1002 | { | |
1003 | /* The psABI says "Each single-precision parameter value | |
1004 | will be assigned to one extended word in the | |
1005 | parameter array, and right-justified within that | |
1006 | word; the left half (even floatregister) is | |
1007 | undefined." Even though the psABI says that "the | |
1008 | left half is undefined", set it to zero here. */ | |
1009 | memset (buf, 0, 4); | |
1010 | valbuf = memcpy (buf + 4, valbuf, 4); | |
1011 | len = 8; | |
1012 | if (element < 16) | |
1013 | regnum = SPARC64_D0_REGNUM; | |
1014 | } | |
1015 | } | |
1016 | else | |
1017 | { | |
1018 | /* Integral and pointer arguments. */ | |
1019 | gdb_assert (len == 8); | |
1020 | if (element < 6) | |
1021 | regnum = SPARC_O0_REGNUM + element; | |
1022 | } | |
1023 | ||
1024 | if (regnum != -1) | |
1025 | { | |
1026 | regcache_cooked_write (regcache, regnum, valbuf); | |
1027 | ||
1028 | /* If we're storing the value in a floating-point register, | |
1029 | also store it in the corresponding %0 register(s). */ | |
1030 | if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D10_REGNUM) | |
1031 | { | |
1032 | gdb_assert (element < 6); | |
1033 | regnum = SPARC_O0_REGNUM + element; | |
1034 | regcache_cooked_write (regcache, regnum, valbuf); | |
1035 | } | |
1036 | else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q8_REGNUM) | |
1037 | { | |
1038 | gdb_assert (element < 6); | |
1039 | regnum = SPARC_O0_REGNUM + element; | |
1040 | regcache_cooked_write (regcache, regnum, valbuf); | |
1041 | regcache_cooked_write (regcache, regnum + 1, valbuf); | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | /* Always store the argument in memeory. */ | |
1046 | write_memory (sp + element * 8, valbuf, len); | |
1047 | element += ((len + 7) / 8); | |
1048 | } | |
1049 | ||
1050 | gdb_assert (element == num_elements); | |
1051 | ||
1052 | /* Take BIAS into account. */ | |
1053 | sp -= BIAS; | |
1054 | return sp; | |
1055 | } | |
1056 | ||
1057 | static CORE_ADDR | |
1058 | sparc64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
1059 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1060 | int nargs, struct value **args, CORE_ADDR sp, | |
1061 | int struct_return, CORE_ADDR struct_addr) | |
1062 | { | |
1063 | /* Set return address. */ | |
1064 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, bp_addr - 8); | |
1065 | ||
1066 | /* Set up function arguments. */ | |
1067 | sp = sparc64_store_arguments (regcache, nargs, args, sp, | |
1068 | struct_return, struct_addr); | |
1069 | ||
1070 | /* Allocate the register save area. */ | |
1071 | sp -= 16 * 8; | |
1072 | ||
1073 | /* Stack should be 16-byte aligned at this point. */ | |
1074 | gdb_assert (sp % 16 == 0); | |
1075 | ||
1076 | /* Finally, update the stack pointer. */ | |
1077 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
1078 | ||
1079 | return sp; | |
1080 | } | |
1081 | \f | |
1082 | ||
1083 | /* Extract from an array REGBUF containing the (raw) register state, a | |
1084 | function return value of TYPE, and copy that into VALBUF. */ | |
1085 | ||
1086 | static void | |
1087 | sparc64_extract_return_value (struct type *type, struct regcache *regcache, | |
1088 | void *valbuf) | |
1089 | { | |
1090 | int len = TYPE_LENGTH (type); | |
1091 | char buf[32]; | |
1092 | int i; | |
1093 | ||
1094 | if (sparc64_structure_or_union_p (type)) | |
1095 | { | |
1096 | /* Structure or Union return values. */ | |
1097 | gdb_assert (len <= 32); | |
1098 | ||
1099 | for (i = 0; i < ((len + 7) / 8); i++) | |
1100 | regcache_cooked_read (regcache, SPARC_O0_REGNUM + i, buf + i * 8); | |
1101 | if (TYPE_CODE (type) != TYPE_CODE_UNION) | |
1102 | sparc64_extract_floating_fields (regcache, type, buf, 0); | |
1103 | memcpy (valbuf, buf, len); | |
1104 | } | |
1105 | else if (sparc64_floating_p (type)) | |
1106 | { | |
1107 | /* Floating return values. */ | |
1108 | for (i = 0; i < len / 4; i++) | |
1109 | regcache_cooked_read (regcache, SPARC_F0_REGNUM + i, buf + i * 4); | |
1110 | memcpy (valbuf, buf, len); | |
1111 | } | |
1112 | else | |
1113 | { | |
1114 | /* Integral and pointer return values. */ | |
1115 | gdb_assert (sparc64_integral_or_pointer_p (type)); | |
1116 | ||
1117 | /* Just stripping off any unused bytes should preserve the | |
1118 | signed-ness just fine. */ | |
1119 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); | |
1120 | memcpy (valbuf, buf + 8 - len, len); | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | /* Write into the appropriate registers a function return value stored | |
1125 | in VALBUF of type TYPE. */ | |
1126 | ||
1127 | static void | |
1128 | sparc64_store_return_value (struct type *type, struct regcache *regcache, | |
1129 | const void *valbuf) | |
1130 | { | |
1131 | int len = TYPE_LENGTH (type); | |
1132 | char buf[16]; | |
1133 | int i; | |
1134 | ||
1135 | if (sparc64_structure_or_union_p (type)) | |
1136 | { | |
1137 | /* Structure or Union return values. */ | |
1138 | gdb_assert (len <= 32); | |
1139 | ||
1140 | /* Simplify matters by storing the complete value (including | |
1141 | floating members) into %o0 and %o1. Floating members are | |
1142 | also store in the appropriate floating-point registers. */ | |
1143 | memset (buf, 0, sizeof (buf)); | |
1144 | memcpy (buf, valbuf, len); | |
1145 | for (i = 0; i < ((len + 7) / 8); i++) | |
1146 | regcache_cooked_write (regcache, SPARC_O0_REGNUM + i, buf + i * 4); | |
1147 | if (TYPE_CODE (type) != TYPE_CODE_UNION) | |
1148 | sparc64_store_floating_fields (regcache, type, buf, 0, 0); | |
1149 | } | |
1150 | else if (sparc64_floating_p (type)) | |
1151 | { | |
1152 | /* Floating return values. */ | |
1153 | memcpy (buf, valbuf, len); | |
1154 | for (i = 0; i < len / 4; i++) | |
1155 | regcache_cooked_write (regcache, SPARC_F0_REGNUM + i, buf + i * 4); | |
1156 | } | |
1157 | else | |
1158 | { | |
1159 | /* Integral and pointer return values. */ | |
1160 | gdb_assert (sparc64_integral_or_pointer_p (type)); | |
1161 | ||
1162 | /* ??? Do we need to do any sign-extension here? */ | |
1163 | memset (buf, 0, 8); | |
1164 | memcpy (buf + 8 - len, valbuf, len); | |
1165 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); | |
1166 | } | |
1167 | } | |
1168 | ||
1169 | /* Extract from REGCACHE, which contains the (raw) register state, the | |
1170 | address in which a function should return its structure value, as a | |
1171 | CORE_ADDR. */ | |
1172 | ||
1173 | static CORE_ADDR | |
1174 | sparc_extract_struct_value_address (struct regcache *regcache) | |
1175 | { | |
1176 | ULONGEST addr; | |
1177 | ||
1178 | regcache_cooked_read_unsigned (regcache, SPARC_O0_REGNUM, &addr); | |
1179 | return addr; | |
1180 | } | |
1181 | ||
1182 | static int | |
1183 | sparc64_use_struct_convention (int gcc_p, struct type *type) | |
1184 | { | |
1185 | /* Structure and union types up to 32 bytes in size are returned in | |
1186 | registers. */ | |
1187 | return (TYPE_LENGTH (type) > 32); | |
1188 | } | |
1189 | ||
1190 | \f | |
1191 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1192 | and most operating systems don't implement it either, so we provide | |
1193 | software single-step mechanism. */ | |
1194 | ||
1195 | static CORE_ADDR | |
1196 | sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc) | |
1197 | { | |
1198 | unsigned long insn = sparc_fetch_instruction (pc); | |
1199 | int conditional_p = X_COND (insn) & 0x7; | |
1200 | int branch_p = 0; | |
1201 | long offset = 0; /* Must be signed for sign-extend. */ | |
1202 | ||
1203 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) | |
1204 | { | |
1205 | /* Branch on Integer Register with Prediction (BPr). */ | |
1206 | branch_p = 1; | |
1207 | conditional_p = 1; | |
1208 | } | |
1209 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) | |
1210 | { | |
1211 | /* Branch on Floating-Point Condition Codes (FBfcc). */ | |
1212 | branch_p = 1; | |
1213 | offset = 4 * X_DISP22 (insn); | |
1214 | } | |
1215 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) | |
1216 | { | |
1217 | /* Branch on Floating-Point Condition Codes with Prediction | |
1218 | (FBPfcc). */ | |
1219 | branch_p = 1; | |
1220 | offset = 4 * X_DISP19 (insn); | |
1221 | } | |
1222 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1223 | { | |
1224 | /* Branch on Integer Condition Codes (Bicc). */ | |
1225 | branch_p = 1; | |
1226 | offset = 4 * X_DISP22 (insn); | |
1227 | } | |
1228 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
1229 | { | |
1230 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ | |
1231 | branch_p = 1; | |
1232 | offset = 4 * X_DISP19 (insn); | |
1233 | } | |
1234 | ||
1235 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1236 | ||
1237 | /* FIXME: Handle the Trap instruction. */ | |
1238 | ||
1239 | if (branch_p) | |
1240 | { | |
1241 | if (conditional_p) | |
1242 | { | |
1243 | /* For conditional branches, return nPC + 4 iff the annul | |
1244 | bit is 1. */ | |
1245 | return (X_A (insn) ? *npc + 4 : 0); | |
1246 | } | |
1247 | else | |
1248 | { | |
1249 | /* For unconditional branches, return the target if its | |
1250 | specified condition is "always" and return nPC + 4 if the | |
1251 | condition is "never". If the annul bit is 1, set *NPC to | |
1252 | zero. */ | |
1253 | if (X_COND (insn) == 0x0) | |
1254 | pc = *npc, offset = 4; | |
1255 | if (X_A (insn)) | |
1256 | *npc = 0; | |
1257 | ||
1258 | gdb_assert (offset != 0); | |
1259 | return pc + offset; | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | void | |
1267 | sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1268 | { | |
1269 | static CORE_ADDR npc, nnpc; | |
1270 | static char npc_save[4], nnpc_save[4]; | |
1271 | ||
1272 | if (insert_breakpoints_p) | |
1273 | { | |
1274 | CORE_ADDR pc; | |
1275 | ||
1276 | gdb_assert (npc == 0); | |
1277 | gdb_assert (nnpc == 0); | |
1278 | ||
1279 | pc = sparc_address_from_register (SPARC64_PC_REGNUM); | |
1280 | npc = sparc_address_from_register (SPARC64_NPC_REGNUM); | |
1281 | ||
1282 | /* Analyze the instruction at PC. */ | |
1283 | nnpc = sparc_analyze_control_transfer (pc, &npc); | |
1284 | if (npc != 0) | |
1285 | target_insert_breakpoint (npc, npc_save); | |
1286 | if (nnpc != 0) | |
1287 | target_insert_breakpoint (nnpc, nnpc_save); | |
1288 | ||
1289 | /* Assert that we have set at least one breakpoint. */ | |
1290 | gdb_assert (npc != 0 || nnpc != 0); | |
1291 | } | |
1292 | else | |
1293 | { | |
1294 | if (npc != 0) | |
1295 | target_remove_breakpoint (npc, npc_save); | |
1296 | if (nnpc != 0) | |
1297 | target_remove_breakpoint (nnpc, nnpc_save); | |
1298 | ||
1299 | npc = 0; | |
1300 | nnpc = 0; | |
1301 | } | |
1302 | } | |
1303 | \f | |
1304 | ||
1305 | static struct gdbarch * | |
1306 | sparc64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1307 | { | |
1308 | struct gdbarch_tdep *tdep; | |
1309 | struct gdbarch *gdbarch; | |
1310 | ||
1311 | /* If there is already a candidate, use it. */ | |
1312 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1313 | if (arches != NULL) | |
1314 | return arches->gdbarch; | |
1315 | ||
1316 | /* Allocate space for the new architecture. */ | |
1317 | tdep = XMALLOC (struct gdbarch_tdep); | |
1318 | gdbarch = gdbarch_alloc (&info, tdep); | |
1319 | ||
1320 | set_gdbarch_long_bit (gdbarch, 64); | |
1321 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1322 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1323 | set_gdbarch_long_double_bit (gdbarch, 128); | |
1324 | ||
1325 | set_gdbarch_num_regs (gdbarch, SPARC64_NUM_REGS); | |
1326 | set_gdbarch_register_name (gdbarch, sparc64_register_name); | |
1327 | set_gdbarch_register_type (gdbarch, sparc64_register_type); | |
1328 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC64_NUM_PSEUDO_REGS); | |
1329 | set_gdbarch_pseudo_register_read (gdbarch, sparc64_pseudo_register_read); | |
1330 | set_gdbarch_pseudo_register_write (gdbarch, sparc64_pseudo_register_write); | |
1331 | ||
1332 | /* Register numbers of various important registers. */ | |
1333 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1334 | set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM); /* %pc */ | |
1335 | set_gdbarch_npc_regnum (gdbarch, SPARC64_NPC_REGNUM); | |
1336 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1337 | ||
1338 | /* Call dummy code. */ | |
1339 | set_gdbarch_push_dummy_call (gdbarch, sparc64_push_dummy_call); | |
1340 | ||
1341 | set_gdbarch_extract_return_value (gdbarch, sparc64_extract_return_value); | |
1342 | set_gdbarch_store_return_value (gdbarch, sparc64_store_return_value); | |
1343 | set_gdbarch_extract_struct_value_address | |
1344 | (gdbarch, sparc_extract_struct_value_address); | |
1345 | set_gdbarch_use_struct_convention (gdbarch, sparc64_use_struct_convention); | |
1346 | ||
1347 | set_gdbarch_skip_prologue (gdbarch, sparc64_skip_prologue); | |
1348 | ||
1349 | /* Stack grows downward. */ | |
1350 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1351 | ||
1352 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); | |
1353 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
1354 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1355 | ||
1356 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
1357 | ||
1358 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); | |
1359 | ||
1360 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); | |
1361 | ||
1362 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); | |
1363 | ||
1364 | set_gdbarch_unwind_pc (gdbarch, sparc64_unwind_pc); | |
1365 | ||
1366 | frame_base_set_default (gdbarch, &sparc64_frame_base); | |
1367 | ||
1368 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
1369 | gdbarch_init_osabi (info, gdbarch); | |
1370 | ||
1371 | frame_unwind_append_sniffer (gdbarch, sparc64_frame_sniffer); | |
1372 | ||
1373 | return gdbarch; | |
1374 | } | |
1375 | \f | |
1376 | /* Helper functions for dealing with register windows. */ | |
1377 | ||
1378 | static void | |
1379 | sparc_supply_rwindow (CORE_ADDR sp, int regnum) | |
1380 | { | |
1381 | int offset = 0; | |
1382 | char buf[8]; | |
1383 | int i; | |
1384 | ||
1385 | /* Clear out the top half of the temporary buffer, and put the | |
1386 | register value in the bottom half if we're in 64-bit mode. */ | |
1387 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1388 | { | |
1389 | memset (buf, 0, 4); | |
1390 | offset = 4; | |
1391 | } | |
1392 | ||
1393 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1394 | { | |
1395 | if (regnum == i || regnum == -1) | |
1396 | { | |
1397 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1398 | buf + offset, 4); | |
1399 | supply_register (i, buf); | |
1400 | } | |
1401 | } | |
1402 | } | |
1403 | ||
1404 | void | |
1405 | sparc64_supply_rwindow (CORE_ADDR sp, int regnum) | |
1406 | { | |
1407 | if (sp & 1) | |
1408 | { | |
1409 | char buf[8]; | |
1410 | int i; | |
1411 | ||
1412 | /* Registers are 64-bit. */ | |
1413 | sp += BIAS; | |
1414 | ||
1415 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1416 | { | |
1417 | if (regnum == i || regnum == -1) | |
1418 | { | |
1419 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), | |
1420 | buf, sizeof (buf)); | |
1421 | supply_register (i, buf); | |
1422 | } | |
1423 | } | |
1424 | } | |
1425 | else | |
1426 | { | |
1427 | /* Registers are 32-bit. Toss any sign-extension of the stack | |
1428 | pointer. */ | |
1429 | sparc_supply_rwindow (sp & 0xffffffffUL, regnum); | |
1430 | } | |
1431 | } | |
1432 | ||
1433 | static void | |
1434 | sparc_fill_rwindow (CORE_ADDR sp, int regnum) | |
1435 | { | |
1436 | int offset = 0; | |
1437 | char buf[8]; | |
1438 | int i; | |
1439 | ||
1440 | /* Only use the bottom half if we're in 64-bit mode. */ | |
1441 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1442 | offset = 4; | |
1443 | ||
1444 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1445 | { | |
1446 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1447 | { | |
1448 | regcache_collect (i, buf); | |
1449 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), buf, 4); | |
1450 | } | |
1451 | } | |
1452 | } | |
1453 | ||
1454 | void | |
1455 | sparc64_fill_rwindow (CORE_ADDR sp, int regnum) | |
1456 | { | |
1457 | if (sp & 1) | |
1458 | { | |
1459 | char buf[8]; | |
1460 | int i; | |
1461 | ||
1462 | /* Registers are 64-bit. */ | |
1463 | sp += BIAS; | |
1464 | ||
1465 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1466 | { | |
1467 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1468 | { | |
1469 | regcache_collect (i, buf); | |
1470 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), | |
1471 | buf, sizeof (buf)); | |
1472 | } | |
1473 | } | |
1474 | } | |
1475 | else | |
1476 | { | |
1477 | /* Registers are 32-bit. Toss any sign-extension of the stack | |
1478 | pointer. */ | |
1479 | sparc_fill_rwindow (sp & 0xffffffffUL, regnum); | |
1480 | } | |
1481 | } | |
1482 | \f | |
1483 | ||
1484 | /* Provide a prototype to silence -Wmissing-prototypes. */ | |
1485 | void _initialize_sparc64_tdep (void); | |
1486 | ||
1487 | void | |
1488 | _initialize_sparc64_tdep (void) | |
1489 | { | |
1490 | register_gdbarch_init (bfd_arch_sparc, sparc64_gdbarch_init); | |
1491 | } |