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[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
7b6bb8da
JB		 2 Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
771b4502
UW		 4
5 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
6 Based on a port by Sid Manning <sid@us.ibm.com>.
7
8 This file is part of GDB.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
a9762ec7 12 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
a9762ec7 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 22
23#include "defs.h"
24#include "arch-utils.h"
25#include "gdbtypes.h"
26#include "gdbcmd.h"
27#include "gdbcore.h"
28#include "gdb_string.h"
29#include "gdb_assert.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "trad-frame.h"
34#include "symtab.h"
35#include "symfile.h"
36#include "value.h"
37#include "inferior.h"
38#include "dis-asm.h"
39#include "objfiles.h"
40#include "language.h"
41#include "regcache.h"
42#include "reggroups.h"
43#include "floatformat.h"
3285f3fe 44#include "block.h"
dcf52cd8 45#include "observer.h"
ff1a52c6 46#include "infcall.h"
54fcddd0 47#include "dwarf2.h"
8dccd430 48#include "exceptions.h"
771b4502
UW		 49#include "spu-tdep.h"
50
794ac428 51
3285f3fe
UW		 52/* The list of available "set spu " and "show spu " commands. */
53static struct cmd_list_element *setspucmdlist = NULL;
54static struct cmd_list_element *showspucmdlist = NULL;
55
56/* Whether to stop for new SPE contexts. */
57static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 58/* Whether to automatically flush the SW-managed cache. */
59static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 60
61
794ac428
UW		 62/* The tdep structure. */
63struct gdbarch_tdep
64{
85e747d2
UW		 65 /* The spufs ID identifying our address space. */
66 int id;
67
794ac428
UW		 68 /* SPU-specific vector type. */
69 struct type *spu_builtin_type_vec128;
70};
71
72
f2d43c2c 73/* SPU-specific vector type. */
794ac428
UW		 74static struct type *
75spu_builtin_type_vec128 (struct gdbarch *gdbarch)
76{
77 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
78
79 if (!tdep->spu_builtin_type_vec128)
80 {
df4df182 81 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 82 struct type *t;
83
e9bb382b
UW		 84 t = arch_composite_type (gdbarch,
85 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 86 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 87 append_composite_type_field (t, "v2_int64",
df4df182 88 init_vector_type (bt->builtin_int64, 2));
794ac428 89 append_composite_type_field (t, "v4_int32",
df4df182 90 init_vector_type (bt->builtin_int32, 4));
794ac428 91 append_composite_type_field (t, "v8_int16",
df4df182 92 init_vector_type (bt->builtin_int16, 8));
794ac428 93 append_composite_type_field (t, "v16_int8",
df4df182 94 init_vector_type (bt->builtin_int8, 16));
794ac428 95 append_composite_type_field (t, "v2_double",
df4df182 96 init_vector_type (bt->builtin_double, 2));
794ac428 97 append_composite_type_field (t, "v4_float",
df4df182 98 init_vector_type (bt->builtin_float, 4));
794ac428 99
876cecd0 100 TYPE_VECTOR (t) = 1;
794ac428
UW		 101 TYPE_NAME (t) = "spu_builtin_type_vec128";
102
103 tdep->spu_builtin_type_vec128 = t;
104 }
105
106 return tdep->spu_builtin_type_vec128;
107}
108
771b4502 109
23d964e7
UW		 110/* The list of available "info spu " commands. */
111static struct cmd_list_element *infospucmdlist = NULL;
112
771b4502
UW		 113/* Registers. */
114
115static const char *
d93859e2 116spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 117{
118 static char *register_names[] =
119 {
120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
123 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
124 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
125 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
126 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
127 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
128 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
129 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
130 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
131 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
132 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
133 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
134 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
135 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 136 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 137 };
138
139 if (reg_nr < 0)
140 return NULL;
141 if (reg_nr >= sizeof register_names / sizeof *register_names)
142 return NULL;
143
144 return register_names[reg_nr];
145}
146
147static struct type *
148spu_register_type (struct gdbarch *gdbarch, int reg_nr)
149{
150 if (reg_nr < SPU_NUM_GPRS)
794ac428 151 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 152
153 switch (reg_nr)
154 {
155 case SPU_ID_REGNUM:
df4df182 156 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 157
158 case SPU_PC_REGNUM:
0dfff4cb 159 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 160
161 case SPU_SP_REGNUM:
0dfff4cb 162 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 163
23d964e7 164 case SPU_FPSCR_REGNUM:
df4df182 165 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 166
167 case SPU_SRR0_REGNUM:
df4df182 168 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 169
170 case SPU_LSLR_REGNUM:
df4df182 171 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 172
173 case SPU_DECR_REGNUM:
df4df182 174 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 175
176 case SPU_DECR_STATUS_REGNUM:
df4df182 177 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 178
771b4502 179 default:
a73c6dcd 180 internal_error (__FILE__, __LINE__, _("invalid regnum"));
771b4502
UW		 181 }
182}
183
184/* Pseudo registers for preferred slots - stack pointer. */
185
05d1431c 186static enum register_status
23d964e7
UW		 187spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
188 gdb_byte *buf)
189{
e17a4113
UW		 190 struct gdbarch *gdbarch = get_regcache_arch (regcache);
191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
05d1431c 192 enum register_status status;
23d964e7
UW		 193 gdb_byte reg[32];
194 char annex[32];
195 ULONGEST id;
196
05d1431c
PA		 197 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
198 if (status != REG_VALID)
199 return status;
23d964e7
UW		 200 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
201 memset (reg, 0, sizeof reg);
202 target_read (&current_target, TARGET_OBJECT_SPU, annex,
203 reg, 0, sizeof reg);
204
e17a4113 205 store_unsigned_integer (buf, 4, byte_order, strtoulst (reg, NULL, 16));
05d1431c 206 return REG_VALID;
23d964e7
UW		 207}
208
05d1431c 209static enum register_status
771b4502
UW		 210spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
211 int regnum, gdb_byte *buf)
212{
213 gdb_byte reg[16];
23d964e7
UW		 214 char annex[32];
215 ULONGEST id;
05d1431c 216 enum register_status status;
771b4502
UW		 217
218 switch (regnum)
219 {
220 case SPU_SP_REGNUM:
05d1431c
PA		 221 status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
222 if (status != REG_VALID)
223 return status;
771b4502 224 memcpy (buf, reg, 4);
05d1431c 225 return status;
771b4502 226
23d964e7 227 case SPU_FPSCR_REGNUM:
05d1431c
PA		 228 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
229 if (status != REG_VALID)
230 return status;
23d964e7
UW		 231 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
232 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
05d1431c 233 return status;
23d964e7
UW		 234
235 case SPU_SRR0_REGNUM:
05d1431c 236 return spu_pseudo_register_read_spu (regcache, "srr0", buf);
23d964e7
UW		 237
238 case SPU_LSLR_REGNUM:
05d1431c 239 return spu_pseudo_register_read_spu (regcache, "lslr", buf);
23d964e7
UW		 240
241 case SPU_DECR_REGNUM:
05d1431c 242 return spu_pseudo_register_read_spu (regcache, "decr", buf);
23d964e7
UW		 243
244 case SPU_DECR_STATUS_REGNUM:
05d1431c 245 return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
23d964e7 246
771b4502
UW		 247 default:
248 internal_error (__FILE__, __LINE__, _("invalid regnum"));
249 }
250}
251
23d964e7
UW		 252static void
253spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
254 const gdb_byte *buf)
255{
e17a4113
UW		 256 struct gdbarch *gdbarch = get_regcache_arch (regcache);
257 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 258 gdb_byte reg[32];
259 char annex[32];
260 ULONGEST id;
261
262 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
263 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
264 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 265 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7
UW		 266 target_write (&current_target, TARGET_OBJECT_SPU, annex,
267 reg, 0, strlen (reg));
268}
269
771b4502
UW		 270static void
271spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
272 int regnum, const gdb_byte *buf)
273{
274 gdb_byte reg[16];
23d964e7
UW		 275 char annex[32];
276 ULONGEST id;
771b4502
UW		 277
278 switch (regnum)
279 {
280 case SPU_SP_REGNUM:
281 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
282 memcpy (reg, buf, 4);
283 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
284 break;
285
23d964e7
UW		 286 case SPU_FPSCR_REGNUM:
287 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
288 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
289 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
290 break;
291
292 case SPU_SRR0_REGNUM:
293 spu_pseudo_register_write_spu (regcache, "srr0", buf);
294 break;
295
296 case SPU_LSLR_REGNUM:
297 spu_pseudo_register_write_spu (regcache, "lslr", buf);
298 break;
299
300 case SPU_DECR_REGNUM:
301 spu_pseudo_register_write_spu (regcache, "decr", buf);
302 break;
303
304 case SPU_DECR_STATUS_REGNUM:
305 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
306 break;
307
771b4502
UW		 308 default:
309 internal_error (__FILE__, __LINE__, _("invalid regnum"));
310 }
311}
312
313/* Value conversion -- access scalar values at the preferred slot. */
314
9acbedc0
UW		 315static struct value *
316spu_value_from_register (struct type *type, int regnum,
317 struct frame_info *frame)
771b4502 318{
9acbedc0
UW		 319 struct value *value = default_value_from_register (type, regnum, frame);
320 int len = TYPE_LENGTH (type);
771b4502 321
9acbedc0
UW		 322 if (regnum < SPU_NUM_GPRS && len < 16)
323 {
324 int preferred_slot = len < 4 ? 4 - len : 0;
325 set_value_offset (value, preferred_slot);
326 }
771b4502 327
9acbedc0 328 return value;
771b4502
UW		 329}
330
331/* Register groups. */
332
333static int
334spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
335 struct reggroup *group)
336{
337 /* Registers displayed via 'info regs'. */
338 if (group == general_reggroup)
339 return 1;
340
341 /* Registers displayed via 'info float'. */
342 if (group == float_reggroup)
343 return 0;
344
345 /* Registers that need to be saved/restored in order to
346 push or pop frames. */
347 if (group == save_reggroup || group == restore_reggroup)
348 return 1;
349
350 return default_register_reggroup_p (gdbarch, regnum, group);
351}
352
ff1a52c6
UW		 353
354/* Address handling. */
36acd84e 355
85e747d2
UW		 356static int
357spu_gdbarch_id (struct gdbarch *gdbarch)
358{
359 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
360 int id = tdep->id;
361
362 /* The objfile architecture of a standalone SPU executable does not
b021a221 363 provide an SPU ID. Retrieve it from the objfile's relocated
85e747d2
UW		 364 address range in this special case. */
365 if (id == -1
366 && symfile_objfile && symfile_objfile->obfd
367 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
368 && symfile_objfile->sections != symfile_objfile->sections_end)
369 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
370
371 return id;
372}
373
ff1a52c6
UW		 374static int
375spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
376{
377 if (dwarf2_addr_class == 1)
378 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
379 else
380 return 0;
381}
382
383static const char *
384spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
385{
386 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
387 return "__ea";
388 else
389 return NULL;
390}
391
392static int
393spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
394 const char *name, int *type_flags_ptr)
395{
396 if (strcmp (name, "__ea") == 0)
397 {
398 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
399 return 1;
400 }
401 else
402 return 0;
403}
404
85e747d2
UW		 405static void
406spu_address_to_pointer (struct gdbarch *gdbarch,
407 struct type *type, gdb_byte *buf, CORE_ADDR addr)
408{
409 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
410 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
411 SPUADDR_ADDR (addr));
412}
413
36acd84e 414static CORE_ADDR
9898f801
UW		 415spu_pointer_to_address (struct gdbarch *gdbarch,
416 struct type *type, const gdb_byte *buf)
36acd84e 417{
85e747d2 418 int id = spu_gdbarch_id (gdbarch);
e17a4113
UW		 419 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
420 ULONGEST addr
421 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 422
ff1a52c6
UW		 423 /* Do not convert __ea pointers. */
424 if (TYPE_ADDRESS_CLASS_1 (type))
425 return addr;
426
d2ed6730 427 return addr? SPUADDR (id, addr) : 0;
36acd84e
UW		 428}
429
430static CORE_ADDR
431spu_integer_to_address (struct gdbarch *gdbarch,
432 struct type *type, const gdb_byte *buf)
433{
85e747d2 434 int id = spu_gdbarch_id (gdbarch);
36acd84e 435 ULONGEST addr = unpack_long (type, buf);
36acd84e 436
d2ed6730 437 return SPUADDR (id, addr);
36acd84e
UW		 438}
439
771b4502
UW		 440
441/* Decoding SPU instructions. */
442
443enum
444 {
445 op_lqd = 0x34,
446 op_lqx = 0x3c4,
447 op_lqa = 0x61,
448 op_lqr = 0x67,
449 op_stqd = 0x24,
450 op_stqx = 0x144,
451 op_stqa = 0x41,
452 op_stqr = 0x47,
453
454 op_il = 0x081,
455 op_ila = 0x21,
456 op_a = 0x0c0,
457 op_ai = 0x1c,
458
a536c6d7 459 op_selb = 0x8,
771b4502
UW		 460
461 op_br = 0x64,
462 op_bra = 0x60,
463 op_brsl = 0x66,
464 op_brasl = 0x62,
465 op_brnz = 0x42,
466 op_brz = 0x40,
467 op_brhnz = 0x46,
468 op_brhz = 0x44,
469 op_bi = 0x1a8,
470 op_bisl = 0x1a9,
471 op_biz = 0x128,
472 op_binz = 0x129,
473 op_bihz = 0x12a,
474 op_bihnz = 0x12b,
475 };
476
477static int
478is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
479{
480 if ((insn >> 21) == op)
481 {
482 *rt = insn & 127;
483 *ra = (insn >> 7) & 127;
484 *rb = (insn >> 14) & 127;
485 return 1;
486 }
487
488 return 0;
489}
490
491static int
492is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
493{
494 if ((insn >> 28) == op)
495 {
496 *rt = (insn >> 21) & 127;
497 *ra = (insn >> 7) & 127;
498 *rb = (insn >> 14) & 127;
499 *rc = insn & 127;
500 return 1;
501 }
502
503 return 0;
504}
505
506static int
507is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
508{
509 if ((insn >> 21) == op)
510 {
511 *rt = insn & 127;
512 *ra = (insn >> 7) & 127;
513 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
514 return 1;
515 }
516
517 return 0;
518}
519
520static int
521is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
522{
523 if ((insn >> 24) == op)
524 {
525 *rt = insn & 127;
526 *ra = (insn >> 7) & 127;
527 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
528 return 1;
529 }
530
531 return 0;
532}
533
534static int
535is_ri16 (unsigned int insn, int op, int *rt, int *i16)
536{
537 if ((insn >> 23) == op)
538 {
539 *rt = insn & 127;
540 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
541 return 1;
542 }
543
544 return 0;
545}
546
547static int
548is_ri18 (unsigned int insn, int op, int *rt, int *i18)
549{
550 if ((insn >> 25) == op)
551 {
552 *rt = insn & 127;
553 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
554 return 1;
555 }
556
557 return 0;
558}
559
560static int
561is_branch (unsigned int insn, int *offset, int *reg)
562{
563 int rt, i7, i16;
564
565 if (is_ri16 (insn, op_br, &rt, &i16)
566 || is_ri16 (insn, op_brsl, &rt, &i16)
567 || is_ri16 (insn, op_brnz, &rt, &i16)
568 || is_ri16 (insn, op_brz, &rt, &i16)
569 || is_ri16 (insn, op_brhnz, &rt, &i16)
570 || is_ri16 (insn, op_brhz, &rt, &i16))
571 {
572 *reg = SPU_PC_REGNUM;
573 *offset = i16 << 2;
574 return 1;
575 }
576
577 if (is_ri16 (insn, op_bra, &rt, &i16)
578 || is_ri16 (insn, op_brasl, &rt, &i16))
579 {
580 *reg = -1;
581 *offset = i16 << 2;
582 return 1;
583 }
584
585 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
586 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
587 || is_ri7 (insn, op_biz, &rt, reg, &i7)
588 || is_ri7 (insn, op_binz, &rt, reg, &i7)
589 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
590 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
591 {
592 *offset = 0;
593 return 1;
594 }
595
596 return 0;
597}
598
599
600/* Prolog parsing. */
601
602struct spu_prologue_data
603 {
604 /* Stack frame size. -1 if analysis was unsuccessful. */
605 int size;
606
607 /* How to find the CFA. The CFA is equal to SP at function entry. */
608 int cfa_reg;
609 int cfa_offset;
610
611 /* Offset relative to CFA where a register is saved. -1 if invalid. */
612 int reg_offset[SPU_NUM_GPRS];
613 };
614
615static CORE_ADDR
e17a4113
UW		 616spu_analyze_prologue (struct gdbarch *gdbarch,
617 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 618 struct spu_prologue_data *data)
619{
e17a4113 620 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 621 int found_sp = 0;
622 int found_fp = 0;
623 int found_lr = 0;
ce50d78b 624 int found_bc = 0;
771b4502
UW		 625 int reg_immed[SPU_NUM_GPRS];
626 gdb_byte buf[16];
627 CORE_ADDR prolog_pc = start_pc;
628 CORE_ADDR pc;
629 int i;
630
631
632 /* Initialize DATA to default values. */
633 data->size = -1;
634
635 data->cfa_reg = SPU_RAW_SP_REGNUM;
636 data->cfa_offset = 0;
637
638 for (i = 0; i < SPU_NUM_GPRS; i++)
639 data->reg_offset[i] = -1;
640
641 /* Set up REG_IMMED array. This is non-zero for a register if we know its
642 preferred slot currently holds this immediate value. */
643 for (i = 0; i < SPU_NUM_GPRS; i++)
644 reg_immed[i] = 0;
645
646 /* Scan instructions until the first branch.
647
648 The following instructions are important prolog components:
649
650 - The first instruction to set up the stack pointer.
651 - The first instruction to set up the frame pointer.
652 - The first instruction to save the link register.
ce50d78b 653 - The first instruction to save the backchain.
771b4502 654
ce50d78b 655 We return the instruction after the latest of these four,
771b4502
UW		 656 or the incoming PC if none is found. The first instruction
657 to set up the stack pointer also defines the frame size.
658
659 Note that instructions saving incoming arguments to their stack
660 slots are not counted as important, because they are hard to
661 identify with certainty. This should not matter much, because
662 arguments are relevant only in code compiled with debug data,
663 and in such code the GDB core will advance until the first source
664 line anyway, using SAL data.
665
666 For purposes of stack unwinding, we analyze the following types
667 of instructions in addition:
668
669 - Any instruction adding to the current frame pointer.
670 - Any instruction loading an immediate constant into a register.
671 - Any instruction storing a register onto the stack.
672
673 These are used to compute the CFA and REG_OFFSET output. */
674
675 for (pc = start_pc; pc < end_pc; pc += 4)
676 {
677 unsigned int insn;
678 int rt, ra, rb, rc, immed;
679
680 if (target_read_memory (pc, buf, 4))
681 break;
e17a4113 682 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 683
684 /* AI is the typical instruction to set up a stack frame.
685 It is also used to initialize the frame pointer. */
686 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
687 {
688 if (rt == data->cfa_reg && ra == data->cfa_reg)
689 data->cfa_offset -= immed;
690
691 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
692 && !found_sp)
693 {
694 found_sp = 1;
695 prolog_pc = pc + 4;
696
697 data->size = -immed;
698 }
699 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
700 && !found_fp)
701 {
702 found_fp = 1;
703 prolog_pc = pc + 4;
704
705 data->cfa_reg = SPU_FP_REGNUM;
706 data->cfa_offset -= immed;
707 }
708 }
709
710 /* A is used to set up stack frames of size >= 512 bytes.
711 If we have tracked the contents of the addend register,
712 we can handle this as well. */
713 else if (is_rr (insn, op_a, &rt, &ra, &rb))
714 {
715 if (rt == data->cfa_reg && ra == data->cfa_reg)
716 {
717 if (reg_immed[rb] != 0)
718 data->cfa_offset -= reg_immed[rb];
719 else
720 data->cfa_reg = -1; /* We don't know the CFA any more. */
721 }
722
723 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
724 && !found_sp)
725 {
726 found_sp = 1;
727 prolog_pc = pc + 4;
728
729 if (reg_immed[rb] != 0)
730 data->size = -reg_immed[rb];
731 }
732 }
733
734 /* We need to track IL and ILA used to load immediate constants
735 in case they are later used as input to an A instruction. */
736 else if (is_ri16 (insn, op_il, &rt, &immed))
737 {
738 reg_immed[rt] = immed;
12102450
UW		 739
740 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
741 found_sp = 1;
771b4502
UW		 742 }
743
744 else if (is_ri18 (insn, op_ila, &rt, &immed))
745 {
746 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 747
748 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
749 found_sp = 1;
771b4502
UW		 750 }
751
752 /* STQD is used to save registers to the stack. */
753 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
754 {
755 if (ra == data->cfa_reg)
756 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
757
758 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
759 && !found_lr)
760 {
761 found_lr = 1;
762 prolog_pc = pc + 4;
763 }
ce50d78b
UW		 764
765 if (ra == SPU_RAW_SP_REGNUM
766 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
767 && !found_bc)
768 {
769 found_bc = 1;
770 prolog_pc = pc + 4;
771 }
771b4502
UW		 772 }
773
774 /* _start uses SELB to set up the stack pointer. */
775 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
776 {
777 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
778 found_sp = 1;
779 }
780
781 /* We terminate if we find a branch. */
782 else if (is_branch (insn, &immed, &ra))
783 break;
784 }
785
786
787 /* If we successfully parsed until here, and didn't find any instruction
788 modifying SP, we assume we have a frameless function. */
789 if (!found_sp)
790 data->size = 0;
791
792 /* Return cooked instead of raw SP. */
793 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
794 data->cfa_reg = SPU_SP_REGNUM;
795
796 return prolog_pc;
797}
798
799/* Return the first instruction after the prologue starting at PC. */
800static CORE_ADDR
6093d2eb 801spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 802{
803 struct spu_prologue_data data;
e17a4113 804 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 805}
806
807/* Return the frame pointer in use at address PC. */
808static void
a54fba4c
MD		 809spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
810 int *reg, LONGEST *offset)
771b4502
UW		 811{
812 struct spu_prologue_data data;
e17a4113 813 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 814
815 if (data.size != -1 && data.cfa_reg != -1)
816 {
817 /* The 'frame pointer' address is CFA minus frame size. */
818 *reg = data.cfa_reg;
819 *offset = data.cfa_offset - data.size;
820 }
821 else
822 {
c378eb4e 823 /* ??? We don't really know ... */
771b4502
UW		 824 *reg = SPU_SP_REGNUM;
825 *offset = 0;
826 }
827}
828
fe5febed
UW		 829/* Return true if we are in the function's epilogue, i.e. after the
830 instruction that destroyed the function's stack frame.
831
832 1) scan forward from the point of execution:
833 a) If you find an instruction that modifies the stack pointer
834 or transfers control (except a return), execution is not in
835 an epilogue, return.
836 b) Stop scanning if you find a return instruction or reach the
837 end of the function or reach the hard limit for the size of
838 an epilogue.
839 2) scan backward from the point of execution:
840 a) If you find an instruction that modifies the stack pointer,
841 execution *is* in an epilogue, return.
842 b) Stop scanning if you reach an instruction that transfers
843 control or the beginning of the function or reach the hard
844 limit for the size of an epilogue. */
845
846static int
847spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
848{
e17a4113 849 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 850 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
851 bfd_byte buf[4];
852 unsigned int insn;
853 int rt, ra, rb, rc, immed;
854
855 /* Find the search limits based on function boundaries and hard limit.
856 We assume the epilogue can be up to 64 instructions long. */
857
858 const int spu_max_epilogue_size = 64 * 4;
859
860 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
861 return 0;
862
863 if (pc - func_start < spu_max_epilogue_size)
864 epilogue_start = func_start;
865 else
866 epilogue_start = pc - spu_max_epilogue_size;
867
868 if (func_end - pc < spu_max_epilogue_size)
869 epilogue_end = func_end;
870 else
871 epilogue_end = pc + spu_max_epilogue_size;
872
873 /* Scan forward until next 'bi $0'. */
874
875 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
876 {
877 if (target_read_memory (scan_pc, buf, 4))
878 return 0;
e17a4113 879 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 880
881 if (is_branch (insn, &immed, &ra))
882 {
883 if (immed == 0 && ra == SPU_LR_REGNUM)
884 break;
885
886 return 0;
887 }
888
889 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
890 || is_rr (insn, op_a, &rt, &ra, &rb)
891 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
892 {
893 if (rt == SPU_RAW_SP_REGNUM)
894 return 0;
895 }
896 }
897
898 if (scan_pc >= epilogue_end)
899 return 0;
900
901 /* Scan backward until adjustment to stack pointer (R1). */
902
903 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
904 {
905 if (target_read_memory (scan_pc, buf, 4))
906 return 0;
e17a4113 907 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 908
909 if (is_branch (insn, &immed, &ra))
910 return 0;
911
912 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
913 || is_rr (insn, op_a, &rt, &ra, &rb)
914 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
915 {
916 if (rt == SPU_RAW_SP_REGNUM)
917 return 1;
918 }
919 }
920
921 return 0;
922}
923
924
771b4502
UW		 925/* Normal stack frames. */
926
927struct spu_unwind_cache
928{
929 CORE_ADDR func;
930 CORE_ADDR frame_base;
931 CORE_ADDR local_base;
932
933 struct trad_frame_saved_reg *saved_regs;
934};
935
936static struct spu_unwind_cache *
8d998b8f 937spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 938 void **this_prologue_cache)
939{
e17a4113 940 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 941 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 942 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 943 struct spu_unwind_cache *info;
944 struct spu_prologue_data data;
85e747d2 945 CORE_ADDR id = tdep->id;
dcf52cd8 946 gdb_byte buf[16];
771b4502
UW		 947
948 if (*this_prologue_cache)
949 return *this_prologue_cache;
950
951 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
952 *this_prologue_cache = info;
8d998b8f 953 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 954 info->frame_base = 0;
955 info->local_base = 0;
956
957 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 958 info->func = get_frame_func (this_frame);
771b4502
UW		 959 if (info->func == 0)
960 {
961 /* Fall back to using the current PC as frame ID. */
8d998b8f 962 info->func = get_frame_pc (this_frame);
771b4502
UW		 963 data.size = -1;
964 }
965 else
e17a4113
UW		 966 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
967 &data);
771b4502
UW		 968
969 /* If successful, use prologue analysis data. */
970 if (data.size != -1 && data.cfa_reg != -1)
971 {
972 CORE_ADDR cfa;
973 int i;
771b4502
UW		 974
975 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 976 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 977 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 978 cfa = SPUADDR (id, cfa);
771b4502
UW		 979
980 /* Call-saved register slots. */
981 for (i = 0; i < SPU_NUM_GPRS; i++)
982 if (i == SPU_LR_REGNUM
983 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
984 if (data.reg_offset[i] != -1)
985 info->saved_regs[i].addr = cfa - data.reg_offset[i];
986
771b4502
UW		 987 /* Frame bases. */
988 info->frame_base = cfa;
989 info->local_base = cfa - data.size;
990 }
991
992 /* Otherwise, fall back to reading the backchain link. */
993 else
994 {
cdc9523a
UW		 995 CORE_ADDR reg;
996 LONGEST backchain;
13def385 997 ULONGEST lslr;
cdc9523a 998 int status;
771b4502 999
13def385
UW		 1000 /* Get local store limit. */
1001 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1002 if (!lslr)
1003 lslr = (ULONGEST) -1;
1004
771b4502 1005 /* Get the backchain. */
8d998b8f 1006 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 1007 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1008 &backchain);
771b4502
UW		 1009
1010 /* A zero backchain terminates the frame chain. Also, sanity
1011 check against the local store size limit. */
13def385 1012 if (status && backchain > 0 && backchain <= lslr)
771b4502
UW		 1013 {
1014 /* Assume the link register is saved into its slot. */
13def385 1015 if (backchain + 16 <= lslr)
c378eb4e
MS		 1016 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1017 backchain + 16);
771b4502 1018
771b4502 1019 /* Frame bases. */
85e747d2
UW		 1020 info->frame_base = SPUADDR (id, backchain);
1021 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1022 }
1023 }
dcf52cd8 1024
c4891da7
UW		 1025 /* If we didn't find a frame, we cannot determine SP / return address. */
1026 if (info->frame_base == 0)
1027 return info;
1028
dcf52cd8 1029 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1030 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1031 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1032
0a44cb36
UW		 1033 /* Read full contents of the unwound link register in order to
1034 be able to determine the return address. */
dcf52cd8
UW		 1035 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1036 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1037 else
8d998b8f 1038 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1039
0a44cb36
UW		 1040 /* Normally, the return address is contained in the slot 0 of the
1041 link register, and slots 1-3 are zero. For an overlay return,
1042 slot 0 contains the address of the overlay manager return stub,
1043 slot 1 contains the partition number of the overlay section to
1044 be returned to, and slot 2 contains the return address within
1045 that section. Return the latter address in that case. */
e17a4113 1046 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1047 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1048 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1049 else
1050 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1051 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1052
1053 return info;
1054}
1055
1056static void
8d998b8f 1057spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1058 void **this_prologue_cache, struct frame_id *this_id)
1059{
1060 struct spu_unwind_cache *info =
8d998b8f 1061 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1062
1063 if (info->frame_base == 0)
1064 return;
1065
1066 *this_id = frame_id_build (info->frame_base, info->func);
1067}
1068
8d998b8f
UW		 1069static struct value *
1070spu_frame_prev_register (struct frame_info *this_frame,
1071 void **this_prologue_cache, int regnum)
771b4502
UW		 1072{
1073 struct spu_unwind_cache *info
8d998b8f 1074 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1075
1076 /* Special-case the stack pointer. */
1077 if (regnum == SPU_RAW_SP_REGNUM)
1078 regnum = SPU_SP_REGNUM;
1079
8d998b8f 1080 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1081}
1082
1083static const struct frame_unwind spu_frame_unwind = {
1084 NORMAL_FRAME,
8fbca658 1085 default_frame_unwind_stop_reason,
771b4502 1086 spu_frame_this_id,
8d998b8f
UW		 1087 spu_frame_prev_register,
1088 NULL,
1089 default_frame_sniffer
771b4502
UW		 1090};
1091
771b4502 1092static CORE_ADDR
8d998b8f 1093spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1094{
1095 struct spu_unwind_cache *info
8d998b8f 1096 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1097 return info->local_base;
1098}
1099
1100static const struct frame_base spu_frame_base = {
1101 &spu_frame_unwind,
1102 spu_frame_base_address,
1103 spu_frame_base_address,
1104 spu_frame_base_address
1105};
1106
1107static CORE_ADDR
1108spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1109{
85e747d2 1110 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1111 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1112 /* Mask off interrupt enable bit. */
85e747d2 1113 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1114}
1115
1116static CORE_ADDR
1117spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1118{
85e747d2
UW		 1119 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1120 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1121 return SPUADDR (tdep->id, sp);
771b4502
UW		 1122}
1123
118dfbaf 1124static CORE_ADDR
61a1198a 1125spu_read_pc (struct regcache *regcache)
118dfbaf 1126{
85e747d2 1127 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1128 ULONGEST pc;
1129 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1130 /* Mask off interrupt enable bit. */
85e747d2 1131 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1132}
1133
1134static void
61a1198a 1135spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1136{
1137 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1138 ULONGEST old_pc;
1139 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1140 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1141 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1142}
1143
771b4502 1144
cc5f0d61
UW		 1145/* Cell/B.E. cross-architecture unwinder support. */
1146
1147struct spu2ppu_cache
1148{
1149 struct frame_id frame_id;
1150 struct regcache *regcache;
1151};
1152
1153static struct gdbarch *
1154spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1155{
1156 struct spu2ppu_cache *cache = *this_cache;
1157 return get_regcache_arch (cache->regcache);
1158}
1159
1160static void
1161spu2ppu_this_id (struct frame_info *this_frame,
1162 void **this_cache, struct frame_id *this_id)
1163{
1164 struct spu2ppu_cache *cache = *this_cache;
1165 *this_id = cache->frame_id;
1166}
1167
1168static struct value *
1169spu2ppu_prev_register (struct frame_info *this_frame,
1170 void **this_cache, int regnum)
1171{
1172 struct spu2ppu_cache *cache = *this_cache;
1173 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1174 gdb_byte *buf;
1175
1176 buf = alloca (register_size (gdbarch, regnum));
1177 regcache_cooked_read (cache->regcache, regnum, buf);
1178 return frame_unwind_got_bytes (this_frame, regnum, buf);
1179}
1180
1181static int
1182spu2ppu_sniffer (const struct frame_unwind *self,
1183 struct frame_info *this_frame, void **this_prologue_cache)
1184{
1185 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1186 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1187 CORE_ADDR base, func, backchain;
1188 gdb_byte buf[4];
1189
1190 if (gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_spu)
1191 return 0;
1192
1193 base = get_frame_sp (this_frame);
1194 func = get_frame_pc (this_frame);
1195 if (target_read_memory (base, buf, 4))
1196 return 0;
1197 backchain = extract_unsigned_integer (buf, 4, byte_order);
1198
1199 if (!backchain)
1200 {
1201 struct frame_info *fi;
1202
1203 struct spu2ppu_cache *cache
1204 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1205
1206 cache->frame_id = frame_id_build (base + 16, func);
1207
1208 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1209 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1210 break;
1211
1212 if (fi)
1213 {
1214 cache->regcache = frame_save_as_regcache (fi);
1215 *this_prologue_cache = cache;
1216 return 1;
1217 }
1218 else
1219 {
1220 struct regcache *regcache;
1221 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch);
1222 cache->regcache = regcache_dup (regcache);
1223 *this_prologue_cache = cache;
1224 return 1;
1225 }
1226 }
1227
1228 return 0;
1229}
1230
1231static void
1232spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1233{
1234 struct spu2ppu_cache *cache = this_cache;
1235 regcache_xfree (cache->regcache);
1236}
1237
1238static const struct frame_unwind spu2ppu_unwind = {
1239 ARCH_FRAME,
8fbca658 1240 default_frame_unwind_stop_reason,
cc5f0d61
UW		 1241 spu2ppu_this_id,
1242 spu2ppu_prev_register,
1243 NULL,
1244 spu2ppu_sniffer,
1245 spu2ppu_dealloc_cache,
1246 spu2ppu_prev_arch,
1247};
1248
1249
771b4502
UW		 1250/* Function calling convention. */
1251
7b3dc0b7
UW		 1252static CORE_ADDR
1253spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1254{
1255 return sp & ~15;
1256}
1257
87805e63
UW		 1258static CORE_ADDR
1259spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1260 struct value **args, int nargs, struct type *value_type,
1261 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1262 struct regcache *regcache)
1263{
1264 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1265 sp = (sp - 4) & ~15;
1266 /* Store the address of that breakpoint */
1267 *bp_addr = sp;
1268 /* The call starts at the callee's entry point. */
1269 *real_pc = funaddr;
1270
1271 return sp;
1272}
1273
771b4502
UW		 1274static int
1275spu_scalar_value_p (struct type *type)
1276{
1277 switch (TYPE_CODE (type))
1278 {
1279 case TYPE_CODE_INT:
1280 case TYPE_CODE_ENUM:
1281 case TYPE_CODE_RANGE:
1282 case TYPE_CODE_CHAR:
1283 case TYPE_CODE_BOOL:
1284 case TYPE_CODE_PTR:
1285 case TYPE_CODE_REF:
1286 return TYPE_LENGTH (type) <= 16;
1287
1288 default:
1289 return 0;
1290 }
1291}
1292
1293static void
1294spu_value_to_regcache (struct regcache *regcache, int regnum,
1295 struct type *type, const gdb_byte *in)
1296{
1297 int len = TYPE_LENGTH (type);
1298
1299 if (spu_scalar_value_p (type))
1300 {
1301 int preferred_slot = len < 4 ? 4 - len : 0;
1302 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1303 }
1304 else
1305 {
1306 while (len >= 16)
1307 {
1308 regcache_cooked_write (regcache, regnum++, in);
1309 in += 16;
1310 len -= 16;
1311 }
1312
1313 if (len > 0)
1314 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1315 }
1316}
1317
1318static void
1319spu_regcache_to_value (struct regcache *regcache, int regnum,
1320 struct type *type, gdb_byte *out)
1321{
1322 int len = TYPE_LENGTH (type);
1323
1324 if (spu_scalar_value_p (type))
1325 {
1326 int preferred_slot = len < 4 ? 4 - len : 0;
1327 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1328 }
1329 else
1330 {
1331 while (len >= 16)
1332 {
1333 regcache_cooked_read (regcache, regnum++, out);
1334 out += 16;
1335 len -= 16;
1336 }
1337
1338 if (len > 0)
1339 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1340 }
1341}
1342
1343static CORE_ADDR
1344spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1345 struct regcache *regcache, CORE_ADDR bp_addr,
1346 int nargs, struct value **args, CORE_ADDR sp,
1347 int struct_return, CORE_ADDR struct_addr)
1348{
e17a4113 1349 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1350 CORE_ADDR sp_delta;
771b4502
UW		 1351 int i;
1352 int regnum = SPU_ARG1_REGNUM;
1353 int stack_arg = -1;
1354 gdb_byte buf[16];
1355
1356 /* Set the return address. */
1357 memset (buf, 0, sizeof buf);
85e747d2 1358 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1359 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1360
1361 /* If STRUCT_RETURN is true, then the struct return address (in
1362 STRUCT_ADDR) will consume the first argument-passing register.
1363 Both adjust the register count and store that value. */
1364 if (struct_return)
1365 {
1366 memset (buf, 0, sizeof buf);
85e747d2 1367 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1368 regcache_cooked_write (regcache, regnum++, buf);
1369 }
1370
1371 /* Fill in argument registers. */
1372 for (i = 0; i < nargs; i++)
1373 {
1374 struct value *arg = args[i];
1375 struct type *type = check_typedef (value_type (arg));
1376 const gdb_byte *contents = value_contents (arg);
1377 int len = TYPE_LENGTH (type);
1378 int n_regs = align_up (len, 16) / 16;
1379
1380 /* If the argument doesn't wholly fit into registers, it and
1381 all subsequent arguments go to the stack. */
1382 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1383 {
1384 stack_arg = i;
1385 break;
1386 }
1387
1388 spu_value_to_regcache (regcache, regnum, type, contents);
1389 regnum += n_regs;
1390 }
1391
1392 /* Overflow arguments go to the stack. */
1393 if (stack_arg != -1)
1394 {
1395 CORE_ADDR ap;
1396
1397 /* Allocate all required stack size. */
1398 for (i = stack_arg; i < nargs; i++)
1399 {
1400 struct type *type = check_typedef (value_type (args[i]));
1401 sp -= align_up (TYPE_LENGTH (type), 16);
1402 }
1403
1404 /* Fill in stack arguments. */
1405 ap = sp;
1406 for (i = stack_arg; i < nargs; i++)
1407 {
1408 struct value *arg = args[i];
1409 struct type *type = check_typedef (value_type (arg));
1410 int len = TYPE_LENGTH (type);
1411 int preferred_slot;
1412
1413 if (spu_scalar_value_p (type))
1414 preferred_slot = len < 4 ? 4 - len : 0;
1415 else
1416 preferred_slot = 0;
1417
1418 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1419 ap += align_up (TYPE_LENGTH (type), 16);
1420 }
1421 }
1422
1423 /* Allocate stack frame header. */
1424 sp -= 32;
1425
ee82e879
UW		 1426 /* Store stack back chain. */
1427 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1428 target_write_memory (sp, buf, 16);
1429
9ff3afda 1430 /* Finally, update all slots of the SP register. */
e17a4113 1431 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1432 for (i = 0; i < 4; i++)
1433 {
e17a4113
UW		 1434 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1435 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1436 }
1437 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1438
1439 return sp;
1440}
1441
1442static struct frame_id
8d998b8f 1443spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1444{
85e747d2 1445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1446 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1447 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1448 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1449}
1450
1451/* Function return value access. */
1452
1453static enum return_value_convention
c055b101
CV		 1454spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1455 struct type *type, struct regcache *regcache,
1456 gdb_byte *out, const gdb_byte *in)
771b4502
UW		 1457{
1458 enum return_value_convention rvc;
54fcddd0
UW		 1459 int opencl_vector = 0;
1460
598cfb71
UW		 1461 if (func_type)
1462 {
1463 func_type = check_typedef (func_type);
1464
1465 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1466 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1467
1468 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1469 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1470 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1471 && TYPE_VECTOR (type))
1472 opencl_vector = 1;
1473 }
771b4502
UW		 1474
1475 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1476 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1477 else
1478 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1479
1480 if (in)
1481 {
1482 switch (rvc)
1483 {
1484 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1485 if (opencl_vector && TYPE_LENGTH (type) == 2)
1486 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1487 else
1488 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
771b4502
UW		 1489 break;
1490
1491 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1492 error (_("Cannot set function return value."));
771b4502
UW		 1493 break;
1494 }
1495 }
1496 else if (out)
1497 {
1498 switch (rvc)
1499 {
1500 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1501 if (opencl_vector && TYPE_LENGTH (type) == 2)
1502 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1503 else
1504 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
771b4502
UW		 1505 break;
1506
1507 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1508 error (_("Function return value unknown."));
771b4502
UW		 1509 break;
1510 }
1511 }
1512
1513 return rvc;
1514}
1515
1516
1517/* Breakpoints. */
1518
1519static const gdb_byte *
c378eb4e
MS		 1520spu_breakpoint_from_pc (struct gdbarch *gdbarch,
1521 CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1522{
1523 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1524
1525 *lenptr = sizeof breakpoint;
1526 return breakpoint;
1527}
1528
d03285ec
UW		 1529static int
1530spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1531 struct bp_target_info *bp_tgt)
1532{
1533 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1534 that in a combined application, we have some breakpoints inserted in SPU
1535 code, and now the application forks (on the PPU side). GDB common code
1536 will assume that the fork system call copied all breakpoints into the new
1537 process' address space, and that all those copies now need to be removed
1538 (see breakpoint.c:detach_breakpoints).
1539
1540 While this is certainly true for PPU side breakpoints, it is not true
1541 for SPU side breakpoints. fork will clone the SPU context file
1542 descriptors, so that all the existing SPU contexts are in accessible
1543 in the new process. However, the contents of the SPU contexts themselves
1544 are *not* cloned. Therefore the effect of detach_breakpoints is to
1545 remove SPU breakpoints from the *original* SPU context's local store
1546 -- this is not the correct behaviour.
1547
1548 The workaround is to check whether the PID we are asked to remove this
1549 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1550 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1551 true in the context of detach_breakpoints. If so, we simply do nothing.
1552 [ Note that for the fork child process, it does not matter if breakpoints
1553 remain inserted, because those SPU contexts are not runnable anyway --
1554 the Linux kernel allows only the original process to invoke spu_run. */
1555
1556 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1557 return 0;
1558
1559 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1560}
1561
771b4502
UW		 1562
1563/* Software single-stepping support. */
1564
63807e1d 1565static int
0b1b3e42 1566spu_software_single_step (struct frame_info *frame)
771b4502 1567{
a6d9a66e 1568 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1569 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1570 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1571 CORE_ADDR pc, next_pc;
1572 unsigned int insn;
1573 int offset, reg;
1574 gdb_byte buf[4];
13def385 1575 ULONGEST lslr;
771b4502 1576
0b1b3e42 1577 pc = get_frame_pc (frame);
771b4502 1578
e0cd558a
UW		 1579 if (target_read_memory (pc, buf, 4))
1580 return 1;
e17a4113 1581 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1582
13def385
UW		 1583 /* Get local store limit. */
1584 lslr = get_frame_register_unsigned (frame, SPU_LSLR_REGNUM);
1585 if (!lslr)
1586 lslr = (ULONGEST) -1;
1587
e0cd558a
UW		 1588 /* Next sequential instruction is at PC + 4, except if the current
1589 instruction is a PPE-assisted call, in which case it is at PC + 8.
1590 Wrap around LS limit to be on the safe side. */
1591 if ((insn & 0xffffff00) == 0x00002100)
13def385 1592 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
e0cd558a 1593 else
13def385 1594 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
771b4502 1595
6c95b8df
PA		 1596 insert_single_step_breakpoint (gdbarch,
1597 aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1598
e0cd558a
UW		 1599 if (is_branch (insn, &offset, &reg))
1600 {
1601 CORE_ADDR target = offset;
771b4502 1602
e0cd558a 1603 if (reg == SPU_PC_REGNUM)
85e747d2 1604 target += SPUADDR_ADDR (pc);
e0cd558a
UW		 1605 else if (reg != -1)
1606 {
8dccd430
PA		 1607 int optim, unavail;
1608
1609 if (get_frame_register_bytes (frame, reg, 0, 4, buf,
1610 &optim, &unavail))
1611 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
1612 else
1613 {
1614 if (optim)
1615 error (_("Could not determine address of "
1616 "single-step breakpoint."));
1617 if (unavail)
1618 throw_error (NOT_AVAILABLE_ERROR,
1619 _("Could not determine address of "
1620 "single-step breakpoint."));
1621 }
771b4502 1622 }
e0cd558a 1623
13def385 1624 target = target & lslr;
e0cd558a 1625 if (target != next_pc)
6c95b8df 1626 insert_single_step_breakpoint (gdbarch, aspace,
85e747d2 1627 SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1628 }
e6590a1b
UW		 1629
1630 return 1;
771b4502
UW		 1631}
1632
6e3f70d7
UW		 1633
1634/* Longjmp support. */
1635
1636static int
1637spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1638{
e17a4113 1639 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1640 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1641 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1642 gdb_byte buf[4];
1643 CORE_ADDR jb_addr;
8dccd430 1644 int optim, unavail;
6e3f70d7
UW		 1645
1646 /* Jump buffer is pointed to by the argument register $r3. */
8dccd430
PA		 1647 if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1648 &optim, &unavail))
1649 return 0;
1650
e17a4113 1651 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1652 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1653 return 0;
1654
e17a4113 1655 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1656 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1657 return 1;
1658}
1659
1660
85e747d2
UW		 1661/* Disassembler. */
1662
1663struct spu_dis_asm_data
1664{
1665 struct gdbarch *gdbarch;
1666 int id;
1667};
1668
1669static void
1670spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1671{
1672 struct spu_dis_asm_data *data = info->application_data;
1673 print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1674}
1675
1676static int
1677gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1678{
c378eb4e
MS		 1679 /* The opcodes disassembler does 18-bit address arithmetic. Make
1680 sure the SPU ID encoded in the high bits is added back when we
1681 call print_address. */
85e747d2
UW		 1682 struct disassemble_info spu_info = *info;
1683 struct spu_dis_asm_data data;
1684 data.gdbarch = info->application_data;
1685 data.id = SPUADDR_SPU (memaddr);
1686
1687 spu_info.application_data = &data;
1688 spu_info.print_address_func = spu_dis_asm_print_address;
1689 return print_insn_spu (memaddr, &spu_info);
1690}
1691
1692
dcf52cd8
UW		 1693/* Target overlays for the SPU overlay manager.
1694
1695 See the documentation of simple_overlay_update for how the
1696 interface is supposed to work.
1697
1698 Data structures used by the overlay manager:
1699
1700 struct ovly_table
1701 {
1702 u32 vma;
1703 u32 size;
1704 u32 pos;
1705 u32 buf;
1706 } _ovly_table[]; -- one entry per overlay section
1707
1708 struct ovly_buf_table
1709 {
1710 u32 mapped;
1711 } _ovly_buf_table[]; -- one entry per overlay buffer
1712
1713 _ovly_table should never change.
1714
c378eb4e
MS		 1715 Both tables are aligned to a 16-byte boundary, the symbols
1716 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1717 size set to the size of the respective array. buf in _ovly_table is
1718 an index into _ovly_buf_table.
dcf52cd8 1719
c378eb4e 1720 mapped is an index into _ovly_table. Both the mapped and buf indices start
dcf52cd8
UW		 1721 from one to reference the first entry in their respective tables. */
1722
1723/* Using the per-objfile private data mechanism, we store for each
1724 objfile an array of "struct spu_overlay_table" structures, one
1725 for each obj_section of the objfile. This structure holds two
1726 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1727 is *not* an overlay section. If it is non-zero, it represents
1728 a target address. The overlay section is mapped iff the target
1729 integer at this location equals MAPPED_VAL. */
1730
1731static const struct objfile_data *spu_overlay_data;
1732
1733struct spu_overlay_table
1734 {
1735 CORE_ADDR mapped_ptr;
1736 CORE_ADDR mapped_val;
1737 };
1738
1739/* Retrieve the overlay table for OBJFILE. If not already cached, read
1740 the _ovly_table data structure from the target and initialize the
1741 spu_overlay_table data structure from it. */
1742static struct spu_overlay_table *
1743spu_get_overlay_table (struct objfile *objfile)
1744{
e17a4113
UW		 1745 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1746 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8
UW		 1747 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1748 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1749 unsigned ovly_table_size, ovly_buf_table_size;
1750 struct spu_overlay_table *tbl;
1751 struct obj_section *osect;
1752 char *ovly_table;
1753 int i;
1754
1755 tbl = objfile_data (objfile, spu_overlay_data);
1756 if (tbl)
1757 return tbl;
1758
1759 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1760 if (!ovly_table_msym)
1761 return NULL;
1762
c378eb4e
MS		 1763 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1764 NULL, objfile);
dcf52cd8
UW		 1765 if (!ovly_buf_table_msym)
1766 return NULL;
1767
1768 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1769 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1770
1771 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1772 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1773
1774 ovly_table = xmalloc (ovly_table_size);
1775 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1776
1777 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1778 objfile->sections_end - objfile->sections,
1779 struct spu_overlay_table);
1780
1781 for (i = 0; i < ovly_table_size / 16; i++)
1782 {
e17a4113
UW		 1783 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1784 4, byte_order);
1785 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1786 4, byte_order);
1787 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1788 4, byte_order);
1789 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1790 4, byte_order);
dcf52cd8
UW		 1791
1792 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1793 continue;
1794
1795 ALL_OBJFILE_OSECTIONS (objfile, osect)
1796 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1797 && pos == osect->the_bfd_section->filepos)
1798 {
1799 int ndx = osect - objfile->sections;
1800 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1801 tbl[ndx].mapped_val = i + 1;
1802 break;
1803 }
1804 }
1805
1806 xfree (ovly_table);
1807 set_objfile_data (objfile, spu_overlay_data, tbl);
1808 return tbl;
1809}
1810
1811/* Read _ovly_buf_table entry from the target to dermine whether
1812 OSECT is currently mapped, and update the mapped state. */
1813static void
1814spu_overlay_update_osect (struct obj_section *osect)
1815{
e17a4113
UW		 1816 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1817 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1818 struct spu_overlay_table *ovly_table;
85e747d2 1819 CORE_ADDR id, val;
dcf52cd8
UW		 1820
1821 ovly_table = spu_get_overlay_table (osect->objfile);
1822 if (!ovly_table)
1823 return;
1824
1825 ovly_table += osect - osect->objfile->sections;
1826 if (ovly_table->mapped_ptr == 0)
1827 return;
1828
85e747d2
UW		 1829 id = SPUADDR_SPU (obj_section_addr (osect));
1830 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1831 4, byte_order);
dcf52cd8
UW		 1832 osect->ovly_mapped = (val == ovly_table->mapped_val);
1833}
1834
1835/* If OSECT is NULL, then update all sections' mapped state.
1836 If OSECT is non-NULL, then update only OSECT's mapped state. */
1837static void
1838spu_overlay_update (struct obj_section *osect)
1839{
1840 /* Just one section. */
1841 if (osect)
1842 spu_overlay_update_osect (osect);
1843
1844 /* All sections. */
1845 else
1846 {
1847 struct objfile *objfile;
1848
1849 ALL_OBJSECTIONS (objfile, osect)
714835d5 1850 if (section_is_overlay (osect))
dcf52cd8
UW		 1851 spu_overlay_update_osect (osect);
1852 }
1853}
1854
1855/* Whenever a new objfile is loaded, read the target's _ovly_table.
1856 If there is one, go through all sections and make sure for non-
1857 overlay sections LMA equals VMA, while for overlay sections LMA
d2ed6730 1858 is larger than SPU_OVERLAY_LMA. */
dcf52cd8
UW		 1859static void
1860spu_overlay_new_objfile (struct objfile *objfile)
1861{
1862 struct spu_overlay_table *ovly_table;
1863 struct obj_section *osect;
1864
1865 /* If we've already touched this file, do nothing. */
1866 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1867 return;
1868
0391f248
UW		 1869 /* Consider only SPU objfiles. */
1870 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1871 return;
1872
dcf52cd8
UW		 1873 /* Check if this objfile has overlays. */
1874 ovly_table = spu_get_overlay_table (objfile);
1875 if (!ovly_table)
1876 return;
1877
1878 /* Now go and fiddle with all the LMAs. */
1879 ALL_OBJFILE_OSECTIONS (objfile, osect)
1880 {
1881 bfd *obfd = objfile->obfd;
1882 asection *bsect = osect->the_bfd_section;
1883 int ndx = osect - objfile->sections;
1884
1885 if (ovly_table[ndx].mapped_ptr == 0)
1886 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1887 else
d2ed6730 1888 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
dcf52cd8
UW		 1889 }
1890}
1891
771b4502 1892
3285f3fe
UW		 1893/* Insert temporary breakpoint on "main" function of newly loaded
1894 SPE context OBJFILE. */
1895static void
1896spu_catch_start (struct objfile *objfile)
1897{
1898 struct minimal_symbol *minsym;
1899 struct symtab *symtab;
1900 CORE_ADDR pc;
1901 char buf[32];
1902
1903 /* Do this only if requested by "set spu stop-on-load on". */
1904 if (!spu_stop_on_load_p)
1905 return;
1906
1907 /* Consider only SPU objfiles. */
1908 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1909 return;
1910
1911 /* The main objfile is handled differently. */
1912 if (objfile == symfile_objfile)
1913 return;
1914
1915 /* There can be multiple symbols named "main". Search for the
1916 "main" in *this* objfile. */
1917 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1918 if (!minsym)
1919 return;
1920
1921 /* If we have debugging information, try to use it -- this
1922 will allow us to properly skip the prologue. */
1923 pc = SYMBOL_VALUE_ADDRESS (minsym);
1924 symtab = find_pc_sect_symtab (pc, SYMBOL_OBJ_SECTION (minsym));
1925 if (symtab != NULL)
1926 {
1927 struct blockvector *bv = BLOCKVECTOR (symtab);
1928 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1929 struct symbol *sym;
1930 struct symtab_and_line sal;
1931
94af9270 1932 sym = lookup_block_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1933 if (sym)
1934 {
1935 fixup_symbol_section (sym, objfile);
1936 sal = find_function_start_sal (sym, 1);
1937 pc = sal.pc;
1938 }
1939 }
1940
1941 /* Use a numerical address for the set_breakpoint command to avoid having
1942 the breakpoint re-set incorrectly. */
1943 xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
d8c09fb5
JK		 1944 create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
1945 NULL /* cond_string */, -1 /* thread */,
1946 0 /* parse_condition_and_thread */, 1 /* tempflag */,
bddaafad 1947 bp_breakpoint /* type_wanted */,
d8c09fb5
JK		 1948 0 /* ignore_count */,
1949 AUTO_BOOLEAN_FALSE /* pending_break_support */,
931bb47f
UW		 1950 &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
1951 1 /* enabled */, 0 /* internal */);
3285f3fe
UW		 1952}
1953
1954
ff1a52c6
UW		 1955/* Look up OBJFILE loaded into FRAME's SPU context. */
1956static struct objfile *
1957spu_objfile_from_frame (struct frame_info *frame)
1958{
1959 struct gdbarch *gdbarch = get_frame_arch (frame);
1960 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1961 struct objfile *obj;
1962
1963 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
1964 return NULL;
1965
1966 ALL_OBJFILES (obj)
1967 {
1968 if (obj->sections != obj->sections_end
1969 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
1970 return obj;
1971 }
1972
1973 return NULL;
1974}
1975
1976/* Flush cache for ea pointer access if available. */
1977static void
1978flush_ea_cache (void)
1979{
1980 struct minimal_symbol *msymbol;
1981 struct objfile *obj;
1982
1983 if (!has_stack_frames ())
1984 return;
1985
1986 obj = spu_objfile_from_frame (get_current_frame ());
1987 if (obj == NULL)
1988 return;
1989
1990 /* Lookup inferior function __cache_flush. */
1991 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
1992 if (msymbol != NULL)
1993 {
1994 struct type *type;
1995 CORE_ADDR addr;
1996
1997 type = objfile_type (obj)->builtin_void;
1998 type = lookup_function_type (type);
1999 type = lookup_pointer_type (type);
2000 addr = SYMBOL_VALUE_ADDRESS (msymbol);
2001
2002 call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
2003 }
2004}
2005
2006/* This handler is called when the inferior has stopped. If it is stopped in
2007 SPU architecture then flush the ea cache if used. */
2008static void
2009spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2010{
2011 if (!spu_auto_flush_cache_p)
2012 return;
2013
2014 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2015 re-entering this function when __cache_flush stops. */
2016 spu_auto_flush_cache_p = 0;
2017 flush_ea_cache ();
2018 spu_auto_flush_cache_p = 1;
2019}
2020
2021
23d964e7
UW		 2022/* "info spu" commands. */
2023
2024static void
2025info_spu_event_command (char *args, int from_tty)
2026{
2027 struct frame_info *frame = get_selected_frame (NULL);
2028 ULONGEST event_status = 0;
2029 ULONGEST event_mask = 0;
2030 struct cleanup *chain;
2031 gdb_byte buf[100];
2032 char annex[32];
2033 LONGEST len;
2034 int rc, id;
2035
0391f248
UW		 2036 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2037 error (_("\"info spu\" is only supported on the SPU architecture."));
2038
23d964e7
UW		 2039 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2040
2041 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2042 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2043 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2044 if (len <= 0)
2045 error (_("Could not read event_status."));
9971ac47 2046 buf[len] = '\0';
23d964e7
UW		 2047 event_status = strtoulst (buf, NULL, 16);
2048
2049 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2050 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2051 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2052 if (len <= 0)
2053 error (_("Could not read event_mask."));
9971ac47 2054 buf[len] = '\0';
23d964e7
UW		 2055 event_mask = strtoulst (buf, NULL, 16);
2056
31a0ae49 2057 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoEvent");
23d964e7 2058
31a0ae49 2059 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2060 {
31a0ae49 2061 ui_out_field_fmt (current_uiout, "event_status",
23d964e7 2062 "0x%s", phex_nz (event_status, 4));
31a0ae49 2063 ui_out_field_fmt (current_uiout, "event_mask",
23d964e7
UW		 2064 "0x%s", phex_nz (event_mask, 4));
2065 }
2066 else
2067 {
2068 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2069 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2070 }
2071
2072 do_cleanups (chain);
2073}
2074
2075static void
2076info_spu_signal_command (char *args, int from_tty)
2077{
2078 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2079 struct gdbarch *gdbarch = get_frame_arch (frame);
2080 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2081 ULONGEST signal1 = 0;
2082 ULONGEST signal1_type = 0;
2083 int signal1_pending = 0;
2084 ULONGEST signal2 = 0;
2085 ULONGEST signal2_type = 0;
2086 int signal2_pending = 0;
2087 struct cleanup *chain;
2088 char annex[32];
2089 gdb_byte buf[100];
2090 LONGEST len;
2091 int rc, id;
2092
e17a4113 2093 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2094 error (_("\"info spu\" is only supported on the SPU architecture."));
2095
23d964e7
UW		 2096 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2097
2098 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2099 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2100 if (len < 0)
2101 error (_("Could not read signal1."));
2102 else if (len == 4)
2103 {
e17a4113 2104 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2105 signal1_pending = 1;
2106 }
2107
2108 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2109 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2110 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2111 if (len <= 0)
2112 error (_("Could not read signal1_type."));
9971ac47 2113 buf[len] = '\0';
23d964e7
UW		 2114 signal1_type = strtoulst (buf, NULL, 16);
2115
2116 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2117 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2118 if (len < 0)
2119 error (_("Could not read signal2."));
2120 else if (len == 4)
2121 {
e17a4113 2122 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2123 signal2_pending = 1;
2124 }
2125
2126 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2127 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2128 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2129 if (len <= 0)
2130 error (_("Could not read signal2_type."));
9971ac47 2131 buf[len] = '\0';
23d964e7
UW		 2132 signal2_type = strtoulst (buf, NULL, 16);
2133
31a0ae49 2134 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoSignal");
23d964e7 2135
31a0ae49 2136 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2137 {
31a0ae49
JK		 2138 ui_out_field_int (current_uiout, "signal1_pending", signal1_pending);
2139 ui_out_field_fmt (current_uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2140 ui_out_field_int (current_uiout, "signal1_type", signal1_type);
2141 ui_out_field_int (current_uiout, "signal2_pending", signal2_pending);
2142 ui_out_field_fmt (current_uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2143 ui_out_field_int (current_uiout, "signal2_type", signal2_type);
23d964e7
UW		 2144 }
2145 else
2146 {
2147 if (signal1_pending)
2148 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2149 else
2150 printf_filtered (_("Signal 1 not pending "));
2151
2152 if (signal1_type)
23d964e7 2153 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2154 else
2155 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2156
2157 if (signal2_pending)
2158 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2159 else
2160 printf_filtered (_("Signal 2 not pending "));
2161
2162 if (signal2_type)
23d964e7 2163 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2164 else
2165 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2166 }
2167
2168 do_cleanups (chain);
2169}
2170
2171static void
e17a4113 2172info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2173 const char *field, const char *msg)
2174{
2175 struct cleanup *chain;
2176 int i;
2177
2178 if (nr <= 0)
2179 return;
2180
31a0ae49 2181 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 1, nr, "mbox");
23d964e7 2182
31a0ae49
JK		 2183 ui_out_table_header (current_uiout, 32, ui_left, field, msg);
2184 ui_out_table_body (current_uiout);
23d964e7
UW		 2185
2186 for (i = 0; i < nr; i++)
2187 {
2188 struct cleanup *val_chain;
2189 ULONGEST val;
31a0ae49 2190 val_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "mbox");
e17a4113 2191 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
31a0ae49 2192 ui_out_field_fmt (current_uiout, field, "0x%s", phex (val, 4));
23d964e7
UW		 2193 do_cleanups (val_chain);
2194
31a0ae49 2195 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2196 printf_filtered ("\n");
2197 }
2198
2199 do_cleanups (chain);
2200}
2201
2202static void
2203info_spu_mailbox_command (char *args, int from_tty)
2204{
2205 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2206 struct gdbarch *gdbarch = get_frame_arch (frame);
2207 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2208 struct cleanup *chain;
2209 char annex[32];
2210 gdb_byte buf[1024];
2211 LONGEST len;
2212 int i, id;
2213
e17a4113 2214 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2215 error (_("\"info spu\" is only supported on the SPU architecture."));
2216
23d964e7
UW		 2217 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2218
31a0ae49 2219 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoMailbox");
23d964e7
UW		 2220
2221 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2222 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2223 buf, 0, sizeof buf);
2224 if (len < 0)
2225 error (_("Could not read mbox_info."));
2226
e17a4113
UW		 2227 info_spu_mailbox_list (buf, len / 4, byte_order,
2228 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2229
2230 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2231 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2232 buf, 0, sizeof buf);
2233 if (len < 0)
2234 error (_("Could not read ibox_info."));
2235
e17a4113
UW		 2236 info_spu_mailbox_list (buf, len / 4, byte_order,
2237 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2238
2239 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2240 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2241 buf, 0, sizeof buf);
2242 if (len < 0)
2243 error (_("Could not read wbox_info."));
2244
e17a4113
UW		 2245 info_spu_mailbox_list (buf, len / 4, byte_order,
2246 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2247
2248 do_cleanups (chain);
2249}
2250
2251static ULONGEST
2252spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2253{
2254 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2255 return (word >> (63 - last)) & mask;
2256}
2257
2258static void
e17a4113 2259info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7
UW		 2260{
2261 static char *spu_mfc_opcode[256] =
2262 {
2263 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2264 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2265 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2266 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2267 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2268 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2269 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2270 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2271 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2272 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2273 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2274 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2275 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2276 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2277 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2278 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2279 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2280 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2281 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2282 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2283 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2284 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2285 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2286 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2287 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2288 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2289 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2290 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2291 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2292 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2293 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2294 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2295 };
2296
12ab8a60
UW		 2297 int *seq = alloca (nr * sizeof (int));
2298 int done = 0;
23d964e7 2299 struct cleanup *chain;
12ab8a60
UW		 2300 int i, j;
2301
2302
2303 /* Determine sequence in which to display (valid) entries. */
2304 for (i = 0; i < nr; i++)
2305 {
2306 /* Search for the first valid entry all of whose
2307 dependencies are met. */
2308 for (j = 0; j < nr; j++)
2309 {
2310 ULONGEST mfc_cq_dw3;
2311 ULONGEST dependencies;
2312
2313 if (done & (1 << (nr - 1 - j)))
2314 continue;
2315
e17a4113
UW		 2316 mfc_cq_dw3
2317 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2318 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2319 continue;
2320
2321 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2322 if ((dependencies & done) != dependencies)
2323 continue;
2324
2325 seq[i] = j;
2326 done |= 1 << (nr - 1 - j);
2327 break;
2328 }
2329
2330 if (j == nr)
2331 break;
2332 }
2333
2334 nr = i;
2335
23d964e7 2336
31a0ae49
JK		 2337 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 10, nr,
2338 "dma_cmd");
23d964e7 2339
31a0ae49
JK		 2340 ui_out_table_header (current_uiout, 7, ui_left, "opcode", "Opcode");
2341 ui_out_table_header (current_uiout, 3, ui_left, "tag", "Tag");
2342 ui_out_table_header (current_uiout, 3, ui_left, "tid", "TId");
2343 ui_out_table_header (current_uiout, 3, ui_left, "rid", "RId");
2344 ui_out_table_header (current_uiout, 18, ui_left, "ea", "EA");
2345 ui_out_table_header (current_uiout, 7, ui_left, "lsa", "LSA");
2346 ui_out_table_header (current_uiout, 7, ui_left, "size", "Size");
2347 ui_out_table_header (current_uiout, 7, ui_left, "lstaddr", "LstAddr");
2348 ui_out_table_header (current_uiout, 7, ui_left, "lstsize", "LstSize");
2349 ui_out_table_header (current_uiout, 1, ui_left, "error_p", "E");
23d964e7 2350
31a0ae49 2351 ui_out_table_body (current_uiout);
23d964e7
UW		 2352
2353 for (i = 0; i < nr; i++)
2354 {
2355 struct cleanup *cmd_chain;
2356 ULONGEST mfc_cq_dw0;
2357 ULONGEST mfc_cq_dw1;
2358 ULONGEST mfc_cq_dw2;
23d964e7
UW		 2359 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
2360 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
2361 ULONGEST mfc_ea;
2362 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2363
2364 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2365 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2366
e17a4113
UW		 2367 mfc_cq_dw0
2368 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2369 mfc_cq_dw1
2370 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2371 mfc_cq_dw2
2372 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2373
2374 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2375 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2376 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2377 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2378 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2379 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2380 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2381
2382 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2383 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2384
2385 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2386 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2387 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2388 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2389 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2390 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2391
31a0ae49 2392 cmd_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "cmd");
23d964e7
UW		 2393
2394 if (spu_mfc_opcode[mfc_cmd_opcode])
31a0ae49 2395 ui_out_field_string (current_uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
23d964e7 2396 else
31a0ae49 2397 ui_out_field_int (current_uiout, "opcode", mfc_cmd_opcode);
23d964e7 2398
31a0ae49
JK		 2399 ui_out_field_int (current_uiout, "tag", mfc_cmd_tag);
2400 ui_out_field_int (current_uiout, "tid", tclass_id);
2401 ui_out_field_int (current_uiout, "rid", rclass_id);
23d964e7
UW		 2402
2403 if (ea_valid_p)
31a0ae49 2404 ui_out_field_fmt (current_uiout, "ea", "0x%s", phex (mfc_ea, 8));
23d964e7 2405 else
31a0ae49 2406 ui_out_field_skip (current_uiout, "ea");
23d964e7 2407
31a0ae49 2408 ui_out_field_fmt (current_uiout, "lsa", "0x%05x", mfc_lsa << 4);
23d964e7 2409 if (qw_valid_p)
31a0ae49 2410 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size << 4);
23d964e7 2411 else
31a0ae49 2412 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size);
23d964e7
UW		 2413
2414 if (list_valid_p)
2415 {
31a0ae49
JK		 2416 ui_out_field_fmt (current_uiout, "lstaddr", "0x%05x", list_lsa << 3);
2417 ui_out_field_fmt (current_uiout, "lstsize", "0x%05x", list_size << 3);
23d964e7
UW		 2418 }
2419 else
2420 {
31a0ae49
JK		 2421 ui_out_field_skip (current_uiout, "lstaddr");
2422 ui_out_field_skip (current_uiout, "lstsize");
23d964e7
UW		 2423 }
2424
2425 if (cmd_error_p)
31a0ae49 2426 ui_out_field_string (current_uiout, "error_p", "*");
23d964e7 2427 else
31a0ae49 2428 ui_out_field_skip (current_uiout, "error_p");
23d964e7
UW		 2429
2430 do_cleanups (cmd_chain);
2431
31a0ae49 2432 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2433 printf_filtered ("\n");
2434 }
2435
2436 do_cleanups (chain);
2437}
2438
2439static void
2440info_spu_dma_command (char *args, int from_tty)
2441{
2442 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2443 struct gdbarch *gdbarch = get_frame_arch (frame);
2444 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2445 ULONGEST dma_info_type;
2446 ULONGEST dma_info_mask;
2447 ULONGEST dma_info_status;
2448 ULONGEST dma_info_stall_and_notify;
2449 ULONGEST dma_info_atomic_command_status;
2450 struct cleanup *chain;
2451 char annex[32];
2452 gdb_byte buf[1024];
2453 LONGEST len;
2454 int i, id;
2455
0391f248
UW		 2456 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2457 error (_("\"info spu\" is only supported on the SPU architecture."));
2458
23d964e7
UW		 2459 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2460
2461 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2462 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2463 buf, 0, 40 + 16 * 32);
2464 if (len <= 0)
2465 error (_("Could not read dma_info."));
2466
e17a4113
UW		 2467 dma_info_type
2468 = extract_unsigned_integer (buf, 8, byte_order);
2469 dma_info_mask
2470 = extract_unsigned_integer (buf + 8, 8, byte_order);
2471 dma_info_status
2472 = extract_unsigned_integer (buf + 16, 8, byte_order);
2473 dma_info_stall_and_notify
2474 = extract_unsigned_integer (buf + 24, 8, byte_order);
2475 dma_info_atomic_command_status
2476 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7 2477
31a0ae49 2478 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoDMA");
23d964e7 2479
31a0ae49 2480 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2481 {
31a0ae49 2482 ui_out_field_fmt (current_uiout, "dma_info_type", "0x%s",
23d964e7 2483 phex_nz (dma_info_type, 4));
31a0ae49 2484 ui_out_field_fmt (current_uiout, "dma_info_mask", "0x%s",
23d964e7 2485 phex_nz (dma_info_mask, 4));
31a0ae49 2486 ui_out_field_fmt (current_uiout, "dma_info_status", "0x%s",
23d964e7 2487 phex_nz (dma_info_status, 4));
31a0ae49 2488 ui_out_field_fmt (current_uiout, "dma_info_stall_and_notify", "0x%s",
23d964e7 2489 phex_nz (dma_info_stall_and_notify, 4));
31a0ae49 2490 ui_out_field_fmt (current_uiout, "dma_info_atomic_command_status", "0x%s",
23d964e7
UW		 2491 phex_nz (dma_info_atomic_command_status, 4));
2492 }
2493 else
2494 {
8fbde58b 2495 const char *query_msg = _("no query pending");
23d964e7 2496
8fbde58b
UW		 2497 if (dma_info_type & 4)
2498 switch (dma_info_type & 3)
2499 {
2500 case 1: query_msg = _("'any' query pending"); break;
2501 case 2: query_msg = _("'all' query pending"); break;
2502 default: query_msg = _("undefined query type"); break;
2503 }
23d964e7
UW		 2504
2505 printf_filtered (_("Tag-Group Status 0x%s\n"),
2506 phex (dma_info_status, 4));
2507 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2508 phex (dma_info_mask, 4), query_msg);
2509 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2510 phex (dma_info_stall_and_notify, 4));
2511 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2512 phex (dma_info_atomic_command_status, 4));
2513 printf_filtered ("\n");
2514 }
2515
e17a4113 2516 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2517 do_cleanups (chain);
2518}
2519
2520static void
2521info_spu_proxydma_command (char *args, int from_tty)
2522{
2523 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2524 struct gdbarch *gdbarch = get_frame_arch (frame);
2525 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2526 ULONGEST dma_info_type;
2527 ULONGEST dma_info_mask;
2528 ULONGEST dma_info_status;
2529 struct cleanup *chain;
2530 char annex[32];
2531 gdb_byte buf[1024];
2532 LONGEST len;
2533 int i, id;
2534
e17a4113 2535 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2536 error (_("\"info spu\" is only supported on the SPU architecture."));
2537
23d964e7
UW		 2538 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2539
2540 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2541 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2542 buf, 0, 24 + 8 * 32);
2543 if (len <= 0)
2544 error (_("Could not read proxydma_info."));
2545
e17a4113
UW		 2546 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2547 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2548 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7 2549
31a0ae49
JK		 2550 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout,
2551 "SPUInfoProxyDMA");
23d964e7 2552
31a0ae49 2553 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2554 {
31a0ae49 2555 ui_out_field_fmt (current_uiout, "proxydma_info_type", "0x%s",
23d964e7 2556 phex_nz (dma_info_type, 4));
31a0ae49 2557 ui_out_field_fmt (current_uiout, "proxydma_info_mask", "0x%s",
23d964e7 2558 phex_nz (dma_info_mask, 4));
31a0ae49 2559 ui_out_field_fmt (current_uiout, "proxydma_info_status", "0x%s",
23d964e7
UW		 2560 phex_nz (dma_info_status, 4));
2561 }
2562 else
2563 {
2564 const char *query_msg;
2565
8fbde58b 2566 switch (dma_info_type & 3)
23d964e7
UW		 2567 {
2568 case 0: query_msg = _("no query pending"); break;
2569 case 1: query_msg = _("'any' query pending"); break;
2570 case 2: query_msg = _("'all' query pending"); break;
2571 default: query_msg = _("undefined query type"); break;
2572 }
2573
2574 printf_filtered (_("Tag-Group Status 0x%s\n"),
2575 phex (dma_info_status, 4));
2576 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2577 phex (dma_info_mask, 4), query_msg);
2578 printf_filtered ("\n");
2579 }
2580
e17a4113 2581 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2582 do_cleanups (chain);
2583}
2584
2585static void
2586info_spu_command (char *args, int from_tty)
2587{
c378eb4e
MS		 2588 printf_unfiltered (_("\"info spu\" must be followed by "
2589 "the name of an SPU facility.\n"));
23d964e7
UW		 2590 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2591}
2592
2593
3285f3fe
UW		 2594/* Root of all "set spu "/"show spu " commands. */
2595
2596static void
2597show_spu_command (char *args, int from_tty)
2598{
2599 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2600}
2601
2602static void
2603set_spu_command (char *args, int from_tty)
2604{
2605 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2606}
2607
2608static void
2609show_spu_stop_on_load (struct ui_file *file, int from_tty,
2610 struct cmd_list_element *c, const char *value)
2611{
2612 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2613 value);
2614}
2615
ff1a52c6
UW		 2616static void
2617show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2618 struct cmd_list_element *c, const char *value)
2619{
2620 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2621 value);
2622}
2623
3285f3fe 2624
771b4502
UW		 2625/* Set up gdbarch struct. */
2626
2627static struct gdbarch *
2628spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2629{
2630 struct gdbarch *gdbarch;
794ac428 2631 struct gdbarch_tdep *tdep;
85e747d2
UW		 2632 int id = -1;
2633
2634 /* Which spufs ID was requested as address space? */
2635 if (info.tdep_info)
2636 id = *(int *)info.tdep_info;
2637 /* For objfile architectures of SPU solibs, decode the ID from the name.
2638 This assumes the filename convention employed by solib-spu.c. */
2639 else if (info.abfd)
2640 {
2641 char *name = strrchr (info.abfd->filename, '@');
2642 if (name)
2643 sscanf (name, "@0x%*x <%d>", &id);
2644 }
771b4502 2645
85e747d2
UW		 2646 /* Find a candidate among extant architectures. */
2647 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2648 arches != NULL;
2649 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2650 {
2651 tdep = gdbarch_tdep (arches->gdbarch);
2652 if (tdep && tdep->id == id)
2653 return arches->gdbarch;
2654 }
771b4502 2655
85e747d2 2656 /* None found, so create a new architecture. */
794ac428 2657 tdep = XCALLOC (1, struct gdbarch_tdep);
85e747d2 2658 tdep->id = id;
794ac428 2659 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2660
2661 /* Disassembler. */
85e747d2 2662 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2663
2664 /* Registers. */
2665 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2666 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2667 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2668 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2669 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2670 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2671 set_gdbarch_register_name (gdbarch, spu_register_name);
2672 set_gdbarch_register_type (gdbarch, spu_register_type);
2673 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2674 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2675 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2676 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2677
2678 /* Data types. */
2679 set_gdbarch_char_signed (gdbarch, 0);
2680 set_gdbarch_ptr_bit (gdbarch, 32);
2681 set_gdbarch_addr_bit (gdbarch, 32);
2682 set_gdbarch_short_bit (gdbarch, 16);
2683 set_gdbarch_int_bit (gdbarch, 32);
2684 set_gdbarch_long_bit (gdbarch, 32);
2685 set_gdbarch_long_long_bit (gdbarch, 64);
2686 set_gdbarch_float_bit (gdbarch, 32);
2687 set_gdbarch_double_bit (gdbarch, 64);
2688 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2689 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2690 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2691 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2692
ff1a52c6 2693 /* Address handling. */
85e747d2 2694 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2695 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2696 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2697 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2698 set_gdbarch_address_class_type_flags_to_name
2699 (gdbarch, spu_address_class_type_flags_to_name);
2700 set_gdbarch_address_class_name_to_type_flags
2701 (gdbarch, spu_address_class_name_to_type_flags);
2702
36acd84e 2703
771b4502 2704 /* Inferior function calls. */
7b3dc0b7
UW		 2705 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2706 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2707 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2708 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2709 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2710 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2711 set_gdbarch_return_value (gdbarch, spu_return_value);
2712
2713 /* Frame handling. */
2714 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2715 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2716 frame_base_set_default (gdbarch, &spu_frame_base);
2717 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2718 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2719 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2720 set_gdbarch_frame_args_skip (gdbarch, 0);
2721 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2722 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502 2723
cc5f0d61
UW		 2724 /* Cell/B.E. cross-architecture unwinder support. */
2725 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2726
771b4502
UW		 2727 /* Breakpoints. */
2728 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2729 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
d03285ec 2730 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
771b4502
UW		 2731 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2732 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2733 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2734
dcf52cd8
UW		 2735 /* Overlays. */
2736 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2737
771b4502
UW		 2738 return gdbarch;
2739}
2740
63807e1d
PA		 2741/* Provide a prototype to silence -Wmissing-prototypes. */
2742extern initialize_file_ftype _initialize_spu_tdep;
2743
771b4502
UW		 2744void
2745_initialize_spu_tdep (void)
2746{
2747 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2748
dcf52cd8
UW		 2749 /* Add ourselves to objfile event chain. */
2750 observer_attach_new_objfile (spu_overlay_new_objfile);
2751 spu_overlay_data = register_objfile_data ();
23d964e7 2752
3285f3fe
UW		 2753 /* Install spu stop-on-load handler. */
2754 observer_attach_new_objfile (spu_catch_start);
2755
ff1a52c6
UW		 2756 /* Add ourselves to normal_stop event chain. */
2757 observer_attach_normal_stop (spu_attach_normal_stop);
2758
3285f3fe
UW		 2759 /* Add root prefix command for all "set spu"/"show spu" commands. */
2760 add_prefix_cmd ("spu", no_class, set_spu_command,
2761 _("Various SPU specific commands."),
2762 &setspucmdlist, "set spu ", 0, &setlist);
2763 add_prefix_cmd ("spu", no_class, show_spu_command,
2764 _("Various SPU specific commands."),
2765 &showspucmdlist, "show spu ", 0, &showlist);
2766
2767 /* Toggle whether or not to add a temporary breakpoint at the "main"
2768 function of new SPE contexts. */
2769 add_setshow_boolean_cmd ("stop-on-load", class_support,
2770 &spu_stop_on_load_p, _("\
2771Set whether to stop for new SPE threads."),
2772 _("\
2773Show whether to stop for new SPE threads."),
2774 _("\
2775Use \"on\" to give control to the user when a new SPE thread\n\
2776enters its \"main\" function.\n\
2777Use \"off\" to disable stopping for new SPE threads."),
2778 NULL,
2779 show_spu_stop_on_load,
2780 &setspucmdlist, &showspucmdlist);
2781
ff1a52c6
UW		 2782 /* Toggle whether or not to automatically flush the software-managed
2783 cache whenever SPE execution stops. */
2784 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2785 &spu_auto_flush_cache_p, _("\
2786Set whether to automatically flush the software-managed cache."),
2787 _("\
2788Show whether to automatically flush the software-managed cache."),
2789 _("\
2790Use \"on\" to automatically flush the software-managed cache\n\
2791whenever SPE execution stops.\n\
2792Use \"off\" to never automatically flush the software-managed cache."),
2793 NULL,
2794 show_spu_auto_flush_cache,
2795 &setspucmdlist, &showspucmdlist);
2796
23d964e7
UW		 2797 /* Add root prefix command for all "info spu" commands. */
2798 add_prefix_cmd ("spu", class_info, info_spu_command,
2799 _("Various SPU specific commands."),
2800 &infospucmdlist, "info spu ", 0, &infolist);
2801
2802 /* Add various "info spu" commands. */
2803 add_cmd ("event", class_info, info_spu_event_command,
2804 _("Display SPU event facility status.\n"),
2805 &infospucmdlist);
2806 add_cmd ("signal", class_info, info_spu_signal_command,
2807 _("Display SPU signal notification facility status.\n"),
2808 &infospucmdlist);
2809 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2810 _("Display SPU mailbox facility status.\n"),
2811 &infospucmdlist);
2812 add_cmd ("dma", class_info, info_spu_dma_command,
2813 _("Display MFC DMA status.\n"),
2814 &infospucmdlist);
2815 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2816 _("Display MFC Proxy-DMA status.\n"),
2817 &infospucmdlist);
771b4502 2818}
GDB Binutils - Deliverables
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