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2011-02-21 Hui Zhu <teawater@gmail.com>
[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
CommitLineData
771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
7b6bb8da
JB		 2 Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
771b4502
UW		 4
5 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
6 Based on a port by Sid Manning <sid@us.ibm.com>.
7
8 This file is part of GDB.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
a9762ec7 12 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
a9762ec7 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 22
23#include "defs.h"
24#include "arch-utils.h"
25#include "gdbtypes.h"
26#include "gdbcmd.h"
27#include "gdbcore.h"
28#include "gdb_string.h"
29#include "gdb_assert.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "trad-frame.h"
34#include "symtab.h"
35#include "symfile.h"
36#include "value.h"
37#include "inferior.h"
38#include "dis-asm.h"
39#include "objfiles.h"
40#include "language.h"
41#include "regcache.h"
42#include "reggroups.h"
43#include "floatformat.h"
3285f3fe 44#include "block.h"
dcf52cd8 45#include "observer.h"
ff1a52c6 46#include "infcall.h"
54fcddd0 47#include "dwarf2.h"
771b4502
UW		 48
49#include "spu-tdep.h"
50
794ac428 51
3285f3fe
UW		 52/* The list of available "set spu " and "show spu " commands. */
53static struct cmd_list_element *setspucmdlist = NULL;
54static struct cmd_list_element *showspucmdlist = NULL;
55
56/* Whether to stop for new SPE contexts. */
57static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 58/* Whether to automatically flush the SW-managed cache. */
59static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 60
61
794ac428
UW		 62/* The tdep structure. */
63struct gdbarch_tdep
64{
85e747d2
UW		 65 /* The spufs ID identifying our address space. */
66 int id;
67
794ac428
UW		 68 /* SPU-specific vector type. */
69 struct type *spu_builtin_type_vec128;
70};
71
72
f2d43c2c 73/* SPU-specific vector type. */
794ac428
UW		 74static struct type *
75spu_builtin_type_vec128 (struct gdbarch *gdbarch)
76{
77 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
78
79 if (!tdep->spu_builtin_type_vec128)
80 {
df4df182 81 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 82 struct type *t;
83
e9bb382b
UW		 84 t = arch_composite_type (gdbarch,
85 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 86 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 87 append_composite_type_field (t, "v2_int64",
df4df182 88 init_vector_type (bt->builtin_int64, 2));
794ac428 89 append_composite_type_field (t, "v4_int32",
df4df182 90 init_vector_type (bt->builtin_int32, 4));
794ac428 91 append_composite_type_field (t, "v8_int16",
df4df182 92 init_vector_type (bt->builtin_int16, 8));
794ac428 93 append_composite_type_field (t, "v16_int8",
df4df182 94 init_vector_type (bt->builtin_int8, 16));
794ac428 95 append_composite_type_field (t, "v2_double",
df4df182 96 init_vector_type (bt->builtin_double, 2));
794ac428 97 append_composite_type_field (t, "v4_float",
df4df182 98 init_vector_type (bt->builtin_float, 4));
794ac428 99
876cecd0 100 TYPE_VECTOR (t) = 1;
794ac428
UW		 101 TYPE_NAME (t) = "spu_builtin_type_vec128";
102
103 tdep->spu_builtin_type_vec128 = t;
104 }
105
106 return tdep->spu_builtin_type_vec128;
107}
108
771b4502 109
23d964e7
UW		 110/* The list of available "info spu " commands. */
111static struct cmd_list_element *infospucmdlist = NULL;
112
771b4502
UW		 113/* Registers. */
114
115static const char *
d93859e2 116spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 117{
118 static char *register_names[] =
119 {
120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
123 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
124 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
125 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
126 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
127 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
128 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
129 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
130 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
131 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
132 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
133 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
134 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
135 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 136 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 137 };
138
139 if (reg_nr < 0)
140 return NULL;
141 if (reg_nr >= sizeof register_names / sizeof *register_names)
142 return NULL;
143
144 return register_names[reg_nr];
145}
146
147static struct type *
148spu_register_type (struct gdbarch *gdbarch, int reg_nr)
149{
150 if (reg_nr < SPU_NUM_GPRS)
794ac428 151 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 152
153 switch (reg_nr)
154 {
155 case SPU_ID_REGNUM:
df4df182 156 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 157
158 case SPU_PC_REGNUM:
0dfff4cb 159 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 160
161 case SPU_SP_REGNUM:
0dfff4cb 162 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 163
23d964e7 164 case SPU_FPSCR_REGNUM:
df4df182 165 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 166
167 case SPU_SRR0_REGNUM:
df4df182 168 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 169
170 case SPU_LSLR_REGNUM:
df4df182 171 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 172
173 case SPU_DECR_REGNUM:
df4df182 174 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 175
176 case SPU_DECR_STATUS_REGNUM:
df4df182 177 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 178
771b4502 179 default:
a73c6dcd 180 internal_error (__FILE__, __LINE__, _("invalid regnum"));
771b4502
UW		 181 }
182}
183
184/* Pseudo registers for preferred slots - stack pointer. */
185
23d964e7
UW		 186static void
187spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
188 gdb_byte *buf)
189{
e17a4113
UW		 190 struct gdbarch *gdbarch = get_regcache_arch (regcache);
191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 192 gdb_byte reg[32];
193 char annex[32];
194 ULONGEST id;
195
196 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
197 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
198 memset (reg, 0, sizeof reg);
199 target_read (&current_target, TARGET_OBJECT_SPU, annex,
200 reg, 0, sizeof reg);
201
e17a4113 202 store_unsigned_integer (buf, 4, byte_order, strtoulst (reg, NULL, 16));
23d964e7
UW		 203}
204
771b4502
UW		 205static void
206spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
207 int regnum, gdb_byte *buf)
208{
209 gdb_byte reg[16];
23d964e7
UW		 210 char annex[32];
211 ULONGEST id;
771b4502
UW		 212
213 switch (regnum)
214 {
215 case SPU_SP_REGNUM:
216 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
217 memcpy (buf, reg, 4);
218 break;
219
23d964e7
UW		 220 case SPU_FPSCR_REGNUM:
221 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
222 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
223 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
224 break;
225
226 case SPU_SRR0_REGNUM:
227 spu_pseudo_register_read_spu (regcache, "srr0", buf);
228 break;
229
230 case SPU_LSLR_REGNUM:
231 spu_pseudo_register_read_spu (regcache, "lslr", buf);
232 break;
233
234 case SPU_DECR_REGNUM:
235 spu_pseudo_register_read_spu (regcache, "decr", buf);
236 break;
237
238 case SPU_DECR_STATUS_REGNUM:
239 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
240 break;
241
771b4502
UW		 242 default:
243 internal_error (__FILE__, __LINE__, _("invalid regnum"));
244 }
245}
246
23d964e7
UW		 247static void
248spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
249 const gdb_byte *buf)
250{
e17a4113
UW		 251 struct gdbarch *gdbarch = get_regcache_arch (regcache);
252 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 253 gdb_byte reg[32];
254 char annex[32];
255 ULONGEST id;
256
257 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
258 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
259 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 260 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7
UW		 261 target_write (&current_target, TARGET_OBJECT_SPU, annex,
262 reg, 0, strlen (reg));
263}
264
771b4502
UW		 265static void
266spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
267 int regnum, const gdb_byte *buf)
268{
269 gdb_byte reg[16];
23d964e7
UW		 270 char annex[32];
271 ULONGEST id;
771b4502
UW		 272
273 switch (regnum)
274 {
275 case SPU_SP_REGNUM:
276 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
277 memcpy (reg, buf, 4);
278 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
279 break;
280
23d964e7
UW		 281 case SPU_FPSCR_REGNUM:
282 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
283 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
284 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
285 break;
286
287 case SPU_SRR0_REGNUM:
288 spu_pseudo_register_write_spu (regcache, "srr0", buf);
289 break;
290
291 case SPU_LSLR_REGNUM:
292 spu_pseudo_register_write_spu (regcache, "lslr", buf);
293 break;
294
295 case SPU_DECR_REGNUM:
296 spu_pseudo_register_write_spu (regcache, "decr", buf);
297 break;
298
299 case SPU_DECR_STATUS_REGNUM:
300 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
301 break;
302
771b4502
UW		 303 default:
304 internal_error (__FILE__, __LINE__, _("invalid regnum"));
305 }
306}
307
308/* Value conversion -- access scalar values at the preferred slot. */
309
9acbedc0
UW		 310static struct value *
311spu_value_from_register (struct type *type, int regnum,
312 struct frame_info *frame)
771b4502 313{
9acbedc0
UW		 314 struct value *value = default_value_from_register (type, regnum, frame);
315 int len = TYPE_LENGTH (type);
771b4502 316
9acbedc0
UW		 317 if (regnum < SPU_NUM_GPRS && len < 16)
318 {
319 int preferred_slot = len < 4 ? 4 - len : 0;
320 set_value_offset (value, preferred_slot);
321 }
771b4502 322
9acbedc0 323 return value;
771b4502
UW		 324}
325
326/* Register groups. */
327
328static int
329spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
330 struct reggroup *group)
331{
332 /* Registers displayed via 'info regs'. */
333 if (group == general_reggroup)
334 return 1;
335
336 /* Registers displayed via 'info float'. */
337 if (group == float_reggroup)
338 return 0;
339
340 /* Registers that need to be saved/restored in order to
341 push or pop frames. */
342 if (group == save_reggroup || group == restore_reggroup)
343 return 1;
344
345 return default_register_reggroup_p (gdbarch, regnum, group);
346}
347
ff1a52c6
UW		 348
349/* Address handling. */
36acd84e 350
85e747d2
UW		 351static int
352spu_gdbarch_id (struct gdbarch *gdbarch)
353{
354 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
355 int id = tdep->id;
356
357 /* The objfile architecture of a standalone SPU executable does not
358 provide an SPU ID. Retrieve it from the the objfile's relocated
359 address range in this special case. */
360 if (id == -1
361 && symfile_objfile && symfile_objfile->obfd
362 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
363 && symfile_objfile->sections != symfile_objfile->sections_end)
364 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
365
366 return id;
367}
368
ff1a52c6
UW		 369static int
370spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
371{
372 if (dwarf2_addr_class == 1)
373 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
374 else
375 return 0;
376}
377
378static const char *
379spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
380{
381 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
382 return "__ea";
383 else
384 return NULL;
385}
386
387static int
388spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
389 const char *name, int *type_flags_ptr)
390{
391 if (strcmp (name, "__ea") == 0)
392 {
393 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
394 return 1;
395 }
396 else
397 return 0;
398}
399
85e747d2
UW		 400static void
401spu_address_to_pointer (struct gdbarch *gdbarch,
402 struct type *type, gdb_byte *buf, CORE_ADDR addr)
403{
404 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
405 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
406 SPUADDR_ADDR (addr));
407}
408
36acd84e 409static CORE_ADDR
9898f801
UW		 410spu_pointer_to_address (struct gdbarch *gdbarch,
411 struct type *type, const gdb_byte *buf)
36acd84e 412{
85e747d2 413 int id = spu_gdbarch_id (gdbarch);
e17a4113
UW		 414 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
415 ULONGEST addr
416 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 417
ff1a52c6
UW		 418 /* Do not convert __ea pointers. */
419 if (TYPE_ADDRESS_CLASS_1 (type))
420 return addr;
421
d2ed6730 422 return addr? SPUADDR (id, addr) : 0;
36acd84e
UW		 423}
424
425static CORE_ADDR
426spu_integer_to_address (struct gdbarch *gdbarch,
427 struct type *type, const gdb_byte *buf)
428{
85e747d2 429 int id = spu_gdbarch_id (gdbarch);
36acd84e 430 ULONGEST addr = unpack_long (type, buf);
36acd84e 431
d2ed6730 432 return SPUADDR (id, addr);
36acd84e
UW		 433}
434
771b4502
UW		 435
436/* Decoding SPU instructions. */
437
438enum
439 {
440 op_lqd = 0x34,
441 op_lqx = 0x3c4,
442 op_lqa = 0x61,
443 op_lqr = 0x67,
444 op_stqd = 0x24,
445 op_stqx = 0x144,
446 op_stqa = 0x41,
447 op_stqr = 0x47,
448
449 op_il = 0x081,
450 op_ila = 0x21,
451 op_a = 0x0c0,
452 op_ai = 0x1c,
453
454 op_selb = 0x4,
455
456 op_br = 0x64,
457 op_bra = 0x60,
458 op_brsl = 0x66,
459 op_brasl = 0x62,
460 op_brnz = 0x42,
461 op_brz = 0x40,
462 op_brhnz = 0x46,
463 op_brhz = 0x44,
464 op_bi = 0x1a8,
465 op_bisl = 0x1a9,
466 op_biz = 0x128,
467 op_binz = 0x129,
468 op_bihz = 0x12a,
469 op_bihnz = 0x12b,
470 };
471
472static int
473is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
474{
475 if ((insn >> 21) == op)
476 {
477 *rt = insn & 127;
478 *ra = (insn >> 7) & 127;
479 *rb = (insn >> 14) & 127;
480 return 1;
481 }
482
483 return 0;
484}
485
486static int
487is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
488{
489 if ((insn >> 28) == op)
490 {
491 *rt = (insn >> 21) & 127;
492 *ra = (insn >> 7) & 127;
493 *rb = (insn >> 14) & 127;
494 *rc = insn & 127;
495 return 1;
496 }
497
498 return 0;
499}
500
501static int
502is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
503{
504 if ((insn >> 21) == op)
505 {
506 *rt = insn & 127;
507 *ra = (insn >> 7) & 127;
508 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
509 return 1;
510 }
511
512 return 0;
513}
514
515static int
516is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
517{
518 if ((insn >> 24) == op)
519 {
520 *rt = insn & 127;
521 *ra = (insn >> 7) & 127;
522 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
523 return 1;
524 }
525
526 return 0;
527}
528
529static int
530is_ri16 (unsigned int insn, int op, int *rt, int *i16)
531{
532 if ((insn >> 23) == op)
533 {
534 *rt = insn & 127;
535 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
536 return 1;
537 }
538
539 return 0;
540}
541
542static int
543is_ri18 (unsigned int insn, int op, int *rt, int *i18)
544{
545 if ((insn >> 25) == op)
546 {
547 *rt = insn & 127;
548 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
549 return 1;
550 }
551
552 return 0;
553}
554
555static int
556is_branch (unsigned int insn, int *offset, int *reg)
557{
558 int rt, i7, i16;
559
560 if (is_ri16 (insn, op_br, &rt, &i16)
561 || is_ri16 (insn, op_brsl, &rt, &i16)
562 || is_ri16 (insn, op_brnz, &rt, &i16)
563 || is_ri16 (insn, op_brz, &rt, &i16)
564 || is_ri16 (insn, op_brhnz, &rt, &i16)
565 || is_ri16 (insn, op_brhz, &rt, &i16))
566 {
567 *reg = SPU_PC_REGNUM;
568 *offset = i16 << 2;
569 return 1;
570 }
571
572 if (is_ri16 (insn, op_bra, &rt, &i16)
573 || is_ri16 (insn, op_brasl, &rt, &i16))
574 {
575 *reg = -1;
576 *offset = i16 << 2;
577 return 1;
578 }
579
580 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
581 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
582 || is_ri7 (insn, op_biz, &rt, reg, &i7)
583 || is_ri7 (insn, op_binz, &rt, reg, &i7)
584 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
585 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
586 {
587 *offset = 0;
588 return 1;
589 }
590
591 return 0;
592}
593
594
595/* Prolog parsing. */
596
597struct spu_prologue_data
598 {
599 /* Stack frame size. -1 if analysis was unsuccessful. */
600 int size;
601
602 /* How to find the CFA. The CFA is equal to SP at function entry. */
603 int cfa_reg;
604 int cfa_offset;
605
606 /* Offset relative to CFA where a register is saved. -1 if invalid. */
607 int reg_offset[SPU_NUM_GPRS];
608 };
609
610static CORE_ADDR
e17a4113
UW		 611spu_analyze_prologue (struct gdbarch *gdbarch,
612 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 613 struct spu_prologue_data *data)
614{
e17a4113 615 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 616 int found_sp = 0;
617 int found_fp = 0;
618 int found_lr = 0;
ce50d78b 619 int found_bc = 0;
771b4502
UW		 620 int reg_immed[SPU_NUM_GPRS];
621 gdb_byte buf[16];
622 CORE_ADDR prolog_pc = start_pc;
623 CORE_ADDR pc;
624 int i;
625
626
627 /* Initialize DATA to default values. */
628 data->size = -1;
629
630 data->cfa_reg = SPU_RAW_SP_REGNUM;
631 data->cfa_offset = 0;
632
633 for (i = 0; i < SPU_NUM_GPRS; i++)
634 data->reg_offset[i] = -1;
635
636 /* Set up REG_IMMED array. This is non-zero for a register if we know its
637 preferred slot currently holds this immediate value. */
638 for (i = 0; i < SPU_NUM_GPRS; i++)
639 reg_immed[i] = 0;
640
641 /* Scan instructions until the first branch.
642
643 The following instructions are important prolog components:
644
645 - The first instruction to set up the stack pointer.
646 - The first instruction to set up the frame pointer.
647 - The first instruction to save the link register.
ce50d78b 648 - The first instruction to save the backchain.
771b4502 649
ce50d78b 650 We return the instruction after the latest of these four,
771b4502
UW		 651 or the incoming PC if none is found. The first instruction
652 to set up the stack pointer also defines the frame size.
653
654 Note that instructions saving incoming arguments to their stack
655 slots are not counted as important, because they are hard to
656 identify with certainty. This should not matter much, because
657 arguments are relevant only in code compiled with debug data,
658 and in such code the GDB core will advance until the first source
659 line anyway, using SAL data.
660
661 For purposes of stack unwinding, we analyze the following types
662 of instructions in addition:
663
664 - Any instruction adding to the current frame pointer.
665 - Any instruction loading an immediate constant into a register.
666 - Any instruction storing a register onto the stack.
667
668 These are used to compute the CFA and REG_OFFSET output. */
669
670 for (pc = start_pc; pc < end_pc; pc += 4)
671 {
672 unsigned int insn;
673 int rt, ra, rb, rc, immed;
674
675 if (target_read_memory (pc, buf, 4))
676 break;
e17a4113 677 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 678
679 /* AI is the typical instruction to set up a stack frame.
680 It is also used to initialize the frame pointer. */
681 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
682 {
683 if (rt == data->cfa_reg && ra == data->cfa_reg)
684 data->cfa_offset -= immed;
685
686 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
687 && !found_sp)
688 {
689 found_sp = 1;
690 prolog_pc = pc + 4;
691
692 data->size = -immed;
693 }
694 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
695 && !found_fp)
696 {
697 found_fp = 1;
698 prolog_pc = pc + 4;
699
700 data->cfa_reg = SPU_FP_REGNUM;
701 data->cfa_offset -= immed;
702 }
703 }
704
705 /* A is used to set up stack frames of size >= 512 bytes.
706 If we have tracked the contents of the addend register,
707 we can handle this as well. */
708 else if (is_rr (insn, op_a, &rt, &ra, &rb))
709 {
710 if (rt == data->cfa_reg && ra == data->cfa_reg)
711 {
712 if (reg_immed[rb] != 0)
713 data->cfa_offset -= reg_immed[rb];
714 else
715 data->cfa_reg = -1; /* We don't know the CFA any more. */
716 }
717
718 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
719 && !found_sp)
720 {
721 found_sp = 1;
722 prolog_pc = pc + 4;
723
724 if (reg_immed[rb] != 0)
725 data->size = -reg_immed[rb];
726 }
727 }
728
729 /* We need to track IL and ILA used to load immediate constants
730 in case they are later used as input to an A instruction. */
731 else if (is_ri16 (insn, op_il, &rt, &immed))
732 {
733 reg_immed[rt] = immed;
12102450
UW		 734
735 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
736 found_sp = 1;
771b4502
UW		 737 }
738
739 else if (is_ri18 (insn, op_ila, &rt, &immed))
740 {
741 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 742
743 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
744 found_sp = 1;
771b4502
UW		 745 }
746
747 /* STQD is used to save registers to the stack. */
748 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
749 {
750 if (ra == data->cfa_reg)
751 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
752
753 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
754 && !found_lr)
755 {
756 found_lr = 1;
757 prolog_pc = pc + 4;
758 }
ce50d78b
UW		 759
760 if (ra == SPU_RAW_SP_REGNUM
761 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
762 && !found_bc)
763 {
764 found_bc = 1;
765 prolog_pc = pc + 4;
766 }
771b4502
UW		 767 }
768
769 /* _start uses SELB to set up the stack pointer. */
770 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
771 {
772 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
773 found_sp = 1;
774 }
775
776 /* We terminate if we find a branch. */
777 else if (is_branch (insn, &immed, &ra))
778 break;
779 }
780
781
782 /* If we successfully parsed until here, and didn't find any instruction
783 modifying SP, we assume we have a frameless function. */
784 if (!found_sp)
785 data->size = 0;
786
787 /* Return cooked instead of raw SP. */
788 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
789 data->cfa_reg = SPU_SP_REGNUM;
790
791 return prolog_pc;
792}
793
794/* Return the first instruction after the prologue starting at PC. */
795static CORE_ADDR
6093d2eb 796spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 797{
798 struct spu_prologue_data data;
e17a4113 799 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 800}
801
802/* Return the frame pointer in use at address PC. */
803static void
a54fba4c
MD		 804spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
805 int *reg, LONGEST *offset)
771b4502
UW		 806{
807 struct spu_prologue_data data;
e17a4113 808 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 809
810 if (data.size != -1 && data.cfa_reg != -1)
811 {
812 /* The 'frame pointer' address is CFA minus frame size. */
813 *reg = data.cfa_reg;
814 *offset = data.cfa_offset - data.size;
815 }
816 else
817 {
c378eb4e 818 /* ??? We don't really know ... */
771b4502
UW		 819 *reg = SPU_SP_REGNUM;
820 *offset = 0;
821 }
822}
823
fe5febed
UW		 824/* Return true if we are in the function's epilogue, i.e. after the
825 instruction that destroyed the function's stack frame.
826
827 1) scan forward from the point of execution:
828 a) If you find an instruction that modifies the stack pointer
829 or transfers control (except a return), execution is not in
830 an epilogue, return.
831 b) Stop scanning if you find a return instruction or reach the
832 end of the function or reach the hard limit for the size of
833 an epilogue.
834 2) scan backward from the point of execution:
835 a) If you find an instruction that modifies the stack pointer,
836 execution *is* in an epilogue, return.
837 b) Stop scanning if you reach an instruction that transfers
838 control or the beginning of the function or reach the hard
839 limit for the size of an epilogue. */
840
841static int
842spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
843{
e17a4113 844 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 845 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
846 bfd_byte buf[4];
847 unsigned int insn;
848 int rt, ra, rb, rc, immed;
849
850 /* Find the search limits based on function boundaries and hard limit.
851 We assume the epilogue can be up to 64 instructions long. */
852
853 const int spu_max_epilogue_size = 64 * 4;
854
855 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
856 return 0;
857
858 if (pc - func_start < spu_max_epilogue_size)
859 epilogue_start = func_start;
860 else
861 epilogue_start = pc - spu_max_epilogue_size;
862
863 if (func_end - pc < spu_max_epilogue_size)
864 epilogue_end = func_end;
865 else
866 epilogue_end = pc + spu_max_epilogue_size;
867
868 /* Scan forward until next 'bi $0'. */
869
870 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
871 {
872 if (target_read_memory (scan_pc, buf, 4))
873 return 0;
e17a4113 874 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 875
876 if (is_branch (insn, &immed, &ra))
877 {
878 if (immed == 0 && ra == SPU_LR_REGNUM)
879 break;
880
881 return 0;
882 }
883
884 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
885 || is_rr (insn, op_a, &rt, &ra, &rb)
886 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
887 {
888 if (rt == SPU_RAW_SP_REGNUM)
889 return 0;
890 }
891 }
892
893 if (scan_pc >= epilogue_end)
894 return 0;
895
896 /* Scan backward until adjustment to stack pointer (R1). */
897
898 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
899 {
900 if (target_read_memory (scan_pc, buf, 4))
901 return 0;
e17a4113 902 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 903
904 if (is_branch (insn, &immed, &ra))
905 return 0;
906
907 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
908 || is_rr (insn, op_a, &rt, &ra, &rb)
909 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
910 {
911 if (rt == SPU_RAW_SP_REGNUM)
912 return 1;
913 }
914 }
915
916 return 0;
917}
918
919
771b4502
UW		 920/* Normal stack frames. */
921
922struct spu_unwind_cache
923{
924 CORE_ADDR func;
925 CORE_ADDR frame_base;
926 CORE_ADDR local_base;
927
928 struct trad_frame_saved_reg *saved_regs;
929};
930
931static struct spu_unwind_cache *
8d998b8f 932spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 933 void **this_prologue_cache)
934{
e17a4113 935 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 936 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 937 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 938 struct spu_unwind_cache *info;
939 struct spu_prologue_data data;
85e747d2 940 CORE_ADDR id = tdep->id;
dcf52cd8 941 gdb_byte buf[16];
771b4502
UW		 942
943 if (*this_prologue_cache)
944 return *this_prologue_cache;
945
946 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
947 *this_prologue_cache = info;
8d998b8f 948 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 949 info->frame_base = 0;
950 info->local_base = 0;
951
952 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 953 info->func = get_frame_func (this_frame);
771b4502
UW		 954 if (info->func == 0)
955 {
956 /* Fall back to using the current PC as frame ID. */
8d998b8f 957 info->func = get_frame_pc (this_frame);
771b4502
UW		 958 data.size = -1;
959 }
960 else
e17a4113
UW		 961 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
962 &data);
771b4502
UW		 963
964 /* If successful, use prologue analysis data. */
965 if (data.size != -1 && data.cfa_reg != -1)
966 {
967 CORE_ADDR cfa;
968 int i;
771b4502
UW		 969
970 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 971 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 972 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 973 cfa = SPUADDR (id, cfa);
771b4502
UW		 974
975 /* Call-saved register slots. */
976 for (i = 0; i < SPU_NUM_GPRS; i++)
977 if (i == SPU_LR_REGNUM
978 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
979 if (data.reg_offset[i] != -1)
980 info->saved_regs[i].addr = cfa - data.reg_offset[i];
981
771b4502
UW		 982 /* Frame bases. */
983 info->frame_base = cfa;
984 info->local_base = cfa - data.size;
985 }
986
987 /* Otherwise, fall back to reading the backchain link. */
988 else
989 {
cdc9523a
UW		 990 CORE_ADDR reg;
991 LONGEST backchain;
13def385 992 ULONGEST lslr;
cdc9523a 993 int status;
771b4502 994
13def385
UW		 995 /* Get local store limit. */
996 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
997 if (!lslr)
998 lslr = (ULONGEST) -1;
999
771b4502 1000 /* Get the backchain. */
8d998b8f 1001 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 1002 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1003 &backchain);
771b4502
UW		 1004
1005 /* A zero backchain terminates the frame chain. Also, sanity
1006 check against the local store size limit. */
13def385 1007 if (status && backchain > 0 && backchain <= lslr)
771b4502
UW		 1008 {
1009 /* Assume the link register is saved into its slot. */
13def385 1010 if (backchain + 16 <= lslr)
c378eb4e
MS		 1011 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1012 backchain + 16);
771b4502 1013
771b4502 1014 /* Frame bases. */
85e747d2
UW		 1015 info->frame_base = SPUADDR (id, backchain);
1016 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1017 }
1018 }
dcf52cd8 1019
c4891da7
UW		 1020 /* If we didn't find a frame, we cannot determine SP / return address. */
1021 if (info->frame_base == 0)
1022 return info;
1023
dcf52cd8 1024 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1025 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1026 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1027
0a44cb36
UW		 1028 /* Read full contents of the unwound link register in order to
1029 be able to determine the return address. */
dcf52cd8
UW		 1030 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1031 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1032 else
8d998b8f 1033 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1034
0a44cb36
UW		 1035 /* Normally, the return address is contained in the slot 0 of the
1036 link register, and slots 1-3 are zero. For an overlay return,
1037 slot 0 contains the address of the overlay manager return stub,
1038 slot 1 contains the partition number of the overlay section to
1039 be returned to, and slot 2 contains the return address within
1040 that section. Return the latter address in that case. */
e17a4113 1041 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1042 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1043 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1044 else
1045 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1046 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1047
1048 return info;
1049}
1050
1051static void
8d998b8f 1052spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1053 void **this_prologue_cache, struct frame_id *this_id)
1054{
1055 struct spu_unwind_cache *info =
8d998b8f 1056 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1057
1058 if (info->frame_base == 0)
1059 return;
1060
1061 *this_id = frame_id_build (info->frame_base, info->func);
1062}
1063
8d998b8f
UW		 1064static struct value *
1065spu_frame_prev_register (struct frame_info *this_frame,
1066 void **this_prologue_cache, int regnum)
771b4502
UW		 1067{
1068 struct spu_unwind_cache *info
8d998b8f 1069 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1070
1071 /* Special-case the stack pointer. */
1072 if (regnum == SPU_RAW_SP_REGNUM)
1073 regnum = SPU_SP_REGNUM;
1074
8d998b8f 1075 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1076}
1077
1078static const struct frame_unwind spu_frame_unwind = {
1079 NORMAL_FRAME,
1080 spu_frame_this_id,
8d998b8f
UW		 1081 spu_frame_prev_register,
1082 NULL,
1083 default_frame_sniffer
771b4502
UW		 1084};
1085
771b4502 1086static CORE_ADDR
8d998b8f 1087spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1088{
1089 struct spu_unwind_cache *info
8d998b8f 1090 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1091 return info->local_base;
1092}
1093
1094static const struct frame_base spu_frame_base = {
1095 &spu_frame_unwind,
1096 spu_frame_base_address,
1097 spu_frame_base_address,
1098 spu_frame_base_address
1099};
1100
1101static CORE_ADDR
1102spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1103{
85e747d2 1104 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1105 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1106 /* Mask off interrupt enable bit. */
85e747d2 1107 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1108}
1109
1110static CORE_ADDR
1111spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1112{
85e747d2
UW		 1113 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1114 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1115 return SPUADDR (tdep->id, sp);
771b4502
UW		 1116}
1117
118dfbaf 1118static CORE_ADDR
61a1198a 1119spu_read_pc (struct regcache *regcache)
118dfbaf 1120{
85e747d2 1121 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1122 ULONGEST pc;
1123 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1124 /* Mask off interrupt enable bit. */
85e747d2 1125 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1126}
1127
1128static void
61a1198a 1129spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1130{
1131 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1132 ULONGEST old_pc;
1133 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1134 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1135 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1136}
1137
771b4502 1138
cc5f0d61
UW		 1139/* Cell/B.E. cross-architecture unwinder support. */
1140
1141struct spu2ppu_cache
1142{
1143 struct frame_id frame_id;
1144 struct regcache *regcache;
1145};
1146
1147static struct gdbarch *
1148spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1149{
1150 struct spu2ppu_cache *cache = *this_cache;
1151 return get_regcache_arch (cache->regcache);
1152}
1153
1154static void
1155spu2ppu_this_id (struct frame_info *this_frame,
1156 void **this_cache, struct frame_id *this_id)
1157{
1158 struct spu2ppu_cache *cache = *this_cache;
1159 *this_id = cache->frame_id;
1160}
1161
1162static struct value *
1163spu2ppu_prev_register (struct frame_info *this_frame,
1164 void **this_cache, int regnum)
1165{
1166 struct spu2ppu_cache *cache = *this_cache;
1167 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1168 gdb_byte *buf;
1169
1170 buf = alloca (register_size (gdbarch, regnum));
1171 regcache_cooked_read (cache->regcache, regnum, buf);
1172 return frame_unwind_got_bytes (this_frame, regnum, buf);
1173}
1174
1175static int
1176spu2ppu_sniffer (const struct frame_unwind *self,
1177 struct frame_info *this_frame, void **this_prologue_cache)
1178{
1179 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1180 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1181 CORE_ADDR base, func, backchain;
1182 gdb_byte buf[4];
1183
1184 if (gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_spu)
1185 return 0;
1186
1187 base = get_frame_sp (this_frame);
1188 func = get_frame_pc (this_frame);
1189 if (target_read_memory (base, buf, 4))
1190 return 0;
1191 backchain = extract_unsigned_integer (buf, 4, byte_order);
1192
1193 if (!backchain)
1194 {
1195 struct frame_info *fi;
1196
1197 struct spu2ppu_cache *cache
1198 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1199
1200 cache->frame_id = frame_id_build (base + 16, func);
1201
1202 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1203 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1204 break;
1205
1206 if (fi)
1207 {
1208 cache->regcache = frame_save_as_regcache (fi);
1209 *this_prologue_cache = cache;
1210 return 1;
1211 }
1212 else
1213 {
1214 struct regcache *regcache;
1215 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch);
1216 cache->regcache = regcache_dup (regcache);
1217 *this_prologue_cache = cache;
1218 return 1;
1219 }
1220 }
1221
1222 return 0;
1223}
1224
1225static void
1226spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1227{
1228 struct spu2ppu_cache *cache = this_cache;
1229 regcache_xfree (cache->regcache);
1230}
1231
1232static const struct frame_unwind spu2ppu_unwind = {
1233 ARCH_FRAME,
1234 spu2ppu_this_id,
1235 spu2ppu_prev_register,
1236 NULL,
1237 spu2ppu_sniffer,
1238 spu2ppu_dealloc_cache,
1239 spu2ppu_prev_arch,
1240};
1241
1242
771b4502
UW		 1243/* Function calling convention. */
1244
7b3dc0b7
UW		 1245static CORE_ADDR
1246spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1247{
1248 return sp & ~15;
1249}
1250
87805e63
UW		 1251static CORE_ADDR
1252spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1253 struct value **args, int nargs, struct type *value_type,
1254 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1255 struct regcache *regcache)
1256{
1257 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1258 sp = (sp - 4) & ~15;
1259 /* Store the address of that breakpoint */
1260 *bp_addr = sp;
1261 /* The call starts at the callee's entry point. */
1262 *real_pc = funaddr;
1263
1264 return sp;
1265}
1266
771b4502
UW		 1267static int
1268spu_scalar_value_p (struct type *type)
1269{
1270 switch (TYPE_CODE (type))
1271 {
1272 case TYPE_CODE_INT:
1273 case TYPE_CODE_ENUM:
1274 case TYPE_CODE_RANGE:
1275 case TYPE_CODE_CHAR:
1276 case TYPE_CODE_BOOL:
1277 case TYPE_CODE_PTR:
1278 case TYPE_CODE_REF:
1279 return TYPE_LENGTH (type) <= 16;
1280
1281 default:
1282 return 0;
1283 }
1284}
1285
1286static void
1287spu_value_to_regcache (struct regcache *regcache, int regnum,
1288 struct type *type, const gdb_byte *in)
1289{
1290 int len = TYPE_LENGTH (type);
1291
1292 if (spu_scalar_value_p (type))
1293 {
1294 int preferred_slot = len < 4 ? 4 - len : 0;
1295 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1296 }
1297 else
1298 {
1299 while (len >= 16)
1300 {
1301 regcache_cooked_write (regcache, regnum++, in);
1302 in += 16;
1303 len -= 16;
1304 }
1305
1306 if (len > 0)
1307 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1308 }
1309}
1310
1311static void
1312spu_regcache_to_value (struct regcache *regcache, int regnum,
1313 struct type *type, gdb_byte *out)
1314{
1315 int len = TYPE_LENGTH (type);
1316
1317 if (spu_scalar_value_p (type))
1318 {
1319 int preferred_slot = len < 4 ? 4 - len : 0;
1320 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1321 }
1322 else
1323 {
1324 while (len >= 16)
1325 {
1326 regcache_cooked_read (regcache, regnum++, out);
1327 out += 16;
1328 len -= 16;
1329 }
1330
1331 if (len > 0)
1332 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1333 }
1334}
1335
1336static CORE_ADDR
1337spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1338 struct regcache *regcache, CORE_ADDR bp_addr,
1339 int nargs, struct value **args, CORE_ADDR sp,
1340 int struct_return, CORE_ADDR struct_addr)
1341{
e17a4113 1342 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1343 CORE_ADDR sp_delta;
771b4502
UW		 1344 int i;
1345 int regnum = SPU_ARG1_REGNUM;
1346 int stack_arg = -1;
1347 gdb_byte buf[16];
1348
1349 /* Set the return address. */
1350 memset (buf, 0, sizeof buf);
85e747d2 1351 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1352 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1353
1354 /* If STRUCT_RETURN is true, then the struct return address (in
1355 STRUCT_ADDR) will consume the first argument-passing register.
1356 Both adjust the register count and store that value. */
1357 if (struct_return)
1358 {
1359 memset (buf, 0, sizeof buf);
85e747d2 1360 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1361 regcache_cooked_write (regcache, regnum++, buf);
1362 }
1363
1364 /* Fill in argument registers. */
1365 for (i = 0; i < nargs; i++)
1366 {
1367 struct value *arg = args[i];
1368 struct type *type = check_typedef (value_type (arg));
1369 const gdb_byte *contents = value_contents (arg);
1370 int len = TYPE_LENGTH (type);
1371 int n_regs = align_up (len, 16) / 16;
1372
1373 /* If the argument doesn't wholly fit into registers, it and
1374 all subsequent arguments go to the stack. */
1375 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1376 {
1377 stack_arg = i;
1378 break;
1379 }
1380
1381 spu_value_to_regcache (regcache, regnum, type, contents);
1382 regnum += n_regs;
1383 }
1384
1385 /* Overflow arguments go to the stack. */
1386 if (stack_arg != -1)
1387 {
1388 CORE_ADDR ap;
1389
1390 /* Allocate all required stack size. */
1391 for (i = stack_arg; i < nargs; i++)
1392 {
1393 struct type *type = check_typedef (value_type (args[i]));
1394 sp -= align_up (TYPE_LENGTH (type), 16);
1395 }
1396
1397 /* Fill in stack arguments. */
1398 ap = sp;
1399 for (i = stack_arg; i < nargs; i++)
1400 {
1401 struct value *arg = args[i];
1402 struct type *type = check_typedef (value_type (arg));
1403 int len = TYPE_LENGTH (type);
1404 int preferred_slot;
1405
1406 if (spu_scalar_value_p (type))
1407 preferred_slot = len < 4 ? 4 - len : 0;
1408 else
1409 preferred_slot = 0;
1410
1411 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1412 ap += align_up (TYPE_LENGTH (type), 16);
1413 }
1414 }
1415
1416 /* Allocate stack frame header. */
1417 sp -= 32;
1418
ee82e879
UW		 1419 /* Store stack back chain. */
1420 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1421 target_write_memory (sp, buf, 16);
1422
9ff3afda 1423 /* Finally, update all slots of the SP register. */
e17a4113 1424 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1425 for (i = 0; i < 4; i++)
1426 {
e17a4113
UW		 1427 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1428 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1429 }
1430 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1431
1432 return sp;
1433}
1434
1435static struct frame_id
8d998b8f 1436spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1437{
85e747d2 1438 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1439 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1440 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1441 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1442}
1443
1444/* Function return value access. */
1445
1446static enum return_value_convention
c055b101
CV		 1447spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1448 struct type *type, struct regcache *regcache,
1449 gdb_byte *out, const gdb_byte *in)
771b4502
UW		 1450{
1451 enum return_value_convention rvc;
54fcddd0
UW		 1452 int opencl_vector = 0;
1453
1454 if (func_type
1455 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1456 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1457 && TYPE_VECTOR (type))
1458 opencl_vector = 1;
771b4502
UW		 1459
1460 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1461 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1462 else
1463 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1464
1465 if (in)
1466 {
1467 switch (rvc)
1468 {
1469 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1470 if (opencl_vector && TYPE_LENGTH (type) == 2)
1471 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1472 else
1473 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
771b4502
UW		 1474 break;
1475
1476 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1477 error (_("Cannot set function return value."));
771b4502
UW		 1478 break;
1479 }
1480 }
1481 else if (out)
1482 {
1483 switch (rvc)
1484 {
1485 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1486 if (opencl_vector && TYPE_LENGTH (type) == 2)
1487 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1488 else
1489 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
771b4502
UW		 1490 break;
1491
1492 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1493 error (_("Function return value unknown."));
771b4502
UW		 1494 break;
1495 }
1496 }
1497
1498 return rvc;
1499}
1500
1501
1502/* Breakpoints. */
1503
1504static const gdb_byte *
c378eb4e
MS		 1505spu_breakpoint_from_pc (struct gdbarch *gdbarch,
1506 CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1507{
1508 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1509
1510 *lenptr = sizeof breakpoint;
1511 return breakpoint;
1512}
1513
d03285ec
UW		 1514static int
1515spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1516 struct bp_target_info *bp_tgt)
1517{
1518 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1519 that in a combined application, we have some breakpoints inserted in SPU
1520 code, and now the application forks (on the PPU side). GDB common code
1521 will assume that the fork system call copied all breakpoints into the new
1522 process' address space, and that all those copies now need to be removed
1523 (see breakpoint.c:detach_breakpoints).
1524
1525 While this is certainly true for PPU side breakpoints, it is not true
1526 for SPU side breakpoints. fork will clone the SPU context file
1527 descriptors, so that all the existing SPU contexts are in accessible
1528 in the new process. However, the contents of the SPU contexts themselves
1529 are *not* cloned. Therefore the effect of detach_breakpoints is to
1530 remove SPU breakpoints from the *original* SPU context's local store
1531 -- this is not the correct behaviour.
1532
1533 The workaround is to check whether the PID we are asked to remove this
1534 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1535 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1536 true in the context of detach_breakpoints. If so, we simply do nothing.
1537 [ Note that for the fork child process, it does not matter if breakpoints
1538 remain inserted, because those SPU contexts are not runnable anyway --
1539 the Linux kernel allows only the original process to invoke spu_run. */
1540
1541 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1542 return 0;
1543
1544 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1545}
1546
771b4502
UW		 1547
1548/* Software single-stepping support. */
1549
63807e1d 1550static int
0b1b3e42 1551spu_software_single_step (struct frame_info *frame)
771b4502 1552{
a6d9a66e 1553 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1554 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1555 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1556 CORE_ADDR pc, next_pc;
1557 unsigned int insn;
1558 int offset, reg;
1559 gdb_byte buf[4];
13def385 1560 ULONGEST lslr;
771b4502 1561
0b1b3e42 1562 pc = get_frame_pc (frame);
771b4502 1563
e0cd558a
UW		 1564 if (target_read_memory (pc, buf, 4))
1565 return 1;
e17a4113 1566 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1567
13def385
UW		 1568 /* Get local store limit. */
1569 lslr = get_frame_register_unsigned (frame, SPU_LSLR_REGNUM);
1570 if (!lslr)
1571 lslr = (ULONGEST) -1;
1572
e0cd558a
UW		 1573 /* Next sequential instruction is at PC + 4, except if the current
1574 instruction is a PPE-assisted call, in which case it is at PC + 8.
1575 Wrap around LS limit to be on the safe side. */
1576 if ((insn & 0xffffff00) == 0x00002100)
13def385 1577 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
e0cd558a 1578 else
13def385 1579 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
771b4502 1580
6c95b8df
PA		 1581 insert_single_step_breakpoint (gdbarch,
1582 aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1583
e0cd558a
UW		 1584 if (is_branch (insn, &offset, &reg))
1585 {
1586 CORE_ADDR target = offset;
771b4502 1587
e0cd558a 1588 if (reg == SPU_PC_REGNUM)
85e747d2 1589 target += SPUADDR_ADDR (pc);
e0cd558a
UW		 1590 else if (reg != -1)
1591 {
0b1b3e42 1592 get_frame_register_bytes (frame, reg, 0, 4, buf);
e17a4113 1593 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
771b4502 1594 }
e0cd558a 1595
13def385 1596 target = target & lslr;
e0cd558a 1597 if (target != next_pc)
6c95b8df 1598 insert_single_step_breakpoint (gdbarch, aspace,
85e747d2 1599 SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1600 }
e6590a1b
UW		 1601
1602 return 1;
771b4502
UW		 1603}
1604
6e3f70d7
UW		 1605
1606/* Longjmp support. */
1607
1608static int
1609spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1610{
e17a4113 1611 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1612 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1613 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1614 gdb_byte buf[4];
1615 CORE_ADDR jb_addr;
1616
1617 /* Jump buffer is pointed to by the argument register $r3. */
1618 get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf);
e17a4113 1619 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1620 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1621 return 0;
1622
e17a4113 1623 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1624 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1625 return 1;
1626}
1627
1628
85e747d2
UW		 1629/* Disassembler. */
1630
1631struct spu_dis_asm_data
1632{
1633 struct gdbarch *gdbarch;
1634 int id;
1635};
1636
1637static void
1638spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1639{
1640 struct spu_dis_asm_data *data = info->application_data;
1641 print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1642}
1643
1644static int
1645gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1646{
c378eb4e
MS		 1647 /* The opcodes disassembler does 18-bit address arithmetic. Make
1648 sure the SPU ID encoded in the high bits is added back when we
1649 call print_address. */
85e747d2
UW		 1650 struct disassemble_info spu_info = *info;
1651 struct spu_dis_asm_data data;
1652 data.gdbarch = info->application_data;
1653 data.id = SPUADDR_SPU (memaddr);
1654
1655 spu_info.application_data = &data;
1656 spu_info.print_address_func = spu_dis_asm_print_address;
1657 return print_insn_spu (memaddr, &spu_info);
1658}
1659
1660
dcf52cd8
UW		 1661/* Target overlays for the SPU overlay manager.
1662
1663 See the documentation of simple_overlay_update for how the
1664 interface is supposed to work.
1665
1666 Data structures used by the overlay manager:
1667
1668 struct ovly_table
1669 {
1670 u32 vma;
1671 u32 size;
1672 u32 pos;
1673 u32 buf;
1674 } _ovly_table[]; -- one entry per overlay section
1675
1676 struct ovly_buf_table
1677 {
1678 u32 mapped;
1679 } _ovly_buf_table[]; -- one entry per overlay buffer
1680
1681 _ovly_table should never change.
1682
c378eb4e
MS		 1683 Both tables are aligned to a 16-byte boundary, the symbols
1684 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1685 size set to the size of the respective array. buf in _ovly_table is
1686 an index into _ovly_buf_table.
dcf52cd8 1687
c378eb4e 1688 mapped is an index into _ovly_table. Both the mapped and buf indices start
dcf52cd8
UW		 1689 from one to reference the first entry in their respective tables. */
1690
1691/* Using the per-objfile private data mechanism, we store for each
1692 objfile an array of "struct spu_overlay_table" structures, one
1693 for each obj_section of the objfile. This structure holds two
1694 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1695 is *not* an overlay section. If it is non-zero, it represents
1696 a target address. The overlay section is mapped iff the target
1697 integer at this location equals MAPPED_VAL. */
1698
1699static const struct objfile_data *spu_overlay_data;
1700
1701struct spu_overlay_table
1702 {
1703 CORE_ADDR mapped_ptr;
1704 CORE_ADDR mapped_val;
1705 };
1706
1707/* Retrieve the overlay table for OBJFILE. If not already cached, read
1708 the _ovly_table data structure from the target and initialize the
1709 spu_overlay_table data structure from it. */
1710static struct spu_overlay_table *
1711spu_get_overlay_table (struct objfile *objfile)
1712{
e17a4113
UW		 1713 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1714 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8
UW		 1715 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1716 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1717 unsigned ovly_table_size, ovly_buf_table_size;
1718 struct spu_overlay_table *tbl;
1719 struct obj_section *osect;
1720 char *ovly_table;
1721 int i;
1722
1723 tbl = objfile_data (objfile, spu_overlay_data);
1724 if (tbl)
1725 return tbl;
1726
1727 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1728 if (!ovly_table_msym)
1729 return NULL;
1730
c378eb4e
MS		 1731 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1732 NULL, objfile);
dcf52cd8
UW		 1733 if (!ovly_buf_table_msym)
1734 return NULL;
1735
1736 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1737 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1738
1739 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1740 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1741
1742 ovly_table = xmalloc (ovly_table_size);
1743 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1744
1745 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1746 objfile->sections_end - objfile->sections,
1747 struct spu_overlay_table);
1748
1749 for (i = 0; i < ovly_table_size / 16; i++)
1750 {
e17a4113
UW		 1751 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1752 4, byte_order);
1753 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1754 4, byte_order);
1755 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1756 4, byte_order);
1757 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1758 4, byte_order);
dcf52cd8
UW		 1759
1760 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1761 continue;
1762
1763 ALL_OBJFILE_OSECTIONS (objfile, osect)
1764 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1765 && pos == osect->the_bfd_section->filepos)
1766 {
1767 int ndx = osect - objfile->sections;
1768 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1769 tbl[ndx].mapped_val = i + 1;
1770 break;
1771 }
1772 }
1773
1774 xfree (ovly_table);
1775 set_objfile_data (objfile, spu_overlay_data, tbl);
1776 return tbl;
1777}
1778
1779/* Read _ovly_buf_table entry from the target to dermine whether
1780 OSECT is currently mapped, and update the mapped state. */
1781static void
1782spu_overlay_update_osect (struct obj_section *osect)
1783{
e17a4113
UW		 1784 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1785 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1786 struct spu_overlay_table *ovly_table;
85e747d2 1787 CORE_ADDR id, val;
dcf52cd8
UW		 1788
1789 ovly_table = spu_get_overlay_table (osect->objfile);
1790 if (!ovly_table)
1791 return;
1792
1793 ovly_table += osect - osect->objfile->sections;
1794 if (ovly_table->mapped_ptr == 0)
1795 return;
1796
85e747d2
UW		 1797 id = SPUADDR_SPU (obj_section_addr (osect));
1798 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1799 4, byte_order);
dcf52cd8
UW		 1800 osect->ovly_mapped = (val == ovly_table->mapped_val);
1801}
1802
1803/* If OSECT is NULL, then update all sections' mapped state.
1804 If OSECT is non-NULL, then update only OSECT's mapped state. */
1805static void
1806spu_overlay_update (struct obj_section *osect)
1807{
1808 /* Just one section. */
1809 if (osect)
1810 spu_overlay_update_osect (osect);
1811
1812 /* All sections. */
1813 else
1814 {
1815 struct objfile *objfile;
1816
1817 ALL_OBJSECTIONS (objfile, osect)
714835d5 1818 if (section_is_overlay (osect))
dcf52cd8
UW		 1819 spu_overlay_update_osect (osect);
1820 }
1821}
1822
1823/* Whenever a new objfile is loaded, read the target's _ovly_table.
1824 If there is one, go through all sections and make sure for non-
1825 overlay sections LMA equals VMA, while for overlay sections LMA
d2ed6730 1826 is larger than SPU_OVERLAY_LMA. */
dcf52cd8
UW		 1827static void
1828spu_overlay_new_objfile (struct objfile *objfile)
1829{
1830 struct spu_overlay_table *ovly_table;
1831 struct obj_section *osect;
1832
1833 /* If we've already touched this file, do nothing. */
1834 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1835 return;
1836
0391f248
UW		 1837 /* Consider only SPU objfiles. */
1838 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1839 return;
1840
dcf52cd8
UW		 1841 /* Check if this objfile has overlays. */
1842 ovly_table = spu_get_overlay_table (objfile);
1843 if (!ovly_table)
1844 return;
1845
1846 /* Now go and fiddle with all the LMAs. */
1847 ALL_OBJFILE_OSECTIONS (objfile, osect)
1848 {
1849 bfd *obfd = objfile->obfd;
1850 asection *bsect = osect->the_bfd_section;
1851 int ndx = osect - objfile->sections;
1852
1853 if (ovly_table[ndx].mapped_ptr == 0)
1854 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1855 else
d2ed6730 1856 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
dcf52cd8
UW		 1857 }
1858}
1859
771b4502 1860
3285f3fe
UW		 1861/* Insert temporary breakpoint on "main" function of newly loaded
1862 SPE context OBJFILE. */
1863static void
1864spu_catch_start (struct objfile *objfile)
1865{
1866 struct minimal_symbol *minsym;
1867 struct symtab *symtab;
1868 CORE_ADDR pc;
1869 char buf[32];
1870
1871 /* Do this only if requested by "set spu stop-on-load on". */
1872 if (!spu_stop_on_load_p)
1873 return;
1874
1875 /* Consider only SPU objfiles. */
1876 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1877 return;
1878
1879 /* The main objfile is handled differently. */
1880 if (objfile == symfile_objfile)
1881 return;
1882
1883 /* There can be multiple symbols named "main". Search for the
1884 "main" in *this* objfile. */
1885 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1886 if (!minsym)
1887 return;
1888
1889 /* If we have debugging information, try to use it -- this
1890 will allow us to properly skip the prologue. */
1891 pc = SYMBOL_VALUE_ADDRESS (minsym);
1892 symtab = find_pc_sect_symtab (pc, SYMBOL_OBJ_SECTION (minsym));
1893 if (symtab != NULL)
1894 {
1895 struct blockvector *bv = BLOCKVECTOR (symtab);
1896 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1897 struct symbol *sym;
1898 struct symtab_and_line sal;
1899
94af9270 1900 sym = lookup_block_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1901 if (sym)
1902 {
1903 fixup_symbol_section (sym, objfile);
1904 sal = find_function_start_sal (sym, 1);
1905 pc = sal.pc;
1906 }
1907 }
1908
1909 /* Use a numerical address for the set_breakpoint command to avoid having
1910 the breakpoint re-set incorrectly. */
1911 xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
d8c09fb5
JK		 1912 create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
1913 NULL /* cond_string */, -1 /* thread */,
1914 0 /* parse_condition_and_thread */, 1 /* tempflag */,
bddaafad 1915 bp_breakpoint /* type_wanted */,
d8c09fb5
JK		 1916 0 /* ignore_count */,
1917 AUTO_BOOLEAN_FALSE /* pending_break_support */,
84f4c1fe 1918 NULL /* ops */, 0 /* from_tty */, 1 /* enabled */,
74884f7b 1919 0 /* internal */);
3285f3fe
UW		 1920}
1921
1922
ff1a52c6
UW		 1923/* Look up OBJFILE loaded into FRAME's SPU context. */
1924static struct objfile *
1925spu_objfile_from_frame (struct frame_info *frame)
1926{
1927 struct gdbarch *gdbarch = get_frame_arch (frame);
1928 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1929 struct objfile *obj;
1930
1931 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
1932 return NULL;
1933
1934 ALL_OBJFILES (obj)
1935 {
1936 if (obj->sections != obj->sections_end
1937 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
1938 return obj;
1939 }
1940
1941 return NULL;
1942}
1943
1944/* Flush cache for ea pointer access if available. */
1945static void
1946flush_ea_cache (void)
1947{
1948 struct minimal_symbol *msymbol;
1949 struct objfile *obj;
1950
1951 if (!has_stack_frames ())
1952 return;
1953
1954 obj = spu_objfile_from_frame (get_current_frame ());
1955 if (obj == NULL)
1956 return;
1957
1958 /* Lookup inferior function __cache_flush. */
1959 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
1960 if (msymbol != NULL)
1961 {
1962 struct type *type;
1963 CORE_ADDR addr;
1964
1965 type = objfile_type (obj)->builtin_void;
1966 type = lookup_function_type (type);
1967 type = lookup_pointer_type (type);
1968 addr = SYMBOL_VALUE_ADDRESS (msymbol);
1969
1970 call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
1971 }
1972}
1973
1974/* This handler is called when the inferior has stopped. If it is stopped in
1975 SPU architecture then flush the ea cache if used. */
1976static void
1977spu_attach_normal_stop (struct bpstats *bs, int print_frame)
1978{
1979 if (!spu_auto_flush_cache_p)
1980 return;
1981
1982 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
1983 re-entering this function when __cache_flush stops. */
1984 spu_auto_flush_cache_p = 0;
1985 flush_ea_cache ();
1986 spu_auto_flush_cache_p = 1;
1987}
1988
1989
23d964e7
UW		 1990/* "info spu" commands. */
1991
1992static void
1993info_spu_event_command (char *args, int from_tty)
1994{
1995 struct frame_info *frame = get_selected_frame (NULL);
1996 ULONGEST event_status = 0;
1997 ULONGEST event_mask = 0;
1998 struct cleanup *chain;
1999 gdb_byte buf[100];
2000 char annex[32];
2001 LONGEST len;
2002 int rc, id;
2003
0391f248
UW		 2004 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2005 error (_("\"info spu\" is only supported on the SPU architecture."));
2006
23d964e7
UW		 2007 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2008
2009 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2010 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2011 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2012 if (len <= 0)
2013 error (_("Could not read event_status."));
9971ac47 2014 buf[len] = '\0';
23d964e7
UW		 2015 event_status = strtoulst (buf, NULL, 16);
2016
2017 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2018 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2019 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2020 if (len <= 0)
2021 error (_("Could not read event_mask."));
9971ac47 2022 buf[len] = '\0';
23d964e7
UW		 2023 event_mask = strtoulst (buf, NULL, 16);
2024
2025 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
2026
2027 if (ui_out_is_mi_like_p (uiout))
2028 {
2029 ui_out_field_fmt (uiout, "event_status",
2030 "0x%s", phex_nz (event_status, 4));
2031 ui_out_field_fmt (uiout, "event_mask",
2032 "0x%s", phex_nz (event_mask, 4));
2033 }
2034 else
2035 {
2036 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2037 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2038 }
2039
2040 do_cleanups (chain);
2041}
2042
2043static void
2044info_spu_signal_command (char *args, int from_tty)
2045{
2046 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2047 struct gdbarch *gdbarch = get_frame_arch (frame);
2048 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2049 ULONGEST signal1 = 0;
2050 ULONGEST signal1_type = 0;
2051 int signal1_pending = 0;
2052 ULONGEST signal2 = 0;
2053 ULONGEST signal2_type = 0;
2054 int signal2_pending = 0;
2055 struct cleanup *chain;
2056 char annex[32];
2057 gdb_byte buf[100];
2058 LONGEST len;
2059 int rc, id;
2060
e17a4113 2061 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2062 error (_("\"info spu\" is only supported on the SPU architecture."));
2063
23d964e7
UW		 2064 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2065
2066 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2067 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2068 if (len < 0)
2069 error (_("Could not read signal1."));
2070 else if (len == 4)
2071 {
e17a4113 2072 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2073 signal1_pending = 1;
2074 }
2075
2076 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2077 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2078 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2079 if (len <= 0)
2080 error (_("Could not read signal1_type."));
9971ac47 2081 buf[len] = '\0';
23d964e7
UW		 2082 signal1_type = strtoulst (buf, NULL, 16);
2083
2084 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2085 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2086 if (len < 0)
2087 error (_("Could not read signal2."));
2088 else if (len == 4)
2089 {
e17a4113 2090 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2091 signal2_pending = 1;
2092 }
2093
2094 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2095 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2096 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2097 if (len <= 0)
2098 error (_("Could not read signal2_type."));
9971ac47 2099 buf[len] = '\0';
23d964e7
UW		 2100 signal2_type = strtoulst (buf, NULL, 16);
2101
2102 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
2103
2104 if (ui_out_is_mi_like_p (uiout))
2105 {
2106 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
2107 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2108 ui_out_field_int (uiout, "signal1_type", signal1_type);
2109 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
2110 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2111 ui_out_field_int (uiout, "signal2_type", signal2_type);
2112 }
2113 else
2114 {
2115 if (signal1_pending)
2116 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2117 else
2118 printf_filtered (_("Signal 1 not pending "));
2119
2120 if (signal1_type)
23d964e7 2121 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2122 else
2123 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2124
2125 if (signal2_pending)
2126 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2127 else
2128 printf_filtered (_("Signal 2 not pending "));
2129
2130 if (signal2_type)
23d964e7 2131 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2132 else
2133 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2134 }
2135
2136 do_cleanups (chain);
2137}
2138
2139static void
e17a4113 2140info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2141 const char *field, const char *msg)
2142{
2143 struct cleanup *chain;
2144 int i;
2145
2146 if (nr <= 0)
2147 return;
2148
2149 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
2150
2151 ui_out_table_header (uiout, 32, ui_left, field, msg);
2152 ui_out_table_body (uiout);
2153
2154 for (i = 0; i < nr; i++)
2155 {
2156 struct cleanup *val_chain;
2157 ULONGEST val;
2158 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
e17a4113 2159 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
23d964e7
UW		 2160 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
2161 do_cleanups (val_chain);
2162
2163 if (!ui_out_is_mi_like_p (uiout))
2164 printf_filtered ("\n");
2165 }
2166
2167 do_cleanups (chain);
2168}
2169
2170static void
2171info_spu_mailbox_command (char *args, int from_tty)
2172{
2173 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2174 struct gdbarch *gdbarch = get_frame_arch (frame);
2175 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2176 struct cleanup *chain;
2177 char annex[32];
2178 gdb_byte buf[1024];
2179 LONGEST len;
2180 int i, id;
2181
e17a4113 2182 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2183 error (_("\"info spu\" is only supported on the SPU architecture."));
2184
23d964e7
UW		 2185 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2186
2187 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
2188
2189 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2190 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2191 buf, 0, sizeof buf);
2192 if (len < 0)
2193 error (_("Could not read mbox_info."));
2194
e17a4113
UW		 2195 info_spu_mailbox_list (buf, len / 4, byte_order,
2196 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2197
2198 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2199 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2200 buf, 0, sizeof buf);
2201 if (len < 0)
2202 error (_("Could not read ibox_info."));
2203
e17a4113
UW		 2204 info_spu_mailbox_list (buf, len / 4, byte_order,
2205 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2206
2207 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2208 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2209 buf, 0, sizeof buf);
2210 if (len < 0)
2211 error (_("Could not read wbox_info."));
2212
e17a4113
UW		 2213 info_spu_mailbox_list (buf, len / 4, byte_order,
2214 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2215
2216 do_cleanups (chain);
2217}
2218
2219static ULONGEST
2220spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2221{
2222 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2223 return (word >> (63 - last)) & mask;
2224}
2225
2226static void
e17a4113 2227info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7
UW		 2228{
2229 static char *spu_mfc_opcode[256] =
2230 {
2231 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2232 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2233 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2234 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2235 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2236 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2237 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2238 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2239 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2240 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2241 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2242 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2243 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2244 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2245 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2246 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2247 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2248 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2249 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2250 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2251 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2252 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2253 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2254 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2255 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2256 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2257 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2258 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2259 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2260 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2261 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2263 };
2264
12ab8a60
UW		 2265 int *seq = alloca (nr * sizeof (int));
2266 int done = 0;
23d964e7 2267 struct cleanup *chain;
12ab8a60
UW		 2268 int i, j;
2269
2270
2271 /* Determine sequence in which to display (valid) entries. */
2272 for (i = 0; i < nr; i++)
2273 {
2274 /* Search for the first valid entry all of whose
2275 dependencies are met. */
2276 for (j = 0; j < nr; j++)
2277 {
2278 ULONGEST mfc_cq_dw3;
2279 ULONGEST dependencies;
2280
2281 if (done & (1 << (nr - 1 - j)))
2282 continue;
2283
e17a4113
UW		 2284 mfc_cq_dw3
2285 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2286 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2287 continue;
2288
2289 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2290 if ((dependencies & done) != dependencies)
2291 continue;
2292
2293 seq[i] = j;
2294 done |= 1 << (nr - 1 - j);
2295 break;
2296 }
2297
2298 if (j == nr)
2299 break;
2300 }
2301
2302 nr = i;
2303
23d964e7
UW		 2304
2305 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
2306
2307 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
2308 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
2309 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
2310 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
2311 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
2312 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
2313 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
2314 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
2315 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
2316 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
2317
2318 ui_out_table_body (uiout);
2319
2320 for (i = 0; i < nr; i++)
2321 {
2322 struct cleanup *cmd_chain;
2323 ULONGEST mfc_cq_dw0;
2324 ULONGEST mfc_cq_dw1;
2325 ULONGEST mfc_cq_dw2;
23d964e7
UW		 2326 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
2327 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
2328 ULONGEST mfc_ea;
2329 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2330
2331 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2332 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2333
e17a4113
UW		 2334 mfc_cq_dw0
2335 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2336 mfc_cq_dw1
2337 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2338 mfc_cq_dw2
2339 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2340
2341 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2342 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2343 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2344 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2345 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2346 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2347 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2348
2349 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2350 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2351
2352 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2353 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2354 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2355 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2356 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2357 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2358
2359 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
2360
2361 if (spu_mfc_opcode[mfc_cmd_opcode])
2362 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
2363 else
2364 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
2365
2366 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
2367 ui_out_field_int (uiout, "tid", tclass_id);
2368 ui_out_field_int (uiout, "rid", rclass_id);
2369
2370 if (ea_valid_p)
2371 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
2372 else
2373 ui_out_field_skip (uiout, "ea");
2374
2375 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
2376 if (qw_valid_p)
2377 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
2378 else
2379 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
2380
2381 if (list_valid_p)
2382 {
2383 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
2384 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
2385 }
2386 else
2387 {
2388 ui_out_field_skip (uiout, "lstaddr");
2389 ui_out_field_skip (uiout, "lstsize");
2390 }
2391
2392 if (cmd_error_p)
2393 ui_out_field_string (uiout, "error_p", "*");
2394 else
2395 ui_out_field_skip (uiout, "error_p");
2396
2397 do_cleanups (cmd_chain);
2398
2399 if (!ui_out_is_mi_like_p (uiout))
2400 printf_filtered ("\n");
2401 }
2402
2403 do_cleanups (chain);
2404}
2405
2406static void
2407info_spu_dma_command (char *args, int from_tty)
2408{
2409 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2410 struct gdbarch *gdbarch = get_frame_arch (frame);
2411 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2412 ULONGEST dma_info_type;
2413 ULONGEST dma_info_mask;
2414 ULONGEST dma_info_status;
2415 ULONGEST dma_info_stall_and_notify;
2416 ULONGEST dma_info_atomic_command_status;
2417 struct cleanup *chain;
2418 char annex[32];
2419 gdb_byte buf[1024];
2420 LONGEST len;
2421 int i, id;
2422
0391f248
UW		 2423 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2424 error (_("\"info spu\" is only supported on the SPU architecture."));
2425
23d964e7
UW		 2426 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2427
2428 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2429 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2430 buf, 0, 40 + 16 * 32);
2431 if (len <= 0)
2432 error (_("Could not read dma_info."));
2433
e17a4113
UW		 2434 dma_info_type
2435 = extract_unsigned_integer (buf, 8, byte_order);
2436 dma_info_mask
2437 = extract_unsigned_integer (buf + 8, 8, byte_order);
2438 dma_info_status
2439 = extract_unsigned_integer (buf + 16, 8, byte_order);
2440 dma_info_stall_and_notify
2441 = extract_unsigned_integer (buf + 24, 8, byte_order);
2442 dma_info_atomic_command_status
2443 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7
UW		 2444
2445 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
2446
2447 if (ui_out_is_mi_like_p (uiout))
2448 {
2449 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
2450 phex_nz (dma_info_type, 4));
2451 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
2452 phex_nz (dma_info_mask, 4));
2453 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
2454 phex_nz (dma_info_status, 4));
2455 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
2456 phex_nz (dma_info_stall_and_notify, 4));
2457 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
2458 phex_nz (dma_info_atomic_command_status, 4));
2459 }
2460 else
2461 {
8fbde58b 2462 const char *query_msg = _("no query pending");
23d964e7 2463
8fbde58b
UW		 2464 if (dma_info_type & 4)
2465 switch (dma_info_type & 3)
2466 {
2467 case 1: query_msg = _("'any' query pending"); break;
2468 case 2: query_msg = _("'all' query pending"); break;
2469 default: query_msg = _("undefined query type"); break;
2470 }
23d964e7
UW		 2471
2472 printf_filtered (_("Tag-Group Status 0x%s\n"),
2473 phex (dma_info_status, 4));
2474 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2475 phex (dma_info_mask, 4), query_msg);
2476 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2477 phex (dma_info_stall_and_notify, 4));
2478 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2479 phex (dma_info_atomic_command_status, 4));
2480 printf_filtered ("\n");
2481 }
2482
e17a4113 2483 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2484 do_cleanups (chain);
2485}
2486
2487static void
2488info_spu_proxydma_command (char *args, int from_tty)
2489{
2490 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2491 struct gdbarch *gdbarch = get_frame_arch (frame);
2492 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2493 ULONGEST dma_info_type;
2494 ULONGEST dma_info_mask;
2495 ULONGEST dma_info_status;
2496 struct cleanup *chain;
2497 char annex[32];
2498 gdb_byte buf[1024];
2499 LONGEST len;
2500 int i, id;
2501
e17a4113 2502 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2503 error (_("\"info spu\" is only supported on the SPU architecture."));
2504
23d964e7
UW		 2505 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2506
2507 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2508 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2509 buf, 0, 24 + 8 * 32);
2510 if (len <= 0)
2511 error (_("Could not read proxydma_info."));
2512
e17a4113
UW		 2513 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2514 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2515 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7
UW		 2516
2517 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
2518
2519 if (ui_out_is_mi_like_p (uiout))
2520 {
2521 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
2522 phex_nz (dma_info_type, 4));
2523 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
2524 phex_nz (dma_info_mask, 4));
2525 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
2526 phex_nz (dma_info_status, 4));
2527 }
2528 else
2529 {
2530 const char *query_msg;
2531
8fbde58b 2532 switch (dma_info_type & 3)
23d964e7
UW		 2533 {
2534 case 0: query_msg = _("no query pending"); break;
2535 case 1: query_msg = _("'any' query pending"); break;
2536 case 2: query_msg = _("'all' query pending"); break;
2537 default: query_msg = _("undefined query type"); break;
2538 }
2539
2540 printf_filtered (_("Tag-Group Status 0x%s\n"),
2541 phex (dma_info_status, 4));
2542 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2543 phex (dma_info_mask, 4), query_msg);
2544 printf_filtered ("\n");
2545 }
2546
e17a4113 2547 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2548 do_cleanups (chain);
2549}
2550
2551static void
2552info_spu_command (char *args, int from_tty)
2553{
c378eb4e
MS		 2554 printf_unfiltered (_("\"info spu\" must be followed by "
2555 "the name of an SPU facility.\n"));
23d964e7
UW		 2556 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2557}
2558
2559
3285f3fe
UW		 2560/* Root of all "set spu "/"show spu " commands. */
2561
2562static void
2563show_spu_command (char *args, int from_tty)
2564{
2565 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2566}
2567
2568static void
2569set_spu_command (char *args, int from_tty)
2570{
2571 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2572}
2573
2574static void
2575show_spu_stop_on_load (struct ui_file *file, int from_tty,
2576 struct cmd_list_element *c, const char *value)
2577{
2578 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2579 value);
2580}
2581
ff1a52c6
UW		 2582static void
2583show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2584 struct cmd_list_element *c, const char *value)
2585{
2586 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2587 value);
2588}
2589
3285f3fe 2590
771b4502
UW		 2591/* Set up gdbarch struct. */
2592
2593static struct gdbarch *
2594spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2595{
2596 struct gdbarch *gdbarch;
794ac428 2597 struct gdbarch_tdep *tdep;
85e747d2
UW		 2598 int id = -1;
2599
2600 /* Which spufs ID was requested as address space? */
2601 if (info.tdep_info)
2602 id = *(int *)info.tdep_info;
2603 /* For objfile architectures of SPU solibs, decode the ID from the name.
2604 This assumes the filename convention employed by solib-spu.c. */
2605 else if (info.abfd)
2606 {
2607 char *name = strrchr (info.abfd->filename, '@');
2608 if (name)
2609 sscanf (name, "@0x%*x <%d>", &id);
2610 }
771b4502 2611
85e747d2
UW		 2612 /* Find a candidate among extant architectures. */
2613 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2614 arches != NULL;
2615 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2616 {
2617 tdep = gdbarch_tdep (arches->gdbarch);
2618 if (tdep && tdep->id == id)
2619 return arches->gdbarch;
2620 }
771b4502 2621
85e747d2 2622 /* None found, so create a new architecture. */
794ac428 2623 tdep = XCALLOC (1, struct gdbarch_tdep);
85e747d2 2624 tdep->id = id;
794ac428 2625 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2626
2627 /* Disassembler. */
85e747d2 2628 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2629
2630 /* Registers. */
2631 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2632 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2633 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2634 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2635 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2636 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2637 set_gdbarch_register_name (gdbarch, spu_register_name);
2638 set_gdbarch_register_type (gdbarch, spu_register_type);
2639 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2640 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2641 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2642 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2643
2644 /* Data types. */
2645 set_gdbarch_char_signed (gdbarch, 0);
2646 set_gdbarch_ptr_bit (gdbarch, 32);
2647 set_gdbarch_addr_bit (gdbarch, 32);
2648 set_gdbarch_short_bit (gdbarch, 16);
2649 set_gdbarch_int_bit (gdbarch, 32);
2650 set_gdbarch_long_bit (gdbarch, 32);
2651 set_gdbarch_long_long_bit (gdbarch, 64);
2652 set_gdbarch_float_bit (gdbarch, 32);
2653 set_gdbarch_double_bit (gdbarch, 64);
2654 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2655 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2656 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2657 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2658
ff1a52c6 2659 /* Address handling. */
85e747d2 2660 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2661 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2662 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2663 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2664 set_gdbarch_address_class_type_flags_to_name
2665 (gdbarch, spu_address_class_type_flags_to_name);
2666 set_gdbarch_address_class_name_to_type_flags
2667 (gdbarch, spu_address_class_name_to_type_flags);
2668
36acd84e 2669
771b4502 2670 /* Inferior function calls. */
7b3dc0b7
UW		 2671 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2672 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2673 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2674 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2675 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2676 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2677 set_gdbarch_return_value (gdbarch, spu_return_value);
2678
2679 /* Frame handling. */
2680 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2681 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2682 frame_base_set_default (gdbarch, &spu_frame_base);
2683 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2684 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2685 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2686 set_gdbarch_frame_args_skip (gdbarch, 0);
2687 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2688 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502 2689
cc5f0d61
UW		 2690 /* Cell/B.E. cross-architecture unwinder support. */
2691 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2692
771b4502
UW		 2693 /* Breakpoints. */
2694 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2695 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
d03285ec 2696 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
771b4502
UW		 2697 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2698 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2699 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2700
dcf52cd8
UW		 2701 /* Overlays. */
2702 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2703
771b4502
UW		 2704 return gdbarch;
2705}
2706
63807e1d
PA		 2707/* Provide a prototype to silence -Wmissing-prototypes. */
2708extern initialize_file_ftype _initialize_spu_tdep;
2709
771b4502
UW		 2710void
2711_initialize_spu_tdep (void)
2712{
2713 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2714
dcf52cd8
UW		 2715 /* Add ourselves to objfile event chain. */
2716 observer_attach_new_objfile (spu_overlay_new_objfile);
2717 spu_overlay_data = register_objfile_data ();
23d964e7 2718
3285f3fe
UW		 2719 /* Install spu stop-on-load handler. */
2720 observer_attach_new_objfile (spu_catch_start);
2721
ff1a52c6
UW		 2722 /* Add ourselves to normal_stop event chain. */
2723 observer_attach_normal_stop (spu_attach_normal_stop);
2724
3285f3fe
UW		 2725 /* Add root prefix command for all "set spu"/"show spu" commands. */
2726 add_prefix_cmd ("spu", no_class, set_spu_command,
2727 _("Various SPU specific commands."),
2728 &setspucmdlist, "set spu ", 0, &setlist);
2729 add_prefix_cmd ("spu", no_class, show_spu_command,
2730 _("Various SPU specific commands."),
2731 &showspucmdlist, "show spu ", 0, &showlist);
2732
2733 /* Toggle whether or not to add a temporary breakpoint at the "main"
2734 function of new SPE contexts. */
2735 add_setshow_boolean_cmd ("stop-on-load", class_support,
2736 &spu_stop_on_load_p, _("\
2737Set whether to stop for new SPE threads."),
2738 _("\
2739Show whether to stop for new SPE threads."),
2740 _("\
2741Use \"on\" to give control to the user when a new SPE thread\n\
2742enters its \"main\" function.\n\
2743Use \"off\" to disable stopping for new SPE threads."),
2744 NULL,
2745 show_spu_stop_on_load,
2746 &setspucmdlist, &showspucmdlist);
2747
ff1a52c6
UW		 2748 /* Toggle whether or not to automatically flush the software-managed
2749 cache whenever SPE execution stops. */
2750 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2751 &spu_auto_flush_cache_p, _("\
2752Set whether to automatically flush the software-managed cache."),
2753 _("\
2754Show whether to automatically flush the software-managed cache."),
2755 _("\
2756Use \"on\" to automatically flush the software-managed cache\n\
2757whenever SPE execution stops.\n\
2758Use \"off\" to never automatically flush the software-managed cache."),
2759 NULL,
2760 show_spu_auto_flush_cache,
2761 &setspucmdlist, &showspucmdlist);
2762
23d964e7
UW		 2763 /* Add root prefix command for all "info spu" commands. */
2764 add_prefix_cmd ("spu", class_info, info_spu_command,
2765 _("Various SPU specific commands."),
2766 &infospucmdlist, "info spu ", 0, &infolist);
2767
2768 /* Add various "info spu" commands. */
2769 add_cmd ("event", class_info, info_spu_event_command,
2770 _("Display SPU event facility status.\n"),
2771 &infospucmdlist);
2772 add_cmd ("signal", class_info, info_spu_signal_command,
2773 _("Display SPU signal notification facility status.\n"),
2774 &infospucmdlist);
2775 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2776 _("Display SPU mailbox facility status.\n"),
2777 &infospucmdlist);
2778 add_cmd ("dma", class_info, info_spu_dma_command,
2779 _("Display MFC DMA status.\n"),
2780 &infospucmdlist);
2781 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2782 _("Display MFC Proxy-DMA status.\n"),
2783 &infospucmdlist);
771b4502 2784}
GDB Binutils - Deliverables
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