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* elf32-ppc.c (allocate_dynrelocs): Ignore dyn_relocs when
[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
9b254dd1 2 Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
27#include "gdb_string.h"
28#include "gdb_assert.h"
29#include "frame.h"
30#include "frame-unwind.h"
31#include "frame-base.h"
32#include "trad-frame.h"
33#include "symtab.h"
34#include "symfile.h"
35#include "value.h"
36#include "inferior.h"
37#include "dis-asm.h"
38#include "objfiles.h"
39#include "language.h"
40#include "regcache.h"
41#include "reggroups.h"
42#include "floatformat.h"
dcf52cd8 43#include "observer.h"
771b4502
UW		 44
45#include "spu-tdep.h"
46
794ac428
UW		 47
48/* The tdep structure. */
49struct gdbarch_tdep
50{
51 /* SPU-specific vector type. */
52 struct type *spu_builtin_type_vec128;
53};
54
55
f2d43c2c 56/* SPU-specific vector type. */
794ac428
UW		 57static struct type *
58spu_builtin_type_vec128 (struct gdbarch *gdbarch)
59{
60 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
61
62 if (!tdep->spu_builtin_type_vec128)
63 {
64 struct type *t;
65
66 t = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION);
67 append_composite_type_field (t, "uint128", builtin_type_int128);
68 append_composite_type_field (t, "v2_int64",
69 init_vector_type (builtin_type_int64, 2));
70 append_composite_type_field (t, "v4_int32",
71 init_vector_type (builtin_type_int32, 4));
72 append_composite_type_field (t, "v8_int16",
73 init_vector_type (builtin_type_int16, 8));
74 append_composite_type_field (t, "v16_int8",
75 init_vector_type (builtin_type_int8, 16));
76 append_composite_type_field (t, "v2_double",
77 init_vector_type (builtin_type_double, 2));
78 append_composite_type_field (t, "v4_float",
79 init_vector_type (builtin_type_float, 4));
80
81 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
82 TYPE_NAME (t) = "spu_builtin_type_vec128";
83
84 tdep->spu_builtin_type_vec128 = t;
85 }
86
87 return tdep->spu_builtin_type_vec128;
88}
89
771b4502 90
23d964e7
UW		 91/* The list of available "info spu " commands. */
92static struct cmd_list_element *infospucmdlist = NULL;
93
771b4502
UW		 94/* Registers. */
95
96static const char *
d93859e2 97spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 98{
99 static char *register_names[] =
100 {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
104 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
105 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
106 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
107 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
108 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
109 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
110 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
111 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
112 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
113 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
114 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
115 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
116 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 117 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 118 };
119
120 if (reg_nr < 0)
121 return NULL;
122 if (reg_nr >= sizeof register_names / sizeof *register_names)
123 return NULL;
124
125 return register_names[reg_nr];
126}
127
128static struct type *
129spu_register_type (struct gdbarch *gdbarch, int reg_nr)
130{
131 if (reg_nr < SPU_NUM_GPRS)
794ac428 132 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 133
134 switch (reg_nr)
135 {
136 case SPU_ID_REGNUM:
137 return builtin_type_uint32;
138
139 case SPU_PC_REGNUM:
140 return builtin_type_void_func_ptr;
141
142 case SPU_SP_REGNUM:
143 return builtin_type_void_data_ptr;
144
23d964e7
UW		 145 case SPU_FPSCR_REGNUM:
146 return builtin_type_uint128;
147
148 case SPU_SRR0_REGNUM:
149 return builtin_type_uint32;
150
151 case SPU_LSLR_REGNUM:
152 return builtin_type_uint32;
153
154 case SPU_DECR_REGNUM:
155 return builtin_type_uint32;
156
157 case SPU_DECR_STATUS_REGNUM:
158 return builtin_type_uint32;
159
771b4502
UW		 160 default:
161 internal_error (__FILE__, __LINE__, "invalid regnum");
162 }
163}
164
165/* Pseudo registers for preferred slots - stack pointer. */
166
23d964e7
UW		 167static void
168spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
169 gdb_byte *buf)
170{
171 gdb_byte reg[32];
172 char annex[32];
173 ULONGEST id;
174
175 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
176 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
177 memset (reg, 0, sizeof reg);
178 target_read (&current_target, TARGET_OBJECT_SPU, annex,
179 reg, 0, sizeof reg);
180
181 store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16));
182}
183
771b4502
UW		 184static void
185spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
186 int regnum, gdb_byte *buf)
187{
188 gdb_byte reg[16];
23d964e7
UW		 189 char annex[32];
190 ULONGEST id;
771b4502
UW		 191
192 switch (regnum)
193 {
194 case SPU_SP_REGNUM:
195 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
196 memcpy (buf, reg, 4);
197 break;
198
23d964e7
UW		 199 case SPU_FPSCR_REGNUM:
200 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
201 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
202 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
203 break;
204
205 case SPU_SRR0_REGNUM:
206 spu_pseudo_register_read_spu (regcache, "srr0", buf);
207 break;
208
209 case SPU_LSLR_REGNUM:
210 spu_pseudo_register_read_spu (regcache, "lslr", buf);
211 break;
212
213 case SPU_DECR_REGNUM:
214 spu_pseudo_register_read_spu (regcache, "decr", buf);
215 break;
216
217 case SPU_DECR_STATUS_REGNUM:
218 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
219 break;
220
771b4502
UW		 221 default:
222 internal_error (__FILE__, __LINE__, _("invalid regnum"));
223 }
224}
225
23d964e7
UW		 226static void
227spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
228 const gdb_byte *buf)
229{
230 gdb_byte reg[32];
231 char annex[32];
232 ULONGEST id;
233
234 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
235 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
236 xsnprintf (reg, sizeof reg, "0x%s",
237 phex_nz (extract_unsigned_integer (buf, 4), 4));
238 target_write (&current_target, TARGET_OBJECT_SPU, annex,
239 reg, 0, strlen (reg));
240}
241
771b4502
UW		 242static void
243spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
244 int regnum, const gdb_byte *buf)
245{
246 gdb_byte reg[16];
23d964e7
UW		 247 char annex[32];
248 ULONGEST id;
771b4502
UW		 249
250 switch (regnum)
251 {
252 case SPU_SP_REGNUM:
253 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
254 memcpy (reg, buf, 4);
255 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
256 break;
257
23d964e7
UW		 258 case SPU_FPSCR_REGNUM:
259 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
260 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
261 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
262 break;
263
264 case SPU_SRR0_REGNUM:
265 spu_pseudo_register_write_spu (regcache, "srr0", buf);
266 break;
267
268 case SPU_LSLR_REGNUM:
269 spu_pseudo_register_write_spu (regcache, "lslr", buf);
270 break;
271
272 case SPU_DECR_REGNUM:
273 spu_pseudo_register_write_spu (regcache, "decr", buf);
274 break;
275
276 case SPU_DECR_STATUS_REGNUM:
277 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
278 break;
279
771b4502
UW		 280 default:
281 internal_error (__FILE__, __LINE__, _("invalid regnum"));
282 }
283}
284
285/* Value conversion -- access scalar values at the preferred slot. */
286
9acbedc0
UW		 287static struct value *
288spu_value_from_register (struct type *type, int regnum,
289 struct frame_info *frame)
771b4502 290{
9acbedc0
UW		 291 struct value *value = default_value_from_register (type, regnum, frame);
292 int len = TYPE_LENGTH (type);
771b4502 293
9acbedc0
UW		 294 if (regnum < SPU_NUM_GPRS && len < 16)
295 {
296 int preferred_slot = len < 4 ? 4 - len : 0;
297 set_value_offset (value, preferred_slot);
298 }
771b4502 299
9acbedc0 300 return value;
771b4502
UW		 301}
302
303/* Register groups. */
304
305static int
306spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
307 struct reggroup *group)
308{
309 /* Registers displayed via 'info regs'. */
310 if (group == general_reggroup)
311 return 1;
312
313 /* Registers displayed via 'info float'. */
314 if (group == float_reggroup)
315 return 0;
316
317 /* Registers that need to be saved/restored in order to
318 push or pop frames. */
319 if (group == save_reggroup || group == restore_reggroup)
320 return 1;
321
322 return default_register_reggroup_p (gdbarch, regnum, group);
323}
324
36acd84e
UW		 325/* Address conversion. */
326
327static CORE_ADDR
328spu_pointer_to_address (struct type *type, const gdb_byte *buf)
329{
330 ULONGEST addr = extract_unsigned_integer (buf, TYPE_LENGTH (type));
331 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
332
333 if (target_has_registers && target_has_stack && target_has_memory)
334 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
335 SPU_LSLR_REGNUM);
336
337 return addr & lslr;
338}
339
340static CORE_ADDR
341spu_integer_to_address (struct gdbarch *gdbarch,
342 struct type *type, const gdb_byte *buf)
343{
344 ULONGEST addr = unpack_long (type, buf);
345 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
346
347 if (target_has_registers && target_has_stack && target_has_memory)
348 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
349 SPU_LSLR_REGNUM);
350
351 return addr & lslr;
352}
353
771b4502
UW		 354
355/* Decoding SPU instructions. */
356
357enum
358 {
359 op_lqd = 0x34,
360 op_lqx = 0x3c4,
361 op_lqa = 0x61,
362 op_lqr = 0x67,
363 op_stqd = 0x24,
364 op_stqx = 0x144,
365 op_stqa = 0x41,
366 op_stqr = 0x47,
367
368 op_il = 0x081,
369 op_ila = 0x21,
370 op_a = 0x0c0,
371 op_ai = 0x1c,
372
373 op_selb = 0x4,
374
375 op_br = 0x64,
376 op_bra = 0x60,
377 op_brsl = 0x66,
378 op_brasl = 0x62,
379 op_brnz = 0x42,
380 op_brz = 0x40,
381 op_brhnz = 0x46,
382 op_brhz = 0x44,
383 op_bi = 0x1a8,
384 op_bisl = 0x1a9,
385 op_biz = 0x128,
386 op_binz = 0x129,
387 op_bihz = 0x12a,
388 op_bihnz = 0x12b,
389 };
390
391static int
392is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
393{
394 if ((insn >> 21) == op)
395 {
396 *rt = insn & 127;
397 *ra = (insn >> 7) & 127;
398 *rb = (insn >> 14) & 127;
399 return 1;
400 }
401
402 return 0;
403}
404
405static int
406is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
407{
408 if ((insn >> 28) == op)
409 {
410 *rt = (insn >> 21) & 127;
411 *ra = (insn >> 7) & 127;
412 *rb = (insn >> 14) & 127;
413 *rc = insn & 127;
414 return 1;
415 }
416
417 return 0;
418}
419
420static int
421is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
422{
423 if ((insn >> 21) == op)
424 {
425 *rt = insn & 127;
426 *ra = (insn >> 7) & 127;
427 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
428 return 1;
429 }
430
431 return 0;
432}
433
434static int
435is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
436{
437 if ((insn >> 24) == op)
438 {
439 *rt = insn & 127;
440 *ra = (insn >> 7) & 127;
441 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
442 return 1;
443 }
444
445 return 0;
446}
447
448static int
449is_ri16 (unsigned int insn, int op, int *rt, int *i16)
450{
451 if ((insn >> 23) == op)
452 {
453 *rt = insn & 127;
454 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
455 return 1;
456 }
457
458 return 0;
459}
460
461static int
462is_ri18 (unsigned int insn, int op, int *rt, int *i18)
463{
464 if ((insn >> 25) == op)
465 {
466 *rt = insn & 127;
467 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
468 return 1;
469 }
470
471 return 0;
472}
473
474static int
475is_branch (unsigned int insn, int *offset, int *reg)
476{
477 int rt, i7, i16;
478
479 if (is_ri16 (insn, op_br, &rt, &i16)
480 || is_ri16 (insn, op_brsl, &rt, &i16)
481 || is_ri16 (insn, op_brnz, &rt, &i16)
482 || is_ri16 (insn, op_brz, &rt, &i16)
483 || is_ri16 (insn, op_brhnz, &rt, &i16)
484 || is_ri16 (insn, op_brhz, &rt, &i16))
485 {
486 *reg = SPU_PC_REGNUM;
487 *offset = i16 << 2;
488 return 1;
489 }
490
491 if (is_ri16 (insn, op_bra, &rt, &i16)
492 || is_ri16 (insn, op_brasl, &rt, &i16))
493 {
494 *reg = -1;
495 *offset = i16 << 2;
496 return 1;
497 }
498
499 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
500 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
501 || is_ri7 (insn, op_biz, &rt, reg, &i7)
502 || is_ri7 (insn, op_binz, &rt, reg, &i7)
503 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
504 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
505 {
506 *offset = 0;
507 return 1;
508 }
509
510 return 0;
511}
512
513
514/* Prolog parsing. */
515
516struct spu_prologue_data
517 {
518 /* Stack frame size. -1 if analysis was unsuccessful. */
519 int size;
520
521 /* How to find the CFA. The CFA is equal to SP at function entry. */
522 int cfa_reg;
523 int cfa_offset;
524
525 /* Offset relative to CFA where a register is saved. -1 if invalid. */
526 int reg_offset[SPU_NUM_GPRS];
527 };
528
529static CORE_ADDR
530spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
531 struct spu_prologue_data *data)
532{
533 int found_sp = 0;
534 int found_fp = 0;
535 int found_lr = 0;
536 int reg_immed[SPU_NUM_GPRS];
537 gdb_byte buf[16];
538 CORE_ADDR prolog_pc = start_pc;
539 CORE_ADDR pc;
540 int i;
541
542
543 /* Initialize DATA to default values. */
544 data->size = -1;
545
546 data->cfa_reg = SPU_RAW_SP_REGNUM;
547 data->cfa_offset = 0;
548
549 for (i = 0; i < SPU_NUM_GPRS; i++)
550 data->reg_offset[i] = -1;
551
552 /* Set up REG_IMMED array. This is non-zero for a register if we know its
553 preferred slot currently holds this immediate value. */
554 for (i = 0; i < SPU_NUM_GPRS; i++)
555 reg_immed[i] = 0;
556
557 /* Scan instructions until the first branch.
558
559 The following instructions are important prolog components:
560
561 - The first instruction to set up the stack pointer.
562 - The first instruction to set up the frame pointer.
563 - The first instruction to save the link register.
564
565 We return the instruction after the latest of these three,
566 or the incoming PC if none is found. The first instruction
567 to set up the stack pointer also defines the frame size.
568
569 Note that instructions saving incoming arguments to their stack
570 slots are not counted as important, because they are hard to
571 identify with certainty. This should not matter much, because
572 arguments are relevant only in code compiled with debug data,
573 and in such code the GDB core will advance until the first source
574 line anyway, using SAL data.
575
576 For purposes of stack unwinding, we analyze the following types
577 of instructions in addition:
578
579 - Any instruction adding to the current frame pointer.
580 - Any instruction loading an immediate constant into a register.
581 - Any instruction storing a register onto the stack.
582
583 These are used to compute the CFA and REG_OFFSET output. */
584
585 for (pc = start_pc; pc < end_pc; pc += 4)
586 {
587 unsigned int insn;
588 int rt, ra, rb, rc, immed;
589
590 if (target_read_memory (pc, buf, 4))
591 break;
592 insn = extract_unsigned_integer (buf, 4);
593
594 /* AI is the typical instruction to set up a stack frame.
595 It is also used to initialize the frame pointer. */
596 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
597 {
598 if (rt == data->cfa_reg && ra == data->cfa_reg)
599 data->cfa_offset -= immed;
600
601 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
602 && !found_sp)
603 {
604 found_sp = 1;
605 prolog_pc = pc + 4;
606
607 data->size = -immed;
608 }
609 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
610 && !found_fp)
611 {
612 found_fp = 1;
613 prolog_pc = pc + 4;
614
615 data->cfa_reg = SPU_FP_REGNUM;
616 data->cfa_offset -= immed;
617 }
618 }
619
620 /* A is used to set up stack frames of size >= 512 bytes.
621 If we have tracked the contents of the addend register,
622 we can handle this as well. */
623 else if (is_rr (insn, op_a, &rt, &ra, &rb))
624 {
625 if (rt == data->cfa_reg && ra == data->cfa_reg)
626 {
627 if (reg_immed[rb] != 0)
628 data->cfa_offset -= reg_immed[rb];
629 else
630 data->cfa_reg = -1; /* We don't know the CFA any more. */
631 }
632
633 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
634 && !found_sp)
635 {
636 found_sp = 1;
637 prolog_pc = pc + 4;
638
639 if (reg_immed[rb] != 0)
640 data->size = -reg_immed[rb];
641 }
642 }
643
644 /* We need to track IL and ILA used to load immediate constants
645 in case they are later used as input to an A instruction. */
646 else if (is_ri16 (insn, op_il, &rt, &immed))
647 {
648 reg_immed[rt] = immed;
12102450
UW		 649
650 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
651 found_sp = 1;
771b4502
UW		 652 }
653
654 else if (is_ri18 (insn, op_ila, &rt, &immed))
655 {
656 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 657
658 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
659 found_sp = 1;
771b4502
UW		 660 }
661
662 /* STQD is used to save registers to the stack. */
663 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
664 {
665 if (ra == data->cfa_reg)
666 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
667
668 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
669 && !found_lr)
670 {
671 found_lr = 1;
672 prolog_pc = pc + 4;
673 }
674 }
675
676 /* _start uses SELB to set up the stack pointer. */
677 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
678 {
679 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
680 found_sp = 1;
681 }
682
683 /* We terminate if we find a branch. */
684 else if (is_branch (insn, &immed, &ra))
685 break;
686 }
687
688
689 /* If we successfully parsed until here, and didn't find any instruction
690 modifying SP, we assume we have a frameless function. */
691 if (!found_sp)
692 data->size = 0;
693
694 /* Return cooked instead of raw SP. */
695 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
696 data->cfa_reg = SPU_SP_REGNUM;
697
698 return prolog_pc;
699}
700
701/* Return the first instruction after the prologue starting at PC. */
702static CORE_ADDR
6093d2eb 703spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 704{
705 struct spu_prologue_data data;
706 return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
707}
708
709/* Return the frame pointer in use at address PC. */
710static void
a54fba4c
MD		 711spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
712 int *reg, LONGEST *offset)
771b4502
UW		 713{
714 struct spu_prologue_data data;
715 spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
716
717 if (data.size != -1 && data.cfa_reg != -1)
718 {
719 /* The 'frame pointer' address is CFA minus frame size. */
720 *reg = data.cfa_reg;
721 *offset = data.cfa_offset - data.size;
722 }
723 else
724 {
725 /* ??? We don't really know ... */
726 *reg = SPU_SP_REGNUM;
727 *offset = 0;
728 }
729}
730
fe5febed
UW		 731/* Return true if we are in the function's epilogue, i.e. after the
732 instruction that destroyed the function's stack frame.
733
734 1) scan forward from the point of execution:
735 a) If you find an instruction that modifies the stack pointer
736 or transfers control (except a return), execution is not in
737 an epilogue, return.
738 b) Stop scanning if you find a return instruction or reach the
739 end of the function or reach the hard limit for the size of
740 an epilogue.
741 2) scan backward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer,
743 execution *is* in an epilogue, return.
744 b) Stop scanning if you reach an instruction that transfers
745 control or the beginning of the function or reach the hard
746 limit for the size of an epilogue. */
747
748static int
749spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
750{
751 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
752 bfd_byte buf[4];
753 unsigned int insn;
754 int rt, ra, rb, rc, immed;
755
756 /* Find the search limits based on function boundaries and hard limit.
757 We assume the epilogue can be up to 64 instructions long. */
758
759 const int spu_max_epilogue_size = 64 * 4;
760
761 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
762 return 0;
763
764 if (pc - func_start < spu_max_epilogue_size)
765 epilogue_start = func_start;
766 else
767 epilogue_start = pc - spu_max_epilogue_size;
768
769 if (func_end - pc < spu_max_epilogue_size)
770 epilogue_end = func_end;
771 else
772 epilogue_end = pc + spu_max_epilogue_size;
773
774 /* Scan forward until next 'bi $0'. */
775
776 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
777 {
778 if (target_read_memory (scan_pc, buf, 4))
779 return 0;
780 insn = extract_unsigned_integer (buf, 4);
781
782 if (is_branch (insn, &immed, &ra))
783 {
784 if (immed == 0 && ra == SPU_LR_REGNUM)
785 break;
786
787 return 0;
788 }
789
790 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
791 || is_rr (insn, op_a, &rt, &ra, &rb)
792 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
793 {
794 if (rt == SPU_RAW_SP_REGNUM)
795 return 0;
796 }
797 }
798
799 if (scan_pc >= epilogue_end)
800 return 0;
801
802 /* Scan backward until adjustment to stack pointer (R1). */
803
804 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
805 {
806 if (target_read_memory (scan_pc, buf, 4))
807 return 0;
808 insn = extract_unsigned_integer (buf, 4);
809
810 if (is_branch (insn, &immed, &ra))
811 return 0;
812
813 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
814 || is_rr (insn, op_a, &rt, &ra, &rb)
815 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
816 {
817 if (rt == SPU_RAW_SP_REGNUM)
818 return 1;
819 }
820 }
821
822 return 0;
823}
824
825
771b4502
UW		 826/* Normal stack frames. */
827
828struct spu_unwind_cache
829{
830 CORE_ADDR func;
831 CORE_ADDR frame_base;
832 CORE_ADDR local_base;
833
834 struct trad_frame_saved_reg *saved_regs;
835};
836
837static struct spu_unwind_cache *
8d998b8f 838spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 839 void **this_prologue_cache)
840{
841 struct spu_unwind_cache *info;
842 struct spu_prologue_data data;
dcf52cd8 843 gdb_byte buf[16];
771b4502
UW		 844
845 if (*this_prologue_cache)
846 return *this_prologue_cache;
847
848 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
849 *this_prologue_cache = info;
8d998b8f 850 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 851 info->frame_base = 0;
852 info->local_base = 0;
853
854 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 855 info->func = get_frame_func (this_frame);
771b4502
UW		 856 if (info->func == 0)
857 {
858 /* Fall back to using the current PC as frame ID. */
8d998b8f 859 info->func = get_frame_pc (this_frame);
771b4502
UW		 860 data.size = -1;
861 }
862 else
8d998b8f 863 spu_analyze_prologue (info->func, get_frame_pc (this_frame), &data);
771b4502
UW		 864
865
866 /* If successful, use prologue analysis data. */
867 if (data.size != -1 && data.cfa_reg != -1)
868 {
869 CORE_ADDR cfa;
870 int i;
771b4502
UW		 871
872 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 873 get_frame_register (this_frame, data.cfa_reg, buf);
771b4502
UW		 874 cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
875
876 /* Call-saved register slots. */
877 for (i = 0; i < SPU_NUM_GPRS; i++)
878 if (i == SPU_LR_REGNUM
879 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
880 if (data.reg_offset[i] != -1)
881 info->saved_regs[i].addr = cfa - data.reg_offset[i];
882
771b4502
UW		 883 /* Frame bases. */
884 info->frame_base = cfa;
885 info->local_base = cfa - data.size;
886 }
887
888 /* Otherwise, fall back to reading the backchain link. */
889 else
890 {
cdc9523a
UW		 891 CORE_ADDR reg;
892 LONGEST backchain;
893 int status;
771b4502
UW		 894
895 /* Get the backchain. */
8d998b8f 896 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
cdc9523a 897 status = safe_read_memory_integer (reg, 4, &backchain);
771b4502
UW		 898
899 /* A zero backchain terminates the frame chain. Also, sanity
900 check against the local store size limit. */
cdc9523a 901 if (status && backchain > 0 && backchain < SPU_LS_SIZE)
771b4502
UW		 902 {
903 /* Assume the link register is saved into its slot. */
904 if (backchain + 16 < SPU_LS_SIZE)
905 info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
906
771b4502
UW		 907 /* Frame bases. */
908 info->frame_base = backchain;
909 info->local_base = reg;
910 }
911 }
dcf52cd8
UW		 912
913 /* The previous SP is equal to the CFA. */
914 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base);
915
0a44cb36
UW		 916 /* Read full contents of the unwound link register in order to
917 be able to determine the return address. */
dcf52cd8
UW		 918 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
919 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
920 else
8d998b8f 921 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 922
0a44cb36
UW		 923 /* Normally, the return address is contained in the slot 0 of the
924 link register, and slots 1-3 are zero. For an overlay return,
925 slot 0 contains the address of the overlay manager return stub,
926 slot 1 contains the partition number of the overlay section to
927 be returned to, and slot 2 contains the return address within
928 that section. Return the latter address in that case. */
dcf52cd8
UW		 929 if (extract_unsigned_integer (buf + 8, 4) != 0)
930 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
931 extract_unsigned_integer (buf + 8, 4));
932 else
933 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
934 extract_unsigned_integer (buf, 4));
771b4502
UW		 935
936 return info;
937}
938
939static void
8d998b8f 940spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 941 void **this_prologue_cache, struct frame_id *this_id)
942{
943 struct spu_unwind_cache *info =
8d998b8f 944 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 945
946 if (info->frame_base == 0)
947 return;
948
949 *this_id = frame_id_build (info->frame_base, info->func);
950}
951
8d998b8f
UW		 952static struct value *
953spu_frame_prev_register (struct frame_info *this_frame,
954 void **this_prologue_cache, int regnum)
771b4502
UW		 955{
956 struct spu_unwind_cache *info
8d998b8f 957 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 958
959 /* Special-case the stack pointer. */
960 if (regnum == SPU_RAW_SP_REGNUM)
961 regnum = SPU_SP_REGNUM;
962
8d998b8f 963 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 964}
965
966static const struct frame_unwind spu_frame_unwind = {
967 NORMAL_FRAME,
968 spu_frame_this_id,
8d998b8f
UW		 969 spu_frame_prev_register,
970 NULL,
971 default_frame_sniffer
771b4502
UW		 972};
973
771b4502 974static CORE_ADDR
8d998b8f 975spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 976{
977 struct spu_unwind_cache *info
8d998b8f 978 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 979 return info->local_base;
980}
981
982static const struct frame_base spu_frame_base = {
983 &spu_frame_unwind,
984 spu_frame_base_address,
985 spu_frame_base_address,
986 spu_frame_base_address
987};
988
989static CORE_ADDR
990spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
991{
118dfbaf
UW		 992 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
993 /* Mask off interrupt enable bit. */
994 return pc & -4;
771b4502
UW		 995}
996
997static CORE_ADDR
998spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
999{
1000 return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1001}
1002
118dfbaf 1003static CORE_ADDR
61a1198a 1004spu_read_pc (struct regcache *regcache)
118dfbaf 1005{
61a1198a
UW		 1006 ULONGEST pc;
1007 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf
UW		 1008 /* Mask off interrupt enable bit. */
1009 return pc & -4;
1010}
1011
1012static void
61a1198a 1013spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1014{
1015 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1016 ULONGEST old_pc;
1017 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1018 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1019 (pc & -4) | (old_pc & 3));
118dfbaf
UW		 1020}
1021
771b4502
UW		 1022
1023/* Function calling convention. */
1024
7b3dc0b7
UW		 1025static CORE_ADDR
1026spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1027{
1028 return sp & ~15;
1029}
1030
771b4502
UW		 1031static int
1032spu_scalar_value_p (struct type *type)
1033{
1034 switch (TYPE_CODE (type))
1035 {
1036 case TYPE_CODE_INT:
1037 case TYPE_CODE_ENUM:
1038 case TYPE_CODE_RANGE:
1039 case TYPE_CODE_CHAR:
1040 case TYPE_CODE_BOOL:
1041 case TYPE_CODE_PTR:
1042 case TYPE_CODE_REF:
1043 return TYPE_LENGTH (type) <= 16;
1044
1045 default:
1046 return 0;
1047 }
1048}
1049
1050static void
1051spu_value_to_regcache (struct regcache *regcache, int regnum,
1052 struct type *type, const gdb_byte *in)
1053{
1054 int len = TYPE_LENGTH (type);
1055
1056 if (spu_scalar_value_p (type))
1057 {
1058 int preferred_slot = len < 4 ? 4 - len : 0;
1059 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1060 }
1061 else
1062 {
1063 while (len >= 16)
1064 {
1065 regcache_cooked_write (regcache, regnum++, in);
1066 in += 16;
1067 len -= 16;
1068 }
1069
1070 if (len > 0)
1071 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1072 }
1073}
1074
1075static void
1076spu_regcache_to_value (struct regcache *regcache, int regnum,
1077 struct type *type, gdb_byte *out)
1078{
1079 int len = TYPE_LENGTH (type);
1080
1081 if (spu_scalar_value_p (type))
1082 {
1083 int preferred_slot = len < 4 ? 4 - len : 0;
1084 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1085 }
1086 else
1087 {
1088 while (len >= 16)
1089 {
1090 regcache_cooked_read (regcache, regnum++, out);
1091 out += 16;
1092 len -= 16;
1093 }
1094
1095 if (len > 0)
1096 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1097 }
1098}
1099
1100static CORE_ADDR
1101spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1102 struct regcache *regcache, CORE_ADDR bp_addr,
1103 int nargs, struct value **args, CORE_ADDR sp,
1104 int struct_return, CORE_ADDR struct_addr)
1105{
1106 int i;
1107 int regnum = SPU_ARG1_REGNUM;
1108 int stack_arg = -1;
1109 gdb_byte buf[16];
1110
1111 /* Set the return address. */
1112 memset (buf, 0, sizeof buf);
1113 store_unsigned_integer (buf, 4, bp_addr);
1114 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1115
1116 /* If STRUCT_RETURN is true, then the struct return address (in
1117 STRUCT_ADDR) will consume the first argument-passing register.
1118 Both adjust the register count and store that value. */
1119 if (struct_return)
1120 {
1121 memset (buf, 0, sizeof buf);
1122 store_unsigned_integer (buf, 4, struct_addr);
1123 regcache_cooked_write (regcache, regnum++, buf);
1124 }
1125
1126 /* Fill in argument registers. */
1127 for (i = 0; i < nargs; i++)
1128 {
1129 struct value *arg = args[i];
1130 struct type *type = check_typedef (value_type (arg));
1131 const gdb_byte *contents = value_contents (arg);
1132 int len = TYPE_LENGTH (type);
1133 int n_regs = align_up (len, 16) / 16;
1134
1135 /* If the argument doesn't wholly fit into registers, it and
1136 all subsequent arguments go to the stack. */
1137 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1138 {
1139 stack_arg = i;
1140 break;
1141 }
1142
1143 spu_value_to_regcache (regcache, regnum, type, contents);
1144 regnum += n_regs;
1145 }
1146
1147 /* Overflow arguments go to the stack. */
1148 if (stack_arg != -1)
1149 {
1150 CORE_ADDR ap;
1151
1152 /* Allocate all required stack size. */
1153 for (i = stack_arg; i < nargs; i++)
1154 {
1155 struct type *type = check_typedef (value_type (args[i]));
1156 sp -= align_up (TYPE_LENGTH (type), 16);
1157 }
1158
1159 /* Fill in stack arguments. */
1160 ap = sp;
1161 for (i = stack_arg; i < nargs; i++)
1162 {
1163 struct value *arg = args[i];
1164 struct type *type = check_typedef (value_type (arg));
1165 int len = TYPE_LENGTH (type);
1166 int preferred_slot;
1167
1168 if (spu_scalar_value_p (type))
1169 preferred_slot = len < 4 ? 4 - len : 0;
1170 else
1171 preferred_slot = 0;
1172
1173 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1174 ap += align_up (TYPE_LENGTH (type), 16);
1175 }
1176 }
1177
1178 /* Allocate stack frame header. */
1179 sp -= 32;
1180
ee82e879
UW		 1181 /* Store stack back chain. */
1182 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1183 target_write_memory (sp, buf, 16);
1184
771b4502
UW		 1185 /* Finally, update the SP register. */
1186 regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp);
1187
1188 return sp;
1189}
1190
1191static struct frame_id
8d998b8f 1192spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1193{
8d998b8f
UW		 1194 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1195 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1196 return frame_id_build (sp, pc & -4);
771b4502
UW		 1197}
1198
1199/* Function return value access. */
1200
1201static enum return_value_convention
c055b101
CV		 1202spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1203 struct type *type, struct regcache *regcache,
1204 gdb_byte *out, const gdb_byte *in)
771b4502
UW		 1205{
1206 enum return_value_convention rvc;
1207
1208 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1209 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1210 else
1211 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1212
1213 if (in)
1214 {
1215 switch (rvc)
1216 {
1217 case RETURN_VALUE_REGISTER_CONVENTION:
1218 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1219 break;
1220
1221 case RETURN_VALUE_STRUCT_CONVENTION:
1222 error ("Cannot set function return value.");
1223 break;
1224 }
1225 }
1226 else if (out)
1227 {
1228 switch (rvc)
1229 {
1230 case RETURN_VALUE_REGISTER_CONVENTION:
1231 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1232 break;
1233
1234 case RETURN_VALUE_STRUCT_CONVENTION:
1235 error ("Function return value unknown.");
1236 break;
1237 }
1238 }
1239
1240 return rvc;
1241}
1242
1243
1244/* Breakpoints. */
1245
1246static const gdb_byte *
67d57894 1247spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1248{
1249 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1250
1251 *lenptr = sizeof breakpoint;
1252 return breakpoint;
1253}
1254
1255
1256/* Software single-stepping support. */
1257
e6590a1b 1258int
0b1b3e42 1259spu_software_single_step (struct frame_info *frame)
771b4502 1260{
e0cd558a
UW		 1261 CORE_ADDR pc, next_pc;
1262 unsigned int insn;
1263 int offset, reg;
1264 gdb_byte buf[4];
771b4502 1265
0b1b3e42 1266 pc = get_frame_pc (frame);
771b4502 1267
e0cd558a
UW		 1268 if (target_read_memory (pc, buf, 4))
1269 return 1;
1270 insn = extract_unsigned_integer (buf, 4);
771b4502 1271
e0cd558a
UW		 1272 /* Next sequential instruction is at PC + 4, except if the current
1273 instruction is a PPE-assisted call, in which case it is at PC + 8.
1274 Wrap around LS limit to be on the safe side. */
1275 if ((insn & 0xffffff00) == 0x00002100)
1276 next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
1277 else
1278 next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
771b4502 1279
e0cd558a 1280 insert_single_step_breakpoint (next_pc);
771b4502 1281
e0cd558a
UW		 1282 if (is_branch (insn, &offset, &reg))
1283 {
1284 CORE_ADDR target = offset;
771b4502 1285
e0cd558a
UW		 1286 if (reg == SPU_PC_REGNUM)
1287 target += pc;
1288 else if (reg != -1)
1289 {
0b1b3e42 1290 get_frame_register_bytes (frame, reg, 0, 4, buf);
e0cd558a 1291 target += extract_unsigned_integer (buf, 4) & -4;
771b4502 1292 }
e0cd558a
UW		 1293
1294 target = target & (SPU_LS_SIZE - 1);
1295 if (target != next_pc)
1296 insert_single_step_breakpoint (target);
771b4502 1297 }
e6590a1b
UW		 1298
1299 return 1;
771b4502
UW		 1300}
1301
dcf52cd8
UW		 1302/* Target overlays for the SPU overlay manager.
1303
1304 See the documentation of simple_overlay_update for how the
1305 interface is supposed to work.
1306
1307 Data structures used by the overlay manager:
1308
1309 struct ovly_table
1310 {
1311 u32 vma;
1312 u32 size;
1313 u32 pos;
1314 u32 buf;
1315 } _ovly_table[]; -- one entry per overlay section
1316
1317 struct ovly_buf_table
1318 {
1319 u32 mapped;
1320 } _ovly_buf_table[]; -- one entry per overlay buffer
1321
1322 _ovly_table should never change.
1323
1324 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1325 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1326 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1327
1328 mapped is an index into _ovly_table. Both the mapped and buf indices start
1329 from one to reference the first entry in their respective tables. */
1330
1331/* Using the per-objfile private data mechanism, we store for each
1332 objfile an array of "struct spu_overlay_table" structures, one
1333 for each obj_section of the objfile. This structure holds two
1334 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1335 is *not* an overlay section. If it is non-zero, it represents
1336 a target address. The overlay section is mapped iff the target
1337 integer at this location equals MAPPED_VAL. */
1338
1339static const struct objfile_data *spu_overlay_data;
1340
1341struct spu_overlay_table
1342 {
1343 CORE_ADDR mapped_ptr;
1344 CORE_ADDR mapped_val;
1345 };
1346
1347/* Retrieve the overlay table for OBJFILE. If not already cached, read
1348 the _ovly_table data structure from the target and initialize the
1349 spu_overlay_table data structure from it. */
1350static struct spu_overlay_table *
1351spu_get_overlay_table (struct objfile *objfile)
1352{
1353 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1354 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1355 unsigned ovly_table_size, ovly_buf_table_size;
1356 struct spu_overlay_table *tbl;
1357 struct obj_section *osect;
1358 char *ovly_table;
1359 int i;
1360
1361 tbl = objfile_data (objfile, spu_overlay_data);
1362 if (tbl)
1363 return tbl;
1364
1365 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1366 if (!ovly_table_msym)
1367 return NULL;
1368
1369 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1370 if (!ovly_buf_table_msym)
1371 return NULL;
1372
1373 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1374 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1375
1376 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1377 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1378
1379 ovly_table = xmalloc (ovly_table_size);
1380 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1381
1382 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1383 objfile->sections_end - objfile->sections,
1384 struct spu_overlay_table);
1385
1386 for (i = 0; i < ovly_table_size / 16; i++)
1387 {
1388 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, 4);
1389 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4);
1390 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, 4);
1391 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, 4);
1392
1393 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1394 continue;
1395
1396 ALL_OBJFILE_OSECTIONS (objfile, osect)
1397 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1398 && pos == osect->the_bfd_section->filepos)
1399 {
1400 int ndx = osect - objfile->sections;
1401 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1402 tbl[ndx].mapped_val = i + 1;
1403 break;
1404 }
1405 }
1406
1407 xfree (ovly_table);
1408 set_objfile_data (objfile, spu_overlay_data, tbl);
1409 return tbl;
1410}
1411
1412/* Read _ovly_buf_table entry from the target to dermine whether
1413 OSECT is currently mapped, and update the mapped state. */
1414static void
1415spu_overlay_update_osect (struct obj_section *osect)
1416{
1417 struct spu_overlay_table *ovly_table;
1418 CORE_ADDR val;
1419
1420 ovly_table = spu_get_overlay_table (osect->objfile);
1421 if (!ovly_table)
1422 return;
1423
1424 ovly_table += osect - osect->objfile->sections;
1425 if (ovly_table->mapped_ptr == 0)
1426 return;
1427
1428 val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4);
1429 osect->ovly_mapped = (val == ovly_table->mapped_val);
1430}
1431
1432/* If OSECT is NULL, then update all sections' mapped state.
1433 If OSECT is non-NULL, then update only OSECT's mapped state. */
1434static void
1435spu_overlay_update (struct obj_section *osect)
1436{
1437 /* Just one section. */
1438 if (osect)
1439 spu_overlay_update_osect (osect);
1440
1441 /* All sections. */
1442 else
1443 {
1444 struct objfile *objfile;
1445
1446 ALL_OBJSECTIONS (objfile, osect)
1447 if (section_is_overlay (osect->the_bfd_section))
1448 spu_overlay_update_osect (osect);
1449 }
1450}
1451
1452/* Whenever a new objfile is loaded, read the target's _ovly_table.
1453 If there is one, go through all sections and make sure for non-
1454 overlay sections LMA equals VMA, while for overlay sections LMA
1455 is larger than local store size. */
1456static void
1457spu_overlay_new_objfile (struct objfile *objfile)
1458{
1459 struct spu_overlay_table *ovly_table;
1460 struct obj_section *osect;
1461
1462 /* If we've already touched this file, do nothing. */
1463 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1464 return;
1465
1466 /* Check if this objfile has overlays. */
1467 ovly_table = spu_get_overlay_table (objfile);
1468 if (!ovly_table)
1469 return;
1470
1471 /* Now go and fiddle with all the LMAs. */
1472 ALL_OBJFILE_OSECTIONS (objfile, osect)
1473 {
1474 bfd *obfd = objfile->obfd;
1475 asection *bsect = osect->the_bfd_section;
1476 int ndx = osect - objfile->sections;
1477
1478 if (ovly_table[ndx].mapped_ptr == 0)
1479 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1480 else
1481 bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1482 }
1483}
1484
771b4502 1485
23d964e7
UW		 1486/* "info spu" commands. */
1487
1488static void
1489info_spu_event_command (char *args, int from_tty)
1490{
1491 struct frame_info *frame = get_selected_frame (NULL);
1492 ULONGEST event_status = 0;
1493 ULONGEST event_mask = 0;
1494 struct cleanup *chain;
1495 gdb_byte buf[100];
1496 char annex[32];
1497 LONGEST len;
1498 int rc, id;
1499
1500 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1501
1502 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1503 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1504 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1505 if (len <= 0)
1506 error (_("Could not read event_status."));
9971ac47 1507 buf[len] = '\0';
23d964e7
UW		 1508 event_status = strtoulst (buf, NULL, 16);
1509
1510 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1511 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1512 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1513 if (len <= 0)
1514 error (_("Could not read event_mask."));
9971ac47 1515 buf[len] = '\0';
23d964e7
UW		 1516 event_mask = strtoulst (buf, NULL, 16);
1517
1518 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1519
1520 if (ui_out_is_mi_like_p (uiout))
1521 {
1522 ui_out_field_fmt (uiout, "event_status",
1523 "0x%s", phex_nz (event_status, 4));
1524 ui_out_field_fmt (uiout, "event_mask",
1525 "0x%s", phex_nz (event_mask, 4));
1526 }
1527 else
1528 {
1529 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1530 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1531 }
1532
1533 do_cleanups (chain);
1534}
1535
1536static void
1537info_spu_signal_command (char *args, int from_tty)
1538{
1539 struct frame_info *frame = get_selected_frame (NULL);
1540 ULONGEST signal1 = 0;
1541 ULONGEST signal1_type = 0;
1542 int signal1_pending = 0;
1543 ULONGEST signal2 = 0;
1544 ULONGEST signal2_type = 0;
1545 int signal2_pending = 0;
1546 struct cleanup *chain;
1547 char annex[32];
1548 gdb_byte buf[100];
1549 LONGEST len;
1550 int rc, id;
1551
1552 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1553
1554 xsnprintf (annex, sizeof annex, "%d/signal1", id);
1555 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1556 if (len < 0)
1557 error (_("Could not read signal1."));
1558 else if (len == 4)
1559 {
1560 signal1 = extract_unsigned_integer (buf, 4);
1561 signal1_pending = 1;
1562 }
1563
1564 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
1565 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1566 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1567 if (len <= 0)
1568 error (_("Could not read signal1_type."));
9971ac47 1569 buf[len] = '\0';
23d964e7
UW		 1570 signal1_type = strtoulst (buf, NULL, 16);
1571
1572 xsnprintf (annex, sizeof annex, "%d/signal2", id);
1573 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1574 if (len < 0)
1575 error (_("Could not read signal2."));
1576 else if (len == 4)
1577 {
1578 signal2 = extract_unsigned_integer (buf, 4);
1579 signal2_pending = 1;
1580 }
1581
1582 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
1583 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1584 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1585 if (len <= 0)
1586 error (_("Could not read signal2_type."));
9971ac47 1587 buf[len] = '\0';
23d964e7
UW		 1588 signal2_type = strtoulst (buf, NULL, 16);
1589
1590 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
1591
1592 if (ui_out_is_mi_like_p (uiout))
1593 {
1594 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
1595 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
1596 ui_out_field_int (uiout, "signal1_type", signal1_type);
1597 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
1598 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
1599 ui_out_field_int (uiout, "signal2_type", signal2_type);
1600 }
1601 else
1602 {
1603 if (signal1_pending)
1604 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
1605 else
1606 printf_filtered (_("Signal 1 not pending "));
1607
1608 if (signal1_type)
23d964e7 1609 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 1610 else
1611 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 1612
1613 if (signal2_pending)
1614 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
1615 else
1616 printf_filtered (_("Signal 2 not pending "));
1617
1618 if (signal2_type)
23d964e7 1619 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 1620 else
1621 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 1622 }
1623
1624 do_cleanups (chain);
1625}
1626
1627static void
1628info_spu_mailbox_list (gdb_byte *buf, int nr,
1629 const char *field, const char *msg)
1630{
1631 struct cleanup *chain;
1632 int i;
1633
1634 if (nr <= 0)
1635 return;
1636
1637 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
1638
1639 ui_out_table_header (uiout, 32, ui_left, field, msg);
1640 ui_out_table_body (uiout);
1641
1642 for (i = 0; i < nr; i++)
1643 {
1644 struct cleanup *val_chain;
1645 ULONGEST val;
1646 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
1647 val = extract_unsigned_integer (buf + 4*i, 4);
1648 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
1649 do_cleanups (val_chain);
1650
1651 if (!ui_out_is_mi_like_p (uiout))
1652 printf_filtered ("\n");
1653 }
1654
1655 do_cleanups (chain);
1656}
1657
1658static void
1659info_spu_mailbox_command (char *args, int from_tty)
1660{
1661 struct frame_info *frame = get_selected_frame (NULL);
1662 struct cleanup *chain;
1663 char annex[32];
1664 gdb_byte buf[1024];
1665 LONGEST len;
1666 int i, id;
1667
1668 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1669
1670 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
1671
1672 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
1673 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1674 buf, 0, sizeof buf);
1675 if (len < 0)
1676 error (_("Could not read mbox_info."));
1677
1678 info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox");
1679
1680 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
1681 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1682 buf, 0, sizeof buf);
1683 if (len < 0)
1684 error (_("Could not read ibox_info."));
1685
1686 info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox");
1687
1688 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
1689 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1690 buf, 0, sizeof buf);
1691 if (len < 0)
1692 error (_("Could not read wbox_info."));
1693
1694 info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox");
1695
1696 do_cleanups (chain);
1697}
1698
1699static ULONGEST
1700spu_mfc_get_bitfield (ULONGEST word, int first, int last)
1701{
1702 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
1703 return (word >> (63 - last)) & mask;
1704}
1705
1706static void
1707info_spu_dma_cmdlist (gdb_byte *buf, int nr)
1708{
1709 static char *spu_mfc_opcode[256] =
1710 {
1711 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1712 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1713 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1714 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1715 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
1716 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
1717 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
1718 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1719 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
1720 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
1721 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1722 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1723 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1724 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1725 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1726 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1727 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
1728 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
1729 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1730 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1731 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
1732 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1733 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
1734 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1735 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1736 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
1737 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1738 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1739 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1740 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1741 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1742 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1743 };
1744
12ab8a60
UW		 1745 int *seq = alloca (nr * sizeof (int));
1746 int done = 0;
23d964e7 1747 struct cleanup *chain;
12ab8a60
UW		 1748 int i, j;
1749
1750
1751 /* Determine sequence in which to display (valid) entries. */
1752 for (i = 0; i < nr; i++)
1753 {
1754 /* Search for the first valid entry all of whose
1755 dependencies are met. */
1756 for (j = 0; j < nr; j++)
1757 {
1758 ULONGEST mfc_cq_dw3;
1759 ULONGEST dependencies;
1760
1761 if (done & (1 << (nr - 1 - j)))
1762 continue;
1763
1764 mfc_cq_dw3 = extract_unsigned_integer (buf + 32*j + 24, 8);
1765 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
1766 continue;
1767
1768 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
1769 if ((dependencies & done) != dependencies)
1770 continue;
1771
1772 seq[i] = j;
1773 done |= 1 << (nr - 1 - j);
1774 break;
1775 }
1776
1777 if (j == nr)
1778 break;
1779 }
1780
1781 nr = i;
1782
23d964e7
UW		 1783
1784 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
1785
1786 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
1787 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
1788 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
1789 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
1790 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
1791 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
1792 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
1793 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
1794 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
1795 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
1796
1797 ui_out_table_body (uiout);
1798
1799 for (i = 0; i < nr; i++)
1800 {
1801 struct cleanup *cmd_chain;
1802 ULONGEST mfc_cq_dw0;
1803 ULONGEST mfc_cq_dw1;
1804 ULONGEST mfc_cq_dw2;
23d964e7
UW		 1805 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
1806 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
1807 ULONGEST mfc_ea;
1808 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
1809
1810 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1811 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1812
12ab8a60
UW		 1813 mfc_cq_dw0 = extract_unsigned_integer (buf + 32*seq[i], 8);
1814 mfc_cq_dw1 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8);
1815 mfc_cq_dw2 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8);
23d964e7
UW		 1816
1817 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
1818 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
1819 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
1820 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
1821 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
1822 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
1823 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
1824
1825 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
1826 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
1827
1828 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
1829 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
1830 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
1831 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
1832 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
1833 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
1834
1835 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
1836
1837 if (spu_mfc_opcode[mfc_cmd_opcode])
1838 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
1839 else
1840 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
1841
1842 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
1843 ui_out_field_int (uiout, "tid", tclass_id);
1844 ui_out_field_int (uiout, "rid", rclass_id);
1845
1846 if (ea_valid_p)
1847 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
1848 else
1849 ui_out_field_skip (uiout, "ea");
1850
1851 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
1852 if (qw_valid_p)
1853 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
1854 else
1855 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
1856
1857 if (list_valid_p)
1858 {
1859 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
1860 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
1861 }
1862 else
1863 {
1864 ui_out_field_skip (uiout, "lstaddr");
1865 ui_out_field_skip (uiout, "lstsize");
1866 }
1867
1868 if (cmd_error_p)
1869 ui_out_field_string (uiout, "error_p", "*");
1870 else
1871 ui_out_field_skip (uiout, "error_p");
1872
1873 do_cleanups (cmd_chain);
1874
1875 if (!ui_out_is_mi_like_p (uiout))
1876 printf_filtered ("\n");
1877 }
1878
1879 do_cleanups (chain);
1880}
1881
1882static void
1883info_spu_dma_command (char *args, int from_tty)
1884{
1885 struct frame_info *frame = get_selected_frame (NULL);
1886 ULONGEST dma_info_type;
1887 ULONGEST dma_info_mask;
1888 ULONGEST dma_info_status;
1889 ULONGEST dma_info_stall_and_notify;
1890 ULONGEST dma_info_atomic_command_status;
1891 struct cleanup *chain;
1892 char annex[32];
1893 gdb_byte buf[1024];
1894 LONGEST len;
1895 int i, id;
1896
1897 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1898
1899 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
1900 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1901 buf, 0, 40 + 16 * 32);
1902 if (len <= 0)
1903 error (_("Could not read dma_info."));
1904
1905 dma_info_type = extract_unsigned_integer (buf, 8);
1906 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1907 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1908 dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8);
1909 dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8);
1910
1911 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
1912
1913 if (ui_out_is_mi_like_p (uiout))
1914 {
1915 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
1916 phex_nz (dma_info_type, 4));
1917 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
1918 phex_nz (dma_info_mask, 4));
1919 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
1920 phex_nz (dma_info_status, 4));
1921 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
1922 phex_nz (dma_info_stall_and_notify, 4));
1923 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
1924 phex_nz (dma_info_atomic_command_status, 4));
1925 }
1926 else
1927 {
1928 const char *query_msg;
1929
1930 switch (dma_info_type)
1931 {
1932 case 0: query_msg = _("no query pending"); break;
1933 case 1: query_msg = _("'any' query pending"); break;
1934 case 2: query_msg = _("'all' query pending"); break;
1935 default: query_msg = _("undefined query type"); break;
1936 }
1937
1938 printf_filtered (_("Tag-Group Status 0x%s\n"),
1939 phex (dma_info_status, 4));
1940 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1941 phex (dma_info_mask, 4), query_msg);
1942 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1943 phex (dma_info_stall_and_notify, 4));
1944 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1945 phex (dma_info_atomic_command_status, 4));
1946 printf_filtered ("\n");
1947 }
1948
1949 info_spu_dma_cmdlist (buf + 40, 16);
1950 do_cleanups (chain);
1951}
1952
1953static void
1954info_spu_proxydma_command (char *args, int from_tty)
1955{
1956 struct frame_info *frame = get_selected_frame (NULL);
1957 ULONGEST dma_info_type;
1958 ULONGEST dma_info_mask;
1959 ULONGEST dma_info_status;
1960 struct cleanup *chain;
1961 char annex[32];
1962 gdb_byte buf[1024];
1963 LONGEST len;
1964 int i, id;
1965
1966 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1967
1968 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
1969 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1970 buf, 0, 24 + 8 * 32);
1971 if (len <= 0)
1972 error (_("Could not read proxydma_info."));
1973
1974 dma_info_type = extract_unsigned_integer (buf, 8);
1975 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1976 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1977
1978 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
1979
1980 if (ui_out_is_mi_like_p (uiout))
1981 {
1982 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
1983 phex_nz (dma_info_type, 4));
1984 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
1985 phex_nz (dma_info_mask, 4));
1986 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
1987 phex_nz (dma_info_status, 4));
1988 }
1989 else
1990 {
1991 const char *query_msg;
1992
1993 switch (dma_info_type)
1994 {
1995 case 0: query_msg = _("no query pending"); break;
1996 case 1: query_msg = _("'any' query pending"); break;
1997 case 2: query_msg = _("'all' query pending"); break;
1998 default: query_msg = _("undefined query type"); break;
1999 }
2000
2001 printf_filtered (_("Tag-Group Status 0x%s\n"),
2002 phex (dma_info_status, 4));
2003 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2004 phex (dma_info_mask, 4), query_msg);
2005 printf_filtered ("\n");
2006 }
2007
2008 info_spu_dma_cmdlist (buf + 24, 8);
2009 do_cleanups (chain);
2010}
2011
2012static void
2013info_spu_command (char *args, int from_tty)
2014{
2015 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
2016 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2017}
2018
2019
771b4502
UW		 2020/* Set up gdbarch struct. */
2021
2022static struct gdbarch *
2023spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2024{
2025 struct gdbarch *gdbarch;
794ac428 2026 struct gdbarch_tdep *tdep;
771b4502
UW		 2027
2028 /* Find a candidate among the list of pre-declared architectures. */
2029 arches = gdbarch_list_lookup_by_info (arches, &info);
2030 if (arches != NULL)
2031 return arches->gdbarch;
2032
2033 /* Is is for us? */
2034 if (info.bfd_arch_info->mach != bfd_mach_spu)
2035 return NULL;
2036
2037 /* Yes, create a new architecture. */
794ac428
UW		 2038 tdep = XCALLOC (1, struct gdbarch_tdep);
2039 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2040
2041 /* Disassembler. */
2042 set_gdbarch_print_insn (gdbarch, print_insn_spu);
2043
2044 /* Registers. */
2045 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2046 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2047 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2048 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2049 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2050 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2051 set_gdbarch_register_name (gdbarch, spu_register_name);
2052 set_gdbarch_register_type (gdbarch, spu_register_type);
2053 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2054 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2055 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2056 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2057
2058 /* Data types. */
2059 set_gdbarch_char_signed (gdbarch, 0);
2060 set_gdbarch_ptr_bit (gdbarch, 32);
2061 set_gdbarch_addr_bit (gdbarch, 32);
2062 set_gdbarch_short_bit (gdbarch, 16);
2063 set_gdbarch_int_bit (gdbarch, 32);
2064 set_gdbarch_long_bit (gdbarch, 32);
2065 set_gdbarch_long_long_bit (gdbarch, 64);
2066 set_gdbarch_float_bit (gdbarch, 32);
2067 set_gdbarch_double_bit (gdbarch, 64);
2068 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2069 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2070 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2071 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2072
36acd84e
UW		 2073 /* Address conversion. */
2074 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2075 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2076
771b4502 2077 /* Inferior function calls. */
7b3dc0b7
UW		 2078 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2079 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2080 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
771b4502 2081 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2082 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2083 set_gdbarch_return_value (gdbarch, spu_return_value);
2084
2085 /* Frame handling. */
2086 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2087 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2088 frame_base_set_default (gdbarch, &spu_frame_base);
2089 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2090 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2091 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2092 set_gdbarch_frame_args_skip (gdbarch, 0);
2093 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2094 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502
UW		 2095
2096 /* Breakpoints. */
2097 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2098 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2099 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2100 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2101
dcf52cd8
UW		 2102 /* Overlays. */
2103 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2104
771b4502
UW		 2105 return gdbarch;
2106}
2107
2108void
2109_initialize_spu_tdep (void)
2110{
2111 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2112
dcf52cd8
UW		 2113 /* Add ourselves to objfile event chain. */
2114 observer_attach_new_objfile (spu_overlay_new_objfile);
2115 spu_overlay_data = register_objfile_data ();
23d964e7
UW		 2116
2117 /* Add root prefix command for all "info spu" commands. */
2118 add_prefix_cmd ("spu", class_info, info_spu_command,
2119 _("Various SPU specific commands."),
2120 &infospucmdlist, "info spu ", 0, &infolist);
2121
2122 /* Add various "info spu" commands. */
2123 add_cmd ("event", class_info, info_spu_event_command,
2124 _("Display SPU event facility status.\n"),
2125 &infospucmdlist);
2126 add_cmd ("signal", class_info, info_spu_signal_command,
2127 _("Display SPU signal notification facility status.\n"),
2128 &infospucmdlist);
2129 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2130 _("Display SPU mailbox facility status.\n"),
2131 &infospucmdlist);
2132 add_cmd ("dma", class_info, info_spu_dma_command,
2133 _("Display MFC DMA status.\n"),
2134 &infospucmdlist);
2135 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2136 _("Display MFC Proxy-DMA status.\n"),
2137 &infospucmdlist);
771b4502 2138}
GDB Binutils - Deliverables
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