projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* valprint.c (val_print): Add new language parameter and use it
[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
CommitLineData
771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
9b254dd1 2 Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
27#include "gdb_string.h"
28#include "gdb_assert.h"
29#include "frame.h"
30#include "frame-unwind.h"
31#include "frame-base.h"
32#include "trad-frame.h"
33#include "symtab.h"
34#include "symfile.h"
35#include "value.h"
36#include "inferior.h"
37#include "dis-asm.h"
38#include "objfiles.h"
39#include "language.h"
40#include "regcache.h"
41#include "reggroups.h"
42#include "floatformat.h"
dcf52cd8 43#include "observer.h"
771b4502
UW		 44
45#include "spu-tdep.h"
46
794ac428
UW		 47
48/* The tdep structure. */
49struct gdbarch_tdep
50{
51 /* SPU-specific vector type. */
52 struct type *spu_builtin_type_vec128;
53};
54
55
f2d43c2c 56/* SPU-specific vector type. */
794ac428
UW		 57static struct type *
58spu_builtin_type_vec128 (struct gdbarch *gdbarch)
59{
60 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
61
62 if (!tdep->spu_builtin_type_vec128)
63 {
64 struct type *t;
65
66 t = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION);
67 append_composite_type_field (t, "uint128", builtin_type_int128);
68 append_composite_type_field (t, "v2_int64",
69 init_vector_type (builtin_type_int64, 2));
70 append_composite_type_field (t, "v4_int32",
71 init_vector_type (builtin_type_int32, 4));
72 append_composite_type_field (t, "v8_int16",
73 init_vector_type (builtin_type_int16, 8));
74 append_composite_type_field (t, "v16_int8",
75 init_vector_type (builtin_type_int8, 16));
76 append_composite_type_field (t, "v2_double",
77 init_vector_type (builtin_type_double, 2));
78 append_composite_type_field (t, "v4_float",
79 init_vector_type (builtin_type_float, 4));
80
81 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
82 TYPE_NAME (t) = "spu_builtin_type_vec128";
83
84 tdep->spu_builtin_type_vec128 = t;
85 }
86
87 return tdep->spu_builtin_type_vec128;
88}
89
771b4502 90
23d964e7
UW		 91/* The list of available "info spu " commands. */
92static struct cmd_list_element *infospucmdlist = NULL;
93
771b4502
UW		 94/* Registers. */
95
96static const char *
d93859e2 97spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 98{
99 static char *register_names[] =
100 {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
104 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
105 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
106 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
107 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
108 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
109 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
110 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
111 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
112 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
113 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
114 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
115 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
116 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 117 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 118 };
119
120 if (reg_nr < 0)
121 return NULL;
122 if (reg_nr >= sizeof register_names / sizeof *register_names)
123 return NULL;
124
125 return register_names[reg_nr];
126}
127
128static struct type *
129spu_register_type (struct gdbarch *gdbarch, int reg_nr)
130{
131 if (reg_nr < SPU_NUM_GPRS)
794ac428 132 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 133
134 switch (reg_nr)
135 {
136 case SPU_ID_REGNUM:
137 return builtin_type_uint32;
138
139 case SPU_PC_REGNUM:
140 return builtin_type_void_func_ptr;
141
142 case SPU_SP_REGNUM:
143 return builtin_type_void_data_ptr;
144
23d964e7
UW		 145 case SPU_FPSCR_REGNUM:
146 return builtin_type_uint128;
147
148 case SPU_SRR0_REGNUM:
149 return builtin_type_uint32;
150
151 case SPU_LSLR_REGNUM:
152 return builtin_type_uint32;
153
154 case SPU_DECR_REGNUM:
155 return builtin_type_uint32;
156
157 case SPU_DECR_STATUS_REGNUM:
158 return builtin_type_uint32;
159
771b4502
UW		 160 default:
161 internal_error (__FILE__, __LINE__, "invalid regnum");
162 }
163}
164
165/* Pseudo registers for preferred slots - stack pointer. */
166
23d964e7
UW		 167static void
168spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
169 gdb_byte *buf)
170{
171 gdb_byte reg[32];
172 char annex[32];
173 ULONGEST id;
174
175 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
176 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
177 memset (reg, 0, sizeof reg);
178 target_read (&current_target, TARGET_OBJECT_SPU, annex,
179 reg, 0, sizeof reg);
180
181 store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16));
182}
183
771b4502
UW		 184static void
185spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
186 int regnum, gdb_byte *buf)
187{
188 gdb_byte reg[16];
23d964e7
UW		 189 char annex[32];
190 ULONGEST id;
771b4502
UW		 191
192 switch (regnum)
193 {
194 case SPU_SP_REGNUM:
195 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
196 memcpy (buf, reg, 4);
197 break;
198
23d964e7
UW		 199 case SPU_FPSCR_REGNUM:
200 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
201 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
202 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
203 break;
204
205 case SPU_SRR0_REGNUM:
206 spu_pseudo_register_read_spu (regcache, "srr0", buf);
207 break;
208
209 case SPU_LSLR_REGNUM:
210 spu_pseudo_register_read_spu (regcache, "lslr", buf);
211 break;
212
213 case SPU_DECR_REGNUM:
214 spu_pseudo_register_read_spu (regcache, "decr", buf);
215 break;
216
217 case SPU_DECR_STATUS_REGNUM:
218 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
219 break;
220
771b4502
UW		 221 default:
222 internal_error (__FILE__, __LINE__, _("invalid regnum"));
223 }
224}
225
23d964e7
UW		 226static void
227spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
228 const gdb_byte *buf)
229{
230 gdb_byte reg[32];
231 char annex[32];
232 ULONGEST id;
233
234 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
235 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
236 xsnprintf (reg, sizeof reg, "0x%s",
237 phex_nz (extract_unsigned_integer (buf, 4), 4));
238 target_write (&current_target, TARGET_OBJECT_SPU, annex,
239 reg, 0, strlen (reg));
240}
241
771b4502
UW		 242static void
243spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
244 int regnum, const gdb_byte *buf)
245{
246 gdb_byte reg[16];
23d964e7
UW		 247 char annex[32];
248 ULONGEST id;
771b4502
UW		 249
250 switch (regnum)
251 {
252 case SPU_SP_REGNUM:
253 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
254 memcpy (reg, buf, 4);
255 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
256 break;
257
23d964e7
UW		 258 case SPU_FPSCR_REGNUM:
259 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
260 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
261 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
262 break;
263
264 case SPU_SRR0_REGNUM:
265 spu_pseudo_register_write_spu (regcache, "srr0", buf);
266 break;
267
268 case SPU_LSLR_REGNUM:
269 spu_pseudo_register_write_spu (regcache, "lslr", buf);
270 break;
271
272 case SPU_DECR_REGNUM:
273 spu_pseudo_register_write_spu (regcache, "decr", buf);
274 break;
275
276 case SPU_DECR_STATUS_REGNUM:
277 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
278 break;
279
771b4502
UW		 280 default:
281 internal_error (__FILE__, __LINE__, _("invalid regnum"));
282 }
283}
284
285/* Value conversion -- access scalar values at the preferred slot. */
286
9acbedc0
UW		 287static struct value *
288spu_value_from_register (struct type *type, int regnum,
289 struct frame_info *frame)
771b4502 290{
9acbedc0
UW		 291 struct value *value = default_value_from_register (type, regnum, frame);
292 int len = TYPE_LENGTH (type);
771b4502 293
9acbedc0
UW		 294 if (regnum < SPU_NUM_GPRS && len < 16)
295 {
296 int preferred_slot = len < 4 ? 4 - len : 0;
297 set_value_offset (value, preferred_slot);
298 }
771b4502 299
9acbedc0 300 return value;
771b4502
UW		 301}
302
303/* Register groups. */
304
305static int
306spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
307 struct reggroup *group)
308{
309 /* Registers displayed via 'info regs'. */
310 if (group == general_reggroup)
311 return 1;
312
313 /* Registers displayed via 'info float'. */
314 if (group == float_reggroup)
315 return 0;
316
317 /* Registers that need to be saved/restored in order to
318 push or pop frames. */
319 if (group == save_reggroup || group == restore_reggroup)
320 return 1;
321
322 return default_register_reggroup_p (gdbarch, regnum, group);
323}
324
36acd84e
UW		 325/* Address conversion. */
326
327static CORE_ADDR
328spu_pointer_to_address (struct type *type, const gdb_byte *buf)
329{
330 ULONGEST addr = extract_unsigned_integer (buf, TYPE_LENGTH (type));
331 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
332
333 if (target_has_registers && target_has_stack && target_has_memory)
334 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
335 SPU_LSLR_REGNUM);
336
337 return addr & lslr;
338}
339
340static CORE_ADDR
341spu_integer_to_address (struct gdbarch *gdbarch,
342 struct type *type, const gdb_byte *buf)
343{
344 ULONGEST addr = unpack_long (type, buf);
345 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
346
347 if (target_has_registers && target_has_stack && target_has_memory)
348 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
349 SPU_LSLR_REGNUM);
350
351 return addr & lslr;
352}
353
771b4502
UW		 354
355/* Decoding SPU instructions. */
356
357enum
358 {
359 op_lqd = 0x34,
360 op_lqx = 0x3c4,
361 op_lqa = 0x61,
362 op_lqr = 0x67,
363 op_stqd = 0x24,
364 op_stqx = 0x144,
365 op_stqa = 0x41,
366 op_stqr = 0x47,
367
368 op_il = 0x081,
369 op_ila = 0x21,
370 op_a = 0x0c0,
371 op_ai = 0x1c,
372
373 op_selb = 0x4,
374
375 op_br = 0x64,
376 op_bra = 0x60,
377 op_brsl = 0x66,
378 op_brasl = 0x62,
379 op_brnz = 0x42,
380 op_brz = 0x40,
381 op_brhnz = 0x46,
382 op_brhz = 0x44,
383 op_bi = 0x1a8,
384 op_bisl = 0x1a9,
385 op_biz = 0x128,
386 op_binz = 0x129,
387 op_bihz = 0x12a,
388 op_bihnz = 0x12b,
389 };
390
391static int
392is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
393{
394 if ((insn >> 21) == op)
395 {
396 *rt = insn & 127;
397 *ra = (insn >> 7) & 127;
398 *rb = (insn >> 14) & 127;
399 return 1;
400 }
401
402 return 0;
403}
404
405static int
406is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
407{
408 if ((insn >> 28) == op)
409 {
410 *rt = (insn >> 21) & 127;
411 *ra = (insn >> 7) & 127;
412 *rb = (insn >> 14) & 127;
413 *rc = insn & 127;
414 return 1;
415 }
416
417 return 0;
418}
419
420static int
421is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
422{
423 if ((insn >> 21) == op)
424 {
425 *rt = insn & 127;
426 *ra = (insn >> 7) & 127;
427 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
428 return 1;
429 }
430
431 return 0;
432}
433
434static int
435is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
436{
437 if ((insn >> 24) == op)
438 {
439 *rt = insn & 127;
440 *ra = (insn >> 7) & 127;
441 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
442 return 1;
443 }
444
445 return 0;
446}
447
448static int
449is_ri16 (unsigned int insn, int op, int *rt, int *i16)
450{
451 if ((insn >> 23) == op)
452 {
453 *rt = insn & 127;
454 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
455 return 1;
456 }
457
458 return 0;
459}
460
461static int
462is_ri18 (unsigned int insn, int op, int *rt, int *i18)
463{
464 if ((insn >> 25) == op)
465 {
466 *rt = insn & 127;
467 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
468 return 1;
469 }
470
471 return 0;
472}
473
474static int
475is_branch (unsigned int insn, int *offset, int *reg)
476{
477 int rt, i7, i16;
478
479 if (is_ri16 (insn, op_br, &rt, &i16)
480 || is_ri16 (insn, op_brsl, &rt, &i16)
481 || is_ri16 (insn, op_brnz, &rt, &i16)
482 || is_ri16 (insn, op_brz, &rt, &i16)
483 || is_ri16 (insn, op_brhnz, &rt, &i16)
484 || is_ri16 (insn, op_brhz, &rt, &i16))
485 {
486 *reg = SPU_PC_REGNUM;
487 *offset = i16 << 2;
488 return 1;
489 }
490
491 if (is_ri16 (insn, op_bra, &rt, &i16)
492 || is_ri16 (insn, op_brasl, &rt, &i16))
493 {
494 *reg = -1;
495 *offset = i16 << 2;
496 return 1;
497 }
498
499 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
500 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
501 || is_ri7 (insn, op_biz, &rt, reg, &i7)
502 || is_ri7 (insn, op_binz, &rt, reg, &i7)
503 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
504 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
505 {
506 *offset = 0;
507 return 1;
508 }
509
510 return 0;
511}
512
513
514/* Prolog parsing. */
515
516struct spu_prologue_data
517 {
518 /* Stack frame size. -1 if analysis was unsuccessful. */
519 int size;
520
521 /* How to find the CFA. The CFA is equal to SP at function entry. */
522 int cfa_reg;
523 int cfa_offset;
524
525 /* Offset relative to CFA where a register is saved. -1 if invalid. */
526 int reg_offset[SPU_NUM_GPRS];
527 };
528
529static CORE_ADDR
530spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
531 struct spu_prologue_data *data)
532{
533 int found_sp = 0;
534 int found_fp = 0;
535 int found_lr = 0;
536 int reg_immed[SPU_NUM_GPRS];
537 gdb_byte buf[16];
538 CORE_ADDR prolog_pc = start_pc;
539 CORE_ADDR pc;
540 int i;
541
542
543 /* Initialize DATA to default values. */
544 data->size = -1;
545
546 data->cfa_reg = SPU_RAW_SP_REGNUM;
547 data->cfa_offset = 0;
548
549 for (i = 0; i < SPU_NUM_GPRS; i++)
550 data->reg_offset[i] = -1;
551
552 /* Set up REG_IMMED array. This is non-zero for a register if we know its
553 preferred slot currently holds this immediate value. */
554 for (i = 0; i < SPU_NUM_GPRS; i++)
555 reg_immed[i] = 0;
556
557 /* Scan instructions until the first branch.
558
559 The following instructions are important prolog components:
560
561 - The first instruction to set up the stack pointer.
562 - The first instruction to set up the frame pointer.
563 - The first instruction to save the link register.
564
565 We return the instruction after the latest of these three,
566 or the incoming PC if none is found. The first instruction
567 to set up the stack pointer also defines the frame size.
568
569 Note that instructions saving incoming arguments to their stack
570 slots are not counted as important, because they are hard to
571 identify with certainty. This should not matter much, because
572 arguments are relevant only in code compiled with debug data,
573 and in such code the GDB core will advance until the first source
574 line anyway, using SAL data.
575
576 For purposes of stack unwinding, we analyze the following types
577 of instructions in addition:
578
579 - Any instruction adding to the current frame pointer.
580 - Any instruction loading an immediate constant into a register.
581 - Any instruction storing a register onto the stack.
582
583 These are used to compute the CFA and REG_OFFSET output. */
584
585 for (pc = start_pc; pc < end_pc; pc += 4)
586 {
587 unsigned int insn;
588 int rt, ra, rb, rc, immed;
589
590 if (target_read_memory (pc, buf, 4))
591 break;
592 insn = extract_unsigned_integer (buf, 4);
593
594 /* AI is the typical instruction to set up a stack frame.
595 It is also used to initialize the frame pointer. */
596 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
597 {
598 if (rt == data->cfa_reg && ra == data->cfa_reg)
599 data->cfa_offset -= immed;
600
601 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
602 && !found_sp)
603 {
604 found_sp = 1;
605 prolog_pc = pc + 4;
606
607 data->size = -immed;
608 }
609 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
610 && !found_fp)
611 {
612 found_fp = 1;
613 prolog_pc = pc + 4;
614
615 data->cfa_reg = SPU_FP_REGNUM;
616 data->cfa_offset -= immed;
617 }
618 }
619
620 /* A is used to set up stack frames of size >= 512 bytes.
621 If we have tracked the contents of the addend register,
622 we can handle this as well. */
623 else if (is_rr (insn, op_a, &rt, &ra, &rb))
624 {
625 if (rt == data->cfa_reg && ra == data->cfa_reg)
626 {
627 if (reg_immed[rb] != 0)
628 data->cfa_offset -= reg_immed[rb];
629 else
630 data->cfa_reg = -1; /* We don't know the CFA any more. */
631 }
632
633 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
634 && !found_sp)
635 {
636 found_sp = 1;
637 prolog_pc = pc + 4;
638
639 if (reg_immed[rb] != 0)
640 data->size = -reg_immed[rb];
641 }
642 }
643
644 /* We need to track IL and ILA used to load immediate constants
645 in case they are later used as input to an A instruction. */
646 else if (is_ri16 (insn, op_il, &rt, &immed))
647 {
648 reg_immed[rt] = immed;
12102450
UW		 649
650 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
651 found_sp = 1;
771b4502
UW		 652 }
653
654 else if (is_ri18 (insn, op_ila, &rt, &immed))
655 {
656 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 657
658 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
659 found_sp = 1;
771b4502
UW		 660 }
661
662 /* STQD is used to save registers to the stack. */
663 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
664 {
665 if (ra == data->cfa_reg)
666 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
667
668 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
669 && !found_lr)
670 {
671 found_lr = 1;
672 prolog_pc = pc + 4;
673 }
674 }
675
676 /* _start uses SELB to set up the stack pointer. */
677 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
678 {
679 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
680 found_sp = 1;
681 }
682
683 /* We terminate if we find a branch. */
684 else if (is_branch (insn, &immed, &ra))
685 break;
686 }
687
688
689 /* If we successfully parsed until here, and didn't find any instruction
690 modifying SP, we assume we have a frameless function. */
691 if (!found_sp)
692 data->size = 0;
693
694 /* Return cooked instead of raw SP. */
695 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
696 data->cfa_reg = SPU_SP_REGNUM;
697
698 return prolog_pc;
699}
700
701/* Return the first instruction after the prologue starting at PC. */
702static CORE_ADDR
6093d2eb 703spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 704{
705 struct spu_prologue_data data;
706 return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
707}
708
709/* Return the frame pointer in use at address PC. */
710static void
a54fba4c
MD		 711spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
712 int *reg, LONGEST *offset)
771b4502
UW		 713{
714 struct spu_prologue_data data;
715 spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
716
717 if (data.size != -1 && data.cfa_reg != -1)
718 {
719 /* The 'frame pointer' address is CFA minus frame size. */
720 *reg = data.cfa_reg;
721 *offset = data.cfa_offset - data.size;
722 }
723 else
724 {
725 /* ??? We don't really know ... */
726 *reg = SPU_SP_REGNUM;
727 *offset = 0;
728 }
729}
730
fe5febed
UW		 731/* Return true if we are in the function's epilogue, i.e. after the
732 instruction that destroyed the function's stack frame.
733
734 1) scan forward from the point of execution:
735 a) If you find an instruction that modifies the stack pointer
736 or transfers control (except a return), execution is not in
737 an epilogue, return.
738 b) Stop scanning if you find a return instruction or reach the
739 end of the function or reach the hard limit for the size of
740 an epilogue.
741 2) scan backward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer,
743 execution *is* in an epilogue, return.
744 b) Stop scanning if you reach an instruction that transfers
745 control or the beginning of the function or reach the hard
746 limit for the size of an epilogue. */
747
748static int
749spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
750{
751 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
752 bfd_byte buf[4];
753 unsigned int insn;
754 int rt, ra, rb, rc, immed;
755
756 /* Find the search limits based on function boundaries and hard limit.
757 We assume the epilogue can be up to 64 instructions long. */
758
759 const int spu_max_epilogue_size = 64 * 4;
760
761 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
762 return 0;
763
764 if (pc - func_start < spu_max_epilogue_size)
765 epilogue_start = func_start;
766 else
767 epilogue_start = pc - spu_max_epilogue_size;
768
769 if (func_end - pc < spu_max_epilogue_size)
770 epilogue_end = func_end;
771 else
772 epilogue_end = pc + spu_max_epilogue_size;
773
774 /* Scan forward until next 'bi $0'. */
775
776 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
777 {
778 if (target_read_memory (scan_pc, buf, 4))
779 return 0;
780 insn = extract_unsigned_integer (buf, 4);
781
782 if (is_branch (insn, &immed, &ra))
783 {
784 if (immed == 0 && ra == SPU_LR_REGNUM)
785 break;
786
787 return 0;
788 }
789
790 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
791 || is_rr (insn, op_a, &rt, &ra, &rb)
792 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
793 {
794 if (rt == SPU_RAW_SP_REGNUM)
795 return 0;
796 }
797 }
798
799 if (scan_pc >= epilogue_end)
800 return 0;
801
802 /* Scan backward until adjustment to stack pointer (R1). */
803
804 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
805 {
806 if (target_read_memory (scan_pc, buf, 4))
807 return 0;
808 insn = extract_unsigned_integer (buf, 4);
809
810 if (is_branch (insn, &immed, &ra))
811 return 0;
812
813 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
814 || is_rr (insn, op_a, &rt, &ra, &rb)
815 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
816 {
817 if (rt == SPU_RAW_SP_REGNUM)
818 return 1;
819 }
820 }
821
822 return 0;
823}
824
825
771b4502
UW		 826/* Normal stack frames. */
827
828struct spu_unwind_cache
829{
830 CORE_ADDR func;
831 CORE_ADDR frame_base;
832 CORE_ADDR local_base;
833
834 struct trad_frame_saved_reg *saved_regs;
835};
836
837static struct spu_unwind_cache *
8d998b8f 838spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 839 void **this_prologue_cache)
840{
841 struct spu_unwind_cache *info;
842 struct spu_prologue_data data;
dcf52cd8 843 gdb_byte buf[16];
771b4502
UW		 844
845 if (*this_prologue_cache)
846 return *this_prologue_cache;
847
848 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
849 *this_prologue_cache = info;
8d998b8f 850 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 851 info->frame_base = 0;
852 info->local_base = 0;
853
854 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 855 info->func = get_frame_func (this_frame);
771b4502
UW		 856 if (info->func == 0)
857 {
858 /* Fall back to using the current PC as frame ID. */
8d998b8f 859 info->func = get_frame_pc (this_frame);
771b4502
UW		 860 data.size = -1;
861 }
862 else
8d998b8f 863 spu_analyze_prologue (info->func, get_frame_pc (this_frame), &data);
771b4502
UW		 864
865
866 /* If successful, use prologue analysis data. */
867 if (data.size != -1 && data.cfa_reg != -1)
868 {
869 CORE_ADDR cfa;
870 int i;
771b4502
UW		 871
872 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 873 get_frame_register (this_frame, data.cfa_reg, buf);
771b4502
UW		 874 cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
875
876 /* Call-saved register slots. */
877 for (i = 0; i < SPU_NUM_GPRS; i++)
878 if (i == SPU_LR_REGNUM
879 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
880 if (data.reg_offset[i] != -1)
881 info->saved_regs[i].addr = cfa - data.reg_offset[i];
882
771b4502
UW		 883 /* Frame bases. */
884 info->frame_base = cfa;
885 info->local_base = cfa - data.size;
886 }
887
888 /* Otherwise, fall back to reading the backchain link. */
889 else
890 {
891 CORE_ADDR reg, backchain;
892
893 /* Get the backchain. */
8d998b8f 894 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
771b4502
UW		 895 backchain = read_memory_unsigned_integer (reg, 4);
896
897 /* A zero backchain terminates the frame chain. Also, sanity
898 check against the local store size limit. */
899 if (backchain != 0 && backchain < SPU_LS_SIZE)
900 {
901 /* Assume the link register is saved into its slot. */
902 if (backchain + 16 < SPU_LS_SIZE)
903 info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
904
771b4502
UW		 905 /* Frame bases. */
906 info->frame_base = backchain;
907 info->local_base = reg;
908 }
909 }
dcf52cd8
UW		 910
911 /* The previous SP is equal to the CFA. */
912 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base);
913
0a44cb36
UW		 914 /* Read full contents of the unwound link register in order to
915 be able to determine the return address. */
dcf52cd8
UW		 916 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
917 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
918 else
8d998b8f 919 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 920
0a44cb36
UW		 921 /* Normally, the return address is contained in the slot 0 of the
922 link register, and slots 1-3 are zero. For an overlay return,
923 slot 0 contains the address of the overlay manager return stub,
924 slot 1 contains the partition number of the overlay section to
925 be returned to, and slot 2 contains the return address within
926 that section. Return the latter address in that case. */
dcf52cd8
UW		 927 if (extract_unsigned_integer (buf + 8, 4) != 0)
928 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
929 extract_unsigned_integer (buf + 8, 4));
930 else
931 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
932 extract_unsigned_integer (buf, 4));
771b4502
UW		 933
934 return info;
935}
936
937static void
8d998b8f 938spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 939 void **this_prologue_cache, struct frame_id *this_id)
940{
941 struct spu_unwind_cache *info =
8d998b8f 942 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 943
944 if (info->frame_base == 0)
945 return;
946
947 *this_id = frame_id_build (info->frame_base, info->func);
948}
949
8d998b8f
UW		 950static struct value *
951spu_frame_prev_register (struct frame_info *this_frame,
952 void **this_prologue_cache, int regnum)
771b4502
UW		 953{
954 struct spu_unwind_cache *info
8d998b8f 955 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 956
957 /* Special-case the stack pointer. */
958 if (regnum == SPU_RAW_SP_REGNUM)
959 regnum = SPU_SP_REGNUM;
960
8d998b8f 961 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 962}
963
964static const struct frame_unwind spu_frame_unwind = {
965 NORMAL_FRAME,
966 spu_frame_this_id,
8d998b8f
UW		 967 spu_frame_prev_register,
968 NULL,
969 default_frame_sniffer
771b4502
UW		 970};
971
771b4502 972static CORE_ADDR
8d998b8f 973spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 974{
975 struct spu_unwind_cache *info
8d998b8f 976 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 977 return info->local_base;
978}
979
980static const struct frame_base spu_frame_base = {
981 &spu_frame_unwind,
982 spu_frame_base_address,
983 spu_frame_base_address,
984 spu_frame_base_address
985};
986
987static CORE_ADDR
988spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
989{
118dfbaf
UW		 990 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
991 /* Mask off interrupt enable bit. */
992 return pc & -4;
771b4502
UW		 993}
994
995static CORE_ADDR
996spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
997{
998 return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
999}
1000
118dfbaf 1001static CORE_ADDR
61a1198a 1002spu_read_pc (struct regcache *regcache)
118dfbaf 1003{
61a1198a
UW		 1004 ULONGEST pc;
1005 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf
UW		 1006 /* Mask off interrupt enable bit. */
1007 return pc & -4;
1008}
1009
1010static void
61a1198a 1011spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1012{
1013 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1014 ULONGEST old_pc;
1015 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1016 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1017 (pc & -4) | (old_pc & 3));
118dfbaf
UW		 1018}
1019
771b4502
UW		 1020
1021/* Function calling convention. */
1022
7b3dc0b7
UW		 1023static CORE_ADDR
1024spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1025{
1026 return sp & ~15;
1027}
1028
771b4502
UW		 1029static int
1030spu_scalar_value_p (struct type *type)
1031{
1032 switch (TYPE_CODE (type))
1033 {
1034 case TYPE_CODE_INT:
1035 case TYPE_CODE_ENUM:
1036 case TYPE_CODE_RANGE:
1037 case TYPE_CODE_CHAR:
1038 case TYPE_CODE_BOOL:
1039 case TYPE_CODE_PTR:
1040 case TYPE_CODE_REF:
1041 return TYPE_LENGTH (type) <= 16;
1042
1043 default:
1044 return 0;
1045 }
1046}
1047
1048static void
1049spu_value_to_regcache (struct regcache *regcache, int regnum,
1050 struct type *type, const gdb_byte *in)
1051{
1052 int len = TYPE_LENGTH (type);
1053
1054 if (spu_scalar_value_p (type))
1055 {
1056 int preferred_slot = len < 4 ? 4 - len : 0;
1057 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1058 }
1059 else
1060 {
1061 while (len >= 16)
1062 {
1063 regcache_cooked_write (regcache, regnum++, in);
1064 in += 16;
1065 len -= 16;
1066 }
1067
1068 if (len > 0)
1069 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1070 }
1071}
1072
1073static void
1074spu_regcache_to_value (struct regcache *regcache, int regnum,
1075 struct type *type, gdb_byte *out)
1076{
1077 int len = TYPE_LENGTH (type);
1078
1079 if (spu_scalar_value_p (type))
1080 {
1081 int preferred_slot = len < 4 ? 4 - len : 0;
1082 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1083 }
1084 else
1085 {
1086 while (len >= 16)
1087 {
1088 regcache_cooked_read (regcache, regnum++, out);
1089 out += 16;
1090 len -= 16;
1091 }
1092
1093 if (len > 0)
1094 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1095 }
1096}
1097
1098static CORE_ADDR
1099spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1100 struct regcache *regcache, CORE_ADDR bp_addr,
1101 int nargs, struct value **args, CORE_ADDR sp,
1102 int struct_return, CORE_ADDR struct_addr)
1103{
1104 int i;
1105 int regnum = SPU_ARG1_REGNUM;
1106 int stack_arg = -1;
1107 gdb_byte buf[16];
1108
1109 /* Set the return address. */
1110 memset (buf, 0, sizeof buf);
1111 store_unsigned_integer (buf, 4, bp_addr);
1112 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1113
1114 /* If STRUCT_RETURN is true, then the struct return address (in
1115 STRUCT_ADDR) will consume the first argument-passing register.
1116 Both adjust the register count and store that value. */
1117 if (struct_return)
1118 {
1119 memset (buf, 0, sizeof buf);
1120 store_unsigned_integer (buf, 4, struct_addr);
1121 regcache_cooked_write (regcache, regnum++, buf);
1122 }
1123
1124 /* Fill in argument registers. */
1125 for (i = 0; i < nargs; i++)
1126 {
1127 struct value *arg = args[i];
1128 struct type *type = check_typedef (value_type (arg));
1129 const gdb_byte *contents = value_contents (arg);
1130 int len = TYPE_LENGTH (type);
1131 int n_regs = align_up (len, 16) / 16;
1132
1133 /* If the argument doesn't wholly fit into registers, it and
1134 all subsequent arguments go to the stack. */
1135 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1136 {
1137 stack_arg = i;
1138 break;
1139 }
1140
1141 spu_value_to_regcache (regcache, regnum, type, contents);
1142 regnum += n_regs;
1143 }
1144
1145 /* Overflow arguments go to the stack. */
1146 if (stack_arg != -1)
1147 {
1148 CORE_ADDR ap;
1149
1150 /* Allocate all required stack size. */
1151 for (i = stack_arg; i < nargs; i++)
1152 {
1153 struct type *type = check_typedef (value_type (args[i]));
1154 sp -= align_up (TYPE_LENGTH (type), 16);
1155 }
1156
1157 /* Fill in stack arguments. */
1158 ap = sp;
1159 for (i = stack_arg; i < nargs; i++)
1160 {
1161 struct value *arg = args[i];
1162 struct type *type = check_typedef (value_type (arg));
1163 int len = TYPE_LENGTH (type);
1164 int preferred_slot;
1165
1166 if (spu_scalar_value_p (type))
1167 preferred_slot = len < 4 ? 4 - len : 0;
1168 else
1169 preferred_slot = 0;
1170
1171 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1172 ap += align_up (TYPE_LENGTH (type), 16);
1173 }
1174 }
1175
1176 /* Allocate stack frame header. */
1177 sp -= 32;
1178
ee82e879
UW		 1179 /* Store stack back chain. */
1180 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1181 target_write_memory (sp, buf, 16);
1182
771b4502
UW		 1183 /* Finally, update the SP register. */
1184 regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp);
1185
1186 return sp;
1187}
1188
1189static struct frame_id
8d998b8f 1190spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1191{
8d998b8f
UW		 1192 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1193 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1194 return frame_id_build (sp, pc & -4);
771b4502
UW		 1195}
1196
1197/* Function return value access. */
1198
1199static enum return_value_convention
c055b101
CV		 1200spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1201 struct type *type, struct regcache *regcache,
1202 gdb_byte *out, const gdb_byte *in)
771b4502
UW		 1203{
1204 enum return_value_convention rvc;
1205
1206 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1207 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1208 else
1209 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1210
1211 if (in)
1212 {
1213 switch (rvc)
1214 {
1215 case RETURN_VALUE_REGISTER_CONVENTION:
1216 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1217 break;
1218
1219 case RETURN_VALUE_STRUCT_CONVENTION:
1220 error ("Cannot set function return value.");
1221 break;
1222 }
1223 }
1224 else if (out)
1225 {
1226 switch (rvc)
1227 {
1228 case RETURN_VALUE_REGISTER_CONVENTION:
1229 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1230 break;
1231
1232 case RETURN_VALUE_STRUCT_CONVENTION:
1233 error ("Function return value unknown.");
1234 break;
1235 }
1236 }
1237
1238 return rvc;
1239}
1240
1241
1242/* Breakpoints. */
1243
1244static const gdb_byte *
67d57894 1245spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1246{
1247 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1248
1249 *lenptr = sizeof breakpoint;
1250 return breakpoint;
1251}
1252
1253
1254/* Software single-stepping support. */
1255
e6590a1b 1256int
0b1b3e42 1257spu_software_single_step (struct frame_info *frame)
771b4502 1258{
e0cd558a
UW		 1259 CORE_ADDR pc, next_pc;
1260 unsigned int insn;
1261 int offset, reg;
1262 gdb_byte buf[4];
771b4502 1263
0b1b3e42 1264 pc = get_frame_pc (frame);
771b4502 1265
e0cd558a
UW		 1266 if (target_read_memory (pc, buf, 4))
1267 return 1;
1268 insn = extract_unsigned_integer (buf, 4);
771b4502 1269
e0cd558a
UW		 1270 /* Next sequential instruction is at PC + 4, except if the current
1271 instruction is a PPE-assisted call, in which case it is at PC + 8.
1272 Wrap around LS limit to be on the safe side. */
1273 if ((insn & 0xffffff00) == 0x00002100)
1274 next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
1275 else
1276 next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
771b4502 1277
e0cd558a 1278 insert_single_step_breakpoint (next_pc);
771b4502 1279
e0cd558a
UW		 1280 if (is_branch (insn, &offset, &reg))
1281 {
1282 CORE_ADDR target = offset;
771b4502 1283
e0cd558a
UW		 1284 if (reg == SPU_PC_REGNUM)
1285 target += pc;
1286 else if (reg != -1)
1287 {
0b1b3e42 1288 get_frame_register_bytes (frame, reg, 0, 4, buf);
e0cd558a 1289 target += extract_unsigned_integer (buf, 4) & -4;
771b4502 1290 }
e0cd558a
UW		 1291
1292 target = target & (SPU_LS_SIZE - 1);
1293 if (target != next_pc)
1294 insert_single_step_breakpoint (target);
771b4502 1295 }
e6590a1b
UW		 1296
1297 return 1;
771b4502
UW		 1298}
1299
dcf52cd8
UW		 1300/* Target overlays for the SPU overlay manager.
1301
1302 See the documentation of simple_overlay_update for how the
1303 interface is supposed to work.
1304
1305 Data structures used by the overlay manager:
1306
1307 struct ovly_table
1308 {
1309 u32 vma;
1310 u32 size;
1311 u32 pos;
1312 u32 buf;
1313 } _ovly_table[]; -- one entry per overlay section
1314
1315 struct ovly_buf_table
1316 {
1317 u32 mapped;
1318 } _ovly_buf_table[]; -- one entry per overlay buffer
1319
1320 _ovly_table should never change.
1321
1322 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1323 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1324 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1325
1326 mapped is an index into _ovly_table. Both the mapped and buf indices start
1327 from one to reference the first entry in their respective tables. */
1328
1329/* Using the per-objfile private data mechanism, we store for each
1330 objfile an array of "struct spu_overlay_table" structures, one
1331 for each obj_section of the objfile. This structure holds two
1332 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1333 is *not* an overlay section. If it is non-zero, it represents
1334 a target address. The overlay section is mapped iff the target
1335 integer at this location equals MAPPED_VAL. */
1336
1337static const struct objfile_data *spu_overlay_data;
1338
1339struct spu_overlay_table
1340 {
1341 CORE_ADDR mapped_ptr;
1342 CORE_ADDR mapped_val;
1343 };
1344
1345/* Retrieve the overlay table for OBJFILE. If not already cached, read
1346 the _ovly_table data structure from the target and initialize the
1347 spu_overlay_table data structure from it. */
1348static struct spu_overlay_table *
1349spu_get_overlay_table (struct objfile *objfile)
1350{
1351 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1352 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1353 unsigned ovly_table_size, ovly_buf_table_size;
1354 struct spu_overlay_table *tbl;
1355 struct obj_section *osect;
1356 char *ovly_table;
1357 int i;
1358
1359 tbl = objfile_data (objfile, spu_overlay_data);
1360 if (tbl)
1361 return tbl;
1362
1363 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1364 if (!ovly_table_msym)
1365 return NULL;
1366
1367 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1368 if (!ovly_buf_table_msym)
1369 return NULL;
1370
1371 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1372 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1373
1374 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1375 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1376
1377 ovly_table = xmalloc (ovly_table_size);
1378 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1379
1380 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1381 objfile->sections_end - objfile->sections,
1382 struct spu_overlay_table);
1383
1384 for (i = 0; i < ovly_table_size / 16; i++)
1385 {
1386 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, 4);
1387 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4);
1388 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, 4);
1389 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, 4);
1390
1391 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1392 continue;
1393
1394 ALL_OBJFILE_OSECTIONS (objfile, osect)
1395 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1396 && pos == osect->the_bfd_section->filepos)
1397 {
1398 int ndx = osect - objfile->sections;
1399 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1400 tbl[ndx].mapped_val = i + 1;
1401 break;
1402 }
1403 }
1404
1405 xfree (ovly_table);
1406 set_objfile_data (objfile, spu_overlay_data, tbl);
1407 return tbl;
1408}
1409
1410/* Read _ovly_buf_table entry from the target to dermine whether
1411 OSECT is currently mapped, and update the mapped state. */
1412static void
1413spu_overlay_update_osect (struct obj_section *osect)
1414{
1415 struct spu_overlay_table *ovly_table;
1416 CORE_ADDR val;
1417
1418 ovly_table = spu_get_overlay_table (osect->objfile);
1419 if (!ovly_table)
1420 return;
1421
1422 ovly_table += osect - osect->objfile->sections;
1423 if (ovly_table->mapped_ptr == 0)
1424 return;
1425
1426 val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4);
1427 osect->ovly_mapped = (val == ovly_table->mapped_val);
1428}
1429
1430/* If OSECT is NULL, then update all sections' mapped state.
1431 If OSECT is non-NULL, then update only OSECT's mapped state. */
1432static void
1433spu_overlay_update (struct obj_section *osect)
1434{
1435 /* Just one section. */
1436 if (osect)
1437 spu_overlay_update_osect (osect);
1438
1439 /* All sections. */
1440 else
1441 {
1442 struct objfile *objfile;
1443
1444 ALL_OBJSECTIONS (objfile, osect)
1445 if (section_is_overlay (osect->the_bfd_section))
1446 spu_overlay_update_osect (osect);
1447 }
1448}
1449
1450/* Whenever a new objfile is loaded, read the target's _ovly_table.
1451 If there is one, go through all sections and make sure for non-
1452 overlay sections LMA equals VMA, while for overlay sections LMA
1453 is larger than local store size. */
1454static void
1455spu_overlay_new_objfile (struct objfile *objfile)
1456{
1457 struct spu_overlay_table *ovly_table;
1458 struct obj_section *osect;
1459
1460 /* If we've already touched this file, do nothing. */
1461 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1462 return;
1463
1464 /* Check if this objfile has overlays. */
1465 ovly_table = spu_get_overlay_table (objfile);
1466 if (!ovly_table)
1467 return;
1468
1469 /* Now go and fiddle with all the LMAs. */
1470 ALL_OBJFILE_OSECTIONS (objfile, osect)
1471 {
1472 bfd *obfd = objfile->obfd;
1473 asection *bsect = osect->the_bfd_section;
1474 int ndx = osect - objfile->sections;
1475
1476 if (ovly_table[ndx].mapped_ptr == 0)
1477 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1478 else
1479 bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1480 }
1481}
1482
771b4502 1483
23d964e7
UW		 1484/* "info spu" commands. */
1485
1486static void
1487info_spu_event_command (char *args, int from_tty)
1488{
1489 struct frame_info *frame = get_selected_frame (NULL);
1490 ULONGEST event_status = 0;
1491 ULONGEST event_mask = 0;
1492 struct cleanup *chain;
1493 gdb_byte buf[100];
1494 char annex[32];
1495 LONGEST len;
1496 int rc, id;
1497
1498 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1499
1500 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1501 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1502 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1503 if (len <= 0)
1504 error (_("Could not read event_status."));
9971ac47 1505 buf[len] = '\0';
23d964e7
UW		 1506 event_status = strtoulst (buf, NULL, 16);
1507
1508 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1509 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1510 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1511 if (len <= 0)
1512 error (_("Could not read event_mask."));
9971ac47 1513 buf[len] = '\0';
23d964e7
UW		 1514 event_mask = strtoulst (buf, NULL, 16);
1515
1516 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1517
1518 if (ui_out_is_mi_like_p (uiout))
1519 {
1520 ui_out_field_fmt (uiout, "event_status",
1521 "0x%s", phex_nz (event_status, 4));
1522 ui_out_field_fmt (uiout, "event_mask",
1523 "0x%s", phex_nz (event_mask, 4));
1524 }
1525 else
1526 {
1527 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1528 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1529 }
1530
1531 do_cleanups (chain);
1532}
1533
1534static void
1535info_spu_signal_command (char *args, int from_tty)
1536{
1537 struct frame_info *frame = get_selected_frame (NULL);
1538 ULONGEST signal1 = 0;
1539 ULONGEST signal1_type = 0;
1540 int signal1_pending = 0;
1541 ULONGEST signal2 = 0;
1542 ULONGEST signal2_type = 0;
1543 int signal2_pending = 0;
1544 struct cleanup *chain;
1545 char annex[32];
1546 gdb_byte buf[100];
1547 LONGEST len;
1548 int rc, id;
1549
1550 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1551
1552 xsnprintf (annex, sizeof annex, "%d/signal1", id);
1553 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1554 if (len < 0)
1555 error (_("Could not read signal1."));
1556 else if (len == 4)
1557 {
1558 signal1 = extract_unsigned_integer (buf, 4);
1559 signal1_pending = 1;
1560 }
1561
1562 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
1563 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1564 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1565 if (len <= 0)
1566 error (_("Could not read signal1_type."));
9971ac47 1567 buf[len] = '\0';
23d964e7
UW		 1568 signal1_type = strtoulst (buf, NULL, 16);
1569
1570 xsnprintf (annex, sizeof annex, "%d/signal2", id);
1571 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1572 if (len < 0)
1573 error (_("Could not read signal2."));
1574 else if (len == 4)
1575 {
1576 signal2 = extract_unsigned_integer (buf, 4);
1577 signal2_pending = 1;
1578 }
1579
1580 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
1581 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1582 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1583 if (len <= 0)
1584 error (_("Could not read signal2_type."));
9971ac47 1585 buf[len] = '\0';
23d964e7
UW		 1586 signal2_type = strtoulst (buf, NULL, 16);
1587
1588 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
1589
1590 if (ui_out_is_mi_like_p (uiout))
1591 {
1592 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
1593 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
1594 ui_out_field_int (uiout, "signal1_type", signal1_type);
1595 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
1596 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
1597 ui_out_field_int (uiout, "signal2_type", signal2_type);
1598 }
1599 else
1600 {
1601 if (signal1_pending)
1602 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
1603 else
1604 printf_filtered (_("Signal 1 not pending "));
1605
1606 if (signal1_type)
23d964e7 1607 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 1608 else
1609 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 1610
1611 if (signal2_pending)
1612 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
1613 else
1614 printf_filtered (_("Signal 2 not pending "));
1615
1616 if (signal2_type)
23d964e7 1617 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 1618 else
1619 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 1620 }
1621
1622 do_cleanups (chain);
1623}
1624
1625static void
1626info_spu_mailbox_list (gdb_byte *buf, int nr,
1627 const char *field, const char *msg)
1628{
1629 struct cleanup *chain;
1630 int i;
1631
1632 if (nr <= 0)
1633 return;
1634
1635 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
1636
1637 ui_out_table_header (uiout, 32, ui_left, field, msg);
1638 ui_out_table_body (uiout);
1639
1640 for (i = 0; i < nr; i++)
1641 {
1642 struct cleanup *val_chain;
1643 ULONGEST val;
1644 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
1645 val = extract_unsigned_integer (buf + 4*i, 4);
1646 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
1647 do_cleanups (val_chain);
1648
1649 if (!ui_out_is_mi_like_p (uiout))
1650 printf_filtered ("\n");
1651 }
1652
1653 do_cleanups (chain);
1654}
1655
1656static void
1657info_spu_mailbox_command (char *args, int from_tty)
1658{
1659 struct frame_info *frame = get_selected_frame (NULL);
1660 struct cleanup *chain;
1661 char annex[32];
1662 gdb_byte buf[1024];
1663 LONGEST len;
1664 int i, id;
1665
1666 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1667
1668 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
1669
1670 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
1671 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1672 buf, 0, sizeof buf);
1673 if (len < 0)
1674 error (_("Could not read mbox_info."));
1675
1676 info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox");
1677
1678 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
1679 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1680 buf, 0, sizeof buf);
1681 if (len < 0)
1682 error (_("Could not read ibox_info."));
1683
1684 info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox");
1685
1686 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
1687 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1688 buf, 0, sizeof buf);
1689 if (len < 0)
1690 error (_("Could not read wbox_info."));
1691
1692 info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox");
1693
1694 do_cleanups (chain);
1695}
1696
1697static ULONGEST
1698spu_mfc_get_bitfield (ULONGEST word, int first, int last)
1699{
1700 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
1701 return (word >> (63 - last)) & mask;
1702}
1703
1704static void
1705info_spu_dma_cmdlist (gdb_byte *buf, int nr)
1706{
1707 static char *spu_mfc_opcode[256] =
1708 {
1709 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1710 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1711 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1712 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1713 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
1714 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
1715 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
1716 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1717 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
1718 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
1719 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1720 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1721 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1722 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1723 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1724 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1725 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
1726 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
1727 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1728 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1729 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
1730 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1731 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
1732 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1733 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1734 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
1735 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1736 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1737 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1738 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1739 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1740 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1741 };
1742
1743 struct cleanup *chain;
1744 int i;
1745
1746 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
1747
1748 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
1749 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
1750 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
1751 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
1752 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
1753 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
1754 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
1755 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
1756 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
1757 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
1758
1759 ui_out_table_body (uiout);
1760
1761 for (i = 0; i < nr; i++)
1762 {
1763 struct cleanup *cmd_chain;
1764 ULONGEST mfc_cq_dw0;
1765 ULONGEST mfc_cq_dw1;
1766 ULONGEST mfc_cq_dw2;
1767 ULONGEST mfc_cq_dw3;
1768 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
1769 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
1770 ULONGEST mfc_ea;
1771 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
1772
1773 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1774 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1775
1776 mfc_cq_dw0 = extract_unsigned_integer (buf + 32*i, 8);
1777 mfc_cq_dw1 = extract_unsigned_integer (buf + 32*i + 8, 8);
1778 mfc_cq_dw2 = extract_unsigned_integer (buf + 32*i + 16, 8);
1779 mfc_cq_dw3 = extract_unsigned_integer (buf + 32*i + 24, 8);
1780
1781 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
1782 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
1783 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
1784 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
1785 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
1786 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
1787 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
1788
1789 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
1790 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
1791
1792 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
1793 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
1794 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
1795 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
1796 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
1797 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
1798
1799 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
1800
1801 if (spu_mfc_opcode[mfc_cmd_opcode])
1802 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
1803 else
1804 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
1805
1806 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
1807 ui_out_field_int (uiout, "tid", tclass_id);
1808 ui_out_field_int (uiout, "rid", rclass_id);
1809
1810 if (ea_valid_p)
1811 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
1812 else
1813 ui_out_field_skip (uiout, "ea");
1814
1815 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
1816 if (qw_valid_p)
1817 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
1818 else
1819 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
1820
1821 if (list_valid_p)
1822 {
1823 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
1824 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
1825 }
1826 else
1827 {
1828 ui_out_field_skip (uiout, "lstaddr");
1829 ui_out_field_skip (uiout, "lstsize");
1830 }
1831
1832 if (cmd_error_p)
1833 ui_out_field_string (uiout, "error_p", "*");
1834 else
1835 ui_out_field_skip (uiout, "error_p");
1836
1837 do_cleanups (cmd_chain);
1838
1839 if (!ui_out_is_mi_like_p (uiout))
1840 printf_filtered ("\n");
1841 }
1842
1843 do_cleanups (chain);
1844}
1845
1846static void
1847info_spu_dma_command (char *args, int from_tty)
1848{
1849 struct frame_info *frame = get_selected_frame (NULL);
1850 ULONGEST dma_info_type;
1851 ULONGEST dma_info_mask;
1852 ULONGEST dma_info_status;
1853 ULONGEST dma_info_stall_and_notify;
1854 ULONGEST dma_info_atomic_command_status;
1855 struct cleanup *chain;
1856 char annex[32];
1857 gdb_byte buf[1024];
1858 LONGEST len;
1859 int i, id;
1860
1861 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1862
1863 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
1864 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1865 buf, 0, 40 + 16 * 32);
1866 if (len <= 0)
1867 error (_("Could not read dma_info."));
1868
1869 dma_info_type = extract_unsigned_integer (buf, 8);
1870 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1871 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1872 dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8);
1873 dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8);
1874
1875 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
1876
1877 if (ui_out_is_mi_like_p (uiout))
1878 {
1879 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
1880 phex_nz (dma_info_type, 4));
1881 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
1882 phex_nz (dma_info_mask, 4));
1883 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
1884 phex_nz (dma_info_status, 4));
1885 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
1886 phex_nz (dma_info_stall_and_notify, 4));
1887 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
1888 phex_nz (dma_info_atomic_command_status, 4));
1889 }
1890 else
1891 {
1892 const char *query_msg;
1893
1894 switch (dma_info_type)
1895 {
1896 case 0: query_msg = _("no query pending"); break;
1897 case 1: query_msg = _("'any' query pending"); break;
1898 case 2: query_msg = _("'all' query pending"); break;
1899 default: query_msg = _("undefined query type"); break;
1900 }
1901
1902 printf_filtered (_("Tag-Group Status 0x%s\n"),
1903 phex (dma_info_status, 4));
1904 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1905 phex (dma_info_mask, 4), query_msg);
1906 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1907 phex (dma_info_stall_and_notify, 4));
1908 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1909 phex (dma_info_atomic_command_status, 4));
1910 printf_filtered ("\n");
1911 }
1912
1913 info_spu_dma_cmdlist (buf + 40, 16);
1914 do_cleanups (chain);
1915}
1916
1917static void
1918info_spu_proxydma_command (char *args, int from_tty)
1919{
1920 struct frame_info *frame = get_selected_frame (NULL);
1921 ULONGEST dma_info_type;
1922 ULONGEST dma_info_mask;
1923 ULONGEST dma_info_status;
1924 struct cleanup *chain;
1925 char annex[32];
1926 gdb_byte buf[1024];
1927 LONGEST len;
1928 int i, id;
1929
1930 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1931
1932 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
1933 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1934 buf, 0, 24 + 8 * 32);
1935 if (len <= 0)
1936 error (_("Could not read proxydma_info."));
1937
1938 dma_info_type = extract_unsigned_integer (buf, 8);
1939 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1940 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1941
1942 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
1943
1944 if (ui_out_is_mi_like_p (uiout))
1945 {
1946 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
1947 phex_nz (dma_info_type, 4));
1948 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
1949 phex_nz (dma_info_mask, 4));
1950 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
1951 phex_nz (dma_info_status, 4));
1952 }
1953 else
1954 {
1955 const char *query_msg;
1956
1957 switch (dma_info_type)
1958 {
1959 case 0: query_msg = _("no query pending"); break;
1960 case 1: query_msg = _("'any' query pending"); break;
1961 case 2: query_msg = _("'all' query pending"); break;
1962 default: query_msg = _("undefined query type"); break;
1963 }
1964
1965 printf_filtered (_("Tag-Group Status 0x%s\n"),
1966 phex (dma_info_status, 4));
1967 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1968 phex (dma_info_mask, 4), query_msg);
1969 printf_filtered ("\n");
1970 }
1971
1972 info_spu_dma_cmdlist (buf + 24, 8);
1973 do_cleanups (chain);
1974}
1975
1976static void
1977info_spu_command (char *args, int from_tty)
1978{
1979 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
1980 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
1981}
1982
1983
771b4502
UW		 1984/* Set up gdbarch struct. */
1985
1986static struct gdbarch *
1987spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1988{
1989 struct gdbarch *gdbarch;
794ac428 1990 struct gdbarch_tdep *tdep;
771b4502
UW		 1991
1992 /* Find a candidate among the list of pre-declared architectures. */
1993 arches = gdbarch_list_lookup_by_info (arches, &info);
1994 if (arches != NULL)
1995 return arches->gdbarch;
1996
1997 /* Is is for us? */
1998 if (info.bfd_arch_info->mach != bfd_mach_spu)
1999 return NULL;
2000
2001 /* Yes, create a new architecture. */
794ac428
UW		 2002 tdep = XCALLOC (1, struct gdbarch_tdep);
2003 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2004
2005 /* Disassembler. */
2006 set_gdbarch_print_insn (gdbarch, print_insn_spu);
2007
2008 /* Registers. */
2009 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2010 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2011 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2012 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2013 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2014 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2015 set_gdbarch_register_name (gdbarch, spu_register_name);
2016 set_gdbarch_register_type (gdbarch, spu_register_type);
2017 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2018 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2019 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2020 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2021
2022 /* Data types. */
2023 set_gdbarch_char_signed (gdbarch, 0);
2024 set_gdbarch_ptr_bit (gdbarch, 32);
2025 set_gdbarch_addr_bit (gdbarch, 32);
2026 set_gdbarch_short_bit (gdbarch, 16);
2027 set_gdbarch_int_bit (gdbarch, 32);
2028 set_gdbarch_long_bit (gdbarch, 32);
2029 set_gdbarch_long_long_bit (gdbarch, 64);
2030 set_gdbarch_float_bit (gdbarch, 32);
2031 set_gdbarch_double_bit (gdbarch, 64);
2032 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2033 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2034 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2035 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2036
36acd84e
UW		 2037 /* Address conversion. */
2038 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2039 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2040
771b4502 2041 /* Inferior function calls. */
7b3dc0b7
UW		 2042 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2043 set_gdbarch_frame_align (gdbarch, spu_frame_align);
771b4502 2044 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2045 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2046 set_gdbarch_return_value (gdbarch, spu_return_value);
2047
2048 /* Frame handling. */
2049 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2050 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2051 frame_base_set_default (gdbarch, &spu_frame_base);
2052 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2053 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2054 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2055 set_gdbarch_frame_args_skip (gdbarch, 0);
2056 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2057 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502
UW		 2058
2059 /* Breakpoints. */
2060 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2061 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2062 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2063 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2064
dcf52cd8
UW		 2065 /* Overlays. */
2066 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2067
771b4502
UW		 2068 return gdbarch;
2069}
2070
2071void
2072_initialize_spu_tdep (void)
2073{
2074 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2075
dcf52cd8
UW		 2076 /* Add ourselves to objfile event chain. */
2077 observer_attach_new_objfile (spu_overlay_new_objfile);
2078 spu_overlay_data = register_objfile_data ();
23d964e7
UW		 2079
2080 /* Add root prefix command for all "info spu" commands. */
2081 add_prefix_cmd ("spu", class_info, info_spu_command,
2082 _("Various SPU specific commands."),
2083 &infospucmdlist, "info spu ", 0, &infolist);
2084
2085 /* Add various "info spu" commands. */
2086 add_cmd ("event", class_info, info_spu_event_command,
2087 _("Display SPU event facility status.\n"),
2088 &infospucmdlist);
2089 add_cmd ("signal", class_info, info_spu_signal_command,
2090 _("Display SPU signal notification facility status.\n"),
2091 &infospucmdlist);
2092 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2093 _("Display SPU mailbox facility status.\n"),
2094 &infospucmdlist);
2095 add_cmd ("dma", class_info, info_spu_dma_command,
2096 _("Display MFC DMA status.\n"),
2097 &infospucmdlist);
2098 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2099 _("Display MFC Proxy-DMA status.\n"),
2100 &infospucmdlist);
771b4502 2101}
GDB Binutils - Deliverables
This page took 0.271143 seconds and 4 git commands to generate.