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[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
0b302171 2 Copyright (C) 2006-2012 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
27#include "gdb_string.h"
28#include "gdb_assert.h"
29#include "frame.h"
30#include "frame-unwind.h"
31#include "frame-base.h"
32#include "trad-frame.h"
33#include "symtab.h"
34#include "symfile.h"
35#include "value.h"
36#include "inferior.h"
37#include "dis-asm.h"
38#include "objfiles.h"
39#include "language.h"
40#include "regcache.h"
41#include "reggroups.h"
42#include "floatformat.h"
3285f3fe 43#include "block.h"
dcf52cd8 44#include "observer.h"
ff1a52c6 45#include "infcall.h"
54fcddd0 46#include "dwarf2.h"
8dccd430 47#include "exceptions.h"
771b4502
UW		 48#include "spu-tdep.h"
49
794ac428 50
3285f3fe
UW		 51/* The list of available "set spu " and "show spu " commands. */
52static struct cmd_list_element *setspucmdlist = NULL;
53static struct cmd_list_element *showspucmdlist = NULL;
54
55/* Whether to stop for new SPE contexts. */
56static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 57/* Whether to automatically flush the SW-managed cache. */
58static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 59
60
794ac428
UW		 61/* The tdep structure. */
62struct gdbarch_tdep
63{
85e747d2
UW		 64 /* The spufs ID identifying our address space. */
65 int id;
66
794ac428
UW		 67 /* SPU-specific vector type. */
68 struct type *spu_builtin_type_vec128;
69};
70
71
f2d43c2c 72/* SPU-specific vector type. */
794ac428
UW		 73static struct type *
74spu_builtin_type_vec128 (struct gdbarch *gdbarch)
75{
76 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
77
78 if (!tdep->spu_builtin_type_vec128)
79 {
df4df182 80 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 81 struct type *t;
82
e9bb382b
UW		 83 t = arch_composite_type (gdbarch,
84 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 85 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 86 append_composite_type_field (t, "v2_int64",
df4df182 87 init_vector_type (bt->builtin_int64, 2));
794ac428 88 append_composite_type_field (t, "v4_int32",
df4df182 89 init_vector_type (bt->builtin_int32, 4));
794ac428 90 append_composite_type_field (t, "v8_int16",
df4df182 91 init_vector_type (bt->builtin_int16, 8));
794ac428 92 append_composite_type_field (t, "v16_int8",
df4df182 93 init_vector_type (bt->builtin_int8, 16));
794ac428 94 append_composite_type_field (t, "v2_double",
df4df182 95 init_vector_type (bt->builtin_double, 2));
794ac428 96 append_composite_type_field (t, "v4_float",
df4df182 97 init_vector_type (bt->builtin_float, 4));
794ac428 98
876cecd0 99 TYPE_VECTOR (t) = 1;
794ac428
UW		 100 TYPE_NAME (t) = "spu_builtin_type_vec128";
101
102 tdep->spu_builtin_type_vec128 = t;
103 }
104
105 return tdep->spu_builtin_type_vec128;
106}
107
771b4502 108
23d964e7
UW		 109/* The list of available "info spu " commands. */
110static struct cmd_list_element *infospucmdlist = NULL;
111
771b4502
UW		 112/* Registers. */
113
114static const char *
d93859e2 115spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 116{
117 static char *register_names[] =
118 {
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
122 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
123 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
124 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
125 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
126 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
127 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
128 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
129 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
130 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
131 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
132 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
133 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
134 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 135 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 136 };
137
138 if (reg_nr < 0)
139 return NULL;
140 if (reg_nr >= sizeof register_names / sizeof *register_names)
141 return NULL;
142
143 return register_names[reg_nr];
144}
145
146static struct type *
147spu_register_type (struct gdbarch *gdbarch, int reg_nr)
148{
149 if (reg_nr < SPU_NUM_GPRS)
794ac428 150 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 151
152 switch (reg_nr)
153 {
154 case SPU_ID_REGNUM:
df4df182 155 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 156
157 case SPU_PC_REGNUM:
0dfff4cb 158 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 159
160 case SPU_SP_REGNUM:
0dfff4cb 161 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 162
23d964e7 163 case SPU_FPSCR_REGNUM:
df4df182 164 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 165
166 case SPU_SRR0_REGNUM:
df4df182 167 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 168
169 case SPU_LSLR_REGNUM:
df4df182 170 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 171
172 case SPU_DECR_REGNUM:
df4df182 173 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 174
175 case SPU_DECR_STATUS_REGNUM:
df4df182 176 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 177
771b4502 178 default:
a73c6dcd 179 internal_error (__FILE__, __LINE__, _("invalid regnum"));
771b4502
UW		 180 }
181}
182
183/* Pseudo registers for preferred slots - stack pointer. */
184
05d1431c 185static enum register_status
23d964e7
UW		 186spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
187 gdb_byte *buf)
188{
e17a4113
UW		 189 struct gdbarch *gdbarch = get_regcache_arch (regcache);
190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
05d1431c 191 enum register_status status;
23d964e7
UW		 192 gdb_byte reg[32];
193 char annex[32];
194 ULONGEST id;
195
05d1431c
PA		 196 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
197 if (status != REG_VALID)
198 return status;
23d964e7
UW		 199 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
200 memset (reg, 0, sizeof reg);
201 target_read (&current_target, TARGET_OBJECT_SPU, annex,
202 reg, 0, sizeof reg);
203
e17a4113 204 store_unsigned_integer (buf, 4, byte_order, strtoulst (reg, NULL, 16));
05d1431c 205 return REG_VALID;
23d964e7
UW		 206}
207
05d1431c 208static enum register_status
771b4502
UW		 209spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
210 int regnum, gdb_byte *buf)
211{
212 gdb_byte reg[16];
23d964e7
UW		 213 char annex[32];
214 ULONGEST id;
05d1431c 215 enum register_status status;
771b4502
UW		 216
217 switch (regnum)
218 {
219 case SPU_SP_REGNUM:
05d1431c
PA		 220 status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
221 if (status != REG_VALID)
222 return status;
771b4502 223 memcpy (buf, reg, 4);
05d1431c 224 return status;
771b4502 225
23d964e7 226 case SPU_FPSCR_REGNUM:
05d1431c
PA		 227 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
228 if (status != REG_VALID)
229 return status;
23d964e7
UW		 230 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
231 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
05d1431c 232 return status;
23d964e7
UW		 233
234 case SPU_SRR0_REGNUM:
05d1431c 235 return spu_pseudo_register_read_spu (regcache, "srr0", buf);
23d964e7
UW		 236
237 case SPU_LSLR_REGNUM:
05d1431c 238 return spu_pseudo_register_read_spu (regcache, "lslr", buf);
23d964e7
UW		 239
240 case SPU_DECR_REGNUM:
05d1431c 241 return spu_pseudo_register_read_spu (regcache, "decr", buf);
23d964e7
UW		 242
243 case SPU_DECR_STATUS_REGNUM:
05d1431c 244 return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
23d964e7 245
771b4502
UW		 246 default:
247 internal_error (__FILE__, __LINE__, _("invalid regnum"));
248 }
249}
250
23d964e7
UW		 251static void
252spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
253 const gdb_byte *buf)
254{
e17a4113
UW		 255 struct gdbarch *gdbarch = get_regcache_arch (regcache);
256 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 257 gdb_byte reg[32];
258 char annex[32];
259 ULONGEST id;
260
261 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
262 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
263 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 264 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7
UW		 265 target_write (&current_target, TARGET_OBJECT_SPU, annex,
266 reg, 0, strlen (reg));
267}
268
771b4502
UW		 269static void
270spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
271 int regnum, const gdb_byte *buf)
272{
273 gdb_byte reg[16];
23d964e7
UW		 274 char annex[32];
275 ULONGEST id;
771b4502
UW		 276
277 switch (regnum)
278 {
279 case SPU_SP_REGNUM:
280 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
281 memcpy (reg, buf, 4);
282 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
283 break;
284
23d964e7
UW		 285 case SPU_FPSCR_REGNUM:
286 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
287 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
288 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
289 break;
290
291 case SPU_SRR0_REGNUM:
292 spu_pseudo_register_write_spu (regcache, "srr0", buf);
293 break;
294
295 case SPU_LSLR_REGNUM:
296 spu_pseudo_register_write_spu (regcache, "lslr", buf);
297 break;
298
299 case SPU_DECR_REGNUM:
300 spu_pseudo_register_write_spu (regcache, "decr", buf);
301 break;
302
303 case SPU_DECR_STATUS_REGNUM:
304 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
305 break;
306
771b4502
UW		 307 default:
308 internal_error (__FILE__, __LINE__, _("invalid regnum"));
309 }
310}
311
312/* Value conversion -- access scalar values at the preferred slot. */
313
9acbedc0
UW		 314static struct value *
315spu_value_from_register (struct type *type, int regnum,
316 struct frame_info *frame)
771b4502 317{
9acbedc0
UW		 318 struct value *value = default_value_from_register (type, regnum, frame);
319 int len = TYPE_LENGTH (type);
771b4502 320
9acbedc0
UW		 321 if (regnum < SPU_NUM_GPRS && len < 16)
322 {
323 int preferred_slot = len < 4 ? 4 - len : 0;
324 set_value_offset (value, preferred_slot);
325 }
771b4502 326
9acbedc0 327 return value;
771b4502
UW		 328}
329
330/* Register groups. */
331
332static int
333spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
334 struct reggroup *group)
335{
336 /* Registers displayed via 'info regs'. */
337 if (group == general_reggroup)
338 return 1;
339
340 /* Registers displayed via 'info float'. */
341 if (group == float_reggroup)
342 return 0;
343
344 /* Registers that need to be saved/restored in order to
345 push or pop frames. */
346 if (group == save_reggroup || group == restore_reggroup)
347 return 1;
348
349 return default_register_reggroup_p (gdbarch, regnum, group);
350}
351
ff1a52c6
UW		 352
353/* Address handling. */
36acd84e 354
85e747d2
UW		 355static int
356spu_gdbarch_id (struct gdbarch *gdbarch)
357{
358 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
359 int id = tdep->id;
360
361 /* The objfile architecture of a standalone SPU executable does not
b021a221 362 provide an SPU ID. Retrieve it from the objfile's relocated
85e747d2
UW		 363 address range in this special case. */
364 if (id == -1
365 && symfile_objfile && symfile_objfile->obfd
366 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
367 && symfile_objfile->sections != symfile_objfile->sections_end)
368 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
369
370 return id;
371}
372
ff1a52c6
UW		 373static int
374spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
375{
376 if (dwarf2_addr_class == 1)
377 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
378 else
379 return 0;
380}
381
382static const char *
383spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
384{
385 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
386 return "__ea";
387 else
388 return NULL;
389}
390
391static int
392spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
393 const char *name, int *type_flags_ptr)
394{
395 if (strcmp (name, "__ea") == 0)
396 {
397 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
398 return 1;
399 }
400 else
401 return 0;
402}
403
85e747d2
UW		 404static void
405spu_address_to_pointer (struct gdbarch *gdbarch,
406 struct type *type, gdb_byte *buf, CORE_ADDR addr)
407{
408 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
409 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
410 SPUADDR_ADDR (addr));
411}
412
36acd84e 413static CORE_ADDR
9898f801
UW		 414spu_pointer_to_address (struct gdbarch *gdbarch,
415 struct type *type, const gdb_byte *buf)
36acd84e 416{
85e747d2 417 int id = spu_gdbarch_id (gdbarch);
e17a4113
UW		 418 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
419 ULONGEST addr
420 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 421
ff1a52c6
UW		 422 /* Do not convert __ea pointers. */
423 if (TYPE_ADDRESS_CLASS_1 (type))
424 return addr;
425
d2ed6730 426 return addr? SPUADDR (id, addr) : 0;
36acd84e
UW		 427}
428
429static CORE_ADDR
430spu_integer_to_address (struct gdbarch *gdbarch,
431 struct type *type, const gdb_byte *buf)
432{
85e747d2 433 int id = spu_gdbarch_id (gdbarch);
36acd84e 434 ULONGEST addr = unpack_long (type, buf);
36acd84e 435
d2ed6730 436 return SPUADDR (id, addr);
36acd84e
UW		 437}
438
771b4502
UW		 439
440/* Decoding SPU instructions. */
441
442enum
443 {
444 op_lqd = 0x34,
445 op_lqx = 0x3c4,
446 op_lqa = 0x61,
447 op_lqr = 0x67,
448 op_stqd = 0x24,
449 op_stqx = 0x144,
450 op_stqa = 0x41,
451 op_stqr = 0x47,
452
453 op_il = 0x081,
454 op_ila = 0x21,
455 op_a = 0x0c0,
456 op_ai = 0x1c,
457
a536c6d7 458 op_selb = 0x8,
771b4502
UW		 459
460 op_br = 0x64,
461 op_bra = 0x60,
462 op_brsl = 0x66,
463 op_brasl = 0x62,
464 op_brnz = 0x42,
465 op_brz = 0x40,
466 op_brhnz = 0x46,
467 op_brhz = 0x44,
468 op_bi = 0x1a8,
469 op_bisl = 0x1a9,
470 op_biz = 0x128,
471 op_binz = 0x129,
472 op_bihz = 0x12a,
473 op_bihnz = 0x12b,
474 };
475
476static int
477is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
478{
479 if ((insn >> 21) == op)
480 {
481 *rt = insn & 127;
482 *ra = (insn >> 7) & 127;
483 *rb = (insn >> 14) & 127;
484 return 1;
485 }
486
487 return 0;
488}
489
490static int
491is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
492{
493 if ((insn >> 28) == op)
494 {
495 *rt = (insn >> 21) & 127;
496 *ra = (insn >> 7) & 127;
497 *rb = (insn >> 14) & 127;
498 *rc = insn & 127;
499 return 1;
500 }
501
502 return 0;
503}
504
505static int
506is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
507{
508 if ((insn >> 21) == op)
509 {
510 *rt = insn & 127;
511 *ra = (insn >> 7) & 127;
512 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
513 return 1;
514 }
515
516 return 0;
517}
518
519static int
520is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
521{
522 if ((insn >> 24) == op)
523 {
524 *rt = insn & 127;
525 *ra = (insn >> 7) & 127;
526 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
527 return 1;
528 }
529
530 return 0;
531}
532
533static int
534is_ri16 (unsigned int insn, int op, int *rt, int *i16)
535{
536 if ((insn >> 23) == op)
537 {
538 *rt = insn & 127;
539 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
540 return 1;
541 }
542
543 return 0;
544}
545
546static int
547is_ri18 (unsigned int insn, int op, int *rt, int *i18)
548{
549 if ((insn >> 25) == op)
550 {
551 *rt = insn & 127;
552 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
553 return 1;
554 }
555
556 return 0;
557}
558
559static int
560is_branch (unsigned int insn, int *offset, int *reg)
561{
562 int rt, i7, i16;
563
564 if (is_ri16 (insn, op_br, &rt, &i16)
565 || is_ri16 (insn, op_brsl, &rt, &i16)
566 || is_ri16 (insn, op_brnz, &rt, &i16)
567 || is_ri16 (insn, op_brz, &rt, &i16)
568 || is_ri16 (insn, op_brhnz, &rt, &i16)
569 || is_ri16 (insn, op_brhz, &rt, &i16))
570 {
571 *reg = SPU_PC_REGNUM;
572 *offset = i16 << 2;
573 return 1;
574 }
575
576 if (is_ri16 (insn, op_bra, &rt, &i16)
577 || is_ri16 (insn, op_brasl, &rt, &i16))
578 {
579 *reg = -1;
580 *offset = i16 << 2;
581 return 1;
582 }
583
584 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
585 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
586 || is_ri7 (insn, op_biz, &rt, reg, &i7)
587 || is_ri7 (insn, op_binz, &rt, reg, &i7)
588 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
589 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
590 {
591 *offset = 0;
592 return 1;
593 }
594
595 return 0;
596}
597
598
599/* Prolog parsing. */
600
601struct spu_prologue_data
602 {
603 /* Stack frame size. -1 if analysis was unsuccessful. */
604 int size;
605
606 /* How to find the CFA. The CFA is equal to SP at function entry. */
607 int cfa_reg;
608 int cfa_offset;
609
610 /* Offset relative to CFA where a register is saved. -1 if invalid. */
611 int reg_offset[SPU_NUM_GPRS];
612 };
613
614static CORE_ADDR
e17a4113
UW		 615spu_analyze_prologue (struct gdbarch *gdbarch,
616 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 617 struct spu_prologue_data *data)
618{
e17a4113 619 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 620 int found_sp = 0;
621 int found_fp = 0;
622 int found_lr = 0;
ce50d78b 623 int found_bc = 0;
771b4502
UW		 624 int reg_immed[SPU_NUM_GPRS];
625 gdb_byte buf[16];
626 CORE_ADDR prolog_pc = start_pc;
627 CORE_ADDR pc;
628 int i;
629
630
631 /* Initialize DATA to default values. */
632 data->size = -1;
633
634 data->cfa_reg = SPU_RAW_SP_REGNUM;
635 data->cfa_offset = 0;
636
637 for (i = 0; i < SPU_NUM_GPRS; i++)
638 data->reg_offset[i] = -1;
639
640 /* Set up REG_IMMED array. This is non-zero for a register if we know its
641 preferred slot currently holds this immediate value. */
642 for (i = 0; i < SPU_NUM_GPRS; i++)
643 reg_immed[i] = 0;
644
645 /* Scan instructions until the first branch.
646
647 The following instructions are important prolog components:
648
649 - The first instruction to set up the stack pointer.
650 - The first instruction to set up the frame pointer.
651 - The first instruction to save the link register.
ce50d78b 652 - The first instruction to save the backchain.
771b4502 653
ce50d78b 654 We return the instruction after the latest of these four,
771b4502
UW		 655 or the incoming PC if none is found. The first instruction
656 to set up the stack pointer also defines the frame size.
657
658 Note that instructions saving incoming arguments to their stack
659 slots are not counted as important, because they are hard to
660 identify with certainty. This should not matter much, because
661 arguments are relevant only in code compiled with debug data,
662 and in such code the GDB core will advance until the first source
663 line anyway, using SAL data.
664
665 For purposes of stack unwinding, we analyze the following types
666 of instructions in addition:
667
668 - Any instruction adding to the current frame pointer.
669 - Any instruction loading an immediate constant into a register.
670 - Any instruction storing a register onto the stack.
671
672 These are used to compute the CFA and REG_OFFSET output. */
673
674 for (pc = start_pc; pc < end_pc; pc += 4)
675 {
676 unsigned int insn;
677 int rt, ra, rb, rc, immed;
678
679 if (target_read_memory (pc, buf, 4))
680 break;
e17a4113 681 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 682
683 /* AI is the typical instruction to set up a stack frame.
684 It is also used to initialize the frame pointer. */
685 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
686 {
687 if (rt == data->cfa_reg && ra == data->cfa_reg)
688 data->cfa_offset -= immed;
689
690 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
691 && !found_sp)
692 {
693 found_sp = 1;
694 prolog_pc = pc + 4;
695
696 data->size = -immed;
697 }
698 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
699 && !found_fp)
700 {
701 found_fp = 1;
702 prolog_pc = pc + 4;
703
704 data->cfa_reg = SPU_FP_REGNUM;
705 data->cfa_offset -= immed;
706 }
707 }
708
709 /* A is used to set up stack frames of size >= 512 bytes.
710 If we have tracked the contents of the addend register,
711 we can handle this as well. */
712 else if (is_rr (insn, op_a, &rt, &ra, &rb))
713 {
714 if (rt == data->cfa_reg && ra == data->cfa_reg)
715 {
716 if (reg_immed[rb] != 0)
717 data->cfa_offset -= reg_immed[rb];
718 else
719 data->cfa_reg = -1; /* We don't know the CFA any more. */
720 }
721
722 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
723 && !found_sp)
724 {
725 found_sp = 1;
726 prolog_pc = pc + 4;
727
728 if (reg_immed[rb] != 0)
729 data->size = -reg_immed[rb];
730 }
731 }
732
733 /* We need to track IL and ILA used to load immediate constants
734 in case they are later used as input to an A instruction. */
735 else if (is_ri16 (insn, op_il, &rt, &immed))
736 {
737 reg_immed[rt] = immed;
12102450
UW		 738
739 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
740 found_sp = 1;
771b4502
UW		 741 }
742
743 else if (is_ri18 (insn, op_ila, &rt, &immed))
744 {
745 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 746
747 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
748 found_sp = 1;
771b4502
UW		 749 }
750
751 /* STQD is used to save registers to the stack. */
752 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
753 {
754 if (ra == data->cfa_reg)
755 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
756
757 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
758 && !found_lr)
759 {
760 found_lr = 1;
761 prolog_pc = pc + 4;
762 }
ce50d78b
UW		 763
764 if (ra == SPU_RAW_SP_REGNUM
765 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
766 && !found_bc)
767 {
768 found_bc = 1;
769 prolog_pc = pc + 4;
770 }
771b4502
UW		 771 }
772
773 /* _start uses SELB to set up the stack pointer. */
774 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
775 {
776 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
777 found_sp = 1;
778 }
779
780 /* We terminate if we find a branch. */
781 else if (is_branch (insn, &immed, &ra))
782 break;
783 }
784
785
786 /* If we successfully parsed until here, and didn't find any instruction
787 modifying SP, we assume we have a frameless function. */
788 if (!found_sp)
789 data->size = 0;
790
791 /* Return cooked instead of raw SP. */
792 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
793 data->cfa_reg = SPU_SP_REGNUM;
794
795 return prolog_pc;
796}
797
798/* Return the first instruction after the prologue starting at PC. */
799static CORE_ADDR
6093d2eb 800spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 801{
802 struct spu_prologue_data data;
e17a4113 803 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 804}
805
806/* Return the frame pointer in use at address PC. */
807static void
a54fba4c
MD		 808spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
809 int *reg, LONGEST *offset)
771b4502
UW		 810{
811 struct spu_prologue_data data;
e17a4113 812 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 813
814 if (data.size != -1 && data.cfa_reg != -1)
815 {
816 /* The 'frame pointer' address is CFA minus frame size. */
817 *reg = data.cfa_reg;
818 *offset = data.cfa_offset - data.size;
819 }
820 else
821 {
c378eb4e 822 /* ??? We don't really know ... */
771b4502
UW		 823 *reg = SPU_SP_REGNUM;
824 *offset = 0;
825 }
826}
827
fe5febed
UW		 828/* Return true if we are in the function's epilogue, i.e. after the
829 instruction that destroyed the function's stack frame.
830
831 1) scan forward from the point of execution:
832 a) If you find an instruction that modifies the stack pointer
833 or transfers control (except a return), execution is not in
834 an epilogue, return.
835 b) Stop scanning if you find a return instruction or reach the
836 end of the function or reach the hard limit for the size of
837 an epilogue.
838 2) scan backward from the point of execution:
839 a) If you find an instruction that modifies the stack pointer,
840 execution *is* in an epilogue, return.
841 b) Stop scanning if you reach an instruction that transfers
842 control or the beginning of the function or reach the hard
843 limit for the size of an epilogue. */
844
845static int
846spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
847{
e17a4113 848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 849 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
850 bfd_byte buf[4];
851 unsigned int insn;
22e048c9 852 int rt, ra, rb, immed;
fe5febed
UW		 853
854 /* Find the search limits based on function boundaries and hard limit.
855 We assume the epilogue can be up to 64 instructions long. */
856
857 const int spu_max_epilogue_size = 64 * 4;
858
859 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
860 return 0;
861
862 if (pc - func_start < spu_max_epilogue_size)
863 epilogue_start = func_start;
864 else
865 epilogue_start = pc - spu_max_epilogue_size;
866
867 if (func_end - pc < spu_max_epilogue_size)
868 epilogue_end = func_end;
869 else
870 epilogue_end = pc + spu_max_epilogue_size;
871
872 /* Scan forward until next 'bi $0'. */
873
874 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
875 {
876 if (target_read_memory (scan_pc, buf, 4))
877 return 0;
e17a4113 878 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 879
880 if (is_branch (insn, &immed, &ra))
881 {
882 if (immed == 0 && ra == SPU_LR_REGNUM)
883 break;
884
885 return 0;
886 }
887
888 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
889 || is_rr (insn, op_a, &rt, &ra, &rb)
890 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
891 {
892 if (rt == SPU_RAW_SP_REGNUM)
893 return 0;
894 }
895 }
896
897 if (scan_pc >= epilogue_end)
898 return 0;
899
900 /* Scan backward until adjustment to stack pointer (R1). */
901
902 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
903 {
904 if (target_read_memory (scan_pc, buf, 4))
905 return 0;
e17a4113 906 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 907
908 if (is_branch (insn, &immed, &ra))
909 return 0;
910
911 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
912 || is_rr (insn, op_a, &rt, &ra, &rb)
913 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
914 {
915 if (rt == SPU_RAW_SP_REGNUM)
916 return 1;
917 }
918 }
919
920 return 0;
921}
922
923
771b4502
UW		 924/* Normal stack frames. */
925
926struct spu_unwind_cache
927{
928 CORE_ADDR func;
929 CORE_ADDR frame_base;
930 CORE_ADDR local_base;
931
932 struct trad_frame_saved_reg *saved_regs;
933};
934
935static struct spu_unwind_cache *
8d998b8f 936spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 937 void **this_prologue_cache)
938{
e17a4113 939 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 940 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 941 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 942 struct spu_unwind_cache *info;
943 struct spu_prologue_data data;
85e747d2 944 CORE_ADDR id = tdep->id;
dcf52cd8 945 gdb_byte buf[16];
771b4502
UW		 946
947 if (*this_prologue_cache)
948 return *this_prologue_cache;
949
950 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
951 *this_prologue_cache = info;
8d998b8f 952 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 953 info->frame_base = 0;
954 info->local_base = 0;
955
956 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 957 info->func = get_frame_func (this_frame);
771b4502
UW		 958 if (info->func == 0)
959 {
960 /* Fall back to using the current PC as frame ID. */
8d998b8f 961 info->func = get_frame_pc (this_frame);
771b4502
UW		 962 data.size = -1;
963 }
964 else
e17a4113
UW		 965 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
966 &data);
771b4502
UW		 967
968 /* If successful, use prologue analysis data. */
969 if (data.size != -1 && data.cfa_reg != -1)
970 {
971 CORE_ADDR cfa;
972 int i;
771b4502
UW		 973
974 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 975 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 976 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 977 cfa = SPUADDR (id, cfa);
771b4502
UW		 978
979 /* Call-saved register slots. */
980 for (i = 0; i < SPU_NUM_GPRS; i++)
981 if (i == SPU_LR_REGNUM
982 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
983 if (data.reg_offset[i] != -1)
984 info->saved_regs[i].addr = cfa - data.reg_offset[i];
985
771b4502
UW		 986 /* Frame bases. */
987 info->frame_base = cfa;
988 info->local_base = cfa - data.size;
989 }
990
991 /* Otherwise, fall back to reading the backchain link. */
992 else
993 {
cdc9523a
UW		 994 CORE_ADDR reg;
995 LONGEST backchain;
13def385 996 ULONGEST lslr;
cdc9523a 997 int status;
771b4502 998
13def385
UW		 999 /* Get local store limit. */
1000 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1001 if (!lslr)
1002 lslr = (ULONGEST) -1;
1003
771b4502 1004 /* Get the backchain. */
8d998b8f 1005 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 1006 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1007 &backchain);
771b4502
UW		 1008
1009 /* A zero backchain terminates the frame chain. Also, sanity
1010 check against the local store size limit. */
13def385 1011 if (status && backchain > 0 && backchain <= lslr)
771b4502
UW		 1012 {
1013 /* Assume the link register is saved into its slot. */
13def385 1014 if (backchain + 16 <= lslr)
c378eb4e
MS		 1015 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1016 backchain + 16);
771b4502 1017
771b4502 1018 /* Frame bases. */
85e747d2
UW		 1019 info->frame_base = SPUADDR (id, backchain);
1020 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1021 }
1022 }
dcf52cd8 1023
c4891da7
UW		 1024 /* If we didn't find a frame, we cannot determine SP / return address. */
1025 if (info->frame_base == 0)
1026 return info;
1027
dcf52cd8 1028 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1029 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1030 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1031
0a44cb36
UW		 1032 /* Read full contents of the unwound link register in order to
1033 be able to determine the return address. */
dcf52cd8
UW		 1034 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1035 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1036 else
8d998b8f 1037 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1038
0a44cb36
UW		 1039 /* Normally, the return address is contained in the slot 0 of the
1040 link register, and slots 1-3 are zero. For an overlay return,
1041 slot 0 contains the address of the overlay manager return stub,
1042 slot 1 contains the partition number of the overlay section to
1043 be returned to, and slot 2 contains the return address within
1044 that section. Return the latter address in that case. */
e17a4113 1045 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1046 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1047 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1048 else
1049 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1050 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1051
1052 return info;
1053}
1054
1055static void
8d998b8f 1056spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1057 void **this_prologue_cache, struct frame_id *this_id)
1058{
1059 struct spu_unwind_cache *info =
8d998b8f 1060 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1061
1062 if (info->frame_base == 0)
1063 return;
1064
1065 *this_id = frame_id_build (info->frame_base, info->func);
1066}
1067
8d998b8f
UW		 1068static struct value *
1069spu_frame_prev_register (struct frame_info *this_frame,
1070 void **this_prologue_cache, int regnum)
771b4502
UW		 1071{
1072 struct spu_unwind_cache *info
8d998b8f 1073 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1074
1075 /* Special-case the stack pointer. */
1076 if (regnum == SPU_RAW_SP_REGNUM)
1077 regnum = SPU_SP_REGNUM;
1078
8d998b8f 1079 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1080}
1081
1082static const struct frame_unwind spu_frame_unwind = {
1083 NORMAL_FRAME,
8fbca658 1084 default_frame_unwind_stop_reason,
771b4502 1085 spu_frame_this_id,
8d998b8f
UW		 1086 spu_frame_prev_register,
1087 NULL,
1088 default_frame_sniffer
771b4502
UW		 1089};
1090
771b4502 1091static CORE_ADDR
8d998b8f 1092spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1093{
1094 struct spu_unwind_cache *info
8d998b8f 1095 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1096 return info->local_base;
1097}
1098
1099static const struct frame_base spu_frame_base = {
1100 &spu_frame_unwind,
1101 spu_frame_base_address,
1102 spu_frame_base_address,
1103 spu_frame_base_address
1104};
1105
1106static CORE_ADDR
1107spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1108{
85e747d2 1109 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1110 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1111 /* Mask off interrupt enable bit. */
85e747d2 1112 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1113}
1114
1115static CORE_ADDR
1116spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1117{
85e747d2
UW		 1118 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1119 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1120 return SPUADDR (tdep->id, sp);
771b4502
UW		 1121}
1122
118dfbaf 1123static CORE_ADDR
61a1198a 1124spu_read_pc (struct regcache *regcache)
118dfbaf 1125{
85e747d2 1126 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1127 ULONGEST pc;
1128 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1129 /* Mask off interrupt enable bit. */
85e747d2 1130 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1131}
1132
1133static void
61a1198a 1134spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1135{
1136 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1137 ULONGEST old_pc;
1138 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1139 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1140 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1141}
1142
771b4502 1143
cc5f0d61
UW		 1144/* Cell/B.E. cross-architecture unwinder support. */
1145
1146struct spu2ppu_cache
1147{
1148 struct frame_id frame_id;
1149 struct regcache *regcache;
1150};
1151
1152static struct gdbarch *
1153spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1154{
1155 struct spu2ppu_cache *cache = *this_cache;
1156 return get_regcache_arch (cache->regcache);
1157}
1158
1159static void
1160spu2ppu_this_id (struct frame_info *this_frame,
1161 void **this_cache, struct frame_id *this_id)
1162{
1163 struct spu2ppu_cache *cache = *this_cache;
1164 *this_id = cache->frame_id;
1165}
1166
1167static struct value *
1168spu2ppu_prev_register (struct frame_info *this_frame,
1169 void **this_cache, int regnum)
1170{
1171 struct spu2ppu_cache *cache = *this_cache;
1172 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1173 gdb_byte *buf;
1174
1175 buf = alloca (register_size (gdbarch, regnum));
1176 regcache_cooked_read (cache->regcache, regnum, buf);
1177 return frame_unwind_got_bytes (this_frame, regnum, buf);
1178}
1179
1180static int
1181spu2ppu_sniffer (const struct frame_unwind *self,
1182 struct frame_info *this_frame, void **this_prologue_cache)
1183{
1184 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1185 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1186 CORE_ADDR base, func, backchain;
1187 gdb_byte buf[4];
1188
1189 if (gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_spu)
1190 return 0;
1191
1192 base = get_frame_sp (this_frame);
1193 func = get_frame_pc (this_frame);
1194 if (target_read_memory (base, buf, 4))
1195 return 0;
1196 backchain = extract_unsigned_integer (buf, 4, byte_order);
1197
1198 if (!backchain)
1199 {
1200 struct frame_info *fi;
1201
1202 struct spu2ppu_cache *cache
1203 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1204
1205 cache->frame_id = frame_id_build (base + 16, func);
1206
1207 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1208 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1209 break;
1210
1211 if (fi)
1212 {
1213 cache->regcache = frame_save_as_regcache (fi);
1214 *this_prologue_cache = cache;
1215 return 1;
1216 }
1217 else
1218 {
1219 struct regcache *regcache;
1220 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch);
1221 cache->regcache = regcache_dup (regcache);
1222 *this_prologue_cache = cache;
1223 return 1;
1224 }
1225 }
1226
1227 return 0;
1228}
1229
1230static void
1231spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1232{
1233 struct spu2ppu_cache *cache = this_cache;
1234 regcache_xfree (cache->regcache);
1235}
1236
1237static const struct frame_unwind spu2ppu_unwind = {
1238 ARCH_FRAME,
8fbca658 1239 default_frame_unwind_stop_reason,
cc5f0d61
UW		 1240 spu2ppu_this_id,
1241 spu2ppu_prev_register,
1242 NULL,
1243 spu2ppu_sniffer,
1244 spu2ppu_dealloc_cache,
1245 spu2ppu_prev_arch,
1246};
1247
1248
771b4502
UW		 1249/* Function calling convention. */
1250
7b3dc0b7
UW		 1251static CORE_ADDR
1252spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1253{
1254 return sp & ~15;
1255}
1256
87805e63
UW		 1257static CORE_ADDR
1258spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1259 struct value **args, int nargs, struct type *value_type,
1260 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1261 struct regcache *regcache)
1262{
1263 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1264 sp = (sp - 4) & ~15;
1265 /* Store the address of that breakpoint */
1266 *bp_addr = sp;
1267 /* The call starts at the callee's entry point. */
1268 *real_pc = funaddr;
1269
1270 return sp;
1271}
1272
771b4502
UW		 1273static int
1274spu_scalar_value_p (struct type *type)
1275{
1276 switch (TYPE_CODE (type))
1277 {
1278 case TYPE_CODE_INT:
1279 case TYPE_CODE_ENUM:
1280 case TYPE_CODE_RANGE:
1281 case TYPE_CODE_CHAR:
1282 case TYPE_CODE_BOOL:
1283 case TYPE_CODE_PTR:
1284 case TYPE_CODE_REF:
1285 return TYPE_LENGTH (type) <= 16;
1286
1287 default:
1288 return 0;
1289 }
1290}
1291
1292static void
1293spu_value_to_regcache (struct regcache *regcache, int regnum,
1294 struct type *type, const gdb_byte *in)
1295{
1296 int len = TYPE_LENGTH (type);
1297
1298 if (spu_scalar_value_p (type))
1299 {
1300 int preferred_slot = len < 4 ? 4 - len : 0;
1301 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1302 }
1303 else
1304 {
1305 while (len >= 16)
1306 {
1307 regcache_cooked_write (regcache, regnum++, in);
1308 in += 16;
1309 len -= 16;
1310 }
1311
1312 if (len > 0)
1313 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1314 }
1315}
1316
1317static void
1318spu_regcache_to_value (struct regcache *regcache, int regnum,
1319 struct type *type, gdb_byte *out)
1320{
1321 int len = TYPE_LENGTH (type);
1322
1323 if (spu_scalar_value_p (type))
1324 {
1325 int preferred_slot = len < 4 ? 4 - len : 0;
1326 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1327 }
1328 else
1329 {
1330 while (len >= 16)
1331 {
1332 regcache_cooked_read (regcache, regnum++, out);
1333 out += 16;
1334 len -= 16;
1335 }
1336
1337 if (len > 0)
1338 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1339 }
1340}
1341
1342static CORE_ADDR
1343spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1344 struct regcache *regcache, CORE_ADDR bp_addr,
1345 int nargs, struct value **args, CORE_ADDR sp,
1346 int struct_return, CORE_ADDR struct_addr)
1347{
e17a4113 1348 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1349 CORE_ADDR sp_delta;
771b4502
UW		 1350 int i;
1351 int regnum = SPU_ARG1_REGNUM;
1352 int stack_arg = -1;
1353 gdb_byte buf[16];
1354
1355 /* Set the return address. */
1356 memset (buf, 0, sizeof buf);
85e747d2 1357 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1358 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1359
1360 /* If STRUCT_RETURN is true, then the struct return address (in
1361 STRUCT_ADDR) will consume the first argument-passing register.
1362 Both adjust the register count and store that value. */
1363 if (struct_return)
1364 {
1365 memset (buf, 0, sizeof buf);
85e747d2 1366 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1367 regcache_cooked_write (regcache, regnum++, buf);
1368 }
1369
1370 /* Fill in argument registers. */
1371 for (i = 0; i < nargs; i++)
1372 {
1373 struct value *arg = args[i];
1374 struct type *type = check_typedef (value_type (arg));
1375 const gdb_byte *contents = value_contents (arg);
1376 int len = TYPE_LENGTH (type);
1377 int n_regs = align_up (len, 16) / 16;
1378
1379 /* If the argument doesn't wholly fit into registers, it and
1380 all subsequent arguments go to the stack. */
1381 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1382 {
1383 stack_arg = i;
1384 break;
1385 }
1386
1387 spu_value_to_regcache (regcache, regnum, type, contents);
1388 regnum += n_regs;
1389 }
1390
1391 /* Overflow arguments go to the stack. */
1392 if (stack_arg != -1)
1393 {
1394 CORE_ADDR ap;
1395
1396 /* Allocate all required stack size. */
1397 for (i = stack_arg; i < nargs; i++)
1398 {
1399 struct type *type = check_typedef (value_type (args[i]));
1400 sp -= align_up (TYPE_LENGTH (type), 16);
1401 }
1402
1403 /* Fill in stack arguments. */
1404 ap = sp;
1405 for (i = stack_arg; i < nargs; i++)
1406 {
1407 struct value *arg = args[i];
1408 struct type *type = check_typedef (value_type (arg));
1409 int len = TYPE_LENGTH (type);
1410 int preferred_slot;
1411
1412 if (spu_scalar_value_p (type))
1413 preferred_slot = len < 4 ? 4 - len : 0;
1414 else
1415 preferred_slot = 0;
1416
1417 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1418 ap += align_up (TYPE_LENGTH (type), 16);
1419 }
1420 }
1421
1422 /* Allocate stack frame header. */
1423 sp -= 32;
1424
ee82e879
UW		 1425 /* Store stack back chain. */
1426 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1427 target_write_memory (sp, buf, 16);
1428
9ff3afda 1429 /* Finally, update all slots of the SP register. */
e17a4113 1430 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1431 for (i = 0; i < 4; i++)
1432 {
e17a4113
UW		 1433 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1434 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1435 }
1436 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1437
1438 return sp;
1439}
1440
1441static struct frame_id
8d998b8f 1442spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1443{
85e747d2 1444 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1445 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1446 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1447 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1448}
1449
1450/* Function return value access. */
1451
1452static enum return_value_convention
6a3a010b 1453spu_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101
CV		 1454 struct type *type, struct regcache *regcache,
1455 gdb_byte *out, const gdb_byte *in)
771b4502 1456{
6a3a010b 1457 struct type *func_type = function ? value_type (function) : NULL;
771b4502 1458 enum return_value_convention rvc;
54fcddd0
UW		 1459 int opencl_vector = 0;
1460
598cfb71
UW		 1461 if (func_type)
1462 {
1463 func_type = check_typedef (func_type);
1464
1465 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1466 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1467
1468 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1469 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1470 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1471 && TYPE_VECTOR (type))
1472 opencl_vector = 1;
1473 }
771b4502
UW		 1474
1475 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1476 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1477 else
1478 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1479
1480 if (in)
1481 {
1482 switch (rvc)
1483 {
1484 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1485 if (opencl_vector && TYPE_LENGTH (type) == 2)
1486 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1487 else
1488 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
771b4502
UW		 1489 break;
1490
1491 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1492 error (_("Cannot set function return value."));
771b4502
UW		 1493 break;
1494 }
1495 }
1496 else if (out)
1497 {
1498 switch (rvc)
1499 {
1500 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1501 if (opencl_vector && TYPE_LENGTH (type) == 2)
1502 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1503 else
1504 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
771b4502
UW		 1505 break;
1506
1507 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1508 error (_("Function return value unknown."));
771b4502
UW		 1509 break;
1510 }
1511 }
1512
1513 return rvc;
1514}
1515
1516
1517/* Breakpoints. */
1518
1519static const gdb_byte *
c378eb4e
MS		 1520spu_breakpoint_from_pc (struct gdbarch *gdbarch,
1521 CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1522{
1523 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1524
1525 *lenptr = sizeof breakpoint;
1526 return breakpoint;
1527}
1528
d03285ec
UW		 1529static int
1530spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1531 struct bp_target_info *bp_tgt)
1532{
1533 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1534 that in a combined application, we have some breakpoints inserted in SPU
1535 code, and now the application forks (on the PPU side). GDB common code
1536 will assume that the fork system call copied all breakpoints into the new
1537 process' address space, and that all those copies now need to be removed
1538 (see breakpoint.c:detach_breakpoints).
1539
1540 While this is certainly true for PPU side breakpoints, it is not true
1541 for SPU side breakpoints. fork will clone the SPU context file
1542 descriptors, so that all the existing SPU contexts are in accessible
1543 in the new process. However, the contents of the SPU contexts themselves
1544 are *not* cloned. Therefore the effect of detach_breakpoints is to
1545 remove SPU breakpoints from the *original* SPU context's local store
1546 -- this is not the correct behaviour.
1547
1548 The workaround is to check whether the PID we are asked to remove this
1549 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1550 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1551 true in the context of detach_breakpoints. If so, we simply do nothing.
1552 [ Note that for the fork child process, it does not matter if breakpoints
1553 remain inserted, because those SPU contexts are not runnable anyway --
1554 the Linux kernel allows only the original process to invoke spu_run. */
1555
1556 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1557 return 0;
1558
1559 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1560}
1561
771b4502
UW		 1562
1563/* Software single-stepping support. */
1564
63807e1d 1565static int
0b1b3e42 1566spu_software_single_step (struct frame_info *frame)
771b4502 1567{
a6d9a66e 1568 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1569 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1570 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1571 CORE_ADDR pc, next_pc;
1572 unsigned int insn;
1573 int offset, reg;
1574 gdb_byte buf[4];
13def385 1575 ULONGEST lslr;
771b4502 1576
0b1b3e42 1577 pc = get_frame_pc (frame);
771b4502 1578
e0cd558a
UW		 1579 if (target_read_memory (pc, buf, 4))
1580 return 1;
e17a4113 1581 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1582
13def385
UW		 1583 /* Get local store limit. */
1584 lslr = get_frame_register_unsigned (frame, SPU_LSLR_REGNUM);
1585 if (!lslr)
1586 lslr = (ULONGEST) -1;
1587
e0cd558a
UW		 1588 /* Next sequential instruction is at PC + 4, except if the current
1589 instruction is a PPE-assisted call, in which case it is at PC + 8.
1590 Wrap around LS limit to be on the safe side. */
1591 if ((insn & 0xffffff00) == 0x00002100)
13def385 1592 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
e0cd558a 1593 else
13def385 1594 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
771b4502 1595
6c95b8df
PA		 1596 insert_single_step_breakpoint (gdbarch,
1597 aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1598
e0cd558a
UW		 1599 if (is_branch (insn, &offset, &reg))
1600 {
1601 CORE_ADDR target = offset;
771b4502 1602
e0cd558a 1603 if (reg == SPU_PC_REGNUM)
85e747d2 1604 target += SPUADDR_ADDR (pc);
e0cd558a
UW		 1605 else if (reg != -1)
1606 {
8dccd430
PA		 1607 int optim, unavail;
1608
1609 if (get_frame_register_bytes (frame, reg, 0, 4, buf,
1610 &optim, &unavail))
1611 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
1612 else
1613 {
1614 if (optim)
1615 error (_("Could not determine address of "
1616 "single-step breakpoint."));
1617 if (unavail)
1618 throw_error (NOT_AVAILABLE_ERROR,
1619 _("Could not determine address of "
1620 "single-step breakpoint."));
1621 }
771b4502 1622 }
e0cd558a 1623
13def385 1624 target = target & lslr;
e0cd558a 1625 if (target != next_pc)
6c95b8df 1626 insert_single_step_breakpoint (gdbarch, aspace,
85e747d2 1627 SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1628 }
e6590a1b
UW		 1629
1630 return 1;
771b4502
UW		 1631}
1632
6e3f70d7
UW		 1633
1634/* Longjmp support. */
1635
1636static int
1637spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1638{
e17a4113 1639 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1640 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1641 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1642 gdb_byte buf[4];
1643 CORE_ADDR jb_addr;
8dccd430 1644 int optim, unavail;
6e3f70d7
UW		 1645
1646 /* Jump buffer is pointed to by the argument register $r3. */
8dccd430
PA		 1647 if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1648 &optim, &unavail))
1649 return 0;
1650
e17a4113 1651 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1652 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1653 return 0;
1654
e17a4113 1655 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1656 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1657 return 1;
1658}
1659
1660
85e747d2
UW		 1661/* Disassembler. */
1662
1663struct spu_dis_asm_data
1664{
1665 struct gdbarch *gdbarch;
1666 int id;
1667};
1668
1669static void
1670spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1671{
1672 struct spu_dis_asm_data *data = info->application_data;
1673 print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1674}
1675
1676static int
1677gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1678{
c378eb4e
MS		 1679 /* The opcodes disassembler does 18-bit address arithmetic. Make
1680 sure the SPU ID encoded in the high bits is added back when we
1681 call print_address. */
85e747d2
UW		 1682 struct disassemble_info spu_info = *info;
1683 struct spu_dis_asm_data data;
1684 data.gdbarch = info->application_data;
1685 data.id = SPUADDR_SPU (memaddr);
1686
1687 spu_info.application_data = &data;
1688 spu_info.print_address_func = spu_dis_asm_print_address;
1689 return print_insn_spu (memaddr, &spu_info);
1690}
1691
1692
dcf52cd8
UW		 1693/* Target overlays for the SPU overlay manager.
1694
1695 See the documentation of simple_overlay_update for how the
1696 interface is supposed to work.
1697
1698 Data structures used by the overlay manager:
1699
1700 struct ovly_table
1701 {
1702 u32 vma;
1703 u32 size;
1704 u32 pos;
1705 u32 buf;
1706 } _ovly_table[]; -- one entry per overlay section
1707
1708 struct ovly_buf_table
1709 {
1710 u32 mapped;
1711 } _ovly_buf_table[]; -- one entry per overlay buffer
1712
1713 _ovly_table should never change.
1714
c378eb4e
MS		 1715 Both tables are aligned to a 16-byte boundary, the symbols
1716 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1717 size set to the size of the respective array. buf in _ovly_table is
1718 an index into _ovly_buf_table.
dcf52cd8 1719
c378eb4e 1720 mapped is an index into _ovly_table. Both the mapped and buf indices start
dcf52cd8
UW		 1721 from one to reference the first entry in their respective tables. */
1722
1723/* Using the per-objfile private data mechanism, we store for each
1724 objfile an array of "struct spu_overlay_table" structures, one
1725 for each obj_section of the objfile. This structure holds two
1726 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1727 is *not* an overlay section. If it is non-zero, it represents
1728 a target address. The overlay section is mapped iff the target
1729 integer at this location equals MAPPED_VAL. */
1730
1731static const struct objfile_data *spu_overlay_data;
1732
1733struct spu_overlay_table
1734 {
1735 CORE_ADDR mapped_ptr;
1736 CORE_ADDR mapped_val;
1737 };
1738
1739/* Retrieve the overlay table for OBJFILE. If not already cached, read
1740 the _ovly_table data structure from the target and initialize the
1741 spu_overlay_table data structure from it. */
1742static struct spu_overlay_table *
1743spu_get_overlay_table (struct objfile *objfile)
1744{
e17a4113
UW		 1745 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1746 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8
UW		 1747 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1748 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1749 unsigned ovly_table_size, ovly_buf_table_size;
1750 struct spu_overlay_table *tbl;
1751 struct obj_section *osect;
1752 char *ovly_table;
1753 int i;
1754
1755 tbl = objfile_data (objfile, spu_overlay_data);
1756 if (tbl)
1757 return tbl;
1758
1759 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1760 if (!ovly_table_msym)
1761 return NULL;
1762
c378eb4e
MS		 1763 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1764 NULL, objfile);
dcf52cd8
UW		 1765 if (!ovly_buf_table_msym)
1766 return NULL;
1767
1768 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1769 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1770
1771 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1772 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1773
1774 ovly_table = xmalloc (ovly_table_size);
1775 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1776
1777 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1778 objfile->sections_end - objfile->sections,
1779 struct spu_overlay_table);
1780
1781 for (i = 0; i < ovly_table_size / 16; i++)
1782 {
e17a4113
UW		 1783 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1784 4, byte_order);
1785 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1786 4, byte_order);
1787 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1788 4, byte_order);
1789 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1790 4, byte_order);
dcf52cd8
UW		 1791
1792 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1793 continue;
1794
1795 ALL_OBJFILE_OSECTIONS (objfile, osect)
1796 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1797 && pos == osect->the_bfd_section->filepos)
1798 {
1799 int ndx = osect - objfile->sections;
1800 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1801 tbl[ndx].mapped_val = i + 1;
1802 break;
1803 }
1804 }
1805
1806 xfree (ovly_table);
1807 set_objfile_data (objfile, spu_overlay_data, tbl);
1808 return tbl;
1809}
1810
1811/* Read _ovly_buf_table entry from the target to dermine whether
1812 OSECT is currently mapped, and update the mapped state. */
1813static void
1814spu_overlay_update_osect (struct obj_section *osect)
1815{
e17a4113
UW		 1816 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1817 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1818 struct spu_overlay_table *ovly_table;
85e747d2 1819 CORE_ADDR id, val;
dcf52cd8
UW		 1820
1821 ovly_table = spu_get_overlay_table (osect->objfile);
1822 if (!ovly_table)
1823 return;
1824
1825 ovly_table += osect - osect->objfile->sections;
1826 if (ovly_table->mapped_ptr == 0)
1827 return;
1828
85e747d2
UW		 1829 id = SPUADDR_SPU (obj_section_addr (osect));
1830 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1831 4, byte_order);
dcf52cd8
UW		 1832 osect->ovly_mapped = (val == ovly_table->mapped_val);
1833}
1834
1835/* If OSECT is NULL, then update all sections' mapped state.
1836 If OSECT is non-NULL, then update only OSECT's mapped state. */
1837static void
1838spu_overlay_update (struct obj_section *osect)
1839{
1840 /* Just one section. */
1841 if (osect)
1842 spu_overlay_update_osect (osect);
1843
1844 /* All sections. */
1845 else
1846 {
1847 struct objfile *objfile;
1848
1849 ALL_OBJSECTIONS (objfile, osect)
714835d5 1850 if (section_is_overlay (osect))
dcf52cd8
UW		 1851 spu_overlay_update_osect (osect);
1852 }
1853}
1854
1855/* Whenever a new objfile is loaded, read the target's _ovly_table.
1856 If there is one, go through all sections and make sure for non-
1857 overlay sections LMA equals VMA, while for overlay sections LMA
d2ed6730 1858 is larger than SPU_OVERLAY_LMA. */
dcf52cd8
UW		 1859static void
1860spu_overlay_new_objfile (struct objfile *objfile)
1861{
1862 struct spu_overlay_table *ovly_table;
1863 struct obj_section *osect;
1864
1865 /* If we've already touched this file, do nothing. */
1866 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1867 return;
1868
0391f248
UW		 1869 /* Consider only SPU objfiles. */
1870 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1871 return;
1872
dcf52cd8
UW		 1873 /* Check if this objfile has overlays. */
1874 ovly_table = spu_get_overlay_table (objfile);
1875 if (!ovly_table)
1876 return;
1877
1878 /* Now go and fiddle with all the LMAs. */
1879 ALL_OBJFILE_OSECTIONS (objfile, osect)
1880 {
1881 bfd *obfd = objfile->obfd;
1882 asection *bsect = osect->the_bfd_section;
1883 int ndx = osect - objfile->sections;
1884
1885 if (ovly_table[ndx].mapped_ptr == 0)
1886 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1887 else
d2ed6730 1888 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
dcf52cd8
UW		 1889 }
1890}
1891
771b4502 1892
3285f3fe
UW		 1893/* Insert temporary breakpoint on "main" function of newly loaded
1894 SPE context OBJFILE. */
1895static void
1896spu_catch_start (struct objfile *objfile)
1897{
1898 struct minimal_symbol *minsym;
1899 struct symtab *symtab;
1900 CORE_ADDR pc;
1901 char buf[32];
1902
1903 /* Do this only if requested by "set spu stop-on-load on". */
1904 if (!spu_stop_on_load_p)
1905 return;
1906
1907 /* Consider only SPU objfiles. */
1908 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1909 return;
1910
1911 /* The main objfile is handled differently. */
1912 if (objfile == symfile_objfile)
1913 return;
1914
1915 /* There can be multiple symbols named "main". Search for the
1916 "main" in *this* objfile. */
1917 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1918 if (!minsym)
1919 return;
1920
1921 /* If we have debugging information, try to use it -- this
1922 will allow us to properly skip the prologue. */
1923 pc = SYMBOL_VALUE_ADDRESS (minsym);
1924 symtab = find_pc_sect_symtab (pc, SYMBOL_OBJ_SECTION (minsym));
1925 if (symtab != NULL)
1926 {
1927 struct blockvector *bv = BLOCKVECTOR (symtab);
1928 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1929 struct symbol *sym;
1930 struct symtab_and_line sal;
1931
94af9270 1932 sym = lookup_block_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1933 if (sym)
1934 {
1935 fixup_symbol_section (sym, objfile);
1936 sal = find_function_start_sal (sym, 1);
1937 pc = sal.pc;
1938 }
1939 }
1940
1941 /* Use a numerical address for the set_breakpoint command to avoid having
1942 the breakpoint re-set incorrectly. */
1943 xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
d8c09fb5
JK		 1944 create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
1945 NULL /* cond_string */, -1 /* thread */,
6a609e58 1946 NULL /* extra_string */,
d8c09fb5 1947 0 /* parse_condition_and_thread */, 1 /* tempflag */,
bddaafad 1948 bp_breakpoint /* type_wanted */,
d8c09fb5
JK		 1949 0 /* ignore_count */,
1950 AUTO_BOOLEAN_FALSE /* pending_break_support */,
931bb47f 1951 &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
44f238bb 1952 1 /* enabled */, 0 /* internal */, 0);
3285f3fe
UW		 1953}
1954
1955
ff1a52c6
UW		 1956/* Look up OBJFILE loaded into FRAME's SPU context. */
1957static struct objfile *
1958spu_objfile_from_frame (struct frame_info *frame)
1959{
1960 struct gdbarch *gdbarch = get_frame_arch (frame);
1961 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1962 struct objfile *obj;
1963
1964 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
1965 return NULL;
1966
1967 ALL_OBJFILES (obj)
1968 {
1969 if (obj->sections != obj->sections_end
1970 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
1971 return obj;
1972 }
1973
1974 return NULL;
1975}
1976
1977/* Flush cache for ea pointer access if available. */
1978static void
1979flush_ea_cache (void)
1980{
1981 struct minimal_symbol *msymbol;
1982 struct objfile *obj;
1983
1984 if (!has_stack_frames ())
1985 return;
1986
1987 obj = spu_objfile_from_frame (get_current_frame ());
1988 if (obj == NULL)
1989 return;
1990
1991 /* Lookup inferior function __cache_flush. */
1992 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
1993 if (msymbol != NULL)
1994 {
1995 struct type *type;
1996 CORE_ADDR addr;
1997
1998 type = objfile_type (obj)->builtin_void;
1999 type = lookup_function_type (type);
2000 type = lookup_pointer_type (type);
2001 addr = SYMBOL_VALUE_ADDRESS (msymbol);
2002
2003 call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
2004 }
2005}
2006
2007/* This handler is called when the inferior has stopped. If it is stopped in
2008 SPU architecture then flush the ea cache if used. */
2009static void
2010spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2011{
2012 if (!spu_auto_flush_cache_p)
2013 return;
2014
2015 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2016 re-entering this function when __cache_flush stops. */
2017 spu_auto_flush_cache_p = 0;
2018 flush_ea_cache ();
2019 spu_auto_flush_cache_p = 1;
2020}
2021
2022
23d964e7
UW		 2023/* "info spu" commands. */
2024
2025static void
2026info_spu_event_command (char *args, int from_tty)
2027{
2028 struct frame_info *frame = get_selected_frame (NULL);
2029 ULONGEST event_status = 0;
2030 ULONGEST event_mask = 0;
2031 struct cleanup *chain;
2032 gdb_byte buf[100];
2033 char annex[32];
2034 LONGEST len;
22e048c9 2035 int id;
23d964e7 2036
0391f248
UW		 2037 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2038 error (_("\"info spu\" is only supported on the SPU architecture."));
2039
23d964e7
UW		 2040 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2041
2042 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2043 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2044 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2045 if (len <= 0)
2046 error (_("Could not read event_status."));
9971ac47 2047 buf[len] = '\0';
23d964e7
UW		 2048 event_status = strtoulst (buf, NULL, 16);
2049
2050 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2051 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2052 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2053 if (len <= 0)
2054 error (_("Could not read event_mask."));
9971ac47 2055 buf[len] = '\0';
23d964e7
UW		 2056 event_mask = strtoulst (buf, NULL, 16);
2057
31a0ae49 2058 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoEvent");
23d964e7 2059
31a0ae49 2060 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2061 {
31a0ae49 2062 ui_out_field_fmt (current_uiout, "event_status",
23d964e7 2063 "0x%s", phex_nz (event_status, 4));
31a0ae49 2064 ui_out_field_fmt (current_uiout, "event_mask",
23d964e7
UW		 2065 "0x%s", phex_nz (event_mask, 4));
2066 }
2067 else
2068 {
2069 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2070 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2071 }
2072
2073 do_cleanups (chain);
2074}
2075
2076static void
2077info_spu_signal_command (char *args, int from_tty)
2078{
2079 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2080 struct gdbarch *gdbarch = get_frame_arch (frame);
2081 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2082 ULONGEST signal1 = 0;
2083 ULONGEST signal1_type = 0;
2084 int signal1_pending = 0;
2085 ULONGEST signal2 = 0;
2086 ULONGEST signal2_type = 0;
2087 int signal2_pending = 0;
2088 struct cleanup *chain;
2089 char annex[32];
2090 gdb_byte buf[100];
2091 LONGEST len;
22e048c9 2092 int id;
23d964e7 2093
e17a4113 2094 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2095 error (_("\"info spu\" is only supported on the SPU architecture."));
2096
23d964e7
UW		 2097 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2098
2099 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2100 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2101 if (len < 0)
2102 error (_("Could not read signal1."));
2103 else if (len == 4)
2104 {
e17a4113 2105 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2106 signal1_pending = 1;
2107 }
2108
2109 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2110 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2111 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2112 if (len <= 0)
2113 error (_("Could not read signal1_type."));
9971ac47 2114 buf[len] = '\0';
23d964e7
UW		 2115 signal1_type = strtoulst (buf, NULL, 16);
2116
2117 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2118 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2119 if (len < 0)
2120 error (_("Could not read signal2."));
2121 else if (len == 4)
2122 {
e17a4113 2123 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2124 signal2_pending = 1;
2125 }
2126
2127 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2128 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2129 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2130 if (len <= 0)
2131 error (_("Could not read signal2_type."));
9971ac47 2132 buf[len] = '\0';
23d964e7
UW		 2133 signal2_type = strtoulst (buf, NULL, 16);
2134
31a0ae49 2135 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoSignal");
23d964e7 2136
31a0ae49 2137 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2138 {
31a0ae49
JK		 2139 ui_out_field_int (current_uiout, "signal1_pending", signal1_pending);
2140 ui_out_field_fmt (current_uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2141 ui_out_field_int (current_uiout, "signal1_type", signal1_type);
2142 ui_out_field_int (current_uiout, "signal2_pending", signal2_pending);
2143 ui_out_field_fmt (current_uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2144 ui_out_field_int (current_uiout, "signal2_type", signal2_type);
23d964e7
UW		 2145 }
2146 else
2147 {
2148 if (signal1_pending)
2149 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2150 else
2151 printf_filtered (_("Signal 1 not pending "));
2152
2153 if (signal1_type)
23d964e7 2154 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2155 else
2156 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2157
2158 if (signal2_pending)
2159 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2160 else
2161 printf_filtered (_("Signal 2 not pending "));
2162
2163 if (signal2_type)
23d964e7 2164 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2165 else
2166 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2167 }
2168
2169 do_cleanups (chain);
2170}
2171
2172static void
e17a4113 2173info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2174 const char *field, const char *msg)
2175{
2176 struct cleanup *chain;
2177 int i;
2178
2179 if (nr <= 0)
2180 return;
2181
31a0ae49 2182 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 1, nr, "mbox");
23d964e7 2183
31a0ae49
JK		 2184 ui_out_table_header (current_uiout, 32, ui_left, field, msg);
2185 ui_out_table_body (current_uiout);
23d964e7
UW		 2186
2187 for (i = 0; i < nr; i++)
2188 {
2189 struct cleanup *val_chain;
2190 ULONGEST val;
31a0ae49 2191 val_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "mbox");
e17a4113 2192 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
31a0ae49 2193 ui_out_field_fmt (current_uiout, field, "0x%s", phex (val, 4));
23d964e7
UW		 2194 do_cleanups (val_chain);
2195
31a0ae49 2196 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2197 printf_filtered ("\n");
2198 }
2199
2200 do_cleanups (chain);
2201}
2202
2203static void
2204info_spu_mailbox_command (char *args, int from_tty)
2205{
2206 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2207 struct gdbarch *gdbarch = get_frame_arch (frame);
2208 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2209 struct cleanup *chain;
2210 char annex[32];
2211 gdb_byte buf[1024];
2212 LONGEST len;
22e048c9 2213 int id;
23d964e7 2214
e17a4113 2215 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2216 error (_("\"info spu\" is only supported on the SPU architecture."));
2217
23d964e7
UW		 2218 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2219
31a0ae49 2220 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoMailbox");
23d964e7
UW		 2221
2222 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2223 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2224 buf, 0, sizeof buf);
2225 if (len < 0)
2226 error (_("Could not read mbox_info."));
2227
e17a4113
UW		 2228 info_spu_mailbox_list (buf, len / 4, byte_order,
2229 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2230
2231 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2232 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2233 buf, 0, sizeof buf);
2234 if (len < 0)
2235 error (_("Could not read ibox_info."));
2236
e17a4113
UW		 2237 info_spu_mailbox_list (buf, len / 4, byte_order,
2238 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2239
2240 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2241 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2242 buf, 0, sizeof buf);
2243 if (len < 0)
2244 error (_("Could not read wbox_info."));
2245
e17a4113
UW		 2246 info_spu_mailbox_list (buf, len / 4, byte_order,
2247 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2248
2249 do_cleanups (chain);
2250}
2251
2252static ULONGEST
2253spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2254{
2255 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2256 return (word >> (63 - last)) & mask;
2257}
2258
2259static void
e17a4113 2260info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7
UW		 2261{
2262 static char *spu_mfc_opcode[256] =
2263 {
2264 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2265 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2266 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2267 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2268 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2269 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2270 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2271 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2272 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2273 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2274 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2275 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2276 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2277 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2278 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2279 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2280 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2281 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2282 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2283 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2284 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2285 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2286 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2287 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2288 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2289 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2290 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2291 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2292 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2293 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2294 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2295 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2296 };
2297
12ab8a60
UW		 2298 int *seq = alloca (nr * sizeof (int));
2299 int done = 0;
23d964e7 2300 struct cleanup *chain;
12ab8a60
UW		 2301 int i, j;
2302
2303
2304 /* Determine sequence in which to display (valid) entries. */
2305 for (i = 0; i < nr; i++)
2306 {
2307 /* Search for the first valid entry all of whose
2308 dependencies are met. */
2309 for (j = 0; j < nr; j++)
2310 {
2311 ULONGEST mfc_cq_dw3;
2312 ULONGEST dependencies;
2313
2314 if (done & (1 << (nr - 1 - j)))
2315 continue;
2316
e17a4113
UW		 2317 mfc_cq_dw3
2318 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2319 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2320 continue;
2321
2322 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2323 if ((dependencies & done) != dependencies)
2324 continue;
2325
2326 seq[i] = j;
2327 done |= 1 << (nr - 1 - j);
2328 break;
2329 }
2330
2331 if (j == nr)
2332 break;
2333 }
2334
2335 nr = i;
2336
23d964e7 2337
31a0ae49
JK		 2338 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 10, nr,
2339 "dma_cmd");
23d964e7 2340
31a0ae49
JK		 2341 ui_out_table_header (current_uiout, 7, ui_left, "opcode", "Opcode");
2342 ui_out_table_header (current_uiout, 3, ui_left, "tag", "Tag");
2343 ui_out_table_header (current_uiout, 3, ui_left, "tid", "TId");
2344 ui_out_table_header (current_uiout, 3, ui_left, "rid", "RId");
2345 ui_out_table_header (current_uiout, 18, ui_left, "ea", "EA");
2346 ui_out_table_header (current_uiout, 7, ui_left, "lsa", "LSA");
2347 ui_out_table_header (current_uiout, 7, ui_left, "size", "Size");
2348 ui_out_table_header (current_uiout, 7, ui_left, "lstaddr", "LstAddr");
2349 ui_out_table_header (current_uiout, 7, ui_left, "lstsize", "LstSize");
2350 ui_out_table_header (current_uiout, 1, ui_left, "error_p", "E");
23d964e7 2351
31a0ae49 2352 ui_out_table_body (current_uiout);
23d964e7
UW		 2353
2354 for (i = 0; i < nr; i++)
2355 {
2356 struct cleanup *cmd_chain;
2357 ULONGEST mfc_cq_dw0;
2358 ULONGEST mfc_cq_dw1;
2359 ULONGEST mfc_cq_dw2;
23d964e7 2360 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
22e048c9 2361 int list_lsa, list_size, mfc_lsa, mfc_size;
23d964e7
UW		 2362 ULONGEST mfc_ea;
2363 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2364
2365 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2366 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2367
e17a4113
UW		 2368 mfc_cq_dw0
2369 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2370 mfc_cq_dw1
2371 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2372 mfc_cq_dw2
2373 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2374
2375 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2376 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2377 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2378 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2379 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2380 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2381 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2382
2383 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2384 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2385
2386 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2387 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2388 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2389 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2390 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2391 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2392
31a0ae49 2393 cmd_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "cmd");
23d964e7
UW		 2394
2395 if (spu_mfc_opcode[mfc_cmd_opcode])
31a0ae49 2396 ui_out_field_string (current_uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
23d964e7 2397 else
31a0ae49 2398 ui_out_field_int (current_uiout, "opcode", mfc_cmd_opcode);
23d964e7 2399
31a0ae49
JK		 2400 ui_out_field_int (current_uiout, "tag", mfc_cmd_tag);
2401 ui_out_field_int (current_uiout, "tid", tclass_id);
2402 ui_out_field_int (current_uiout, "rid", rclass_id);
23d964e7
UW		 2403
2404 if (ea_valid_p)
31a0ae49 2405 ui_out_field_fmt (current_uiout, "ea", "0x%s", phex (mfc_ea, 8));
23d964e7 2406 else
31a0ae49 2407 ui_out_field_skip (current_uiout, "ea");
23d964e7 2408
31a0ae49 2409 ui_out_field_fmt (current_uiout, "lsa", "0x%05x", mfc_lsa << 4);
23d964e7 2410 if (qw_valid_p)
31a0ae49 2411 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size << 4);
23d964e7 2412 else
31a0ae49 2413 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size);
23d964e7
UW		 2414
2415 if (list_valid_p)
2416 {
31a0ae49
JK		 2417 ui_out_field_fmt (current_uiout, "lstaddr", "0x%05x", list_lsa << 3);
2418 ui_out_field_fmt (current_uiout, "lstsize", "0x%05x", list_size << 3);
23d964e7
UW		 2419 }
2420 else
2421 {
31a0ae49
JK		 2422 ui_out_field_skip (current_uiout, "lstaddr");
2423 ui_out_field_skip (current_uiout, "lstsize");
23d964e7
UW		 2424 }
2425
2426 if (cmd_error_p)
31a0ae49 2427 ui_out_field_string (current_uiout, "error_p", "*");
23d964e7 2428 else
31a0ae49 2429 ui_out_field_skip (current_uiout, "error_p");
23d964e7
UW		 2430
2431 do_cleanups (cmd_chain);
2432
31a0ae49 2433 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2434 printf_filtered ("\n");
2435 }
2436
2437 do_cleanups (chain);
2438}
2439
2440static void
2441info_spu_dma_command (char *args, int from_tty)
2442{
2443 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2444 struct gdbarch *gdbarch = get_frame_arch (frame);
2445 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2446 ULONGEST dma_info_type;
2447 ULONGEST dma_info_mask;
2448 ULONGEST dma_info_status;
2449 ULONGEST dma_info_stall_and_notify;
2450 ULONGEST dma_info_atomic_command_status;
2451 struct cleanup *chain;
2452 char annex[32];
2453 gdb_byte buf[1024];
2454 LONGEST len;
22e048c9 2455 int id;
23d964e7 2456
0391f248
UW		 2457 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2458 error (_("\"info spu\" is only supported on the SPU architecture."));
2459
23d964e7
UW		 2460 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2461
2462 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2463 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2464 buf, 0, 40 + 16 * 32);
2465 if (len <= 0)
2466 error (_("Could not read dma_info."));
2467
e17a4113
UW		 2468 dma_info_type
2469 = extract_unsigned_integer (buf, 8, byte_order);
2470 dma_info_mask
2471 = extract_unsigned_integer (buf + 8, 8, byte_order);
2472 dma_info_status
2473 = extract_unsigned_integer (buf + 16, 8, byte_order);
2474 dma_info_stall_and_notify
2475 = extract_unsigned_integer (buf + 24, 8, byte_order);
2476 dma_info_atomic_command_status
2477 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7 2478
31a0ae49 2479 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoDMA");
23d964e7 2480
31a0ae49 2481 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2482 {
31a0ae49 2483 ui_out_field_fmt (current_uiout, "dma_info_type", "0x%s",
23d964e7 2484 phex_nz (dma_info_type, 4));
31a0ae49 2485 ui_out_field_fmt (current_uiout, "dma_info_mask", "0x%s",
23d964e7 2486 phex_nz (dma_info_mask, 4));
31a0ae49 2487 ui_out_field_fmt (current_uiout, "dma_info_status", "0x%s",
23d964e7 2488 phex_nz (dma_info_status, 4));
31a0ae49 2489 ui_out_field_fmt (current_uiout, "dma_info_stall_and_notify", "0x%s",
23d964e7 2490 phex_nz (dma_info_stall_and_notify, 4));
31a0ae49 2491 ui_out_field_fmt (current_uiout, "dma_info_atomic_command_status", "0x%s",
23d964e7
UW		 2492 phex_nz (dma_info_atomic_command_status, 4));
2493 }
2494 else
2495 {
8fbde58b 2496 const char *query_msg = _("no query pending");
23d964e7 2497
8fbde58b
UW		 2498 if (dma_info_type & 4)
2499 switch (dma_info_type & 3)
2500 {
2501 case 1: query_msg = _("'any' query pending"); break;
2502 case 2: query_msg = _("'all' query pending"); break;
2503 default: query_msg = _("undefined query type"); break;
2504 }
23d964e7
UW		 2505
2506 printf_filtered (_("Tag-Group Status 0x%s\n"),
2507 phex (dma_info_status, 4));
2508 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2509 phex (dma_info_mask, 4), query_msg);
2510 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2511 phex (dma_info_stall_and_notify, 4));
2512 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2513 phex (dma_info_atomic_command_status, 4));
2514 printf_filtered ("\n");
2515 }
2516
e17a4113 2517 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2518 do_cleanups (chain);
2519}
2520
2521static void
2522info_spu_proxydma_command (char *args, int from_tty)
2523{
2524 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2525 struct gdbarch *gdbarch = get_frame_arch (frame);
2526 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2527 ULONGEST dma_info_type;
2528 ULONGEST dma_info_mask;
2529 ULONGEST dma_info_status;
2530 struct cleanup *chain;
2531 char annex[32];
2532 gdb_byte buf[1024];
2533 LONGEST len;
22e048c9 2534 int id;
23d964e7 2535
e17a4113 2536 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2537 error (_("\"info spu\" is only supported on the SPU architecture."));
2538
23d964e7
UW		 2539 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2540
2541 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2542 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2543 buf, 0, 24 + 8 * 32);
2544 if (len <= 0)
2545 error (_("Could not read proxydma_info."));
2546
e17a4113
UW		 2547 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2548 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2549 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7 2550
31a0ae49
JK		 2551 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout,
2552 "SPUInfoProxyDMA");
23d964e7 2553
31a0ae49 2554 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2555 {
31a0ae49 2556 ui_out_field_fmt (current_uiout, "proxydma_info_type", "0x%s",
23d964e7 2557 phex_nz (dma_info_type, 4));
31a0ae49 2558 ui_out_field_fmt (current_uiout, "proxydma_info_mask", "0x%s",
23d964e7 2559 phex_nz (dma_info_mask, 4));
31a0ae49 2560 ui_out_field_fmt (current_uiout, "proxydma_info_status", "0x%s",
23d964e7
UW		 2561 phex_nz (dma_info_status, 4));
2562 }
2563 else
2564 {
2565 const char *query_msg;
2566
8fbde58b 2567 switch (dma_info_type & 3)
23d964e7
UW		 2568 {
2569 case 0: query_msg = _("no query pending"); break;
2570 case 1: query_msg = _("'any' query pending"); break;
2571 case 2: query_msg = _("'all' query pending"); break;
2572 default: query_msg = _("undefined query type"); break;
2573 }
2574
2575 printf_filtered (_("Tag-Group Status 0x%s\n"),
2576 phex (dma_info_status, 4));
2577 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2578 phex (dma_info_mask, 4), query_msg);
2579 printf_filtered ("\n");
2580 }
2581
e17a4113 2582 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2583 do_cleanups (chain);
2584}
2585
2586static void
2587info_spu_command (char *args, int from_tty)
2588{
c378eb4e
MS		 2589 printf_unfiltered (_("\"info spu\" must be followed by "
2590 "the name of an SPU facility.\n"));
23d964e7
UW		 2591 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2592}
2593
2594
3285f3fe
UW		 2595/* Root of all "set spu "/"show spu " commands. */
2596
2597static void
2598show_spu_command (char *args, int from_tty)
2599{
2600 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2601}
2602
2603static void
2604set_spu_command (char *args, int from_tty)
2605{
2606 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2607}
2608
2609static void
2610show_spu_stop_on_load (struct ui_file *file, int from_tty,
2611 struct cmd_list_element *c, const char *value)
2612{
2613 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2614 value);
2615}
2616
ff1a52c6
UW		 2617static void
2618show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2619 struct cmd_list_element *c, const char *value)
2620{
2621 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2622 value);
2623}
2624
3285f3fe 2625
771b4502
UW		 2626/* Set up gdbarch struct. */
2627
2628static struct gdbarch *
2629spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2630{
2631 struct gdbarch *gdbarch;
794ac428 2632 struct gdbarch_tdep *tdep;
85e747d2
UW		 2633 int id = -1;
2634
2635 /* Which spufs ID was requested as address space? */
2636 if (info.tdep_info)
2637 id = *(int *)info.tdep_info;
2638 /* For objfile architectures of SPU solibs, decode the ID from the name.
2639 This assumes the filename convention employed by solib-spu.c. */
2640 else if (info.abfd)
2641 {
2642 char *name = strrchr (info.abfd->filename, '@');
2643 if (name)
2644 sscanf (name, "@0x%*x <%d>", &id);
2645 }
771b4502 2646
85e747d2
UW		 2647 /* Find a candidate among extant architectures. */
2648 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2649 arches != NULL;
2650 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2651 {
2652 tdep = gdbarch_tdep (arches->gdbarch);
2653 if (tdep && tdep->id == id)
2654 return arches->gdbarch;
2655 }
771b4502 2656
85e747d2 2657 /* None found, so create a new architecture. */
794ac428 2658 tdep = XCALLOC (1, struct gdbarch_tdep);
85e747d2 2659 tdep->id = id;
794ac428 2660 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2661
2662 /* Disassembler. */
85e747d2 2663 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2664
2665 /* Registers. */
2666 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2667 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2668 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2669 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2670 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2671 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2672 set_gdbarch_register_name (gdbarch, spu_register_name);
2673 set_gdbarch_register_type (gdbarch, spu_register_type);
2674 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2675 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2676 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2677 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2678
2679 /* Data types. */
2680 set_gdbarch_char_signed (gdbarch, 0);
2681 set_gdbarch_ptr_bit (gdbarch, 32);
2682 set_gdbarch_addr_bit (gdbarch, 32);
2683 set_gdbarch_short_bit (gdbarch, 16);
2684 set_gdbarch_int_bit (gdbarch, 32);
2685 set_gdbarch_long_bit (gdbarch, 32);
2686 set_gdbarch_long_long_bit (gdbarch, 64);
2687 set_gdbarch_float_bit (gdbarch, 32);
2688 set_gdbarch_double_bit (gdbarch, 64);
2689 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2690 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2691 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2692 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2693
ff1a52c6 2694 /* Address handling. */
85e747d2 2695 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2696 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2697 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2698 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2699 set_gdbarch_address_class_type_flags_to_name
2700 (gdbarch, spu_address_class_type_flags_to_name);
2701 set_gdbarch_address_class_name_to_type_flags
2702 (gdbarch, spu_address_class_name_to_type_flags);
2703
36acd84e 2704
771b4502 2705 /* Inferior function calls. */
7b3dc0b7
UW		 2706 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2707 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2708 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2709 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2710 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2711 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2712 set_gdbarch_return_value (gdbarch, spu_return_value);
2713
2714 /* Frame handling. */
2715 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2716 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2717 frame_base_set_default (gdbarch, &spu_frame_base);
2718 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2719 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2720 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2721 set_gdbarch_frame_args_skip (gdbarch, 0);
2722 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2723 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502 2724
cc5f0d61
UW		 2725 /* Cell/B.E. cross-architecture unwinder support. */
2726 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2727
771b4502
UW		 2728 /* Breakpoints. */
2729 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2730 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
d03285ec 2731 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
771b4502
UW		 2732 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2733 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2734 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2735
dcf52cd8
UW		 2736 /* Overlays. */
2737 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2738
771b4502
UW		 2739 return gdbarch;
2740}
2741
63807e1d
PA		 2742/* Provide a prototype to silence -Wmissing-prototypes. */
2743extern initialize_file_ftype _initialize_spu_tdep;
2744
771b4502
UW		 2745void
2746_initialize_spu_tdep (void)
2747{
2748 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2749
dcf52cd8
UW		 2750 /* Add ourselves to objfile event chain. */
2751 observer_attach_new_objfile (spu_overlay_new_objfile);
2752 spu_overlay_data = register_objfile_data ();
23d964e7 2753
3285f3fe
UW		 2754 /* Install spu stop-on-load handler. */
2755 observer_attach_new_objfile (spu_catch_start);
2756
ff1a52c6
UW		 2757 /* Add ourselves to normal_stop event chain. */
2758 observer_attach_normal_stop (spu_attach_normal_stop);
2759
3285f3fe
UW		 2760 /* Add root prefix command for all "set spu"/"show spu" commands. */
2761 add_prefix_cmd ("spu", no_class, set_spu_command,
2762 _("Various SPU specific commands."),
2763 &setspucmdlist, "set spu ", 0, &setlist);
2764 add_prefix_cmd ("spu", no_class, show_spu_command,
2765 _("Various SPU specific commands."),
2766 &showspucmdlist, "show spu ", 0, &showlist);
2767
2768 /* Toggle whether or not to add a temporary breakpoint at the "main"
2769 function of new SPE contexts. */
2770 add_setshow_boolean_cmd ("stop-on-load", class_support,
2771 &spu_stop_on_load_p, _("\
2772Set whether to stop for new SPE threads."),
2773 _("\
2774Show whether to stop for new SPE threads."),
2775 _("\
2776Use \"on\" to give control to the user when a new SPE thread\n\
2777enters its \"main\" function.\n\
2778Use \"off\" to disable stopping for new SPE threads."),
2779 NULL,
2780 show_spu_stop_on_load,
2781 &setspucmdlist, &showspucmdlist);
2782
ff1a52c6
UW		 2783 /* Toggle whether or not to automatically flush the software-managed
2784 cache whenever SPE execution stops. */
2785 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2786 &spu_auto_flush_cache_p, _("\
2787Set whether to automatically flush the software-managed cache."),
2788 _("\
2789Show whether to automatically flush the software-managed cache."),
2790 _("\
2791Use \"on\" to automatically flush the software-managed cache\n\
2792whenever SPE execution stops.\n\
2793Use \"off\" to never automatically flush the software-managed cache."),
2794 NULL,
2795 show_spu_auto_flush_cache,
2796 &setspucmdlist, &showspucmdlist);
2797
23d964e7
UW		 2798 /* Add root prefix command for all "info spu" commands. */
2799 add_prefix_cmd ("spu", class_info, info_spu_command,
2800 _("Various SPU specific commands."),
2801 &infospucmdlist, "info spu ", 0, &infolist);
2802
2803 /* Add various "info spu" commands. */
2804 add_cmd ("event", class_info, info_spu_event_command,
2805 _("Display SPU event facility status.\n"),
2806 &infospucmdlist);
2807 add_cmd ("signal", class_info, info_spu_signal_command,
2808 _("Display SPU signal notification facility status.\n"),
2809 &infospucmdlist);
2810 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2811 _("Display SPU mailbox facility status.\n"),
2812 &infospucmdlist);
2813 add_cmd ("dma", class_info, info_spu_dma_command,
2814 _("Display MFC DMA status.\n"),
2815 &infospucmdlist);
2816 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2817 _("Display MFC Proxy-DMA status.\n"),
2818 &infospucmdlist);
771b4502 2819}
GDB Binutils - Deliverables
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