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771b4502 | 1 | /* SPU target-dependent code for GDB, the GNU debugger. |
0fb0cc75 | 2 | Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
771b4502 UW |
3 | |
4 | Contributed by Ulrich Weigand <uweigand@de.ibm.com>. | |
5 | Based on a port by Sid Manning <sid@us.ibm.com>. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
771b4502 UW |
12 | (at your option) any later version. |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
771b4502 UW |
21 | |
22 | #include "defs.h" | |
23 | #include "arch-utils.h" | |
24 | #include "gdbtypes.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
27 | #include "gdb_string.h" | |
28 | #include "gdb_assert.h" | |
29 | #include "frame.h" | |
30 | #include "frame-unwind.h" | |
31 | #include "frame-base.h" | |
32 | #include "trad-frame.h" | |
33 | #include "symtab.h" | |
34 | #include "symfile.h" | |
35 | #include "value.h" | |
36 | #include "inferior.h" | |
37 | #include "dis-asm.h" | |
38 | #include "objfiles.h" | |
39 | #include "language.h" | |
40 | #include "regcache.h" | |
41 | #include "reggroups.h" | |
42 | #include "floatformat.h" | |
3285f3fe | 43 | #include "block.h" |
dcf52cd8 | 44 | #include "observer.h" |
771b4502 UW |
45 | |
46 | #include "spu-tdep.h" | |
47 | ||
794ac428 | 48 | |
3285f3fe UW |
49 | /* The list of available "set spu " and "show spu " commands. */ |
50 | static struct cmd_list_element *setspucmdlist = NULL; | |
51 | static struct cmd_list_element *showspucmdlist = NULL; | |
52 | ||
53 | /* Whether to stop for new SPE contexts. */ | |
54 | static int spu_stop_on_load_p = 0; | |
55 | ||
56 | ||
794ac428 UW |
57 | /* The tdep structure. */ |
58 | struct gdbarch_tdep | |
59 | { | |
85e747d2 UW |
60 | /* The spufs ID identifying our address space. */ |
61 | int id; | |
62 | ||
794ac428 UW |
63 | /* SPU-specific vector type. */ |
64 | struct type *spu_builtin_type_vec128; | |
65 | }; | |
66 | ||
67 | ||
f2d43c2c | 68 | /* SPU-specific vector type. */ |
794ac428 UW |
69 | static struct type * |
70 | spu_builtin_type_vec128 (struct gdbarch *gdbarch) | |
71 | { | |
72 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
73 | ||
74 | if (!tdep->spu_builtin_type_vec128) | |
75 | { | |
df4df182 | 76 | const struct builtin_type *bt = builtin_type (gdbarch); |
794ac428 UW |
77 | struct type *t; |
78 | ||
e9bb382b UW |
79 | t = arch_composite_type (gdbarch, |
80 | "__spu_builtin_type_vec128", TYPE_CODE_UNION); | |
df4df182 | 81 | append_composite_type_field (t, "uint128", bt->builtin_int128); |
794ac428 | 82 | append_composite_type_field (t, "v2_int64", |
df4df182 | 83 | init_vector_type (bt->builtin_int64, 2)); |
794ac428 | 84 | append_composite_type_field (t, "v4_int32", |
df4df182 | 85 | init_vector_type (bt->builtin_int32, 4)); |
794ac428 | 86 | append_composite_type_field (t, "v8_int16", |
df4df182 | 87 | init_vector_type (bt->builtin_int16, 8)); |
794ac428 | 88 | append_composite_type_field (t, "v16_int8", |
df4df182 | 89 | init_vector_type (bt->builtin_int8, 16)); |
794ac428 | 90 | append_composite_type_field (t, "v2_double", |
df4df182 | 91 | init_vector_type (bt->builtin_double, 2)); |
794ac428 | 92 | append_composite_type_field (t, "v4_float", |
df4df182 | 93 | init_vector_type (bt->builtin_float, 4)); |
794ac428 | 94 | |
876cecd0 | 95 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
96 | TYPE_NAME (t) = "spu_builtin_type_vec128"; |
97 | ||
98 | tdep->spu_builtin_type_vec128 = t; | |
99 | } | |
100 | ||
101 | return tdep->spu_builtin_type_vec128; | |
102 | } | |
103 | ||
771b4502 | 104 | |
23d964e7 UW |
105 | /* The list of available "info spu " commands. */ |
106 | static struct cmd_list_element *infospucmdlist = NULL; | |
107 | ||
771b4502 UW |
108 | /* Registers. */ |
109 | ||
110 | static const char * | |
d93859e2 | 111 | spu_register_name (struct gdbarch *gdbarch, int reg_nr) |
771b4502 UW |
112 | { |
113 | static char *register_names[] = | |
114 | { | |
115 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
116 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
117 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
118 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
119 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
120 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
121 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
122 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
123 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
124 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
125 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
126 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
127 | "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", | |
128 | "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", | |
129 | "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", | |
130 | "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", | |
23d964e7 | 131 | "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status" |
771b4502 UW |
132 | }; |
133 | ||
134 | if (reg_nr < 0) | |
135 | return NULL; | |
136 | if (reg_nr >= sizeof register_names / sizeof *register_names) | |
137 | return NULL; | |
138 | ||
139 | return register_names[reg_nr]; | |
140 | } | |
141 | ||
142 | static struct type * | |
143 | spu_register_type (struct gdbarch *gdbarch, int reg_nr) | |
144 | { | |
145 | if (reg_nr < SPU_NUM_GPRS) | |
794ac428 | 146 | return spu_builtin_type_vec128 (gdbarch); |
771b4502 UW |
147 | |
148 | switch (reg_nr) | |
149 | { | |
150 | case SPU_ID_REGNUM: | |
df4df182 | 151 | return builtin_type (gdbarch)->builtin_uint32; |
771b4502 UW |
152 | |
153 | case SPU_PC_REGNUM: | |
0dfff4cb | 154 | return builtin_type (gdbarch)->builtin_func_ptr; |
771b4502 UW |
155 | |
156 | case SPU_SP_REGNUM: | |
0dfff4cb | 157 | return builtin_type (gdbarch)->builtin_data_ptr; |
771b4502 | 158 | |
23d964e7 | 159 | case SPU_FPSCR_REGNUM: |
df4df182 | 160 | return builtin_type (gdbarch)->builtin_uint128; |
23d964e7 UW |
161 | |
162 | case SPU_SRR0_REGNUM: | |
df4df182 | 163 | return builtin_type (gdbarch)->builtin_uint32; |
23d964e7 UW |
164 | |
165 | case SPU_LSLR_REGNUM: | |
df4df182 | 166 | return builtin_type (gdbarch)->builtin_uint32; |
23d964e7 UW |
167 | |
168 | case SPU_DECR_REGNUM: | |
df4df182 | 169 | return builtin_type (gdbarch)->builtin_uint32; |
23d964e7 UW |
170 | |
171 | case SPU_DECR_STATUS_REGNUM: | |
df4df182 | 172 | return builtin_type (gdbarch)->builtin_uint32; |
23d964e7 | 173 | |
771b4502 UW |
174 | default: |
175 | internal_error (__FILE__, __LINE__, "invalid regnum"); | |
176 | } | |
177 | } | |
178 | ||
179 | /* Pseudo registers for preferred slots - stack pointer. */ | |
180 | ||
23d964e7 UW |
181 | static void |
182 | spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname, | |
183 | gdb_byte *buf) | |
184 | { | |
e17a4113 UW |
185 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
186 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
23d964e7 UW |
187 | gdb_byte reg[32]; |
188 | char annex[32]; | |
189 | ULONGEST id; | |
190 | ||
191 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); | |
192 | xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname); | |
193 | memset (reg, 0, sizeof reg); | |
194 | target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
195 | reg, 0, sizeof reg); | |
196 | ||
e17a4113 | 197 | store_unsigned_integer (buf, 4, byte_order, strtoulst (reg, NULL, 16)); |
23d964e7 UW |
198 | } |
199 | ||
771b4502 UW |
200 | static void |
201 | spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
202 | int regnum, gdb_byte *buf) | |
203 | { | |
204 | gdb_byte reg[16]; | |
23d964e7 UW |
205 | char annex[32]; |
206 | ULONGEST id; | |
771b4502 UW |
207 | |
208 | switch (regnum) | |
209 | { | |
210 | case SPU_SP_REGNUM: | |
211 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); | |
212 | memcpy (buf, reg, 4); | |
213 | break; | |
214 | ||
23d964e7 UW |
215 | case SPU_FPSCR_REGNUM: |
216 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); | |
217 | xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id); | |
218 | target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16); | |
219 | break; | |
220 | ||
221 | case SPU_SRR0_REGNUM: | |
222 | spu_pseudo_register_read_spu (regcache, "srr0", buf); | |
223 | break; | |
224 | ||
225 | case SPU_LSLR_REGNUM: | |
226 | spu_pseudo_register_read_spu (regcache, "lslr", buf); | |
227 | break; | |
228 | ||
229 | case SPU_DECR_REGNUM: | |
230 | spu_pseudo_register_read_spu (regcache, "decr", buf); | |
231 | break; | |
232 | ||
233 | case SPU_DECR_STATUS_REGNUM: | |
234 | spu_pseudo_register_read_spu (regcache, "decr_status", buf); | |
235 | break; | |
236 | ||
771b4502 UW |
237 | default: |
238 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
239 | } | |
240 | } | |
241 | ||
23d964e7 UW |
242 | static void |
243 | spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname, | |
244 | const gdb_byte *buf) | |
245 | { | |
e17a4113 UW |
246 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
247 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
23d964e7 UW |
248 | gdb_byte reg[32]; |
249 | char annex[32]; | |
250 | ULONGEST id; | |
251 | ||
252 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); | |
253 | xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname); | |
254 | xsnprintf (reg, sizeof reg, "0x%s", | |
e17a4113 | 255 | phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4)); |
23d964e7 UW |
256 | target_write (¤t_target, TARGET_OBJECT_SPU, annex, |
257 | reg, 0, strlen (reg)); | |
258 | } | |
259 | ||
771b4502 UW |
260 | static void |
261 | spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
262 | int regnum, const gdb_byte *buf) | |
263 | { | |
264 | gdb_byte reg[16]; | |
23d964e7 UW |
265 | char annex[32]; |
266 | ULONGEST id; | |
771b4502 UW |
267 | |
268 | switch (regnum) | |
269 | { | |
270 | case SPU_SP_REGNUM: | |
271 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); | |
272 | memcpy (reg, buf, 4); | |
273 | regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg); | |
274 | break; | |
275 | ||
23d964e7 UW |
276 | case SPU_FPSCR_REGNUM: |
277 | regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id); | |
278 | xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id); | |
279 | target_write (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16); | |
280 | break; | |
281 | ||
282 | case SPU_SRR0_REGNUM: | |
283 | spu_pseudo_register_write_spu (regcache, "srr0", buf); | |
284 | break; | |
285 | ||
286 | case SPU_LSLR_REGNUM: | |
287 | spu_pseudo_register_write_spu (regcache, "lslr", buf); | |
288 | break; | |
289 | ||
290 | case SPU_DECR_REGNUM: | |
291 | spu_pseudo_register_write_spu (regcache, "decr", buf); | |
292 | break; | |
293 | ||
294 | case SPU_DECR_STATUS_REGNUM: | |
295 | spu_pseudo_register_write_spu (regcache, "decr_status", buf); | |
296 | break; | |
297 | ||
771b4502 UW |
298 | default: |
299 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
300 | } | |
301 | } | |
302 | ||
303 | /* Value conversion -- access scalar values at the preferred slot. */ | |
304 | ||
9acbedc0 UW |
305 | static struct value * |
306 | spu_value_from_register (struct type *type, int regnum, | |
307 | struct frame_info *frame) | |
771b4502 | 308 | { |
9acbedc0 UW |
309 | struct value *value = default_value_from_register (type, regnum, frame); |
310 | int len = TYPE_LENGTH (type); | |
771b4502 | 311 | |
9acbedc0 UW |
312 | if (regnum < SPU_NUM_GPRS && len < 16) |
313 | { | |
314 | int preferred_slot = len < 4 ? 4 - len : 0; | |
315 | set_value_offset (value, preferred_slot); | |
316 | } | |
771b4502 | 317 | |
9acbedc0 | 318 | return value; |
771b4502 UW |
319 | } |
320 | ||
321 | /* Register groups. */ | |
322 | ||
323 | static int | |
324 | spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
325 | struct reggroup *group) | |
326 | { | |
327 | /* Registers displayed via 'info regs'. */ | |
328 | if (group == general_reggroup) | |
329 | return 1; | |
330 | ||
331 | /* Registers displayed via 'info float'. */ | |
332 | if (group == float_reggroup) | |
333 | return 0; | |
334 | ||
335 | /* Registers that need to be saved/restored in order to | |
336 | push or pop frames. */ | |
337 | if (group == save_reggroup || group == restore_reggroup) | |
338 | return 1; | |
339 | ||
340 | return default_register_reggroup_p (gdbarch, regnum, group); | |
341 | } | |
342 | ||
36acd84e UW |
343 | /* Address conversion. */ |
344 | ||
85e747d2 UW |
345 | static int |
346 | spu_gdbarch_id (struct gdbarch *gdbarch) | |
347 | { | |
348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
349 | int id = tdep->id; | |
350 | ||
351 | /* The objfile architecture of a standalone SPU executable does not | |
352 | provide an SPU ID. Retrieve it from the the objfile's relocated | |
353 | address range in this special case. */ | |
354 | if (id == -1 | |
355 | && symfile_objfile && symfile_objfile->obfd | |
356 | && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu | |
357 | && symfile_objfile->sections != symfile_objfile->sections_end) | |
358 | id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections)); | |
359 | ||
360 | return id; | |
361 | } | |
362 | ||
363 | static ULONGEST | |
364 | spu_lslr (int id) | |
365 | { | |
366 | gdb_byte buf[32]; | |
367 | char annex[32]; | |
368 | ||
369 | if (id == -1) | |
370 | return SPU_LS_SIZE - 1; | |
371 | ||
372 | xsnprintf (annex, sizeof annex, "%d/lslr", id); | |
373 | memset (buf, 0, sizeof buf); | |
374 | target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
375 | buf, 0, sizeof buf); | |
376 | ||
377 | return strtoulst (buf, NULL, 16); | |
378 | } | |
379 | ||
380 | static void | |
381 | spu_address_to_pointer (struct gdbarch *gdbarch, | |
382 | struct type *type, gdb_byte *buf, CORE_ADDR addr) | |
383 | { | |
384 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
385 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, | |
386 | SPUADDR_ADDR (addr)); | |
387 | } | |
388 | ||
36acd84e | 389 | static CORE_ADDR |
9898f801 UW |
390 | spu_pointer_to_address (struct gdbarch *gdbarch, |
391 | struct type *type, const gdb_byte *buf) | |
36acd84e | 392 | { |
85e747d2 UW |
393 | int id = spu_gdbarch_id (gdbarch); |
394 | ULONGEST lslr = spu_lslr (id); | |
e17a4113 UW |
395 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
396 | ULONGEST addr | |
397 | = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); | |
36acd84e | 398 | |
85e747d2 | 399 | return addr? SPUADDR (id, addr & lslr) : 0; |
36acd84e UW |
400 | } |
401 | ||
402 | static CORE_ADDR | |
403 | spu_integer_to_address (struct gdbarch *gdbarch, | |
404 | struct type *type, const gdb_byte *buf) | |
405 | { | |
85e747d2 UW |
406 | int id = spu_gdbarch_id (gdbarch); |
407 | ULONGEST lslr = spu_lslr (id); | |
36acd84e | 408 | ULONGEST addr = unpack_long (type, buf); |
36acd84e | 409 | |
85e747d2 | 410 | return SPUADDR (id, addr & lslr); |
36acd84e UW |
411 | } |
412 | ||
771b4502 UW |
413 | |
414 | /* Decoding SPU instructions. */ | |
415 | ||
416 | enum | |
417 | { | |
418 | op_lqd = 0x34, | |
419 | op_lqx = 0x3c4, | |
420 | op_lqa = 0x61, | |
421 | op_lqr = 0x67, | |
422 | op_stqd = 0x24, | |
423 | op_stqx = 0x144, | |
424 | op_stqa = 0x41, | |
425 | op_stqr = 0x47, | |
426 | ||
427 | op_il = 0x081, | |
428 | op_ila = 0x21, | |
429 | op_a = 0x0c0, | |
430 | op_ai = 0x1c, | |
431 | ||
432 | op_selb = 0x4, | |
433 | ||
434 | op_br = 0x64, | |
435 | op_bra = 0x60, | |
436 | op_brsl = 0x66, | |
437 | op_brasl = 0x62, | |
438 | op_brnz = 0x42, | |
439 | op_brz = 0x40, | |
440 | op_brhnz = 0x46, | |
441 | op_brhz = 0x44, | |
442 | op_bi = 0x1a8, | |
443 | op_bisl = 0x1a9, | |
444 | op_biz = 0x128, | |
445 | op_binz = 0x129, | |
446 | op_bihz = 0x12a, | |
447 | op_bihnz = 0x12b, | |
448 | }; | |
449 | ||
450 | static int | |
451 | is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb) | |
452 | { | |
453 | if ((insn >> 21) == op) | |
454 | { | |
455 | *rt = insn & 127; | |
456 | *ra = (insn >> 7) & 127; | |
457 | *rb = (insn >> 14) & 127; | |
458 | return 1; | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static int | |
465 | is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc) | |
466 | { | |
467 | if ((insn >> 28) == op) | |
468 | { | |
469 | *rt = (insn >> 21) & 127; | |
470 | *ra = (insn >> 7) & 127; | |
471 | *rb = (insn >> 14) & 127; | |
472 | *rc = insn & 127; | |
473 | return 1; | |
474 | } | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static int | |
480 | is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7) | |
481 | { | |
482 | if ((insn >> 21) == op) | |
483 | { | |
484 | *rt = insn & 127; | |
485 | *ra = (insn >> 7) & 127; | |
486 | *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40; | |
487 | return 1; | |
488 | } | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static int | |
494 | is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10) | |
495 | { | |
496 | if ((insn >> 24) == op) | |
497 | { | |
498 | *rt = insn & 127; | |
499 | *ra = (insn >> 7) & 127; | |
500 | *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200; | |
501 | return 1; | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | static int | |
508 | is_ri16 (unsigned int insn, int op, int *rt, int *i16) | |
509 | { | |
510 | if ((insn >> 23) == op) | |
511 | { | |
512 | *rt = insn & 127; | |
513 | *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000; | |
514 | return 1; | |
515 | } | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static int | |
521 | is_ri18 (unsigned int insn, int op, int *rt, int *i18) | |
522 | { | |
523 | if ((insn >> 25) == op) | |
524 | { | |
525 | *rt = insn & 127; | |
526 | *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000; | |
527 | return 1; | |
528 | } | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
533 | static int | |
534 | is_branch (unsigned int insn, int *offset, int *reg) | |
535 | { | |
536 | int rt, i7, i16; | |
537 | ||
538 | if (is_ri16 (insn, op_br, &rt, &i16) | |
539 | || is_ri16 (insn, op_brsl, &rt, &i16) | |
540 | || is_ri16 (insn, op_brnz, &rt, &i16) | |
541 | || is_ri16 (insn, op_brz, &rt, &i16) | |
542 | || is_ri16 (insn, op_brhnz, &rt, &i16) | |
543 | || is_ri16 (insn, op_brhz, &rt, &i16)) | |
544 | { | |
545 | *reg = SPU_PC_REGNUM; | |
546 | *offset = i16 << 2; | |
547 | return 1; | |
548 | } | |
549 | ||
550 | if (is_ri16 (insn, op_bra, &rt, &i16) | |
551 | || is_ri16 (insn, op_brasl, &rt, &i16)) | |
552 | { | |
553 | *reg = -1; | |
554 | *offset = i16 << 2; | |
555 | return 1; | |
556 | } | |
557 | ||
558 | if (is_ri7 (insn, op_bi, &rt, reg, &i7) | |
559 | || is_ri7 (insn, op_bisl, &rt, reg, &i7) | |
560 | || is_ri7 (insn, op_biz, &rt, reg, &i7) | |
561 | || is_ri7 (insn, op_binz, &rt, reg, &i7) | |
562 | || is_ri7 (insn, op_bihz, &rt, reg, &i7) | |
563 | || is_ri7 (insn, op_bihnz, &rt, reg, &i7)) | |
564 | { | |
565 | *offset = 0; | |
566 | return 1; | |
567 | } | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | ||
573 | /* Prolog parsing. */ | |
574 | ||
575 | struct spu_prologue_data | |
576 | { | |
577 | /* Stack frame size. -1 if analysis was unsuccessful. */ | |
578 | int size; | |
579 | ||
580 | /* How to find the CFA. The CFA is equal to SP at function entry. */ | |
581 | int cfa_reg; | |
582 | int cfa_offset; | |
583 | ||
584 | /* Offset relative to CFA where a register is saved. -1 if invalid. */ | |
585 | int reg_offset[SPU_NUM_GPRS]; | |
586 | }; | |
587 | ||
588 | static CORE_ADDR | |
e17a4113 UW |
589 | spu_analyze_prologue (struct gdbarch *gdbarch, |
590 | CORE_ADDR start_pc, CORE_ADDR end_pc, | |
771b4502 UW |
591 | struct spu_prologue_data *data) |
592 | { | |
e17a4113 | 593 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
771b4502 UW |
594 | int found_sp = 0; |
595 | int found_fp = 0; | |
596 | int found_lr = 0; | |
597 | int reg_immed[SPU_NUM_GPRS]; | |
598 | gdb_byte buf[16]; | |
599 | CORE_ADDR prolog_pc = start_pc; | |
600 | CORE_ADDR pc; | |
601 | int i; | |
602 | ||
603 | ||
604 | /* Initialize DATA to default values. */ | |
605 | data->size = -1; | |
606 | ||
607 | data->cfa_reg = SPU_RAW_SP_REGNUM; | |
608 | data->cfa_offset = 0; | |
609 | ||
610 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
611 | data->reg_offset[i] = -1; | |
612 | ||
613 | /* Set up REG_IMMED array. This is non-zero for a register if we know its | |
614 | preferred slot currently holds this immediate value. */ | |
615 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
616 | reg_immed[i] = 0; | |
617 | ||
618 | /* Scan instructions until the first branch. | |
619 | ||
620 | The following instructions are important prolog components: | |
621 | ||
622 | - The first instruction to set up the stack pointer. | |
623 | - The first instruction to set up the frame pointer. | |
624 | - The first instruction to save the link register. | |
625 | ||
626 | We return the instruction after the latest of these three, | |
627 | or the incoming PC if none is found. The first instruction | |
628 | to set up the stack pointer also defines the frame size. | |
629 | ||
630 | Note that instructions saving incoming arguments to their stack | |
631 | slots are not counted as important, because they are hard to | |
632 | identify with certainty. This should not matter much, because | |
633 | arguments are relevant only in code compiled with debug data, | |
634 | and in such code the GDB core will advance until the first source | |
635 | line anyway, using SAL data. | |
636 | ||
637 | For purposes of stack unwinding, we analyze the following types | |
638 | of instructions in addition: | |
639 | ||
640 | - Any instruction adding to the current frame pointer. | |
641 | - Any instruction loading an immediate constant into a register. | |
642 | - Any instruction storing a register onto the stack. | |
643 | ||
644 | These are used to compute the CFA and REG_OFFSET output. */ | |
645 | ||
646 | for (pc = start_pc; pc < end_pc; pc += 4) | |
647 | { | |
648 | unsigned int insn; | |
649 | int rt, ra, rb, rc, immed; | |
650 | ||
651 | if (target_read_memory (pc, buf, 4)) | |
652 | break; | |
e17a4113 | 653 | insn = extract_unsigned_integer (buf, 4, byte_order); |
771b4502 UW |
654 | |
655 | /* AI is the typical instruction to set up a stack frame. | |
656 | It is also used to initialize the frame pointer. */ | |
657 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed)) | |
658 | { | |
659 | if (rt == data->cfa_reg && ra == data->cfa_reg) | |
660 | data->cfa_offset -= immed; | |
661 | ||
662 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
663 | && !found_sp) | |
664 | { | |
665 | found_sp = 1; | |
666 | prolog_pc = pc + 4; | |
667 | ||
668 | data->size = -immed; | |
669 | } | |
670 | else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
671 | && !found_fp) | |
672 | { | |
673 | found_fp = 1; | |
674 | prolog_pc = pc + 4; | |
675 | ||
676 | data->cfa_reg = SPU_FP_REGNUM; | |
677 | data->cfa_offset -= immed; | |
678 | } | |
679 | } | |
680 | ||
681 | /* A is used to set up stack frames of size >= 512 bytes. | |
682 | If we have tracked the contents of the addend register, | |
683 | we can handle this as well. */ | |
684 | else if (is_rr (insn, op_a, &rt, &ra, &rb)) | |
685 | { | |
686 | if (rt == data->cfa_reg && ra == data->cfa_reg) | |
687 | { | |
688 | if (reg_immed[rb] != 0) | |
689 | data->cfa_offset -= reg_immed[rb]; | |
690 | else | |
691 | data->cfa_reg = -1; /* We don't know the CFA any more. */ | |
692 | } | |
693 | ||
694 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
695 | && !found_sp) | |
696 | { | |
697 | found_sp = 1; | |
698 | prolog_pc = pc + 4; | |
699 | ||
700 | if (reg_immed[rb] != 0) | |
701 | data->size = -reg_immed[rb]; | |
702 | } | |
703 | } | |
704 | ||
705 | /* We need to track IL and ILA used to load immediate constants | |
706 | in case they are later used as input to an A instruction. */ | |
707 | else if (is_ri16 (insn, op_il, &rt, &immed)) | |
708 | { | |
709 | reg_immed[rt] = immed; | |
12102450 UW |
710 | |
711 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) | |
712 | found_sp = 1; | |
771b4502 UW |
713 | } |
714 | ||
715 | else if (is_ri18 (insn, op_ila, &rt, &immed)) | |
716 | { | |
717 | reg_immed[rt] = immed & 0x3ffff; | |
12102450 UW |
718 | |
719 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) | |
720 | found_sp = 1; | |
771b4502 UW |
721 | } |
722 | ||
723 | /* STQD is used to save registers to the stack. */ | |
724 | else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed)) | |
725 | { | |
726 | if (ra == data->cfa_reg) | |
727 | data->reg_offset[rt] = data->cfa_offset - (immed << 4); | |
728 | ||
729 | if (ra == data->cfa_reg && rt == SPU_LR_REGNUM | |
730 | && !found_lr) | |
731 | { | |
732 | found_lr = 1; | |
733 | prolog_pc = pc + 4; | |
734 | } | |
735 | } | |
736 | ||
737 | /* _start uses SELB to set up the stack pointer. */ | |
738 | else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc)) | |
739 | { | |
740 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) | |
741 | found_sp = 1; | |
742 | } | |
743 | ||
744 | /* We terminate if we find a branch. */ | |
745 | else if (is_branch (insn, &immed, &ra)) | |
746 | break; | |
747 | } | |
748 | ||
749 | ||
750 | /* If we successfully parsed until here, and didn't find any instruction | |
751 | modifying SP, we assume we have a frameless function. */ | |
752 | if (!found_sp) | |
753 | data->size = 0; | |
754 | ||
755 | /* Return cooked instead of raw SP. */ | |
756 | if (data->cfa_reg == SPU_RAW_SP_REGNUM) | |
757 | data->cfa_reg = SPU_SP_REGNUM; | |
758 | ||
759 | return prolog_pc; | |
760 | } | |
761 | ||
762 | /* Return the first instruction after the prologue starting at PC. */ | |
763 | static CORE_ADDR | |
6093d2eb | 764 | spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
771b4502 UW |
765 | { |
766 | struct spu_prologue_data data; | |
e17a4113 | 767 | return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data); |
771b4502 UW |
768 | } |
769 | ||
770 | /* Return the frame pointer in use at address PC. */ | |
771 | static void | |
a54fba4c MD |
772 | spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, |
773 | int *reg, LONGEST *offset) | |
771b4502 UW |
774 | { |
775 | struct spu_prologue_data data; | |
e17a4113 | 776 | spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data); |
771b4502 UW |
777 | |
778 | if (data.size != -1 && data.cfa_reg != -1) | |
779 | { | |
780 | /* The 'frame pointer' address is CFA minus frame size. */ | |
781 | *reg = data.cfa_reg; | |
782 | *offset = data.cfa_offset - data.size; | |
783 | } | |
784 | else | |
785 | { | |
786 | /* ??? We don't really know ... */ | |
787 | *reg = SPU_SP_REGNUM; | |
788 | *offset = 0; | |
789 | } | |
790 | } | |
791 | ||
fe5febed UW |
792 | /* Return true if we are in the function's epilogue, i.e. after the |
793 | instruction that destroyed the function's stack frame. | |
794 | ||
795 | 1) scan forward from the point of execution: | |
796 | a) If you find an instruction that modifies the stack pointer | |
797 | or transfers control (except a return), execution is not in | |
798 | an epilogue, return. | |
799 | b) Stop scanning if you find a return instruction or reach the | |
800 | end of the function or reach the hard limit for the size of | |
801 | an epilogue. | |
802 | 2) scan backward from the point of execution: | |
803 | a) If you find an instruction that modifies the stack pointer, | |
804 | execution *is* in an epilogue, return. | |
805 | b) Stop scanning if you reach an instruction that transfers | |
806 | control or the beginning of the function or reach the hard | |
807 | limit for the size of an epilogue. */ | |
808 | ||
809 | static int | |
810 | spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
811 | { | |
e17a4113 | 812 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
fe5febed UW |
813 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; |
814 | bfd_byte buf[4]; | |
815 | unsigned int insn; | |
816 | int rt, ra, rb, rc, immed; | |
817 | ||
818 | /* Find the search limits based on function boundaries and hard limit. | |
819 | We assume the epilogue can be up to 64 instructions long. */ | |
820 | ||
821 | const int spu_max_epilogue_size = 64 * 4; | |
822 | ||
823 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
824 | return 0; | |
825 | ||
826 | if (pc - func_start < spu_max_epilogue_size) | |
827 | epilogue_start = func_start; | |
828 | else | |
829 | epilogue_start = pc - spu_max_epilogue_size; | |
830 | ||
831 | if (func_end - pc < spu_max_epilogue_size) | |
832 | epilogue_end = func_end; | |
833 | else | |
834 | epilogue_end = pc + spu_max_epilogue_size; | |
835 | ||
836 | /* Scan forward until next 'bi $0'. */ | |
837 | ||
838 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4) | |
839 | { | |
840 | if (target_read_memory (scan_pc, buf, 4)) | |
841 | return 0; | |
e17a4113 | 842 | insn = extract_unsigned_integer (buf, 4, byte_order); |
fe5febed UW |
843 | |
844 | if (is_branch (insn, &immed, &ra)) | |
845 | { | |
846 | if (immed == 0 && ra == SPU_LR_REGNUM) | |
847 | break; | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
852 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed) | |
853 | || is_rr (insn, op_a, &rt, &ra, &rb) | |
854 | || is_ri10 (insn, op_lqd, &rt, &ra, &immed)) | |
855 | { | |
856 | if (rt == SPU_RAW_SP_REGNUM) | |
857 | return 0; | |
858 | } | |
859 | } | |
860 | ||
861 | if (scan_pc >= epilogue_end) | |
862 | return 0; | |
863 | ||
864 | /* Scan backward until adjustment to stack pointer (R1). */ | |
865 | ||
866 | for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4) | |
867 | { | |
868 | if (target_read_memory (scan_pc, buf, 4)) | |
869 | return 0; | |
e17a4113 | 870 | insn = extract_unsigned_integer (buf, 4, byte_order); |
fe5febed UW |
871 | |
872 | if (is_branch (insn, &immed, &ra)) | |
873 | return 0; | |
874 | ||
875 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed) | |
876 | || is_rr (insn, op_a, &rt, &ra, &rb) | |
877 | || is_ri10 (insn, op_lqd, &rt, &ra, &immed)) | |
878 | { | |
879 | if (rt == SPU_RAW_SP_REGNUM) | |
880 | return 1; | |
881 | } | |
882 | } | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
887 | ||
771b4502 UW |
888 | /* Normal stack frames. */ |
889 | ||
890 | struct spu_unwind_cache | |
891 | { | |
892 | CORE_ADDR func; | |
893 | CORE_ADDR frame_base; | |
894 | CORE_ADDR local_base; | |
895 | ||
896 | struct trad_frame_saved_reg *saved_regs; | |
897 | }; | |
898 | ||
899 | static struct spu_unwind_cache * | |
8d998b8f | 900 | spu_frame_unwind_cache (struct frame_info *this_frame, |
771b4502 UW |
901 | void **this_prologue_cache) |
902 | { | |
e17a4113 | 903 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
85e747d2 | 904 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 905 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
771b4502 UW |
906 | struct spu_unwind_cache *info; |
907 | struct spu_prologue_data data; | |
85e747d2 | 908 | CORE_ADDR id = tdep->id; |
dcf52cd8 | 909 | gdb_byte buf[16]; |
771b4502 UW |
910 | |
911 | if (*this_prologue_cache) | |
912 | return *this_prologue_cache; | |
913 | ||
914 | info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache); | |
915 | *this_prologue_cache = info; | |
8d998b8f | 916 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
771b4502 UW |
917 | info->frame_base = 0; |
918 | info->local_base = 0; | |
919 | ||
920 | /* Find the start of the current function, and analyze its prologue. */ | |
8d998b8f | 921 | info->func = get_frame_func (this_frame); |
771b4502 UW |
922 | if (info->func == 0) |
923 | { | |
924 | /* Fall back to using the current PC as frame ID. */ | |
8d998b8f | 925 | info->func = get_frame_pc (this_frame); |
771b4502 UW |
926 | data.size = -1; |
927 | } | |
928 | else | |
e17a4113 UW |
929 | spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame), |
930 | &data); | |
771b4502 UW |
931 | |
932 | /* If successful, use prologue analysis data. */ | |
933 | if (data.size != -1 && data.cfa_reg != -1) | |
934 | { | |
935 | CORE_ADDR cfa; | |
936 | int i; | |
771b4502 UW |
937 | |
938 | /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */ | |
8d998b8f | 939 | get_frame_register (this_frame, data.cfa_reg, buf); |
e17a4113 | 940 | cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset; |
85e747d2 | 941 | cfa = SPUADDR (id, cfa); |
771b4502 UW |
942 | |
943 | /* Call-saved register slots. */ | |
944 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
945 | if (i == SPU_LR_REGNUM | |
946 | || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM)) | |
947 | if (data.reg_offset[i] != -1) | |
948 | info->saved_regs[i].addr = cfa - data.reg_offset[i]; | |
949 | ||
771b4502 UW |
950 | /* Frame bases. */ |
951 | info->frame_base = cfa; | |
952 | info->local_base = cfa - data.size; | |
953 | } | |
954 | ||
955 | /* Otherwise, fall back to reading the backchain link. */ | |
956 | else | |
957 | { | |
cdc9523a UW |
958 | CORE_ADDR reg; |
959 | LONGEST backchain; | |
960 | int status; | |
771b4502 UW |
961 | |
962 | /* Get the backchain. */ | |
8d998b8f | 963 | reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM); |
85e747d2 UW |
964 | status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order, |
965 | &backchain); | |
771b4502 UW |
966 | |
967 | /* A zero backchain terminates the frame chain. Also, sanity | |
968 | check against the local store size limit. */ | |
cdc9523a | 969 | if (status && backchain > 0 && backchain < SPU_LS_SIZE) |
771b4502 UW |
970 | { |
971 | /* Assume the link register is saved into its slot. */ | |
972 | if (backchain + 16 < SPU_LS_SIZE) | |
85e747d2 | 973 | info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id, backchain + 16); |
771b4502 | 974 | |
771b4502 | 975 | /* Frame bases. */ |
85e747d2 UW |
976 | info->frame_base = SPUADDR (id, backchain); |
977 | info->local_base = SPUADDR (id, reg); | |
771b4502 UW |
978 | } |
979 | } | |
dcf52cd8 | 980 | |
c4891da7 UW |
981 | /* If we didn't find a frame, we cannot determine SP / return address. */ |
982 | if (info->frame_base == 0) | |
983 | return info; | |
984 | ||
dcf52cd8 | 985 | /* The previous SP is equal to the CFA. */ |
85e747d2 UW |
986 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, |
987 | SPUADDR_ADDR (info->frame_base)); | |
dcf52cd8 | 988 | |
0a44cb36 UW |
989 | /* Read full contents of the unwound link register in order to |
990 | be able to determine the return address. */ | |
dcf52cd8 UW |
991 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) |
992 | target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16); | |
993 | else | |
8d998b8f | 994 | get_frame_register (this_frame, SPU_LR_REGNUM, buf); |
dcf52cd8 | 995 | |
0a44cb36 UW |
996 | /* Normally, the return address is contained in the slot 0 of the |
997 | link register, and slots 1-3 are zero. For an overlay return, | |
998 | slot 0 contains the address of the overlay manager return stub, | |
999 | slot 1 contains the partition number of the overlay section to | |
1000 | be returned to, and slot 2 contains the return address within | |
1001 | that section. Return the latter address in that case. */ | |
e17a4113 | 1002 | if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0) |
dcf52cd8 | 1003 | trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM, |
e17a4113 | 1004 | extract_unsigned_integer (buf + 8, 4, byte_order)); |
dcf52cd8 UW |
1005 | else |
1006 | trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM, | |
e17a4113 | 1007 | extract_unsigned_integer (buf, 4, byte_order)); |
771b4502 UW |
1008 | |
1009 | return info; | |
1010 | } | |
1011 | ||
1012 | static void | |
8d998b8f | 1013 | spu_frame_this_id (struct frame_info *this_frame, |
771b4502 UW |
1014 | void **this_prologue_cache, struct frame_id *this_id) |
1015 | { | |
1016 | struct spu_unwind_cache *info = | |
8d998b8f | 1017 | spu_frame_unwind_cache (this_frame, this_prologue_cache); |
771b4502 UW |
1018 | |
1019 | if (info->frame_base == 0) | |
1020 | return; | |
1021 | ||
1022 | *this_id = frame_id_build (info->frame_base, info->func); | |
1023 | } | |
1024 | ||
8d998b8f UW |
1025 | static struct value * |
1026 | spu_frame_prev_register (struct frame_info *this_frame, | |
1027 | void **this_prologue_cache, int regnum) | |
771b4502 UW |
1028 | { |
1029 | struct spu_unwind_cache *info | |
8d998b8f | 1030 | = spu_frame_unwind_cache (this_frame, this_prologue_cache); |
771b4502 UW |
1031 | |
1032 | /* Special-case the stack pointer. */ | |
1033 | if (regnum == SPU_RAW_SP_REGNUM) | |
1034 | regnum = SPU_SP_REGNUM; | |
1035 | ||
8d998b8f | 1036 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
771b4502 UW |
1037 | } |
1038 | ||
1039 | static const struct frame_unwind spu_frame_unwind = { | |
1040 | NORMAL_FRAME, | |
1041 | spu_frame_this_id, | |
8d998b8f UW |
1042 | spu_frame_prev_register, |
1043 | NULL, | |
1044 | default_frame_sniffer | |
771b4502 UW |
1045 | }; |
1046 | ||
771b4502 | 1047 | static CORE_ADDR |
8d998b8f | 1048 | spu_frame_base_address (struct frame_info *this_frame, void **this_cache) |
771b4502 UW |
1049 | { |
1050 | struct spu_unwind_cache *info | |
8d998b8f | 1051 | = spu_frame_unwind_cache (this_frame, this_cache); |
771b4502 UW |
1052 | return info->local_base; |
1053 | } | |
1054 | ||
1055 | static const struct frame_base spu_frame_base = { | |
1056 | &spu_frame_unwind, | |
1057 | spu_frame_base_address, | |
1058 | spu_frame_base_address, | |
1059 | spu_frame_base_address | |
1060 | }; | |
1061 | ||
1062 | static CORE_ADDR | |
1063 | spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1064 | { | |
85e747d2 | 1065 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
118dfbaf UW |
1066 | CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM); |
1067 | /* Mask off interrupt enable bit. */ | |
85e747d2 | 1068 | return SPUADDR (tdep->id, pc & -4); |
771b4502 UW |
1069 | } |
1070 | ||
1071 | static CORE_ADDR | |
1072 | spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1073 | { | |
85e747d2 UW |
1074 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1075 | CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); | |
1076 | return SPUADDR (tdep->id, sp); | |
771b4502 UW |
1077 | } |
1078 | ||
118dfbaf | 1079 | static CORE_ADDR |
61a1198a | 1080 | spu_read_pc (struct regcache *regcache) |
118dfbaf | 1081 | { |
85e747d2 | 1082 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
61a1198a UW |
1083 | ULONGEST pc; |
1084 | regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc); | |
118dfbaf | 1085 | /* Mask off interrupt enable bit. */ |
85e747d2 | 1086 | return SPUADDR (tdep->id, pc & -4); |
118dfbaf UW |
1087 | } |
1088 | ||
1089 | static void | |
61a1198a | 1090 | spu_write_pc (struct regcache *regcache, CORE_ADDR pc) |
118dfbaf UW |
1091 | { |
1092 | /* Keep interrupt enabled state unchanged. */ | |
61a1198a UW |
1093 | ULONGEST old_pc; |
1094 | regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc); | |
1095 | regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM, | |
85e747d2 | 1096 | (SPUADDR_ADDR (pc) & -4) | (old_pc & 3)); |
118dfbaf UW |
1097 | } |
1098 | ||
771b4502 | 1099 | |
cc5f0d61 UW |
1100 | /* Cell/B.E. cross-architecture unwinder support. */ |
1101 | ||
1102 | struct spu2ppu_cache | |
1103 | { | |
1104 | struct frame_id frame_id; | |
1105 | struct regcache *regcache; | |
1106 | }; | |
1107 | ||
1108 | static struct gdbarch * | |
1109 | spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache) | |
1110 | { | |
1111 | struct spu2ppu_cache *cache = *this_cache; | |
1112 | return get_regcache_arch (cache->regcache); | |
1113 | } | |
1114 | ||
1115 | static void | |
1116 | spu2ppu_this_id (struct frame_info *this_frame, | |
1117 | void **this_cache, struct frame_id *this_id) | |
1118 | { | |
1119 | struct spu2ppu_cache *cache = *this_cache; | |
1120 | *this_id = cache->frame_id; | |
1121 | } | |
1122 | ||
1123 | static struct value * | |
1124 | spu2ppu_prev_register (struct frame_info *this_frame, | |
1125 | void **this_cache, int regnum) | |
1126 | { | |
1127 | struct spu2ppu_cache *cache = *this_cache; | |
1128 | struct gdbarch *gdbarch = get_regcache_arch (cache->regcache); | |
1129 | gdb_byte *buf; | |
1130 | ||
1131 | buf = alloca (register_size (gdbarch, regnum)); | |
1132 | regcache_cooked_read (cache->regcache, regnum, buf); | |
1133 | return frame_unwind_got_bytes (this_frame, regnum, buf); | |
1134 | } | |
1135 | ||
1136 | static int | |
1137 | spu2ppu_sniffer (const struct frame_unwind *self, | |
1138 | struct frame_info *this_frame, void **this_prologue_cache) | |
1139 | { | |
1140 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1141 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1142 | CORE_ADDR base, func, backchain; | |
1143 | gdb_byte buf[4]; | |
1144 | ||
1145 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_spu) | |
1146 | return 0; | |
1147 | ||
1148 | base = get_frame_sp (this_frame); | |
1149 | func = get_frame_pc (this_frame); | |
1150 | if (target_read_memory (base, buf, 4)) | |
1151 | return 0; | |
1152 | backchain = extract_unsigned_integer (buf, 4, byte_order); | |
1153 | ||
1154 | if (!backchain) | |
1155 | { | |
1156 | struct frame_info *fi; | |
1157 | ||
1158 | struct spu2ppu_cache *cache | |
1159 | = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache); | |
1160 | ||
1161 | cache->frame_id = frame_id_build (base + 16, func); | |
1162 | ||
1163 | for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi)) | |
1164 | if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu) | |
1165 | break; | |
1166 | ||
1167 | if (fi) | |
1168 | { | |
1169 | cache->regcache = frame_save_as_regcache (fi); | |
1170 | *this_prologue_cache = cache; | |
1171 | return 1; | |
1172 | } | |
1173 | else | |
1174 | { | |
1175 | struct regcache *regcache; | |
1176 | regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch); | |
1177 | cache->regcache = regcache_dup (regcache); | |
1178 | *this_prologue_cache = cache; | |
1179 | return 1; | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | static void | |
1187 | spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache) | |
1188 | { | |
1189 | struct spu2ppu_cache *cache = this_cache; | |
1190 | regcache_xfree (cache->regcache); | |
1191 | } | |
1192 | ||
1193 | static const struct frame_unwind spu2ppu_unwind = { | |
1194 | ARCH_FRAME, | |
1195 | spu2ppu_this_id, | |
1196 | spu2ppu_prev_register, | |
1197 | NULL, | |
1198 | spu2ppu_sniffer, | |
1199 | spu2ppu_dealloc_cache, | |
1200 | spu2ppu_prev_arch, | |
1201 | }; | |
1202 | ||
1203 | ||
771b4502 UW |
1204 | /* Function calling convention. */ |
1205 | ||
7b3dc0b7 UW |
1206 | static CORE_ADDR |
1207 | spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1208 | { | |
1209 | return sp & ~15; | |
1210 | } | |
1211 | ||
87805e63 UW |
1212 | static CORE_ADDR |
1213 | spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
1214 | struct value **args, int nargs, struct type *value_type, | |
1215 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
1216 | struct regcache *regcache) | |
1217 | { | |
1218 | /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */ | |
1219 | sp = (sp - 4) & ~15; | |
1220 | /* Store the address of that breakpoint */ | |
1221 | *bp_addr = sp; | |
1222 | /* The call starts at the callee's entry point. */ | |
1223 | *real_pc = funaddr; | |
1224 | ||
1225 | return sp; | |
1226 | } | |
1227 | ||
771b4502 UW |
1228 | static int |
1229 | spu_scalar_value_p (struct type *type) | |
1230 | { | |
1231 | switch (TYPE_CODE (type)) | |
1232 | { | |
1233 | case TYPE_CODE_INT: | |
1234 | case TYPE_CODE_ENUM: | |
1235 | case TYPE_CODE_RANGE: | |
1236 | case TYPE_CODE_CHAR: | |
1237 | case TYPE_CODE_BOOL: | |
1238 | case TYPE_CODE_PTR: | |
1239 | case TYPE_CODE_REF: | |
1240 | return TYPE_LENGTH (type) <= 16; | |
1241 | ||
1242 | default: | |
1243 | return 0; | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | static void | |
1248 | spu_value_to_regcache (struct regcache *regcache, int regnum, | |
1249 | struct type *type, const gdb_byte *in) | |
1250 | { | |
1251 | int len = TYPE_LENGTH (type); | |
1252 | ||
1253 | if (spu_scalar_value_p (type)) | |
1254 | { | |
1255 | int preferred_slot = len < 4 ? 4 - len : 0; | |
1256 | regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in); | |
1257 | } | |
1258 | else | |
1259 | { | |
1260 | while (len >= 16) | |
1261 | { | |
1262 | regcache_cooked_write (regcache, regnum++, in); | |
1263 | in += 16; | |
1264 | len -= 16; | |
1265 | } | |
1266 | ||
1267 | if (len > 0) | |
1268 | regcache_cooked_write_part (regcache, regnum, 0, len, in); | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | static void | |
1273 | spu_regcache_to_value (struct regcache *regcache, int regnum, | |
1274 | struct type *type, gdb_byte *out) | |
1275 | { | |
1276 | int len = TYPE_LENGTH (type); | |
1277 | ||
1278 | if (spu_scalar_value_p (type)) | |
1279 | { | |
1280 | int preferred_slot = len < 4 ? 4 - len : 0; | |
1281 | regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out); | |
1282 | } | |
1283 | else | |
1284 | { | |
1285 | while (len >= 16) | |
1286 | { | |
1287 | regcache_cooked_read (regcache, regnum++, out); | |
1288 | out += 16; | |
1289 | len -= 16; | |
1290 | } | |
1291 | ||
1292 | if (len > 0) | |
1293 | regcache_cooked_read_part (regcache, regnum, 0, len, out); | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | static CORE_ADDR | |
1298 | spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1299 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1300 | int nargs, struct value **args, CORE_ADDR sp, | |
1301 | int struct_return, CORE_ADDR struct_addr) | |
1302 | { | |
e17a4113 | 1303 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9ff3afda | 1304 | CORE_ADDR sp_delta; |
771b4502 UW |
1305 | int i; |
1306 | int regnum = SPU_ARG1_REGNUM; | |
1307 | int stack_arg = -1; | |
1308 | gdb_byte buf[16]; | |
1309 | ||
1310 | /* Set the return address. */ | |
1311 | memset (buf, 0, sizeof buf); | |
85e747d2 | 1312 | store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr)); |
771b4502 UW |
1313 | regcache_cooked_write (regcache, SPU_LR_REGNUM, buf); |
1314 | ||
1315 | /* If STRUCT_RETURN is true, then the struct return address (in | |
1316 | STRUCT_ADDR) will consume the first argument-passing register. | |
1317 | Both adjust the register count and store that value. */ | |
1318 | if (struct_return) | |
1319 | { | |
1320 | memset (buf, 0, sizeof buf); | |
85e747d2 | 1321 | store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr)); |
771b4502 UW |
1322 | regcache_cooked_write (regcache, regnum++, buf); |
1323 | } | |
1324 | ||
1325 | /* Fill in argument registers. */ | |
1326 | for (i = 0; i < nargs; i++) | |
1327 | { | |
1328 | struct value *arg = args[i]; | |
1329 | struct type *type = check_typedef (value_type (arg)); | |
1330 | const gdb_byte *contents = value_contents (arg); | |
1331 | int len = TYPE_LENGTH (type); | |
1332 | int n_regs = align_up (len, 16) / 16; | |
1333 | ||
1334 | /* If the argument doesn't wholly fit into registers, it and | |
1335 | all subsequent arguments go to the stack. */ | |
1336 | if (regnum + n_regs - 1 > SPU_ARGN_REGNUM) | |
1337 | { | |
1338 | stack_arg = i; | |
1339 | break; | |
1340 | } | |
1341 | ||
1342 | spu_value_to_regcache (regcache, regnum, type, contents); | |
1343 | regnum += n_regs; | |
1344 | } | |
1345 | ||
1346 | /* Overflow arguments go to the stack. */ | |
1347 | if (stack_arg != -1) | |
1348 | { | |
1349 | CORE_ADDR ap; | |
1350 | ||
1351 | /* Allocate all required stack size. */ | |
1352 | for (i = stack_arg; i < nargs; i++) | |
1353 | { | |
1354 | struct type *type = check_typedef (value_type (args[i])); | |
1355 | sp -= align_up (TYPE_LENGTH (type), 16); | |
1356 | } | |
1357 | ||
1358 | /* Fill in stack arguments. */ | |
1359 | ap = sp; | |
1360 | for (i = stack_arg; i < nargs; i++) | |
1361 | { | |
1362 | struct value *arg = args[i]; | |
1363 | struct type *type = check_typedef (value_type (arg)); | |
1364 | int len = TYPE_LENGTH (type); | |
1365 | int preferred_slot; | |
1366 | ||
1367 | if (spu_scalar_value_p (type)) | |
1368 | preferred_slot = len < 4 ? 4 - len : 0; | |
1369 | else | |
1370 | preferred_slot = 0; | |
1371 | ||
1372 | target_write_memory (ap + preferred_slot, value_contents (arg), len); | |
1373 | ap += align_up (TYPE_LENGTH (type), 16); | |
1374 | } | |
1375 | } | |
1376 | ||
1377 | /* Allocate stack frame header. */ | |
1378 | sp -= 32; | |
1379 | ||
ee82e879 UW |
1380 | /* Store stack back chain. */ |
1381 | regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf); | |
1382 | target_write_memory (sp, buf, 16); | |
1383 | ||
9ff3afda | 1384 | /* Finally, update all slots of the SP register. */ |
e17a4113 | 1385 | sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order); |
9ff3afda UW |
1386 | for (i = 0; i < 4; i++) |
1387 | { | |
e17a4113 UW |
1388 | CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order); |
1389 | store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta); | |
9ff3afda UW |
1390 | } |
1391 | regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf); | |
771b4502 UW |
1392 | |
1393 | return sp; | |
1394 | } | |
1395 | ||
1396 | static struct frame_id | |
8d998b8f | 1397 | spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
771b4502 | 1398 | { |
85e747d2 | 1399 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
8d998b8f UW |
1400 | CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM); |
1401 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM); | |
85e747d2 | 1402 | return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4)); |
771b4502 UW |
1403 | } |
1404 | ||
1405 | /* Function return value access. */ | |
1406 | ||
1407 | static enum return_value_convention | |
c055b101 CV |
1408 | spu_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1409 | struct type *type, struct regcache *regcache, | |
1410 | gdb_byte *out, const gdb_byte *in) | |
771b4502 UW |
1411 | { |
1412 | enum return_value_convention rvc; | |
1413 | ||
1414 | if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16) | |
1415 | rvc = RETURN_VALUE_REGISTER_CONVENTION; | |
1416 | else | |
1417 | rvc = RETURN_VALUE_STRUCT_CONVENTION; | |
1418 | ||
1419 | if (in) | |
1420 | { | |
1421 | switch (rvc) | |
1422 | { | |
1423 | case RETURN_VALUE_REGISTER_CONVENTION: | |
1424 | spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in); | |
1425 | break; | |
1426 | ||
1427 | case RETURN_VALUE_STRUCT_CONVENTION: | |
1428 | error ("Cannot set function return value."); | |
1429 | break; | |
1430 | } | |
1431 | } | |
1432 | else if (out) | |
1433 | { | |
1434 | switch (rvc) | |
1435 | { | |
1436 | case RETURN_VALUE_REGISTER_CONVENTION: | |
1437 | spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out); | |
1438 | break; | |
1439 | ||
1440 | case RETURN_VALUE_STRUCT_CONVENTION: | |
1441 | error ("Function return value unknown."); | |
1442 | break; | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | return rvc; | |
1447 | } | |
1448 | ||
1449 | ||
1450 | /* Breakpoints. */ | |
1451 | ||
1452 | static const gdb_byte * | |
67d57894 | 1453 | spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr) |
771b4502 UW |
1454 | { |
1455 | static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff }; | |
1456 | ||
1457 | *lenptr = sizeof breakpoint; | |
1458 | return breakpoint; | |
1459 | } | |
1460 | ||
1461 | ||
1462 | /* Software single-stepping support. */ | |
1463 | ||
63807e1d | 1464 | static int |
0b1b3e42 | 1465 | spu_software_single_step (struct frame_info *frame) |
771b4502 | 1466 | { |
a6d9a66e | 1467 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 1468 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e0cd558a UW |
1469 | CORE_ADDR pc, next_pc; |
1470 | unsigned int insn; | |
1471 | int offset, reg; | |
1472 | gdb_byte buf[4]; | |
771b4502 | 1473 | |
0b1b3e42 | 1474 | pc = get_frame_pc (frame); |
771b4502 | 1475 | |
e0cd558a UW |
1476 | if (target_read_memory (pc, buf, 4)) |
1477 | return 1; | |
e17a4113 | 1478 | insn = extract_unsigned_integer (buf, 4, byte_order); |
771b4502 | 1479 | |
e0cd558a UW |
1480 | /* Next sequential instruction is at PC + 4, except if the current |
1481 | instruction is a PPE-assisted call, in which case it is at PC + 8. | |
1482 | Wrap around LS limit to be on the safe side. */ | |
1483 | if ((insn & 0xffffff00) == 0x00002100) | |
85e747d2 | 1484 | next_pc = (SPUADDR_ADDR (pc) + 8) & (SPU_LS_SIZE - 1); |
e0cd558a | 1485 | else |
85e747d2 | 1486 | next_pc = (SPUADDR_ADDR (pc) + 4) & (SPU_LS_SIZE - 1); |
771b4502 | 1487 | |
85e747d2 | 1488 | insert_single_step_breakpoint (gdbarch, SPUADDR (SPUADDR_SPU (pc), next_pc)); |
771b4502 | 1489 | |
e0cd558a UW |
1490 | if (is_branch (insn, &offset, ®)) |
1491 | { | |
1492 | CORE_ADDR target = offset; | |
771b4502 | 1493 | |
e0cd558a | 1494 | if (reg == SPU_PC_REGNUM) |
85e747d2 | 1495 | target += SPUADDR_ADDR (pc); |
e0cd558a UW |
1496 | else if (reg != -1) |
1497 | { | |
0b1b3e42 | 1498 | get_frame_register_bytes (frame, reg, 0, 4, buf); |
e17a4113 | 1499 | target += extract_unsigned_integer (buf, 4, byte_order) & -4; |
771b4502 | 1500 | } |
e0cd558a UW |
1501 | |
1502 | target = target & (SPU_LS_SIZE - 1); | |
1503 | if (target != next_pc) | |
85e747d2 UW |
1504 | insert_single_step_breakpoint (gdbarch, |
1505 | SPUADDR (SPUADDR_SPU (pc), target)); | |
771b4502 | 1506 | } |
e6590a1b UW |
1507 | |
1508 | return 1; | |
771b4502 UW |
1509 | } |
1510 | ||
6e3f70d7 UW |
1511 | |
1512 | /* Longjmp support. */ | |
1513 | ||
1514 | static int | |
1515 | spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
1516 | { | |
e17a4113 | 1517 | struct gdbarch *gdbarch = get_frame_arch (frame); |
85e747d2 | 1518 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 1519 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
6e3f70d7 UW |
1520 | gdb_byte buf[4]; |
1521 | CORE_ADDR jb_addr; | |
1522 | ||
1523 | /* Jump buffer is pointed to by the argument register $r3. */ | |
1524 | get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf); | |
e17a4113 | 1525 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
85e747d2 | 1526 | if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4)) |
6e3f70d7 UW |
1527 | return 0; |
1528 | ||
e17a4113 | 1529 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
85e747d2 | 1530 | *pc = SPUADDR (tdep->id, *pc); |
6e3f70d7 UW |
1531 | return 1; |
1532 | } | |
1533 | ||
1534 | ||
85e747d2 UW |
1535 | /* Disassembler. */ |
1536 | ||
1537 | struct spu_dis_asm_data | |
1538 | { | |
1539 | struct gdbarch *gdbarch; | |
1540 | int id; | |
1541 | }; | |
1542 | ||
1543 | static void | |
1544 | spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info) | |
1545 | { | |
1546 | struct spu_dis_asm_data *data = info->application_data; | |
1547 | print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream); | |
1548 | } | |
1549 | ||
1550 | static int | |
1551 | gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info) | |
1552 | { | |
1553 | /* The opcodes disassembler does 18-bit address arithmetic. Make sure the | |
1554 | SPU ID encoded in the high bits is added back when we call print_address. */ | |
1555 | struct disassemble_info spu_info = *info; | |
1556 | struct spu_dis_asm_data data; | |
1557 | data.gdbarch = info->application_data; | |
1558 | data.id = SPUADDR_SPU (memaddr); | |
1559 | ||
1560 | spu_info.application_data = &data; | |
1561 | spu_info.print_address_func = spu_dis_asm_print_address; | |
1562 | return print_insn_spu (memaddr, &spu_info); | |
1563 | } | |
1564 | ||
1565 | ||
dcf52cd8 UW |
1566 | /* Target overlays for the SPU overlay manager. |
1567 | ||
1568 | See the documentation of simple_overlay_update for how the | |
1569 | interface is supposed to work. | |
1570 | ||
1571 | Data structures used by the overlay manager: | |
1572 | ||
1573 | struct ovly_table | |
1574 | { | |
1575 | u32 vma; | |
1576 | u32 size; | |
1577 | u32 pos; | |
1578 | u32 buf; | |
1579 | } _ovly_table[]; -- one entry per overlay section | |
1580 | ||
1581 | struct ovly_buf_table | |
1582 | { | |
1583 | u32 mapped; | |
1584 | } _ovly_buf_table[]; -- one entry per overlay buffer | |
1585 | ||
1586 | _ovly_table should never change. | |
1587 | ||
1588 | Both tables are aligned to a 16-byte boundary, the symbols _ovly_table | |
1589 | and _ovly_buf_table are of type STT_OBJECT and their size set to the size | |
1590 | of the respective array. buf in _ovly_table is an index into _ovly_buf_table. | |
1591 | ||
1592 | mapped is an index into _ovly_table. Both the mapped and buf indices start | |
1593 | from one to reference the first entry in their respective tables. */ | |
1594 | ||
1595 | /* Using the per-objfile private data mechanism, we store for each | |
1596 | objfile an array of "struct spu_overlay_table" structures, one | |
1597 | for each obj_section of the objfile. This structure holds two | |
1598 | fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this | |
1599 | is *not* an overlay section. If it is non-zero, it represents | |
1600 | a target address. The overlay section is mapped iff the target | |
1601 | integer at this location equals MAPPED_VAL. */ | |
1602 | ||
1603 | static const struct objfile_data *spu_overlay_data; | |
1604 | ||
1605 | struct spu_overlay_table | |
1606 | { | |
1607 | CORE_ADDR mapped_ptr; | |
1608 | CORE_ADDR mapped_val; | |
1609 | }; | |
1610 | ||
1611 | /* Retrieve the overlay table for OBJFILE. If not already cached, read | |
1612 | the _ovly_table data structure from the target and initialize the | |
1613 | spu_overlay_table data structure from it. */ | |
1614 | static struct spu_overlay_table * | |
1615 | spu_get_overlay_table (struct objfile *objfile) | |
1616 | { | |
e17a4113 UW |
1617 | enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)? |
1618 | BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; | |
dcf52cd8 UW |
1619 | struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym; |
1620 | CORE_ADDR ovly_table_base, ovly_buf_table_base; | |
1621 | unsigned ovly_table_size, ovly_buf_table_size; | |
1622 | struct spu_overlay_table *tbl; | |
1623 | struct obj_section *osect; | |
1624 | char *ovly_table; | |
1625 | int i; | |
1626 | ||
1627 | tbl = objfile_data (objfile, spu_overlay_data); | |
1628 | if (tbl) | |
1629 | return tbl; | |
1630 | ||
1631 | ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile); | |
1632 | if (!ovly_table_msym) | |
1633 | return NULL; | |
1634 | ||
1635 | ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile); | |
1636 | if (!ovly_buf_table_msym) | |
1637 | return NULL; | |
1638 | ||
1639 | ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym); | |
1640 | ovly_table_size = MSYMBOL_SIZE (ovly_table_msym); | |
1641 | ||
1642 | ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym); | |
1643 | ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym); | |
1644 | ||
1645 | ovly_table = xmalloc (ovly_table_size); | |
1646 | read_memory (ovly_table_base, ovly_table, ovly_table_size); | |
1647 | ||
1648 | tbl = OBSTACK_CALLOC (&objfile->objfile_obstack, | |
1649 | objfile->sections_end - objfile->sections, | |
1650 | struct spu_overlay_table); | |
1651 | ||
1652 | for (i = 0; i < ovly_table_size / 16; i++) | |
1653 | { | |
e17a4113 UW |
1654 | CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, |
1655 | 4, byte_order); | |
1656 | CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, | |
1657 | 4, byte_order); | |
1658 | CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, | |
1659 | 4, byte_order); | |
1660 | CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, | |
1661 | 4, byte_order); | |
dcf52cd8 UW |
1662 | |
1663 | if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size) | |
1664 | continue; | |
1665 | ||
1666 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
1667 | if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section) | |
1668 | && pos == osect->the_bfd_section->filepos) | |
1669 | { | |
1670 | int ndx = osect - objfile->sections; | |
1671 | tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4; | |
1672 | tbl[ndx].mapped_val = i + 1; | |
1673 | break; | |
1674 | } | |
1675 | } | |
1676 | ||
1677 | xfree (ovly_table); | |
1678 | set_objfile_data (objfile, spu_overlay_data, tbl); | |
1679 | return tbl; | |
1680 | } | |
1681 | ||
1682 | /* Read _ovly_buf_table entry from the target to dermine whether | |
1683 | OSECT is currently mapped, and update the mapped state. */ | |
1684 | static void | |
1685 | spu_overlay_update_osect (struct obj_section *osect) | |
1686 | { | |
e17a4113 UW |
1687 | enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)? |
1688 | BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; | |
dcf52cd8 | 1689 | struct spu_overlay_table *ovly_table; |
85e747d2 | 1690 | CORE_ADDR id, val; |
dcf52cd8 UW |
1691 | |
1692 | ovly_table = spu_get_overlay_table (osect->objfile); | |
1693 | if (!ovly_table) | |
1694 | return; | |
1695 | ||
1696 | ovly_table += osect - osect->objfile->sections; | |
1697 | if (ovly_table->mapped_ptr == 0) | |
1698 | return; | |
1699 | ||
85e747d2 UW |
1700 | id = SPUADDR_SPU (obj_section_addr (osect)); |
1701 | val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr), | |
1702 | 4, byte_order); | |
dcf52cd8 UW |
1703 | osect->ovly_mapped = (val == ovly_table->mapped_val); |
1704 | } | |
1705 | ||
1706 | /* If OSECT is NULL, then update all sections' mapped state. | |
1707 | If OSECT is non-NULL, then update only OSECT's mapped state. */ | |
1708 | static void | |
1709 | spu_overlay_update (struct obj_section *osect) | |
1710 | { | |
1711 | /* Just one section. */ | |
1712 | if (osect) | |
1713 | spu_overlay_update_osect (osect); | |
1714 | ||
1715 | /* All sections. */ | |
1716 | else | |
1717 | { | |
1718 | struct objfile *objfile; | |
1719 | ||
1720 | ALL_OBJSECTIONS (objfile, osect) | |
714835d5 | 1721 | if (section_is_overlay (osect)) |
dcf52cd8 UW |
1722 | spu_overlay_update_osect (osect); |
1723 | } | |
1724 | } | |
1725 | ||
1726 | /* Whenever a new objfile is loaded, read the target's _ovly_table. | |
1727 | If there is one, go through all sections and make sure for non- | |
1728 | overlay sections LMA equals VMA, while for overlay sections LMA | |
1729 | is larger than local store size. */ | |
1730 | static void | |
1731 | spu_overlay_new_objfile (struct objfile *objfile) | |
1732 | { | |
1733 | struct spu_overlay_table *ovly_table; | |
1734 | struct obj_section *osect; | |
1735 | ||
1736 | /* If we've already touched this file, do nothing. */ | |
1737 | if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL) | |
1738 | return; | |
1739 | ||
0391f248 UW |
1740 | /* Consider only SPU objfiles. */ |
1741 | if (bfd_get_arch (objfile->obfd) != bfd_arch_spu) | |
1742 | return; | |
1743 | ||
dcf52cd8 UW |
1744 | /* Check if this objfile has overlays. */ |
1745 | ovly_table = spu_get_overlay_table (objfile); | |
1746 | if (!ovly_table) | |
1747 | return; | |
1748 | ||
1749 | /* Now go and fiddle with all the LMAs. */ | |
1750 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
1751 | { | |
1752 | bfd *obfd = objfile->obfd; | |
1753 | asection *bsect = osect->the_bfd_section; | |
1754 | int ndx = osect - objfile->sections; | |
1755 | ||
1756 | if (ovly_table[ndx].mapped_ptr == 0) | |
1757 | bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect); | |
1758 | else | |
1759 | bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE; | |
1760 | } | |
1761 | } | |
1762 | ||
771b4502 | 1763 | |
3285f3fe UW |
1764 | /* Insert temporary breakpoint on "main" function of newly loaded |
1765 | SPE context OBJFILE. */ | |
1766 | static void | |
1767 | spu_catch_start (struct objfile *objfile) | |
1768 | { | |
1769 | struct minimal_symbol *minsym; | |
1770 | struct symtab *symtab; | |
1771 | CORE_ADDR pc; | |
1772 | char buf[32]; | |
1773 | ||
1774 | /* Do this only if requested by "set spu stop-on-load on". */ | |
1775 | if (!spu_stop_on_load_p) | |
1776 | return; | |
1777 | ||
1778 | /* Consider only SPU objfiles. */ | |
1779 | if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu) | |
1780 | return; | |
1781 | ||
1782 | /* The main objfile is handled differently. */ | |
1783 | if (objfile == symfile_objfile) | |
1784 | return; | |
1785 | ||
1786 | /* There can be multiple symbols named "main". Search for the | |
1787 | "main" in *this* objfile. */ | |
1788 | minsym = lookup_minimal_symbol ("main", NULL, objfile); | |
1789 | if (!minsym) | |
1790 | return; | |
1791 | ||
1792 | /* If we have debugging information, try to use it -- this | |
1793 | will allow us to properly skip the prologue. */ | |
1794 | pc = SYMBOL_VALUE_ADDRESS (minsym); | |
1795 | symtab = find_pc_sect_symtab (pc, SYMBOL_OBJ_SECTION (minsym)); | |
1796 | if (symtab != NULL) | |
1797 | { | |
1798 | struct blockvector *bv = BLOCKVECTOR (symtab); | |
1799 | struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK); | |
1800 | struct symbol *sym; | |
1801 | struct symtab_and_line sal; | |
1802 | ||
1803 | sym = lookup_block_symbol (block, "main", NULL, VAR_DOMAIN); | |
1804 | if (sym) | |
1805 | { | |
1806 | fixup_symbol_section (sym, objfile); | |
1807 | sal = find_function_start_sal (sym, 1); | |
1808 | pc = sal.pc; | |
1809 | } | |
1810 | } | |
1811 | ||
1812 | /* Use a numerical address for the set_breakpoint command to avoid having | |
1813 | the breakpoint re-set incorrectly. */ | |
1814 | xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc)); | |
1815 | set_breakpoint (get_objfile_arch (objfile), | |
1816 | buf, NULL /* condition */, | |
1817 | 0 /* hardwareflag */, 1 /* tempflag */, | |
1818 | -1 /* thread */, 0 /* ignore_count */, | |
1819 | 0 /* pending */, 1 /* enabled */); | |
1820 | } | |
1821 | ||
1822 | ||
23d964e7 UW |
1823 | /* "info spu" commands. */ |
1824 | ||
1825 | static void | |
1826 | info_spu_event_command (char *args, int from_tty) | |
1827 | { | |
1828 | struct frame_info *frame = get_selected_frame (NULL); | |
1829 | ULONGEST event_status = 0; | |
1830 | ULONGEST event_mask = 0; | |
1831 | struct cleanup *chain; | |
1832 | gdb_byte buf[100]; | |
1833 | char annex[32]; | |
1834 | LONGEST len; | |
1835 | int rc, id; | |
1836 | ||
0391f248 UW |
1837 | if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu) |
1838 | error (_("\"info spu\" is only supported on the SPU architecture.")); | |
1839 | ||
23d964e7 UW |
1840 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
1841 | ||
1842 | xsnprintf (annex, sizeof annex, "%d/event_status", id); | |
1843 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
9971ac47 | 1844 | buf, 0, (sizeof (buf) - 1)); |
23d964e7 UW |
1845 | if (len <= 0) |
1846 | error (_("Could not read event_status.")); | |
9971ac47 | 1847 | buf[len] = '\0'; |
23d964e7 UW |
1848 | event_status = strtoulst (buf, NULL, 16); |
1849 | ||
1850 | xsnprintf (annex, sizeof annex, "%d/event_mask", id); | |
1851 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
9971ac47 | 1852 | buf, 0, (sizeof (buf) - 1)); |
23d964e7 UW |
1853 | if (len <= 0) |
1854 | error (_("Could not read event_mask.")); | |
9971ac47 | 1855 | buf[len] = '\0'; |
23d964e7 UW |
1856 | event_mask = strtoulst (buf, NULL, 16); |
1857 | ||
1858 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent"); | |
1859 | ||
1860 | if (ui_out_is_mi_like_p (uiout)) | |
1861 | { | |
1862 | ui_out_field_fmt (uiout, "event_status", | |
1863 | "0x%s", phex_nz (event_status, 4)); | |
1864 | ui_out_field_fmt (uiout, "event_mask", | |
1865 | "0x%s", phex_nz (event_mask, 4)); | |
1866 | } | |
1867 | else | |
1868 | { | |
1869 | printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4)); | |
1870 | printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4)); | |
1871 | } | |
1872 | ||
1873 | do_cleanups (chain); | |
1874 | } | |
1875 | ||
1876 | static void | |
1877 | info_spu_signal_command (char *args, int from_tty) | |
1878 | { | |
1879 | struct frame_info *frame = get_selected_frame (NULL); | |
e17a4113 UW |
1880 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1881 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
23d964e7 UW |
1882 | ULONGEST signal1 = 0; |
1883 | ULONGEST signal1_type = 0; | |
1884 | int signal1_pending = 0; | |
1885 | ULONGEST signal2 = 0; | |
1886 | ULONGEST signal2_type = 0; | |
1887 | int signal2_pending = 0; | |
1888 | struct cleanup *chain; | |
1889 | char annex[32]; | |
1890 | gdb_byte buf[100]; | |
1891 | LONGEST len; | |
1892 | int rc, id; | |
1893 | ||
e17a4113 | 1894 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu) |
0391f248 UW |
1895 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
1896 | ||
23d964e7 UW |
1897 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
1898 | ||
1899 | xsnprintf (annex, sizeof annex, "%d/signal1", id); | |
1900 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4); | |
1901 | if (len < 0) | |
1902 | error (_("Could not read signal1.")); | |
1903 | else if (len == 4) | |
1904 | { | |
e17a4113 | 1905 | signal1 = extract_unsigned_integer (buf, 4, byte_order); |
23d964e7 UW |
1906 | signal1_pending = 1; |
1907 | } | |
1908 | ||
1909 | xsnprintf (annex, sizeof annex, "%d/signal1_type", id); | |
1910 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
9971ac47 | 1911 | buf, 0, (sizeof (buf) - 1)); |
23d964e7 UW |
1912 | if (len <= 0) |
1913 | error (_("Could not read signal1_type.")); | |
9971ac47 | 1914 | buf[len] = '\0'; |
23d964e7 UW |
1915 | signal1_type = strtoulst (buf, NULL, 16); |
1916 | ||
1917 | xsnprintf (annex, sizeof annex, "%d/signal2", id); | |
1918 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4); | |
1919 | if (len < 0) | |
1920 | error (_("Could not read signal2.")); | |
1921 | else if (len == 4) | |
1922 | { | |
e17a4113 | 1923 | signal2 = extract_unsigned_integer (buf, 4, byte_order); |
23d964e7 UW |
1924 | signal2_pending = 1; |
1925 | } | |
1926 | ||
1927 | xsnprintf (annex, sizeof annex, "%d/signal2_type", id); | |
1928 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
9971ac47 | 1929 | buf, 0, (sizeof (buf) - 1)); |
23d964e7 UW |
1930 | if (len <= 0) |
1931 | error (_("Could not read signal2_type.")); | |
9971ac47 | 1932 | buf[len] = '\0'; |
23d964e7 UW |
1933 | signal2_type = strtoulst (buf, NULL, 16); |
1934 | ||
1935 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal"); | |
1936 | ||
1937 | if (ui_out_is_mi_like_p (uiout)) | |
1938 | { | |
1939 | ui_out_field_int (uiout, "signal1_pending", signal1_pending); | |
1940 | ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4)); | |
1941 | ui_out_field_int (uiout, "signal1_type", signal1_type); | |
1942 | ui_out_field_int (uiout, "signal2_pending", signal2_pending); | |
1943 | ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4)); | |
1944 | ui_out_field_int (uiout, "signal2_type", signal2_type); | |
1945 | } | |
1946 | else | |
1947 | { | |
1948 | if (signal1_pending) | |
1949 | printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4)); | |
1950 | else | |
1951 | printf_filtered (_("Signal 1 not pending ")); | |
1952 | ||
1953 | if (signal1_type) | |
23d964e7 | 1954 | printf_filtered (_("(Type Or)\n")); |
b94c4f7d UW |
1955 | else |
1956 | printf_filtered (_("(Type Overwrite)\n")); | |
23d964e7 UW |
1957 | |
1958 | if (signal2_pending) | |
1959 | printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4)); | |
1960 | else | |
1961 | printf_filtered (_("Signal 2 not pending ")); | |
1962 | ||
1963 | if (signal2_type) | |
23d964e7 | 1964 | printf_filtered (_("(Type Or)\n")); |
b94c4f7d UW |
1965 | else |
1966 | printf_filtered (_("(Type Overwrite)\n")); | |
23d964e7 UW |
1967 | } |
1968 | ||
1969 | do_cleanups (chain); | |
1970 | } | |
1971 | ||
1972 | static void | |
e17a4113 | 1973 | info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order, |
23d964e7 UW |
1974 | const char *field, const char *msg) |
1975 | { | |
1976 | struct cleanup *chain; | |
1977 | int i; | |
1978 | ||
1979 | if (nr <= 0) | |
1980 | return; | |
1981 | ||
1982 | chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox"); | |
1983 | ||
1984 | ui_out_table_header (uiout, 32, ui_left, field, msg); | |
1985 | ui_out_table_body (uiout); | |
1986 | ||
1987 | for (i = 0; i < nr; i++) | |
1988 | { | |
1989 | struct cleanup *val_chain; | |
1990 | ULONGEST val; | |
1991 | val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox"); | |
e17a4113 | 1992 | val = extract_unsigned_integer (buf + 4*i, 4, byte_order); |
23d964e7 UW |
1993 | ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4)); |
1994 | do_cleanups (val_chain); | |
1995 | ||
1996 | if (!ui_out_is_mi_like_p (uiout)) | |
1997 | printf_filtered ("\n"); | |
1998 | } | |
1999 | ||
2000 | do_cleanups (chain); | |
2001 | } | |
2002 | ||
2003 | static void | |
2004 | info_spu_mailbox_command (char *args, int from_tty) | |
2005 | { | |
2006 | struct frame_info *frame = get_selected_frame (NULL); | |
e17a4113 UW |
2007 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2008 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
23d964e7 UW |
2009 | struct cleanup *chain; |
2010 | char annex[32]; | |
2011 | gdb_byte buf[1024]; | |
2012 | LONGEST len; | |
2013 | int i, id; | |
2014 | ||
e17a4113 | 2015 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu) |
0391f248 UW |
2016 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
2017 | ||
23d964e7 UW |
2018 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
2019 | ||
2020 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox"); | |
2021 | ||
2022 | xsnprintf (annex, sizeof annex, "%d/mbox_info", id); | |
2023 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
2024 | buf, 0, sizeof buf); | |
2025 | if (len < 0) | |
2026 | error (_("Could not read mbox_info.")); | |
2027 | ||
e17a4113 UW |
2028 | info_spu_mailbox_list (buf, len / 4, byte_order, |
2029 | "mbox", "SPU Outbound Mailbox"); | |
23d964e7 UW |
2030 | |
2031 | xsnprintf (annex, sizeof annex, "%d/ibox_info", id); | |
2032 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
2033 | buf, 0, sizeof buf); | |
2034 | if (len < 0) | |
2035 | error (_("Could not read ibox_info.")); | |
2036 | ||
e17a4113 UW |
2037 | info_spu_mailbox_list (buf, len / 4, byte_order, |
2038 | "ibox", "SPU Outbound Interrupt Mailbox"); | |
23d964e7 UW |
2039 | |
2040 | xsnprintf (annex, sizeof annex, "%d/wbox_info", id); | |
2041 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
2042 | buf, 0, sizeof buf); | |
2043 | if (len < 0) | |
2044 | error (_("Could not read wbox_info.")); | |
2045 | ||
e17a4113 UW |
2046 | info_spu_mailbox_list (buf, len / 4, byte_order, |
2047 | "wbox", "SPU Inbound Mailbox"); | |
23d964e7 UW |
2048 | |
2049 | do_cleanups (chain); | |
2050 | } | |
2051 | ||
2052 | static ULONGEST | |
2053 | spu_mfc_get_bitfield (ULONGEST word, int first, int last) | |
2054 | { | |
2055 | ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1)); | |
2056 | return (word >> (63 - last)) & mask; | |
2057 | } | |
2058 | ||
2059 | static void | |
e17a4113 | 2060 | info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order) |
23d964e7 UW |
2061 | { |
2062 | static char *spu_mfc_opcode[256] = | |
2063 | { | |
2064 | /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2065 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2066 | /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2067 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2068 | /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL, | |
2069 | "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL, | |
2070 | /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL, | |
2071 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2072 | /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL, | |
2073 | "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL, | |
2074 | /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2075 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2076 | /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2077 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2078 | /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2079 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2080 | /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL, | |
2081 | NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf", | |
2082 | /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2083 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2084 | /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL, | |
2085 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2086 | /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL, | |
2087 | "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2088 | /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2089 | "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL, | |
2090 | /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2091 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2092 | /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2093 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2094 | /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2095 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
2096 | }; | |
2097 | ||
12ab8a60 UW |
2098 | int *seq = alloca (nr * sizeof (int)); |
2099 | int done = 0; | |
23d964e7 | 2100 | struct cleanup *chain; |
12ab8a60 UW |
2101 | int i, j; |
2102 | ||
2103 | ||
2104 | /* Determine sequence in which to display (valid) entries. */ | |
2105 | for (i = 0; i < nr; i++) | |
2106 | { | |
2107 | /* Search for the first valid entry all of whose | |
2108 | dependencies are met. */ | |
2109 | for (j = 0; j < nr; j++) | |
2110 | { | |
2111 | ULONGEST mfc_cq_dw3; | |
2112 | ULONGEST dependencies; | |
2113 | ||
2114 | if (done & (1 << (nr - 1 - j))) | |
2115 | continue; | |
2116 | ||
e17a4113 UW |
2117 | mfc_cq_dw3 |
2118 | = extract_unsigned_integer (buf + 32*j + 24,8, byte_order); | |
12ab8a60 UW |
2119 | if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16)) |
2120 | continue; | |
2121 | ||
2122 | dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1); | |
2123 | if ((dependencies & done) != dependencies) | |
2124 | continue; | |
2125 | ||
2126 | seq[i] = j; | |
2127 | done |= 1 << (nr - 1 - j); | |
2128 | break; | |
2129 | } | |
2130 | ||
2131 | if (j == nr) | |
2132 | break; | |
2133 | } | |
2134 | ||
2135 | nr = i; | |
2136 | ||
23d964e7 UW |
2137 | |
2138 | chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd"); | |
2139 | ||
2140 | ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode"); | |
2141 | ui_out_table_header (uiout, 3, ui_left, "tag", "Tag"); | |
2142 | ui_out_table_header (uiout, 3, ui_left, "tid", "TId"); | |
2143 | ui_out_table_header (uiout, 3, ui_left, "rid", "RId"); | |
2144 | ui_out_table_header (uiout, 18, ui_left, "ea", "EA"); | |
2145 | ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA"); | |
2146 | ui_out_table_header (uiout, 7, ui_left, "size", "Size"); | |
2147 | ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr"); | |
2148 | ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize"); | |
2149 | ui_out_table_header (uiout, 1, ui_left, "error_p", "E"); | |
2150 | ||
2151 | ui_out_table_body (uiout); | |
2152 | ||
2153 | for (i = 0; i < nr; i++) | |
2154 | { | |
2155 | struct cleanup *cmd_chain; | |
2156 | ULONGEST mfc_cq_dw0; | |
2157 | ULONGEST mfc_cq_dw1; | |
2158 | ULONGEST mfc_cq_dw2; | |
23d964e7 UW |
2159 | int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id; |
2160 | int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size; | |
2161 | ULONGEST mfc_ea; | |
2162 | int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p; | |
2163 | ||
2164 | /* Decode contents of MFC Command Queue Context Save/Restore Registers. | |
2165 | See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */ | |
2166 | ||
e17a4113 UW |
2167 | mfc_cq_dw0 |
2168 | = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order); | |
2169 | mfc_cq_dw1 | |
2170 | = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order); | |
2171 | mfc_cq_dw2 | |
2172 | = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order); | |
23d964e7 UW |
2173 | |
2174 | list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14); | |
2175 | list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26); | |
2176 | mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34); | |
2177 | mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39); | |
2178 | list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40); | |
2179 | rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43); | |
2180 | tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46); | |
2181 | ||
2182 | mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12 | |
2183 | | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36); | |
2184 | ||
2185 | mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13); | |
2186 | mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24); | |
2187 | noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37); | |
2188 | qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38); | |
2189 | ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39); | |
2190 | cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40); | |
2191 | ||
2192 | cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd"); | |
2193 | ||
2194 | if (spu_mfc_opcode[mfc_cmd_opcode]) | |
2195 | ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]); | |
2196 | else | |
2197 | ui_out_field_int (uiout, "opcode", mfc_cmd_opcode); | |
2198 | ||
2199 | ui_out_field_int (uiout, "tag", mfc_cmd_tag); | |
2200 | ui_out_field_int (uiout, "tid", tclass_id); | |
2201 | ui_out_field_int (uiout, "rid", rclass_id); | |
2202 | ||
2203 | if (ea_valid_p) | |
2204 | ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8)); | |
2205 | else | |
2206 | ui_out_field_skip (uiout, "ea"); | |
2207 | ||
2208 | ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4); | |
2209 | if (qw_valid_p) | |
2210 | ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4); | |
2211 | else | |
2212 | ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size); | |
2213 | ||
2214 | if (list_valid_p) | |
2215 | { | |
2216 | ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3); | |
2217 | ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3); | |
2218 | } | |
2219 | else | |
2220 | { | |
2221 | ui_out_field_skip (uiout, "lstaddr"); | |
2222 | ui_out_field_skip (uiout, "lstsize"); | |
2223 | } | |
2224 | ||
2225 | if (cmd_error_p) | |
2226 | ui_out_field_string (uiout, "error_p", "*"); | |
2227 | else | |
2228 | ui_out_field_skip (uiout, "error_p"); | |
2229 | ||
2230 | do_cleanups (cmd_chain); | |
2231 | ||
2232 | if (!ui_out_is_mi_like_p (uiout)) | |
2233 | printf_filtered ("\n"); | |
2234 | } | |
2235 | ||
2236 | do_cleanups (chain); | |
2237 | } | |
2238 | ||
2239 | static void | |
2240 | info_spu_dma_command (char *args, int from_tty) | |
2241 | { | |
2242 | struct frame_info *frame = get_selected_frame (NULL); | |
e17a4113 UW |
2243 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2244 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
23d964e7 UW |
2245 | ULONGEST dma_info_type; |
2246 | ULONGEST dma_info_mask; | |
2247 | ULONGEST dma_info_status; | |
2248 | ULONGEST dma_info_stall_and_notify; | |
2249 | ULONGEST dma_info_atomic_command_status; | |
2250 | struct cleanup *chain; | |
2251 | char annex[32]; | |
2252 | gdb_byte buf[1024]; | |
2253 | LONGEST len; | |
2254 | int i, id; | |
2255 | ||
0391f248 UW |
2256 | if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu) |
2257 | error (_("\"info spu\" is only supported on the SPU architecture.")); | |
2258 | ||
23d964e7 UW |
2259 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
2260 | ||
2261 | xsnprintf (annex, sizeof annex, "%d/dma_info", id); | |
2262 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
2263 | buf, 0, 40 + 16 * 32); | |
2264 | if (len <= 0) | |
2265 | error (_("Could not read dma_info.")); | |
2266 | ||
e17a4113 UW |
2267 | dma_info_type |
2268 | = extract_unsigned_integer (buf, 8, byte_order); | |
2269 | dma_info_mask | |
2270 | = extract_unsigned_integer (buf + 8, 8, byte_order); | |
2271 | dma_info_status | |
2272 | = extract_unsigned_integer (buf + 16, 8, byte_order); | |
2273 | dma_info_stall_and_notify | |
2274 | = extract_unsigned_integer (buf + 24, 8, byte_order); | |
2275 | dma_info_atomic_command_status | |
2276 | = extract_unsigned_integer (buf + 32, 8, byte_order); | |
23d964e7 UW |
2277 | |
2278 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA"); | |
2279 | ||
2280 | if (ui_out_is_mi_like_p (uiout)) | |
2281 | { | |
2282 | ui_out_field_fmt (uiout, "dma_info_type", "0x%s", | |
2283 | phex_nz (dma_info_type, 4)); | |
2284 | ui_out_field_fmt (uiout, "dma_info_mask", "0x%s", | |
2285 | phex_nz (dma_info_mask, 4)); | |
2286 | ui_out_field_fmt (uiout, "dma_info_status", "0x%s", | |
2287 | phex_nz (dma_info_status, 4)); | |
2288 | ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s", | |
2289 | phex_nz (dma_info_stall_and_notify, 4)); | |
2290 | ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s", | |
2291 | phex_nz (dma_info_atomic_command_status, 4)); | |
2292 | } | |
2293 | else | |
2294 | { | |
8fbde58b | 2295 | const char *query_msg = _("no query pending"); |
23d964e7 | 2296 | |
8fbde58b UW |
2297 | if (dma_info_type & 4) |
2298 | switch (dma_info_type & 3) | |
2299 | { | |
2300 | case 1: query_msg = _("'any' query pending"); break; | |
2301 | case 2: query_msg = _("'all' query pending"); break; | |
2302 | default: query_msg = _("undefined query type"); break; | |
2303 | } | |
23d964e7 UW |
2304 | |
2305 | printf_filtered (_("Tag-Group Status 0x%s\n"), | |
2306 | phex (dma_info_status, 4)); | |
2307 | printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"), | |
2308 | phex (dma_info_mask, 4), query_msg); | |
2309 | printf_filtered (_("Stall-and-Notify 0x%s\n"), | |
2310 | phex (dma_info_stall_and_notify, 4)); | |
2311 | printf_filtered (_("Atomic Cmd Status 0x%s\n"), | |
2312 | phex (dma_info_atomic_command_status, 4)); | |
2313 | printf_filtered ("\n"); | |
2314 | } | |
2315 | ||
e17a4113 | 2316 | info_spu_dma_cmdlist (buf + 40, 16, byte_order); |
23d964e7 UW |
2317 | do_cleanups (chain); |
2318 | } | |
2319 | ||
2320 | static void | |
2321 | info_spu_proxydma_command (char *args, int from_tty) | |
2322 | { | |
2323 | struct frame_info *frame = get_selected_frame (NULL); | |
e17a4113 UW |
2324 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2325 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
23d964e7 UW |
2326 | ULONGEST dma_info_type; |
2327 | ULONGEST dma_info_mask; | |
2328 | ULONGEST dma_info_status; | |
2329 | struct cleanup *chain; | |
2330 | char annex[32]; | |
2331 | gdb_byte buf[1024]; | |
2332 | LONGEST len; | |
2333 | int i, id; | |
2334 | ||
e17a4113 | 2335 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu) |
0391f248 UW |
2336 | error (_("\"info spu\" is only supported on the SPU architecture.")); |
2337 | ||
23d964e7 UW |
2338 | id = get_frame_register_unsigned (frame, SPU_ID_REGNUM); |
2339 | ||
2340 | xsnprintf (annex, sizeof annex, "%d/proxydma_info", id); | |
2341 | len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, | |
2342 | buf, 0, 24 + 8 * 32); | |
2343 | if (len <= 0) | |
2344 | error (_("Could not read proxydma_info.")); | |
2345 | ||
e17a4113 UW |
2346 | dma_info_type = extract_unsigned_integer (buf, 8, byte_order); |
2347 | dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order); | |
2348 | dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order); | |
23d964e7 UW |
2349 | |
2350 | chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA"); | |
2351 | ||
2352 | if (ui_out_is_mi_like_p (uiout)) | |
2353 | { | |
2354 | ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s", | |
2355 | phex_nz (dma_info_type, 4)); | |
2356 | ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s", | |
2357 | phex_nz (dma_info_mask, 4)); | |
2358 | ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s", | |
2359 | phex_nz (dma_info_status, 4)); | |
2360 | } | |
2361 | else | |
2362 | { | |
2363 | const char *query_msg; | |
2364 | ||
8fbde58b | 2365 | switch (dma_info_type & 3) |
23d964e7 UW |
2366 | { |
2367 | case 0: query_msg = _("no query pending"); break; | |
2368 | case 1: query_msg = _("'any' query pending"); break; | |
2369 | case 2: query_msg = _("'all' query pending"); break; | |
2370 | default: query_msg = _("undefined query type"); break; | |
2371 | } | |
2372 | ||
2373 | printf_filtered (_("Tag-Group Status 0x%s\n"), | |
2374 | phex (dma_info_status, 4)); | |
2375 | printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"), | |
2376 | phex (dma_info_mask, 4), query_msg); | |
2377 | printf_filtered ("\n"); | |
2378 | } | |
2379 | ||
e17a4113 | 2380 | info_spu_dma_cmdlist (buf + 24, 8, byte_order); |
23d964e7 UW |
2381 | do_cleanups (chain); |
2382 | } | |
2383 | ||
2384 | static void | |
2385 | info_spu_command (char *args, int from_tty) | |
2386 | { | |
2387 | printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n")); | |
2388 | help_list (infospucmdlist, "info spu ", -1, gdb_stdout); | |
2389 | } | |
2390 | ||
2391 | ||
3285f3fe UW |
2392 | /* Root of all "set spu "/"show spu " commands. */ |
2393 | ||
2394 | static void | |
2395 | show_spu_command (char *args, int from_tty) | |
2396 | { | |
2397 | help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout); | |
2398 | } | |
2399 | ||
2400 | static void | |
2401 | set_spu_command (char *args, int from_tty) | |
2402 | { | |
2403 | help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout); | |
2404 | } | |
2405 | ||
2406 | static void | |
2407 | show_spu_stop_on_load (struct ui_file *file, int from_tty, | |
2408 | struct cmd_list_element *c, const char *value) | |
2409 | { | |
2410 | fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"), | |
2411 | value); | |
2412 | } | |
2413 | ||
2414 | ||
771b4502 UW |
2415 | /* Set up gdbarch struct. */ |
2416 | ||
2417 | static struct gdbarch * | |
2418 | spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2419 | { | |
2420 | struct gdbarch *gdbarch; | |
794ac428 | 2421 | struct gdbarch_tdep *tdep; |
85e747d2 UW |
2422 | int id = -1; |
2423 | ||
2424 | /* Which spufs ID was requested as address space? */ | |
2425 | if (info.tdep_info) | |
2426 | id = *(int *)info.tdep_info; | |
2427 | /* For objfile architectures of SPU solibs, decode the ID from the name. | |
2428 | This assumes the filename convention employed by solib-spu.c. */ | |
2429 | else if (info.abfd) | |
2430 | { | |
2431 | char *name = strrchr (info.abfd->filename, '@'); | |
2432 | if (name) | |
2433 | sscanf (name, "@0x%*x <%d>", &id); | |
2434 | } | |
771b4502 | 2435 | |
85e747d2 UW |
2436 | /* Find a candidate among extant architectures. */ |
2437 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2438 | arches != NULL; | |
2439 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2440 | { | |
2441 | tdep = gdbarch_tdep (arches->gdbarch); | |
2442 | if (tdep && tdep->id == id) | |
2443 | return arches->gdbarch; | |
2444 | } | |
771b4502 | 2445 | |
85e747d2 | 2446 | /* None found, so create a new architecture. */ |
794ac428 | 2447 | tdep = XCALLOC (1, struct gdbarch_tdep); |
85e747d2 | 2448 | tdep->id = id; |
794ac428 | 2449 | gdbarch = gdbarch_alloc (&info, tdep); |
771b4502 UW |
2450 | |
2451 | /* Disassembler. */ | |
85e747d2 | 2452 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu); |
771b4502 UW |
2453 | |
2454 | /* Registers. */ | |
2455 | set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS); | |
2456 | set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS); | |
2457 | set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM); | |
2458 | set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM); | |
118dfbaf UW |
2459 | set_gdbarch_read_pc (gdbarch, spu_read_pc); |
2460 | set_gdbarch_write_pc (gdbarch, spu_write_pc); | |
771b4502 UW |
2461 | set_gdbarch_register_name (gdbarch, spu_register_name); |
2462 | set_gdbarch_register_type (gdbarch, spu_register_type); | |
2463 | set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read); | |
2464 | set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write); | |
9acbedc0 | 2465 | set_gdbarch_value_from_register (gdbarch, spu_value_from_register); |
771b4502 UW |
2466 | set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p); |
2467 | ||
2468 | /* Data types. */ | |
2469 | set_gdbarch_char_signed (gdbarch, 0); | |
2470 | set_gdbarch_ptr_bit (gdbarch, 32); | |
2471 | set_gdbarch_addr_bit (gdbarch, 32); | |
2472 | set_gdbarch_short_bit (gdbarch, 16); | |
2473 | set_gdbarch_int_bit (gdbarch, 32); | |
2474 | set_gdbarch_long_bit (gdbarch, 32); | |
2475 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2476 | set_gdbarch_float_bit (gdbarch, 32); | |
2477 | set_gdbarch_double_bit (gdbarch, 64); | |
2478 | set_gdbarch_long_double_bit (gdbarch, 64); | |
8da61cc4 DJ |
2479 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
2480 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
2481 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
771b4502 | 2482 | |
36acd84e | 2483 | /* Address conversion. */ |
85e747d2 | 2484 | set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer); |
36acd84e UW |
2485 | set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address); |
2486 | set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address); | |
2487 | ||
771b4502 | 2488 | /* Inferior function calls. */ |
7b3dc0b7 UW |
2489 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
2490 | set_gdbarch_frame_align (gdbarch, spu_frame_align); | |
5141027d | 2491 | set_gdbarch_frame_red_zone_size (gdbarch, 2000); |
87805e63 | 2492 | set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code); |
771b4502 | 2493 | set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call); |
8d998b8f | 2494 | set_gdbarch_dummy_id (gdbarch, spu_dummy_id); |
771b4502 UW |
2495 | set_gdbarch_return_value (gdbarch, spu_return_value); |
2496 | ||
2497 | /* Frame handling. */ | |
2498 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8d998b8f | 2499 | frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind); |
771b4502 UW |
2500 | frame_base_set_default (gdbarch, &spu_frame_base); |
2501 | set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc); | |
2502 | set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp); | |
2503 | set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer); | |
2504 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2505 | set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue); | |
fe5febed | 2506 | set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p); |
771b4502 | 2507 | |
cc5f0d61 UW |
2508 | /* Cell/B.E. cross-architecture unwinder support. */ |
2509 | frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind); | |
2510 | ||
771b4502 UW |
2511 | /* Breakpoints. */ |
2512 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
2513 | set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc); | |
2514 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); | |
2515 | set_gdbarch_software_single_step (gdbarch, spu_software_single_step); | |
6e3f70d7 | 2516 | set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target); |
771b4502 | 2517 | |
dcf52cd8 UW |
2518 | /* Overlays. */ |
2519 | set_gdbarch_overlay_update (gdbarch, spu_overlay_update); | |
2520 | ||
771b4502 UW |
2521 | return gdbarch; |
2522 | } | |
2523 | ||
63807e1d PA |
2524 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2525 | extern initialize_file_ftype _initialize_spu_tdep; | |
2526 | ||
771b4502 UW |
2527 | void |
2528 | _initialize_spu_tdep (void) | |
2529 | { | |
2530 | register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init); | |
f2d43c2c | 2531 | |
dcf52cd8 UW |
2532 | /* Add ourselves to objfile event chain. */ |
2533 | observer_attach_new_objfile (spu_overlay_new_objfile); | |
2534 | spu_overlay_data = register_objfile_data (); | |
23d964e7 | 2535 | |
3285f3fe UW |
2536 | /* Install spu stop-on-load handler. */ |
2537 | observer_attach_new_objfile (spu_catch_start); | |
2538 | ||
2539 | /* Add root prefix command for all "set spu"/"show spu" commands. */ | |
2540 | add_prefix_cmd ("spu", no_class, set_spu_command, | |
2541 | _("Various SPU specific commands."), | |
2542 | &setspucmdlist, "set spu ", 0, &setlist); | |
2543 | add_prefix_cmd ("spu", no_class, show_spu_command, | |
2544 | _("Various SPU specific commands."), | |
2545 | &showspucmdlist, "show spu ", 0, &showlist); | |
2546 | ||
2547 | /* Toggle whether or not to add a temporary breakpoint at the "main" | |
2548 | function of new SPE contexts. */ | |
2549 | add_setshow_boolean_cmd ("stop-on-load", class_support, | |
2550 | &spu_stop_on_load_p, _("\ | |
2551 | Set whether to stop for new SPE threads."), | |
2552 | _("\ | |
2553 | Show whether to stop for new SPE threads."), | |
2554 | _("\ | |
2555 | Use \"on\" to give control to the user when a new SPE thread\n\ | |
2556 | enters its \"main\" function.\n\ | |
2557 | Use \"off\" to disable stopping for new SPE threads."), | |
2558 | NULL, | |
2559 | show_spu_stop_on_load, | |
2560 | &setspucmdlist, &showspucmdlist); | |
2561 | ||
23d964e7 UW |
2562 | /* Add root prefix command for all "info spu" commands. */ |
2563 | add_prefix_cmd ("spu", class_info, info_spu_command, | |
2564 | _("Various SPU specific commands."), | |
2565 | &infospucmdlist, "info spu ", 0, &infolist); | |
2566 | ||
2567 | /* Add various "info spu" commands. */ | |
2568 | add_cmd ("event", class_info, info_spu_event_command, | |
2569 | _("Display SPU event facility status.\n"), | |
2570 | &infospucmdlist); | |
2571 | add_cmd ("signal", class_info, info_spu_signal_command, | |
2572 | _("Display SPU signal notification facility status.\n"), | |
2573 | &infospucmdlist); | |
2574 | add_cmd ("mailbox", class_info, info_spu_mailbox_command, | |
2575 | _("Display SPU mailbox facility status.\n"), | |
2576 | &infospucmdlist); | |
2577 | add_cmd ("dma", class_info, info_spu_dma_command, | |
2578 | _("Display MFC DMA status.\n"), | |
2579 | &infospucmdlist); | |
2580 | add_cmd ("proxydma", class_info, info_spu_proxydma_command, | |
2581 | _("Display MFC Proxy-DMA status.\n"), | |
2582 | &infospucmdlist); | |
771b4502 | 2583 | } |