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* gdbarch.sh (read_pc): Add REGCACHE argument. Remove PTID argument.
[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
6aba47ca 2 Copyright (C) 2006, 2007 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
23
24#include "defs.h"
25#include "arch-utils.h"
26#include "gdbtypes.h"
27#include "gdbcmd.h"
28#include "gdbcore.h"
29#include "gdb_string.h"
30#include "gdb_assert.h"
31#include "frame.h"
32#include "frame-unwind.h"
33#include "frame-base.h"
34#include "trad-frame.h"
35#include "symtab.h"
36#include "symfile.h"
37#include "value.h"
38#include "inferior.h"
39#include "dis-asm.h"
40#include "objfiles.h"
41#include "language.h"
42#include "regcache.h"
43#include "reggroups.h"
44#include "floatformat.h"
dcf52cd8 45#include "observer.h"
771b4502
UW		 46
47#include "spu-tdep.h"
48
f2d43c2c
UW		 49/* SPU-specific vector type. */
50struct type *spu_builtin_type_vec128;
771b4502 51
23d964e7
UW		 52/* The list of available "info spu " commands. */
53static struct cmd_list_element *infospucmdlist = NULL;
54
771b4502
UW		 55/* Registers. */
56
57static const char *
58spu_register_name (int reg_nr)
59{
60 static char *register_names[] =
61 {
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
63 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
64 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
65 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
66 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
67 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
68 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
69 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
70 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
71 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
72 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
73 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
74 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
75 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
76 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
77 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 78 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 79 };
80
81 if (reg_nr < 0)
82 return NULL;
83 if (reg_nr >= sizeof register_names / sizeof *register_names)
84 return NULL;
85
86 return register_names[reg_nr];
87}
88
89static struct type *
90spu_register_type (struct gdbarch *gdbarch, int reg_nr)
91{
92 if (reg_nr < SPU_NUM_GPRS)
f2d43c2c 93 return spu_builtin_type_vec128;
771b4502
UW		 94
95 switch (reg_nr)
96 {
97 case SPU_ID_REGNUM:
98 return builtin_type_uint32;
99
100 case SPU_PC_REGNUM:
101 return builtin_type_void_func_ptr;
102
103 case SPU_SP_REGNUM:
104 return builtin_type_void_data_ptr;
105
23d964e7
UW		 106 case SPU_FPSCR_REGNUM:
107 return builtin_type_uint128;
108
109 case SPU_SRR0_REGNUM:
110 return builtin_type_uint32;
111
112 case SPU_LSLR_REGNUM:
113 return builtin_type_uint32;
114
115 case SPU_DECR_REGNUM:
116 return builtin_type_uint32;
117
118 case SPU_DECR_STATUS_REGNUM:
119 return builtin_type_uint32;
120
771b4502
UW		 121 default:
122 internal_error (__FILE__, __LINE__, "invalid regnum");
123 }
124}
125
126/* Pseudo registers for preferred slots - stack pointer. */
127
23d964e7
UW		 128static void
129spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
130 gdb_byte *buf)
131{
132 gdb_byte reg[32];
133 char annex[32];
134 ULONGEST id;
135
136 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
137 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
138 memset (reg, 0, sizeof reg);
139 target_read (&current_target, TARGET_OBJECT_SPU, annex,
140 reg, 0, sizeof reg);
141
142 store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16));
143}
144
771b4502
UW		 145static void
146spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
147 int regnum, gdb_byte *buf)
148{
149 gdb_byte reg[16];
23d964e7
UW		 150 char annex[32];
151 ULONGEST id;
771b4502
UW		 152
153 switch (regnum)
154 {
155 case SPU_SP_REGNUM:
156 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
157 memcpy (buf, reg, 4);
158 break;
159
23d964e7
UW		 160 case SPU_FPSCR_REGNUM:
161 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
162 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
163 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
164 break;
165
166 case SPU_SRR0_REGNUM:
167 spu_pseudo_register_read_spu (regcache, "srr0", buf);
168 break;
169
170 case SPU_LSLR_REGNUM:
171 spu_pseudo_register_read_spu (regcache, "lslr", buf);
172 break;
173
174 case SPU_DECR_REGNUM:
175 spu_pseudo_register_read_spu (regcache, "decr", buf);
176 break;
177
178 case SPU_DECR_STATUS_REGNUM:
179 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
180 break;
181
771b4502
UW		 182 default:
183 internal_error (__FILE__, __LINE__, _("invalid regnum"));
184 }
185}
186
23d964e7
UW		 187static void
188spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
189 const gdb_byte *buf)
190{
191 gdb_byte reg[32];
192 char annex[32];
193 ULONGEST id;
194
195 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
196 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
197 xsnprintf (reg, sizeof reg, "0x%s",
198 phex_nz (extract_unsigned_integer (buf, 4), 4));
199 target_write (&current_target, TARGET_OBJECT_SPU, annex,
200 reg, 0, strlen (reg));
201}
202
771b4502
UW		 203static void
204spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
205 int regnum, const gdb_byte *buf)
206{
207 gdb_byte reg[16];
23d964e7
UW		 208 char annex[32];
209 ULONGEST id;
771b4502
UW		 210
211 switch (regnum)
212 {
213 case SPU_SP_REGNUM:
214 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
215 memcpy (reg, buf, 4);
216 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
217 break;
218
23d964e7
UW		 219 case SPU_FPSCR_REGNUM:
220 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
221 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
222 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
223 break;
224
225 case SPU_SRR0_REGNUM:
226 spu_pseudo_register_write_spu (regcache, "srr0", buf);
227 break;
228
229 case SPU_LSLR_REGNUM:
230 spu_pseudo_register_write_spu (regcache, "lslr", buf);
231 break;
232
233 case SPU_DECR_REGNUM:
234 spu_pseudo_register_write_spu (regcache, "decr", buf);
235 break;
236
237 case SPU_DECR_STATUS_REGNUM:
238 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
239 break;
240
771b4502
UW		 241 default:
242 internal_error (__FILE__, __LINE__, _("invalid regnum"));
243 }
244}
245
246/* Value conversion -- access scalar values at the preferred slot. */
247
9acbedc0
UW		 248static struct value *
249spu_value_from_register (struct type *type, int regnum,
250 struct frame_info *frame)
771b4502 251{
9acbedc0
UW		 252 struct value *value = default_value_from_register (type, regnum, frame);
253 int len = TYPE_LENGTH (type);
771b4502 254
9acbedc0
UW		 255 if (regnum < SPU_NUM_GPRS && len < 16)
256 {
257 int preferred_slot = len < 4 ? 4 - len : 0;
258 set_value_offset (value, preferred_slot);
259 }
771b4502 260
9acbedc0 261 return value;
771b4502
UW		 262}
263
264/* Register groups. */
265
266static int
267spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
268 struct reggroup *group)
269{
270 /* Registers displayed via 'info regs'. */
271 if (group == general_reggroup)
272 return 1;
273
274 /* Registers displayed via 'info float'. */
275 if (group == float_reggroup)
276 return 0;
277
278 /* Registers that need to be saved/restored in order to
279 push or pop frames. */
280 if (group == save_reggroup || group == restore_reggroup)
281 return 1;
282
283 return default_register_reggroup_p (gdbarch, regnum, group);
284}
285
286
287/* Decoding SPU instructions. */
288
289enum
290 {
291 op_lqd = 0x34,
292 op_lqx = 0x3c4,
293 op_lqa = 0x61,
294 op_lqr = 0x67,
295 op_stqd = 0x24,
296 op_stqx = 0x144,
297 op_stqa = 0x41,
298 op_stqr = 0x47,
299
300 op_il = 0x081,
301 op_ila = 0x21,
302 op_a = 0x0c0,
303 op_ai = 0x1c,
304
305 op_selb = 0x4,
306
307 op_br = 0x64,
308 op_bra = 0x60,
309 op_brsl = 0x66,
310 op_brasl = 0x62,
311 op_brnz = 0x42,
312 op_brz = 0x40,
313 op_brhnz = 0x46,
314 op_brhz = 0x44,
315 op_bi = 0x1a8,
316 op_bisl = 0x1a9,
317 op_biz = 0x128,
318 op_binz = 0x129,
319 op_bihz = 0x12a,
320 op_bihnz = 0x12b,
321 };
322
323static int
324is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
325{
326 if ((insn >> 21) == op)
327 {
328 *rt = insn & 127;
329 *ra = (insn >> 7) & 127;
330 *rb = (insn >> 14) & 127;
331 return 1;
332 }
333
334 return 0;
335}
336
337static int
338is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
339{
340 if ((insn >> 28) == op)
341 {
342 *rt = (insn >> 21) & 127;
343 *ra = (insn >> 7) & 127;
344 *rb = (insn >> 14) & 127;
345 *rc = insn & 127;
346 return 1;
347 }
348
349 return 0;
350}
351
352static int
353is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
354{
355 if ((insn >> 21) == op)
356 {
357 *rt = insn & 127;
358 *ra = (insn >> 7) & 127;
359 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
360 return 1;
361 }
362
363 return 0;
364}
365
366static int
367is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
368{
369 if ((insn >> 24) == op)
370 {
371 *rt = insn & 127;
372 *ra = (insn >> 7) & 127;
373 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
374 return 1;
375 }
376
377 return 0;
378}
379
380static int
381is_ri16 (unsigned int insn, int op, int *rt, int *i16)
382{
383 if ((insn >> 23) == op)
384 {
385 *rt = insn & 127;
386 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
387 return 1;
388 }
389
390 return 0;
391}
392
393static int
394is_ri18 (unsigned int insn, int op, int *rt, int *i18)
395{
396 if ((insn >> 25) == op)
397 {
398 *rt = insn & 127;
399 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
400 return 1;
401 }
402
403 return 0;
404}
405
406static int
407is_branch (unsigned int insn, int *offset, int *reg)
408{
409 int rt, i7, i16;
410
411 if (is_ri16 (insn, op_br, &rt, &i16)
412 || is_ri16 (insn, op_brsl, &rt, &i16)
413 || is_ri16 (insn, op_brnz, &rt, &i16)
414 || is_ri16 (insn, op_brz, &rt, &i16)
415 || is_ri16 (insn, op_brhnz, &rt, &i16)
416 || is_ri16 (insn, op_brhz, &rt, &i16))
417 {
418 *reg = SPU_PC_REGNUM;
419 *offset = i16 << 2;
420 return 1;
421 }
422
423 if (is_ri16 (insn, op_bra, &rt, &i16)
424 || is_ri16 (insn, op_brasl, &rt, &i16))
425 {
426 *reg = -1;
427 *offset = i16 << 2;
428 return 1;
429 }
430
431 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
432 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
433 || is_ri7 (insn, op_biz, &rt, reg, &i7)
434 || is_ri7 (insn, op_binz, &rt, reg, &i7)
435 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
436 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
437 {
438 *offset = 0;
439 return 1;
440 }
441
442 return 0;
443}
444
445
446/* Prolog parsing. */
447
448struct spu_prologue_data
449 {
450 /* Stack frame size. -1 if analysis was unsuccessful. */
451 int size;
452
453 /* How to find the CFA. The CFA is equal to SP at function entry. */
454 int cfa_reg;
455 int cfa_offset;
456
457 /* Offset relative to CFA where a register is saved. -1 if invalid. */
458 int reg_offset[SPU_NUM_GPRS];
459 };
460
461static CORE_ADDR
462spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
463 struct spu_prologue_data *data)
464{
465 int found_sp = 0;
466 int found_fp = 0;
467 int found_lr = 0;
468 int reg_immed[SPU_NUM_GPRS];
469 gdb_byte buf[16];
470 CORE_ADDR prolog_pc = start_pc;
471 CORE_ADDR pc;
472 int i;
473
474
475 /* Initialize DATA to default values. */
476 data->size = -1;
477
478 data->cfa_reg = SPU_RAW_SP_REGNUM;
479 data->cfa_offset = 0;
480
481 for (i = 0; i < SPU_NUM_GPRS; i++)
482 data->reg_offset[i] = -1;
483
484 /* Set up REG_IMMED array. This is non-zero for a register if we know its
485 preferred slot currently holds this immediate value. */
486 for (i = 0; i < SPU_NUM_GPRS; i++)
487 reg_immed[i] = 0;
488
489 /* Scan instructions until the first branch.
490
491 The following instructions are important prolog components:
492
493 - The first instruction to set up the stack pointer.
494 - The first instruction to set up the frame pointer.
495 - The first instruction to save the link register.
496
497 We return the instruction after the latest of these three,
498 or the incoming PC if none is found. The first instruction
499 to set up the stack pointer also defines the frame size.
500
501 Note that instructions saving incoming arguments to their stack
502 slots are not counted as important, because they are hard to
503 identify with certainty. This should not matter much, because
504 arguments are relevant only in code compiled with debug data,
505 and in such code the GDB core will advance until the first source
506 line anyway, using SAL data.
507
508 For purposes of stack unwinding, we analyze the following types
509 of instructions in addition:
510
511 - Any instruction adding to the current frame pointer.
512 - Any instruction loading an immediate constant into a register.
513 - Any instruction storing a register onto the stack.
514
515 These are used to compute the CFA and REG_OFFSET output. */
516
517 for (pc = start_pc; pc < end_pc; pc += 4)
518 {
519 unsigned int insn;
520 int rt, ra, rb, rc, immed;
521
522 if (target_read_memory (pc, buf, 4))
523 break;
524 insn = extract_unsigned_integer (buf, 4);
525
526 /* AI is the typical instruction to set up a stack frame.
527 It is also used to initialize the frame pointer. */
528 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
529 {
530 if (rt == data->cfa_reg && ra == data->cfa_reg)
531 data->cfa_offset -= immed;
532
533 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
534 && !found_sp)
535 {
536 found_sp = 1;
537 prolog_pc = pc + 4;
538
539 data->size = -immed;
540 }
541 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
542 && !found_fp)
543 {
544 found_fp = 1;
545 prolog_pc = pc + 4;
546
547 data->cfa_reg = SPU_FP_REGNUM;
548 data->cfa_offset -= immed;
549 }
550 }
551
552 /* A is used to set up stack frames of size >= 512 bytes.
553 If we have tracked the contents of the addend register,
554 we can handle this as well. */
555 else if (is_rr (insn, op_a, &rt, &ra, &rb))
556 {
557 if (rt == data->cfa_reg && ra == data->cfa_reg)
558 {
559 if (reg_immed[rb] != 0)
560 data->cfa_offset -= reg_immed[rb];
561 else
562 data->cfa_reg = -1; /* We don't know the CFA any more. */
563 }
564
565 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
566 && !found_sp)
567 {
568 found_sp = 1;
569 prolog_pc = pc + 4;
570
571 if (reg_immed[rb] != 0)
572 data->size = -reg_immed[rb];
573 }
574 }
575
576 /* We need to track IL and ILA used to load immediate constants
577 in case they are later used as input to an A instruction. */
578 else if (is_ri16 (insn, op_il, &rt, &immed))
579 {
580 reg_immed[rt] = immed;
12102450
UW		 581
582 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
583 found_sp = 1;
771b4502
UW		 584 }
585
586 else if (is_ri18 (insn, op_ila, &rt, &immed))
587 {
588 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 589
590 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
591 found_sp = 1;
771b4502
UW		 592 }
593
594 /* STQD is used to save registers to the stack. */
595 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
596 {
597 if (ra == data->cfa_reg)
598 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
599
600 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
601 && !found_lr)
602 {
603 found_lr = 1;
604 prolog_pc = pc + 4;
605 }
606 }
607
608 /* _start uses SELB to set up the stack pointer. */
609 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
610 {
611 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
612 found_sp = 1;
613 }
614
615 /* We terminate if we find a branch. */
616 else if (is_branch (insn, &immed, &ra))
617 break;
618 }
619
620
621 /* If we successfully parsed until here, and didn't find any instruction
622 modifying SP, we assume we have a frameless function. */
623 if (!found_sp)
624 data->size = 0;
625
626 /* Return cooked instead of raw SP. */
627 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
628 data->cfa_reg = SPU_SP_REGNUM;
629
630 return prolog_pc;
631}
632
633/* Return the first instruction after the prologue starting at PC. */
634static CORE_ADDR
635spu_skip_prologue (CORE_ADDR pc)
636{
637 struct spu_prologue_data data;
638 return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
639}
640
641/* Return the frame pointer in use at address PC. */
642static void
643spu_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset)
644{
645 struct spu_prologue_data data;
646 spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
647
648 if (data.size != -1 && data.cfa_reg != -1)
649 {
650 /* The 'frame pointer' address is CFA minus frame size. */
651 *reg = data.cfa_reg;
652 *offset = data.cfa_offset - data.size;
653 }
654 else
655 {
656 /* ??? We don't really know ... */
657 *reg = SPU_SP_REGNUM;
658 *offset = 0;
659 }
660}
661
fe5febed
UW		 662/* Return true if we are in the function's epilogue, i.e. after the
663 instruction that destroyed the function's stack frame.
664
665 1) scan forward from the point of execution:
666 a) If you find an instruction that modifies the stack pointer
667 or transfers control (except a return), execution is not in
668 an epilogue, return.
669 b) Stop scanning if you find a return instruction or reach the
670 end of the function or reach the hard limit for the size of
671 an epilogue.
672 2) scan backward from the point of execution:
673 a) If you find an instruction that modifies the stack pointer,
674 execution *is* in an epilogue, return.
675 b) Stop scanning if you reach an instruction that transfers
676 control or the beginning of the function or reach the hard
677 limit for the size of an epilogue. */
678
679static int
680spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
681{
682 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
683 bfd_byte buf[4];
684 unsigned int insn;
685 int rt, ra, rb, rc, immed;
686
687 /* Find the search limits based on function boundaries and hard limit.
688 We assume the epilogue can be up to 64 instructions long. */
689
690 const int spu_max_epilogue_size = 64 * 4;
691
692 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
693 return 0;
694
695 if (pc - func_start < spu_max_epilogue_size)
696 epilogue_start = func_start;
697 else
698 epilogue_start = pc - spu_max_epilogue_size;
699
700 if (func_end - pc < spu_max_epilogue_size)
701 epilogue_end = func_end;
702 else
703 epilogue_end = pc + spu_max_epilogue_size;
704
705 /* Scan forward until next 'bi $0'. */
706
707 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
708 {
709 if (target_read_memory (scan_pc, buf, 4))
710 return 0;
711 insn = extract_unsigned_integer (buf, 4);
712
713 if (is_branch (insn, &immed, &ra))
714 {
715 if (immed == 0 && ra == SPU_LR_REGNUM)
716 break;
717
718 return 0;
719 }
720
721 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
722 || is_rr (insn, op_a, &rt, &ra, &rb)
723 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
724 {
725 if (rt == SPU_RAW_SP_REGNUM)
726 return 0;
727 }
728 }
729
730 if (scan_pc >= epilogue_end)
731 return 0;
732
733 /* Scan backward until adjustment to stack pointer (R1). */
734
735 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
736 {
737 if (target_read_memory (scan_pc, buf, 4))
738 return 0;
739 insn = extract_unsigned_integer (buf, 4);
740
741 if (is_branch (insn, &immed, &ra))
742 return 0;
743
744 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
745 || is_rr (insn, op_a, &rt, &ra, &rb)
746 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
747 {
748 if (rt == SPU_RAW_SP_REGNUM)
749 return 1;
750 }
751 }
752
753 return 0;
754}
755
756
771b4502
UW		 757/* Normal stack frames. */
758
759struct spu_unwind_cache
760{
761 CORE_ADDR func;
762 CORE_ADDR frame_base;
763 CORE_ADDR local_base;
764
765 struct trad_frame_saved_reg *saved_regs;
766};
767
768static struct spu_unwind_cache *
769spu_frame_unwind_cache (struct frame_info *next_frame,
770 void **this_prologue_cache)
771{
772 struct spu_unwind_cache *info;
773 struct spu_prologue_data data;
dcf52cd8 774 gdb_byte buf[16];
771b4502
UW		 775
776 if (*this_prologue_cache)
777 return *this_prologue_cache;
778
779 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
780 *this_prologue_cache = info;
781 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
782 info->frame_base = 0;
783 info->local_base = 0;
784
785 /* Find the start of the current function, and analyze its prologue. */
93d42b30 786 info->func = frame_func_unwind (next_frame, NORMAL_FRAME);
771b4502
UW		 787 if (info->func == 0)
788 {
789 /* Fall back to using the current PC as frame ID. */
790 info->func = frame_pc_unwind (next_frame);
791 data.size = -1;
792 }
793 else
794 spu_analyze_prologue (info->func, frame_pc_unwind (next_frame), &data);
795
796
797 /* If successful, use prologue analysis data. */
798 if (data.size != -1 && data.cfa_reg != -1)
799 {
800 CORE_ADDR cfa;
801 int i;
771b4502
UW		 802
803 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
804 frame_unwind_register (next_frame, data.cfa_reg, buf);
805 cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
806
807 /* Call-saved register slots. */
808 for (i = 0; i < SPU_NUM_GPRS; i++)
809 if (i == SPU_LR_REGNUM
810 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
811 if (data.reg_offset[i] != -1)
812 info->saved_regs[i].addr = cfa - data.reg_offset[i];
813
771b4502
UW		 814 /* Frame bases. */
815 info->frame_base = cfa;
816 info->local_base = cfa - data.size;
817 }
818
819 /* Otherwise, fall back to reading the backchain link. */
820 else
821 {
822 CORE_ADDR reg, backchain;
823
824 /* Get the backchain. */
825 reg = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
826 backchain = read_memory_unsigned_integer (reg, 4);
827
828 /* A zero backchain terminates the frame chain. Also, sanity
829 check against the local store size limit. */
830 if (backchain != 0 && backchain < SPU_LS_SIZE)
831 {
832 /* Assume the link register is saved into its slot. */
833 if (backchain + 16 < SPU_LS_SIZE)
834 info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
835
771b4502
UW		 836 /* Frame bases. */
837 info->frame_base = backchain;
838 info->local_base = reg;
839 }
840 }
dcf52cd8
UW		 841
842 /* The previous SP is equal to the CFA. */
843 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base);
844
0a44cb36
UW		 845 /* Read full contents of the unwound link register in order to
846 be able to determine the return address. */
dcf52cd8
UW		 847 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
848 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
849 else
850 frame_unwind_register (next_frame, SPU_LR_REGNUM, buf);
851
0a44cb36
UW		 852 /* Normally, the return address is contained in the slot 0 of the
853 link register, and slots 1-3 are zero. For an overlay return,
854 slot 0 contains the address of the overlay manager return stub,
855 slot 1 contains the partition number of the overlay section to
856 be returned to, and slot 2 contains the return address within
857 that section. Return the latter address in that case. */
dcf52cd8
UW		 858 if (extract_unsigned_integer (buf + 8, 4) != 0)
859 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
860 extract_unsigned_integer (buf + 8, 4));
861 else
862 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
863 extract_unsigned_integer (buf, 4));
771b4502
UW		 864
865 return info;
866}
867
868static void
869spu_frame_this_id (struct frame_info *next_frame,
870 void **this_prologue_cache, struct frame_id *this_id)
871{
872 struct spu_unwind_cache *info =
873 spu_frame_unwind_cache (next_frame, this_prologue_cache);
874
875 if (info->frame_base == 0)
876 return;
877
878 *this_id = frame_id_build (info->frame_base, info->func);
879}
880
881static void
882spu_frame_prev_register (struct frame_info *next_frame,
883 void **this_prologue_cache,
884 int regnum, int *optimizedp,
885 enum lval_type *lvalp, CORE_ADDR * addrp,
886 int *realnump, gdb_byte *bufferp)
887{
888 struct spu_unwind_cache *info
889 = spu_frame_unwind_cache (next_frame, this_prologue_cache);
890
891 /* Special-case the stack pointer. */
892 if (regnum == SPU_RAW_SP_REGNUM)
893 regnum = SPU_SP_REGNUM;
894
895 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
896 optimizedp, lvalp, addrp, realnump, bufferp);
897}
898
899static const struct frame_unwind spu_frame_unwind = {
900 NORMAL_FRAME,
901 spu_frame_this_id,
902 spu_frame_prev_register
903};
904
905const struct frame_unwind *
906spu_frame_sniffer (struct frame_info *next_frame)
907{
908 return &spu_frame_unwind;
909}
910
911static CORE_ADDR
912spu_frame_base_address (struct frame_info *next_frame, void **this_cache)
913{
914 struct spu_unwind_cache *info
915 = spu_frame_unwind_cache (next_frame, this_cache);
916 return info->local_base;
917}
918
919static const struct frame_base spu_frame_base = {
920 &spu_frame_unwind,
921 spu_frame_base_address,
922 spu_frame_base_address,
923 spu_frame_base_address
924};
925
926static CORE_ADDR
927spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
928{
118dfbaf
UW		 929 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
930 /* Mask off interrupt enable bit. */
931 return pc & -4;
771b4502
UW		 932}
933
934static CORE_ADDR
935spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
936{
937 return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
938}
939
118dfbaf 940static CORE_ADDR
61a1198a 941spu_read_pc (struct regcache *regcache)
118dfbaf 942{
61a1198a
UW		 943 ULONGEST pc;
944 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf
UW		 945 /* Mask off interrupt enable bit. */
946 return pc & -4;
947}
948
949static void
61a1198a 950spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 951{
952 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 953 ULONGEST old_pc;
954 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
955 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
956 (pc & -4) | (old_pc & 3));
118dfbaf
UW		 957}
958
771b4502
UW		 959
960/* Function calling convention. */
961
7b3dc0b7
UW		 962static CORE_ADDR
963spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
964{
965 return sp & ~15;
966}
967
771b4502
UW		 968static int
969spu_scalar_value_p (struct type *type)
970{
971 switch (TYPE_CODE (type))
972 {
973 case TYPE_CODE_INT:
974 case TYPE_CODE_ENUM:
975 case TYPE_CODE_RANGE:
976 case TYPE_CODE_CHAR:
977 case TYPE_CODE_BOOL:
978 case TYPE_CODE_PTR:
979 case TYPE_CODE_REF:
980 return TYPE_LENGTH (type) <= 16;
981
982 default:
983 return 0;
984 }
985}
986
987static void
988spu_value_to_regcache (struct regcache *regcache, int regnum,
989 struct type *type, const gdb_byte *in)
990{
991 int len = TYPE_LENGTH (type);
992
993 if (spu_scalar_value_p (type))
994 {
995 int preferred_slot = len < 4 ? 4 - len : 0;
996 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
997 }
998 else
999 {
1000 while (len >= 16)
1001 {
1002 regcache_cooked_write (regcache, regnum++, in);
1003 in += 16;
1004 len -= 16;
1005 }
1006
1007 if (len > 0)
1008 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1009 }
1010}
1011
1012static void
1013spu_regcache_to_value (struct regcache *regcache, int regnum,
1014 struct type *type, gdb_byte *out)
1015{
1016 int len = TYPE_LENGTH (type);
1017
1018 if (spu_scalar_value_p (type))
1019 {
1020 int preferred_slot = len < 4 ? 4 - len : 0;
1021 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1022 }
1023 else
1024 {
1025 while (len >= 16)
1026 {
1027 regcache_cooked_read (regcache, regnum++, out);
1028 out += 16;
1029 len -= 16;
1030 }
1031
1032 if (len > 0)
1033 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1034 }
1035}
1036
1037static CORE_ADDR
1038spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1039 struct regcache *regcache, CORE_ADDR bp_addr,
1040 int nargs, struct value **args, CORE_ADDR sp,
1041 int struct_return, CORE_ADDR struct_addr)
1042{
1043 int i;
1044 int regnum = SPU_ARG1_REGNUM;
1045 int stack_arg = -1;
1046 gdb_byte buf[16];
1047
1048 /* Set the return address. */
1049 memset (buf, 0, sizeof buf);
1050 store_unsigned_integer (buf, 4, bp_addr);
1051 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1052
1053 /* If STRUCT_RETURN is true, then the struct return address (in
1054 STRUCT_ADDR) will consume the first argument-passing register.
1055 Both adjust the register count and store that value. */
1056 if (struct_return)
1057 {
1058 memset (buf, 0, sizeof buf);
1059 store_unsigned_integer (buf, 4, struct_addr);
1060 regcache_cooked_write (regcache, regnum++, buf);
1061 }
1062
1063 /* Fill in argument registers. */
1064 for (i = 0; i < nargs; i++)
1065 {
1066 struct value *arg = args[i];
1067 struct type *type = check_typedef (value_type (arg));
1068 const gdb_byte *contents = value_contents (arg);
1069 int len = TYPE_LENGTH (type);
1070 int n_regs = align_up (len, 16) / 16;
1071
1072 /* If the argument doesn't wholly fit into registers, it and
1073 all subsequent arguments go to the stack. */
1074 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1075 {
1076 stack_arg = i;
1077 break;
1078 }
1079
1080 spu_value_to_regcache (regcache, regnum, type, contents);
1081 regnum += n_regs;
1082 }
1083
1084 /* Overflow arguments go to the stack. */
1085 if (stack_arg != -1)
1086 {
1087 CORE_ADDR ap;
1088
1089 /* Allocate all required stack size. */
1090 for (i = stack_arg; i < nargs; i++)
1091 {
1092 struct type *type = check_typedef (value_type (args[i]));
1093 sp -= align_up (TYPE_LENGTH (type), 16);
1094 }
1095
1096 /* Fill in stack arguments. */
1097 ap = sp;
1098 for (i = stack_arg; i < nargs; i++)
1099 {
1100 struct value *arg = args[i];
1101 struct type *type = check_typedef (value_type (arg));
1102 int len = TYPE_LENGTH (type);
1103 int preferred_slot;
1104
1105 if (spu_scalar_value_p (type))
1106 preferred_slot = len < 4 ? 4 - len : 0;
1107 else
1108 preferred_slot = 0;
1109
1110 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1111 ap += align_up (TYPE_LENGTH (type), 16);
1112 }
1113 }
1114
1115 /* Allocate stack frame header. */
1116 sp -= 32;
1117
ee82e879
UW		 1118 /* Store stack back chain. */
1119 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1120 target_write_memory (sp, buf, 16);
1121
771b4502
UW		 1122 /* Finally, update the SP register. */
1123 regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp);
1124
1125 return sp;
1126}
1127
1128static struct frame_id
1129spu_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1130{
1131 return frame_id_build (spu_unwind_sp (gdbarch, next_frame),
1132 spu_unwind_pc (gdbarch, next_frame));
1133}
1134
1135/* Function return value access. */
1136
1137static enum return_value_convention
1138spu_return_value (struct gdbarch *gdbarch, struct type *type,
1139 struct regcache *regcache, gdb_byte *out, const gdb_byte *in)
1140{
1141 enum return_value_convention rvc;
1142
1143 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1144 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1145 else
1146 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1147
1148 if (in)
1149 {
1150 switch (rvc)
1151 {
1152 case RETURN_VALUE_REGISTER_CONVENTION:
1153 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1154 break;
1155
1156 case RETURN_VALUE_STRUCT_CONVENTION:
1157 error ("Cannot set function return value.");
1158 break;
1159 }
1160 }
1161 else if (out)
1162 {
1163 switch (rvc)
1164 {
1165 case RETURN_VALUE_REGISTER_CONVENTION:
1166 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1167 break;
1168
1169 case RETURN_VALUE_STRUCT_CONVENTION:
1170 error ("Function return value unknown.");
1171 break;
1172 }
1173 }
1174
1175 return rvc;
1176}
1177
1178
1179/* Breakpoints. */
1180
1181static const gdb_byte *
1182spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
1183{
1184 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1185
1186 *lenptr = sizeof breakpoint;
1187 return breakpoint;
1188}
1189
1190
1191/* Software single-stepping support. */
1192
e6590a1b 1193int
0b1b3e42 1194spu_software_single_step (struct frame_info *frame)
771b4502 1195{
e0cd558a
UW		 1196 CORE_ADDR pc, next_pc;
1197 unsigned int insn;
1198 int offset, reg;
1199 gdb_byte buf[4];
771b4502 1200
0b1b3e42 1201 pc = get_frame_pc (frame);
771b4502 1202
e0cd558a
UW		 1203 if (target_read_memory (pc, buf, 4))
1204 return 1;
1205 insn = extract_unsigned_integer (buf, 4);
771b4502 1206
e0cd558a
UW		 1207 /* Next sequential instruction is at PC + 4, except if the current
1208 instruction is a PPE-assisted call, in which case it is at PC + 8.
1209 Wrap around LS limit to be on the safe side. */
1210 if ((insn & 0xffffff00) == 0x00002100)
1211 next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
1212 else
1213 next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
771b4502 1214
e0cd558a 1215 insert_single_step_breakpoint (next_pc);
771b4502 1216
e0cd558a
UW		 1217 if (is_branch (insn, &offset, &reg))
1218 {
1219 CORE_ADDR target = offset;
771b4502 1220
e0cd558a
UW		 1221 if (reg == SPU_PC_REGNUM)
1222 target += pc;
1223 else if (reg != -1)
1224 {
0b1b3e42 1225 get_frame_register_bytes (frame, reg, 0, 4, buf);
e0cd558a 1226 target += extract_unsigned_integer (buf, 4) & -4;
771b4502 1227 }
e0cd558a
UW		 1228
1229 target = target & (SPU_LS_SIZE - 1);
1230 if (target != next_pc)
1231 insert_single_step_breakpoint (target);
771b4502 1232 }
e6590a1b
UW		 1233
1234 return 1;
771b4502
UW		 1235}
1236
dcf52cd8
UW		 1237/* Target overlays for the SPU overlay manager.
1238
1239 See the documentation of simple_overlay_update for how the
1240 interface is supposed to work.
1241
1242 Data structures used by the overlay manager:
1243
1244 struct ovly_table
1245 {
1246 u32 vma;
1247 u32 size;
1248 u32 pos;
1249 u32 buf;
1250 } _ovly_table[]; -- one entry per overlay section
1251
1252 struct ovly_buf_table
1253 {
1254 u32 mapped;
1255 } _ovly_buf_table[]; -- one entry per overlay buffer
1256
1257 _ovly_table should never change.
1258
1259 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1260 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1261 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1262
1263 mapped is an index into _ovly_table. Both the mapped and buf indices start
1264 from one to reference the first entry in their respective tables. */
1265
1266/* Using the per-objfile private data mechanism, we store for each
1267 objfile an array of "struct spu_overlay_table" structures, one
1268 for each obj_section of the objfile. This structure holds two
1269 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1270 is *not* an overlay section. If it is non-zero, it represents
1271 a target address. The overlay section is mapped iff the target
1272 integer at this location equals MAPPED_VAL. */
1273
1274static const struct objfile_data *spu_overlay_data;
1275
1276struct spu_overlay_table
1277 {
1278 CORE_ADDR mapped_ptr;
1279 CORE_ADDR mapped_val;
1280 };
1281
1282/* Retrieve the overlay table for OBJFILE. If not already cached, read
1283 the _ovly_table data structure from the target and initialize the
1284 spu_overlay_table data structure from it. */
1285static struct spu_overlay_table *
1286spu_get_overlay_table (struct objfile *objfile)
1287{
1288 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1289 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1290 unsigned ovly_table_size, ovly_buf_table_size;
1291 struct spu_overlay_table *tbl;
1292 struct obj_section *osect;
1293 char *ovly_table;
1294 int i;
1295
1296 tbl = objfile_data (objfile, spu_overlay_data);
1297 if (tbl)
1298 return tbl;
1299
1300 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1301 if (!ovly_table_msym)
1302 return NULL;
1303
1304 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1305 if (!ovly_buf_table_msym)
1306 return NULL;
1307
1308 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1309 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1310
1311 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1312 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1313
1314 ovly_table = xmalloc (ovly_table_size);
1315 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1316
1317 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1318 objfile->sections_end - objfile->sections,
1319 struct spu_overlay_table);
1320
1321 for (i = 0; i < ovly_table_size / 16; i++)
1322 {
1323 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, 4);
1324 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4);
1325 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, 4);
1326 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, 4);
1327
1328 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1329 continue;
1330
1331 ALL_OBJFILE_OSECTIONS (objfile, osect)
1332 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1333 && pos == osect->the_bfd_section->filepos)
1334 {
1335 int ndx = osect - objfile->sections;
1336 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1337 tbl[ndx].mapped_val = i + 1;
1338 break;
1339 }
1340 }
1341
1342 xfree (ovly_table);
1343 set_objfile_data (objfile, spu_overlay_data, tbl);
1344 return tbl;
1345}
1346
1347/* Read _ovly_buf_table entry from the target to dermine whether
1348 OSECT is currently mapped, and update the mapped state. */
1349static void
1350spu_overlay_update_osect (struct obj_section *osect)
1351{
1352 struct spu_overlay_table *ovly_table;
1353 CORE_ADDR val;
1354
1355 ovly_table = spu_get_overlay_table (osect->objfile);
1356 if (!ovly_table)
1357 return;
1358
1359 ovly_table += osect - osect->objfile->sections;
1360 if (ovly_table->mapped_ptr == 0)
1361 return;
1362
1363 val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4);
1364 osect->ovly_mapped = (val == ovly_table->mapped_val);
1365}
1366
1367/* If OSECT is NULL, then update all sections' mapped state.
1368 If OSECT is non-NULL, then update only OSECT's mapped state. */
1369static void
1370spu_overlay_update (struct obj_section *osect)
1371{
1372 /* Just one section. */
1373 if (osect)
1374 spu_overlay_update_osect (osect);
1375
1376 /* All sections. */
1377 else
1378 {
1379 struct objfile *objfile;
1380
1381 ALL_OBJSECTIONS (objfile, osect)
1382 if (section_is_overlay (osect->the_bfd_section))
1383 spu_overlay_update_osect (osect);
1384 }
1385}
1386
1387/* Whenever a new objfile is loaded, read the target's _ovly_table.
1388 If there is one, go through all sections and make sure for non-
1389 overlay sections LMA equals VMA, while for overlay sections LMA
1390 is larger than local store size. */
1391static void
1392spu_overlay_new_objfile (struct objfile *objfile)
1393{
1394 struct spu_overlay_table *ovly_table;
1395 struct obj_section *osect;
1396
1397 /* If we've already touched this file, do nothing. */
1398 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1399 return;
1400
1401 /* Check if this objfile has overlays. */
1402 ovly_table = spu_get_overlay_table (objfile);
1403 if (!ovly_table)
1404 return;
1405
1406 /* Now go and fiddle with all the LMAs. */
1407 ALL_OBJFILE_OSECTIONS (objfile, osect)
1408 {
1409 bfd *obfd = objfile->obfd;
1410 asection *bsect = osect->the_bfd_section;
1411 int ndx = osect - objfile->sections;
1412
1413 if (ovly_table[ndx].mapped_ptr == 0)
1414 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1415 else
1416 bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1417 }
1418}
1419
771b4502 1420
23d964e7
UW		 1421/* "info spu" commands. */
1422
1423static void
1424info_spu_event_command (char *args, int from_tty)
1425{
1426 struct frame_info *frame = get_selected_frame (NULL);
1427 ULONGEST event_status = 0;
1428 ULONGEST event_mask = 0;
1429 struct cleanup *chain;
1430 gdb_byte buf[100];
1431 char annex[32];
1432 LONGEST len;
1433 int rc, id;
1434
1435 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1436
1437 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1438 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1439 buf, 0, sizeof buf);
1440 if (len <= 0)
1441 error (_("Could not read event_status."));
1442 event_status = strtoulst (buf, NULL, 16);
1443
1444 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1445 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1446 buf, 0, sizeof buf);
1447 if (len <= 0)
1448 error (_("Could not read event_mask."));
1449 event_mask = strtoulst (buf, NULL, 16);
1450
1451 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1452
1453 if (ui_out_is_mi_like_p (uiout))
1454 {
1455 ui_out_field_fmt (uiout, "event_status",
1456 "0x%s", phex_nz (event_status, 4));
1457 ui_out_field_fmt (uiout, "event_mask",
1458 "0x%s", phex_nz (event_mask, 4));
1459 }
1460 else
1461 {
1462 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1463 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1464 }
1465
1466 do_cleanups (chain);
1467}
1468
1469static void
1470info_spu_signal_command (char *args, int from_tty)
1471{
1472 struct frame_info *frame = get_selected_frame (NULL);
1473 ULONGEST signal1 = 0;
1474 ULONGEST signal1_type = 0;
1475 int signal1_pending = 0;
1476 ULONGEST signal2 = 0;
1477 ULONGEST signal2_type = 0;
1478 int signal2_pending = 0;
1479 struct cleanup *chain;
1480 char annex[32];
1481 gdb_byte buf[100];
1482 LONGEST len;
1483 int rc, id;
1484
1485 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1486
1487 xsnprintf (annex, sizeof annex, "%d/signal1", id);
1488 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1489 if (len < 0)
1490 error (_("Could not read signal1."));
1491 else if (len == 4)
1492 {
1493 signal1 = extract_unsigned_integer (buf, 4);
1494 signal1_pending = 1;
1495 }
1496
1497 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
1498 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1499 buf, 0, sizeof buf);
1500 if (len <= 0)
1501 error (_("Could not read signal1_type."));
1502 signal1_type = strtoulst (buf, NULL, 16);
1503
1504 xsnprintf (annex, sizeof annex, "%d/signal2", id);
1505 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1506 if (len < 0)
1507 error (_("Could not read signal2."));
1508 else if (len == 4)
1509 {
1510 signal2 = extract_unsigned_integer (buf, 4);
1511 signal2_pending = 1;
1512 }
1513
1514 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
1515 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1516 buf, 0, sizeof buf);
1517 if (len <= 0)
1518 error (_("Could not read signal2_type."));
1519 signal2_type = strtoulst (buf, NULL, 16);
1520
1521 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
1522
1523 if (ui_out_is_mi_like_p (uiout))
1524 {
1525 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
1526 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
1527 ui_out_field_int (uiout, "signal1_type", signal1_type);
1528 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
1529 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
1530 ui_out_field_int (uiout, "signal2_type", signal2_type);
1531 }
1532 else
1533 {
1534 if (signal1_pending)
1535 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
1536 else
1537 printf_filtered (_("Signal 1 not pending "));
1538
1539 if (signal1_type)
1540 printf_filtered (_("(Type Overwrite)\n"));
1541 else
1542 printf_filtered (_("(Type Or)\n"));
1543
1544 if (signal2_pending)
1545 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
1546 else
1547 printf_filtered (_("Signal 2 not pending "));
1548
1549 if (signal2_type)
1550 printf_filtered (_("(Type Overwrite)\n"));
1551 else
1552 printf_filtered (_("(Type Or)\n"));
1553 }
1554
1555 do_cleanups (chain);
1556}
1557
1558static void
1559info_spu_mailbox_list (gdb_byte *buf, int nr,
1560 const char *field, const char *msg)
1561{
1562 struct cleanup *chain;
1563 int i;
1564
1565 if (nr <= 0)
1566 return;
1567
1568 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
1569
1570 ui_out_table_header (uiout, 32, ui_left, field, msg);
1571 ui_out_table_body (uiout);
1572
1573 for (i = 0; i < nr; i++)
1574 {
1575 struct cleanup *val_chain;
1576 ULONGEST val;
1577 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
1578 val = extract_unsigned_integer (buf + 4*i, 4);
1579 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
1580 do_cleanups (val_chain);
1581
1582 if (!ui_out_is_mi_like_p (uiout))
1583 printf_filtered ("\n");
1584 }
1585
1586 do_cleanups (chain);
1587}
1588
1589static void
1590info_spu_mailbox_command (char *args, int from_tty)
1591{
1592 struct frame_info *frame = get_selected_frame (NULL);
1593 struct cleanup *chain;
1594 char annex[32];
1595 gdb_byte buf[1024];
1596 LONGEST len;
1597 int i, id;
1598
1599 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1600
1601 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
1602
1603 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
1604 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1605 buf, 0, sizeof buf);
1606 if (len < 0)
1607 error (_("Could not read mbox_info."));
1608
1609 info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox");
1610
1611 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
1612 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1613 buf, 0, sizeof buf);
1614 if (len < 0)
1615 error (_("Could not read ibox_info."));
1616
1617 info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox");
1618
1619 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
1620 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1621 buf, 0, sizeof buf);
1622 if (len < 0)
1623 error (_("Could not read wbox_info."));
1624
1625 info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox");
1626
1627 do_cleanups (chain);
1628}
1629
1630static ULONGEST
1631spu_mfc_get_bitfield (ULONGEST word, int first, int last)
1632{
1633 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
1634 return (word >> (63 - last)) & mask;
1635}
1636
1637static void
1638info_spu_dma_cmdlist (gdb_byte *buf, int nr)
1639{
1640 static char *spu_mfc_opcode[256] =
1641 {
1642 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1643 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1644 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1645 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1646 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
1647 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
1648 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
1649 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1650 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
1651 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
1652 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1653 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1654 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1655 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1656 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1657 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1658 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
1659 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
1660 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1661 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1662 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
1663 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1664 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
1665 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1666 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1667 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
1668 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1669 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1670 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1671 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1672 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1673 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1674 };
1675
1676 struct cleanup *chain;
1677 int i;
1678
1679 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
1680
1681 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
1682 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
1683 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
1684 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
1685 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
1686 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
1687 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
1688 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
1689 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
1690 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
1691
1692 ui_out_table_body (uiout);
1693
1694 for (i = 0; i < nr; i++)
1695 {
1696 struct cleanup *cmd_chain;
1697 ULONGEST mfc_cq_dw0;
1698 ULONGEST mfc_cq_dw1;
1699 ULONGEST mfc_cq_dw2;
1700 ULONGEST mfc_cq_dw3;
1701 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
1702 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
1703 ULONGEST mfc_ea;
1704 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
1705
1706 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1707 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1708
1709 mfc_cq_dw0 = extract_unsigned_integer (buf + 32*i, 8);
1710 mfc_cq_dw1 = extract_unsigned_integer (buf + 32*i + 8, 8);
1711 mfc_cq_dw2 = extract_unsigned_integer (buf + 32*i + 16, 8);
1712 mfc_cq_dw3 = extract_unsigned_integer (buf + 32*i + 24, 8);
1713
1714 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
1715 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
1716 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
1717 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
1718 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
1719 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
1720 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
1721
1722 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
1723 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
1724
1725 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
1726 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
1727 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
1728 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
1729 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
1730 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
1731
1732 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
1733
1734 if (spu_mfc_opcode[mfc_cmd_opcode])
1735 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
1736 else
1737 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
1738
1739 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
1740 ui_out_field_int (uiout, "tid", tclass_id);
1741 ui_out_field_int (uiout, "rid", rclass_id);
1742
1743 if (ea_valid_p)
1744 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
1745 else
1746 ui_out_field_skip (uiout, "ea");
1747
1748 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
1749 if (qw_valid_p)
1750 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
1751 else
1752 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
1753
1754 if (list_valid_p)
1755 {
1756 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
1757 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
1758 }
1759 else
1760 {
1761 ui_out_field_skip (uiout, "lstaddr");
1762 ui_out_field_skip (uiout, "lstsize");
1763 }
1764
1765 if (cmd_error_p)
1766 ui_out_field_string (uiout, "error_p", "*");
1767 else
1768 ui_out_field_skip (uiout, "error_p");
1769
1770 do_cleanups (cmd_chain);
1771
1772 if (!ui_out_is_mi_like_p (uiout))
1773 printf_filtered ("\n");
1774 }
1775
1776 do_cleanups (chain);
1777}
1778
1779static void
1780info_spu_dma_command (char *args, int from_tty)
1781{
1782 struct frame_info *frame = get_selected_frame (NULL);
1783 ULONGEST dma_info_type;
1784 ULONGEST dma_info_mask;
1785 ULONGEST dma_info_status;
1786 ULONGEST dma_info_stall_and_notify;
1787 ULONGEST dma_info_atomic_command_status;
1788 struct cleanup *chain;
1789 char annex[32];
1790 gdb_byte buf[1024];
1791 LONGEST len;
1792 int i, id;
1793
1794 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1795
1796 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
1797 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1798 buf, 0, 40 + 16 * 32);
1799 if (len <= 0)
1800 error (_("Could not read dma_info."));
1801
1802 dma_info_type = extract_unsigned_integer (buf, 8);
1803 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1804 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1805 dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8);
1806 dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8);
1807
1808 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
1809
1810 if (ui_out_is_mi_like_p (uiout))
1811 {
1812 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
1813 phex_nz (dma_info_type, 4));
1814 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
1815 phex_nz (dma_info_mask, 4));
1816 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
1817 phex_nz (dma_info_status, 4));
1818 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
1819 phex_nz (dma_info_stall_and_notify, 4));
1820 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
1821 phex_nz (dma_info_atomic_command_status, 4));
1822 }
1823 else
1824 {
1825 const char *query_msg;
1826
1827 switch (dma_info_type)
1828 {
1829 case 0: query_msg = _("no query pending"); break;
1830 case 1: query_msg = _("'any' query pending"); break;
1831 case 2: query_msg = _("'all' query pending"); break;
1832 default: query_msg = _("undefined query type"); break;
1833 }
1834
1835 printf_filtered (_("Tag-Group Status 0x%s\n"),
1836 phex (dma_info_status, 4));
1837 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1838 phex (dma_info_mask, 4), query_msg);
1839 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1840 phex (dma_info_stall_and_notify, 4));
1841 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1842 phex (dma_info_atomic_command_status, 4));
1843 printf_filtered ("\n");
1844 }
1845
1846 info_spu_dma_cmdlist (buf + 40, 16);
1847 do_cleanups (chain);
1848}
1849
1850static void
1851info_spu_proxydma_command (char *args, int from_tty)
1852{
1853 struct frame_info *frame = get_selected_frame (NULL);
1854 ULONGEST dma_info_type;
1855 ULONGEST dma_info_mask;
1856 ULONGEST dma_info_status;
1857 struct cleanup *chain;
1858 char annex[32];
1859 gdb_byte buf[1024];
1860 LONGEST len;
1861 int i, id;
1862
1863 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1864
1865 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
1866 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1867 buf, 0, 24 + 8 * 32);
1868 if (len <= 0)
1869 error (_("Could not read proxydma_info."));
1870
1871 dma_info_type = extract_unsigned_integer (buf, 8);
1872 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1873 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1874
1875 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
1876
1877 if (ui_out_is_mi_like_p (uiout))
1878 {
1879 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
1880 phex_nz (dma_info_type, 4));
1881 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
1882 phex_nz (dma_info_mask, 4));
1883 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
1884 phex_nz (dma_info_status, 4));
1885 }
1886 else
1887 {
1888 const char *query_msg;
1889
1890 switch (dma_info_type)
1891 {
1892 case 0: query_msg = _("no query pending"); break;
1893 case 1: query_msg = _("'any' query pending"); break;
1894 case 2: query_msg = _("'all' query pending"); break;
1895 default: query_msg = _("undefined query type"); break;
1896 }
1897
1898 printf_filtered (_("Tag-Group Status 0x%s\n"),
1899 phex (dma_info_status, 4));
1900 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1901 phex (dma_info_mask, 4), query_msg);
1902 printf_filtered ("\n");
1903 }
1904
1905 info_spu_dma_cmdlist (buf + 24, 8);
1906 do_cleanups (chain);
1907}
1908
1909static void
1910info_spu_command (char *args, int from_tty)
1911{
1912 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
1913 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
1914}
1915
1916
771b4502
UW		 1917/* Set up gdbarch struct. */
1918
1919static struct gdbarch *
1920spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1921{
1922 struct gdbarch *gdbarch;
1923
1924 /* Find a candidate among the list of pre-declared architectures. */
1925 arches = gdbarch_list_lookup_by_info (arches, &info);
1926 if (arches != NULL)
1927 return arches->gdbarch;
1928
1929 /* Is is for us? */
1930 if (info.bfd_arch_info->mach != bfd_mach_spu)
1931 return NULL;
1932
1933 /* Yes, create a new architecture. */
1934 gdbarch = gdbarch_alloc (&info, NULL);
1935
1936 /* Disassembler. */
1937 set_gdbarch_print_insn (gdbarch, print_insn_spu);
1938
1939 /* Registers. */
1940 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
1941 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
1942 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
1943 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 1944 set_gdbarch_read_pc (gdbarch, spu_read_pc);
1945 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 1946 set_gdbarch_register_name (gdbarch, spu_register_name);
1947 set_gdbarch_register_type (gdbarch, spu_register_type);
1948 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
1949 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 1950 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 1951 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
1952
1953 /* Data types. */
1954 set_gdbarch_char_signed (gdbarch, 0);
1955 set_gdbarch_ptr_bit (gdbarch, 32);
1956 set_gdbarch_addr_bit (gdbarch, 32);
1957 set_gdbarch_short_bit (gdbarch, 16);
1958 set_gdbarch_int_bit (gdbarch, 32);
1959 set_gdbarch_long_bit (gdbarch, 32);
1960 set_gdbarch_long_long_bit (gdbarch, 64);
1961 set_gdbarch_float_bit (gdbarch, 32);
1962 set_gdbarch_double_bit (gdbarch, 64);
1963 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 1964 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1965 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1966 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502
UW		 1967
1968 /* Inferior function calls. */
7b3dc0b7
UW		 1969 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1970 set_gdbarch_frame_align (gdbarch, spu_frame_align);
771b4502
UW		 1971 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
1972 set_gdbarch_unwind_dummy_id (gdbarch, spu_unwind_dummy_id);
1973 set_gdbarch_return_value (gdbarch, spu_return_value);
1974
1975 /* Frame handling. */
1976 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1977 frame_unwind_append_sniffer (gdbarch, spu_frame_sniffer);
1978 frame_base_set_default (gdbarch, &spu_frame_base);
1979 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
1980 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
1981 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
1982 set_gdbarch_frame_args_skip (gdbarch, 0);
1983 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 1984 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502
UW		 1985
1986 /* Breakpoints. */
1987 set_gdbarch_decr_pc_after_break (gdbarch, 4);
1988 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
1989 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
1990 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
1991
dcf52cd8
UW		 1992 /* Overlays. */
1993 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
1994
771b4502
UW		 1995 return gdbarch;
1996}
1997
f2d43c2c
UW		 1998/* Implement a SPU-specific vector type as replacement
1999 for __gdb_builtin_type_vec128. */
2000static void
2001spu_init_vector_type (void)
2002{
2003 struct type *type;
2004
2005 type = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION);
2006 append_composite_type_field (type, "uint128", builtin_type_int128);
2007 append_composite_type_field (type, "v2_int64", builtin_type_v2_int64);
2008 append_composite_type_field (type, "v4_int32", builtin_type_v4_int32);
2009 append_composite_type_field (type, "v8_int16", builtin_type_v8_int16);
2010 append_composite_type_field (type, "v16_int8", builtin_type_v16_int8);
2011 append_composite_type_field (type, "v2_double", builtin_type_v2_double);
2012 append_composite_type_field (type, "v4_float", builtin_type_v4_float);
2013
2014 TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR;
2015 TYPE_NAME (type) = "spu_builtin_type_vec128";
2016 spu_builtin_type_vec128 = type;
2017}
2018
771b4502
UW		 2019void
2020_initialize_spu_tdep (void)
2021{
2022 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c
UW		 2023
2024 spu_init_vector_type ();
dcf52cd8
UW		 2025
2026 /* Add ourselves to objfile event chain. */
2027 observer_attach_new_objfile (spu_overlay_new_objfile);
2028 spu_overlay_data = register_objfile_data ();
23d964e7
UW		 2029
2030 /* Add root prefix command for all "info spu" commands. */
2031 add_prefix_cmd ("spu", class_info, info_spu_command,
2032 _("Various SPU specific commands."),
2033 &infospucmdlist, "info spu ", 0, &infolist);
2034
2035 /* Add various "info spu" commands. */
2036 add_cmd ("event", class_info, info_spu_event_command,
2037 _("Display SPU event facility status.\n"),
2038 &infospucmdlist);
2039 add_cmd ("signal", class_info, info_spu_signal_command,
2040 _("Display SPU signal notification facility status.\n"),
2041 &infospucmdlist);
2042 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2043 _("Display SPU mailbox facility status.\n"),
2044 &infospucmdlist);
2045 add_cmd ("dma", class_info, info_spu_dma_command,
2046 _("Display MFC DMA status.\n"),
2047 &infospucmdlist);
2048 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2049 _("Display MFC Proxy-DMA status.\n"),
2050 &infospucmdlist);
771b4502 2051}
GDB Binutils - Deliverables
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