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Rename in_function_epilogue_p to stack_frame_destroyed_p
[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
CommitLineData
771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
32d0add0 2 Copyright (C) 2006-2015 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
771b4502
UW		 27#include "frame.h"
28#include "frame-unwind.h"
29#include "frame-base.h"
30#include "trad-frame.h"
31#include "symtab.h"
32#include "symfile.h"
33#include "value.h"
34#include "inferior.h"
35#include "dis-asm.h"
36#include "objfiles.h"
37#include "language.h"
38#include "regcache.h"
39#include "reggroups.h"
40#include "floatformat.h"
3285f3fe 41#include "block.h"
dcf52cd8 42#include "observer.h"
ff1a52c6 43#include "infcall.h"
54fcddd0 44#include "dwarf2.h"
7ce16bd4
UW		 45#include "dwarf2-frame.h"
46#include "ax.h"
771b4502
UW		 47#include "spu-tdep.h"
48
794ac428 49
3285f3fe
UW		 50/* The list of available "set spu " and "show spu " commands. */
51static struct cmd_list_element *setspucmdlist = NULL;
52static struct cmd_list_element *showspucmdlist = NULL;
53
54/* Whether to stop for new SPE contexts. */
55static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 56/* Whether to automatically flush the SW-managed cache. */
57static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 58
59
794ac428
UW		 60/* The tdep structure. */
61struct gdbarch_tdep
62{
85e747d2
UW		 63 /* The spufs ID identifying our address space. */
64 int id;
65
794ac428
UW		 66 /* SPU-specific vector type. */
67 struct type *spu_builtin_type_vec128;
68};
69
70
f2d43c2c 71/* SPU-specific vector type. */
794ac428
UW		 72static struct type *
73spu_builtin_type_vec128 (struct gdbarch *gdbarch)
74{
75 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
76
77 if (!tdep->spu_builtin_type_vec128)
78 {
df4df182 79 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 80 struct type *t;
81
e9bb382b
UW		 82 t = arch_composite_type (gdbarch,
83 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 84 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 85 append_composite_type_field (t, "v2_int64",
df4df182 86 init_vector_type (bt->builtin_int64, 2));
794ac428 87 append_composite_type_field (t, "v4_int32",
df4df182 88 init_vector_type (bt->builtin_int32, 4));
794ac428 89 append_composite_type_field (t, "v8_int16",
df4df182 90 init_vector_type (bt->builtin_int16, 8));
794ac428 91 append_composite_type_field (t, "v16_int8",
df4df182 92 init_vector_type (bt->builtin_int8, 16));
794ac428 93 append_composite_type_field (t, "v2_double",
df4df182 94 init_vector_type (bt->builtin_double, 2));
794ac428 95 append_composite_type_field (t, "v4_float",
df4df182 96 init_vector_type (bt->builtin_float, 4));
794ac428 97
876cecd0 98 TYPE_VECTOR (t) = 1;
794ac428
UW		 99 TYPE_NAME (t) = "spu_builtin_type_vec128";
100
101 tdep->spu_builtin_type_vec128 = t;
102 }
103
104 return tdep->spu_builtin_type_vec128;
105}
106
771b4502 107
23d964e7
UW		 108/* The list of available "info spu " commands. */
109static struct cmd_list_element *infospucmdlist = NULL;
110
771b4502
UW		 111/* Registers. */
112
113static const char *
d93859e2 114spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 115{
116 static char *register_names[] =
117 {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
122 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
123 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
124 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
125 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
126 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
127 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
128 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
129 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
130 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
131 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
132 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
133 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 134 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 135 };
136
137 if (reg_nr < 0)
138 return NULL;
139 if (reg_nr >= sizeof register_names / sizeof *register_names)
140 return NULL;
141
142 return register_names[reg_nr];
143}
144
145static struct type *
146spu_register_type (struct gdbarch *gdbarch, int reg_nr)
147{
148 if (reg_nr < SPU_NUM_GPRS)
794ac428 149 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 150
151 switch (reg_nr)
152 {
153 case SPU_ID_REGNUM:
df4df182 154 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 155
156 case SPU_PC_REGNUM:
0dfff4cb 157 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 158
159 case SPU_SP_REGNUM:
0dfff4cb 160 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 161
23d964e7 162 case SPU_FPSCR_REGNUM:
df4df182 163 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 164
165 case SPU_SRR0_REGNUM:
df4df182 166 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 167
168 case SPU_LSLR_REGNUM:
df4df182 169 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 170
171 case SPU_DECR_REGNUM:
df4df182 172 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 173
174 case SPU_DECR_STATUS_REGNUM:
df4df182 175 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 176
771b4502 177 default:
a73c6dcd 178 internal_error (__FILE__, __LINE__, _("invalid regnum"));
771b4502
UW		 179 }
180}
181
182/* Pseudo registers for preferred slots - stack pointer. */
183
05d1431c 184static enum register_status
23d964e7
UW		 185spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
186 gdb_byte *buf)
187{
e17a4113
UW		 188 struct gdbarch *gdbarch = get_regcache_arch (regcache);
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
05d1431c 190 enum register_status status;
23d964e7
UW		 191 gdb_byte reg[32];
192 char annex[32];
193 ULONGEST id;
001f13d8 194 ULONGEST ul;
23d964e7 195
05d1431c
PA		 196 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
197 if (status != REG_VALID)
198 return status;
23d964e7
UW		 199 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
200 memset (reg, 0, sizeof reg);
201 target_read (&current_target, TARGET_OBJECT_SPU, annex,
202 reg, 0, sizeof reg);
203
001f13d8
PA		 204 ul = strtoulst ((char *) reg, NULL, 16);
205 store_unsigned_integer (buf, 4, byte_order, ul);
05d1431c 206 return REG_VALID;
23d964e7
UW		 207}
208
05d1431c 209static enum register_status
771b4502
UW		 210spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
211 int regnum, gdb_byte *buf)
212{
213 gdb_byte reg[16];
23d964e7
UW		 214 char annex[32];
215 ULONGEST id;
05d1431c 216 enum register_status status;
771b4502
UW		 217
218 switch (regnum)
219 {
220 case SPU_SP_REGNUM:
05d1431c
PA		 221 status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
222 if (status != REG_VALID)
223 return status;
771b4502 224 memcpy (buf, reg, 4);
05d1431c 225 return status;
771b4502 226
23d964e7 227 case SPU_FPSCR_REGNUM:
05d1431c
PA		 228 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
229 if (status != REG_VALID)
230 return status;
23d964e7
UW		 231 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
232 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
05d1431c 233 return status;
23d964e7
UW		 234
235 case SPU_SRR0_REGNUM:
05d1431c 236 return spu_pseudo_register_read_spu (regcache, "srr0", buf);
23d964e7
UW		 237
238 case SPU_LSLR_REGNUM:
05d1431c 239 return spu_pseudo_register_read_spu (regcache, "lslr", buf);
23d964e7
UW		 240
241 case SPU_DECR_REGNUM:
05d1431c 242 return spu_pseudo_register_read_spu (regcache, "decr", buf);
23d964e7
UW		 243
244 case SPU_DECR_STATUS_REGNUM:
05d1431c 245 return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
23d964e7 246
771b4502
UW		 247 default:
248 internal_error (__FILE__, __LINE__, _("invalid regnum"));
249 }
250}
251
23d964e7
UW		 252static void
253spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
254 const gdb_byte *buf)
255{
e17a4113
UW		 256 struct gdbarch *gdbarch = get_regcache_arch (regcache);
257 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
001f13d8 258 char reg[32];
23d964e7
UW		 259 char annex[32];
260 ULONGEST id;
261
262 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
263 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
264 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 265 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7 266 target_write (&current_target, TARGET_OBJECT_SPU, annex,
001f13d8 267 (gdb_byte *) reg, 0, strlen (reg));
23d964e7
UW		 268}
269
771b4502
UW		 270static void
271spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
272 int regnum, const gdb_byte *buf)
273{
274 gdb_byte reg[16];
23d964e7
UW		 275 char annex[32];
276 ULONGEST id;
771b4502
UW		 277
278 switch (regnum)
279 {
280 case SPU_SP_REGNUM:
281 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
282 memcpy (reg, buf, 4);
283 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
284 break;
285
23d964e7
UW		 286 case SPU_FPSCR_REGNUM:
287 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
288 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
289 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
290 break;
291
292 case SPU_SRR0_REGNUM:
293 spu_pseudo_register_write_spu (regcache, "srr0", buf);
294 break;
295
296 case SPU_LSLR_REGNUM:
297 spu_pseudo_register_write_spu (regcache, "lslr", buf);
298 break;
299
300 case SPU_DECR_REGNUM:
301 spu_pseudo_register_write_spu (regcache, "decr", buf);
302 break;
303
304 case SPU_DECR_STATUS_REGNUM:
305 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
306 break;
307
771b4502
UW		 308 default:
309 internal_error (__FILE__, __LINE__, _("invalid regnum"));
310 }
311}
312
7ce16bd4
UW		 313static int
314spu_ax_pseudo_register_collect (struct gdbarch *gdbarch,
315 struct agent_expr *ax, int regnum)
316{
317 switch (regnum)
318 {
319 case SPU_SP_REGNUM:
320 ax_reg_mask (ax, SPU_RAW_SP_REGNUM);
321 return 0;
322
323 case SPU_FPSCR_REGNUM:
324 case SPU_SRR0_REGNUM:
325 case SPU_LSLR_REGNUM:
326 case SPU_DECR_REGNUM:
327 case SPU_DECR_STATUS_REGNUM:
328 return -1;
329
330 default:
331 internal_error (__FILE__, __LINE__, _("invalid regnum"));
332 }
333}
334
335static int
336spu_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
337 struct agent_expr *ax, int regnum)
338{
339 switch (regnum)
340 {
341 case SPU_SP_REGNUM:
342 ax_reg (ax, SPU_RAW_SP_REGNUM);
343 return 0;
344
345 case SPU_FPSCR_REGNUM:
346 case SPU_SRR0_REGNUM:
347 case SPU_LSLR_REGNUM:
348 case SPU_DECR_REGNUM:
349 case SPU_DECR_STATUS_REGNUM:
350 return -1;
351
352 default:
353 internal_error (__FILE__, __LINE__, _("invalid regnum"));
354 }
355}
356
357
771b4502
UW		 358/* Value conversion -- access scalar values at the preferred slot. */
359
9acbedc0 360static struct value *
2ed3c037
UW		 361spu_value_from_register (struct gdbarch *gdbarch, struct type *type,
362 int regnum, struct frame_id frame_id)
771b4502 363{
2ed3c037
UW		 364 struct value *value = default_value_from_register (gdbarch, type,
365 regnum, frame_id);
bad43aa5 366 int len = TYPE_LENGTH (type);
771b4502 367
bad43aa5 368 if (regnum < SPU_NUM_GPRS && len < 16)
9acbedc0 369 {
bad43aa5 370 int preferred_slot = len < 4 ? 4 - len : 0;
9acbedc0
UW		 371 set_value_offset (value, preferred_slot);
372 }
771b4502 373
9acbedc0 374 return value;
771b4502
UW		 375}
376
377/* Register groups. */
378
379static int
380spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
381 struct reggroup *group)
382{
383 /* Registers displayed via 'info regs'. */
384 if (group == general_reggroup)
385 return 1;
386
387 /* Registers displayed via 'info float'. */
388 if (group == float_reggroup)
389 return 0;
390
391 /* Registers that need to be saved/restored in order to
392 push or pop frames. */
393 if (group == save_reggroup || group == restore_reggroup)
394 return 1;
395
396 return default_register_reggroup_p (gdbarch, regnum, group);
397}
398
7ce16bd4
UW		 399/* DWARF-2 register numbers. */
400
401static int
402spu_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
403{
404 /* Use cooked instead of raw SP. */
405 return (reg == SPU_RAW_SP_REGNUM)? SPU_SP_REGNUM : reg;
406}
407
ff1a52c6
UW		 408
409/* Address handling. */
36acd84e 410
85e747d2
UW		 411static int
412spu_gdbarch_id (struct gdbarch *gdbarch)
413{
414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
415 int id = tdep->id;
416
417 /* The objfile architecture of a standalone SPU executable does not
b021a221 418 provide an SPU ID. Retrieve it from the objfile's relocated
85e747d2
UW		 419 address range in this special case. */
420 if (id == -1
421 && symfile_objfile && symfile_objfile->obfd
422 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
423 && symfile_objfile->sections != symfile_objfile->sections_end)
424 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
425
426 return id;
427}
428
ff1a52c6
UW		 429static int
430spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
431{
432 if (dwarf2_addr_class == 1)
433 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
434 else
435 return 0;
436}
437
438static const char *
439spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
440{
441 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
442 return "__ea";
443 else
444 return NULL;
445}
446
447static int
448spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
449 const char *name, int *type_flags_ptr)
450{
451 if (strcmp (name, "__ea") == 0)
452 {
453 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
454 return 1;
455 }
456 else
457 return 0;
458}
459
85e747d2
UW		 460static void
461spu_address_to_pointer (struct gdbarch *gdbarch,
462 struct type *type, gdb_byte *buf, CORE_ADDR addr)
463{
464 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
465 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
466 SPUADDR_ADDR (addr));
467}
468
36acd84e 469static CORE_ADDR
9898f801
UW		 470spu_pointer_to_address (struct gdbarch *gdbarch,
471 struct type *type, const gdb_byte *buf)
36acd84e 472{
85e747d2 473 int id = spu_gdbarch_id (gdbarch);
e17a4113
UW		 474 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
475 ULONGEST addr
476 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 477
ff1a52c6
UW		 478 /* Do not convert __ea pointers. */
479 if (TYPE_ADDRESS_CLASS_1 (type))
480 return addr;
481
d2ed6730 482 return addr? SPUADDR (id, addr) : 0;
36acd84e
UW		 483}
484
485static CORE_ADDR
486spu_integer_to_address (struct gdbarch *gdbarch,
487 struct type *type, const gdb_byte *buf)
488{
85e747d2 489 int id = spu_gdbarch_id (gdbarch);
36acd84e 490 ULONGEST addr = unpack_long (type, buf);
36acd84e 491
d2ed6730 492 return SPUADDR (id, addr);
36acd84e
UW		 493}
494
771b4502
UW		 495
496/* Decoding SPU instructions. */
497
498enum
499 {
500 op_lqd = 0x34,
501 op_lqx = 0x3c4,
502 op_lqa = 0x61,
503 op_lqr = 0x67,
504 op_stqd = 0x24,
505 op_stqx = 0x144,
506 op_stqa = 0x41,
507 op_stqr = 0x47,
508
509 op_il = 0x081,
510 op_ila = 0x21,
511 op_a = 0x0c0,
512 op_ai = 0x1c,
513
a536c6d7 514 op_selb = 0x8,
771b4502
UW		 515
516 op_br = 0x64,
517 op_bra = 0x60,
518 op_brsl = 0x66,
519 op_brasl = 0x62,
520 op_brnz = 0x42,
521 op_brz = 0x40,
522 op_brhnz = 0x46,
523 op_brhz = 0x44,
524 op_bi = 0x1a8,
525 op_bisl = 0x1a9,
526 op_biz = 0x128,
527 op_binz = 0x129,
528 op_bihz = 0x12a,
529 op_bihnz = 0x12b,
530 };
531
532static int
533is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
534{
535 if ((insn >> 21) == op)
536 {
537 *rt = insn & 127;
538 *ra = (insn >> 7) & 127;
539 *rb = (insn >> 14) & 127;
540 return 1;
541 }
542
543 return 0;
544}
545
546static int
547is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
548{
549 if ((insn >> 28) == op)
550 {
551 *rt = (insn >> 21) & 127;
552 *ra = (insn >> 7) & 127;
553 *rb = (insn >> 14) & 127;
554 *rc = insn & 127;
555 return 1;
556 }
557
558 return 0;
559}
560
561static int
562is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
563{
564 if ((insn >> 21) == op)
565 {
566 *rt = insn & 127;
567 *ra = (insn >> 7) & 127;
568 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
569 return 1;
570 }
571
572 return 0;
573}
574
575static int
576is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
577{
578 if ((insn >> 24) == op)
579 {
580 *rt = insn & 127;
581 *ra = (insn >> 7) & 127;
582 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
583 return 1;
584 }
585
586 return 0;
587}
588
589static int
590is_ri16 (unsigned int insn, int op, int *rt, int *i16)
591{
592 if ((insn >> 23) == op)
593 {
594 *rt = insn & 127;
595 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
596 return 1;
597 }
598
599 return 0;
600}
601
602static int
603is_ri18 (unsigned int insn, int op, int *rt, int *i18)
604{
605 if ((insn >> 25) == op)
606 {
607 *rt = insn & 127;
608 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
609 return 1;
610 }
611
612 return 0;
613}
614
615static int
616is_branch (unsigned int insn, int *offset, int *reg)
617{
618 int rt, i7, i16;
619
620 if (is_ri16 (insn, op_br, &rt, &i16)
621 || is_ri16 (insn, op_brsl, &rt, &i16)
622 || is_ri16 (insn, op_brnz, &rt, &i16)
623 || is_ri16 (insn, op_brz, &rt, &i16)
624 || is_ri16 (insn, op_brhnz, &rt, &i16)
625 || is_ri16 (insn, op_brhz, &rt, &i16))
626 {
627 *reg = SPU_PC_REGNUM;
628 *offset = i16 << 2;
629 return 1;
630 }
631
632 if (is_ri16 (insn, op_bra, &rt, &i16)
633 || is_ri16 (insn, op_brasl, &rt, &i16))
634 {
635 *reg = -1;
636 *offset = i16 << 2;
637 return 1;
638 }
639
640 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
641 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
642 || is_ri7 (insn, op_biz, &rt, reg, &i7)
643 || is_ri7 (insn, op_binz, &rt, reg, &i7)
644 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
645 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
646 {
647 *offset = 0;
648 return 1;
649 }
650
651 return 0;
652}
653
654
655/* Prolog parsing. */
656
657struct spu_prologue_data
658 {
659 /* Stack frame size. -1 if analysis was unsuccessful. */
660 int size;
661
662 /* How to find the CFA. The CFA is equal to SP at function entry. */
663 int cfa_reg;
664 int cfa_offset;
665
666 /* Offset relative to CFA where a register is saved. -1 if invalid. */
667 int reg_offset[SPU_NUM_GPRS];
668 };
669
670static CORE_ADDR
e17a4113
UW		 671spu_analyze_prologue (struct gdbarch *gdbarch,
672 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 673 struct spu_prologue_data *data)
674{
e17a4113 675 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 676 int found_sp = 0;
677 int found_fp = 0;
678 int found_lr = 0;
ce50d78b 679 int found_bc = 0;
771b4502
UW		 680 int reg_immed[SPU_NUM_GPRS];
681 gdb_byte buf[16];
682 CORE_ADDR prolog_pc = start_pc;
683 CORE_ADDR pc;
684 int i;
685
686
687 /* Initialize DATA to default values. */
688 data->size = -1;
689
690 data->cfa_reg = SPU_RAW_SP_REGNUM;
691 data->cfa_offset = 0;
692
693 for (i = 0; i < SPU_NUM_GPRS; i++)
694 data->reg_offset[i] = -1;
695
696 /* Set up REG_IMMED array. This is non-zero for a register if we know its
697 preferred slot currently holds this immediate value. */
698 for (i = 0; i < SPU_NUM_GPRS; i++)
699 reg_immed[i] = 0;
700
701 /* Scan instructions until the first branch.
702
703 The following instructions are important prolog components:
704
705 - The first instruction to set up the stack pointer.
706 - The first instruction to set up the frame pointer.
707 - The first instruction to save the link register.
ce50d78b 708 - The first instruction to save the backchain.
771b4502 709
ce50d78b 710 We return the instruction after the latest of these four,
771b4502
UW		 711 or the incoming PC if none is found. The first instruction
712 to set up the stack pointer also defines the frame size.
713
714 Note that instructions saving incoming arguments to their stack
715 slots are not counted as important, because they are hard to
716 identify with certainty. This should not matter much, because
717 arguments are relevant only in code compiled with debug data,
718 and in such code the GDB core will advance until the first source
719 line anyway, using SAL data.
720
721 For purposes of stack unwinding, we analyze the following types
722 of instructions in addition:
723
724 - Any instruction adding to the current frame pointer.
725 - Any instruction loading an immediate constant into a register.
726 - Any instruction storing a register onto the stack.
727
728 These are used to compute the CFA and REG_OFFSET output. */
729
730 for (pc = start_pc; pc < end_pc; pc += 4)
731 {
732 unsigned int insn;
733 int rt, ra, rb, rc, immed;
734
735 if (target_read_memory (pc, buf, 4))
736 break;
e17a4113 737 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 738
739 /* AI is the typical instruction to set up a stack frame.
740 It is also used to initialize the frame pointer. */
741 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
742 {
743 if (rt == data->cfa_reg && ra == data->cfa_reg)
744 data->cfa_offset -= immed;
745
746 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
747 && !found_sp)
748 {
749 found_sp = 1;
750 prolog_pc = pc + 4;
751
752 data->size = -immed;
753 }
754 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
755 && !found_fp)
756 {
757 found_fp = 1;
758 prolog_pc = pc + 4;
759
760 data->cfa_reg = SPU_FP_REGNUM;
761 data->cfa_offset -= immed;
762 }
763 }
764
765 /* A is used to set up stack frames of size >= 512 bytes.
766 If we have tracked the contents of the addend register,
767 we can handle this as well. */
768 else if (is_rr (insn, op_a, &rt, &ra, &rb))
769 {
770 if (rt == data->cfa_reg && ra == data->cfa_reg)
771 {
772 if (reg_immed[rb] != 0)
773 data->cfa_offset -= reg_immed[rb];
774 else
775 data->cfa_reg = -1; /* We don't know the CFA any more. */
776 }
777
778 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
779 && !found_sp)
780 {
781 found_sp = 1;
782 prolog_pc = pc + 4;
783
784 if (reg_immed[rb] != 0)
785 data->size = -reg_immed[rb];
786 }
787 }
788
789 /* We need to track IL and ILA used to load immediate constants
790 in case they are later used as input to an A instruction. */
791 else if (is_ri16 (insn, op_il, &rt, &immed))
792 {
793 reg_immed[rt] = immed;
12102450
UW		 794
795 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
796 found_sp = 1;
771b4502
UW		 797 }
798
799 else if (is_ri18 (insn, op_ila, &rt, &immed))
800 {
801 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 802
803 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
804 found_sp = 1;
771b4502
UW		 805 }
806
807 /* STQD is used to save registers to the stack. */
808 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
809 {
810 if (ra == data->cfa_reg)
811 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
812
813 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
814 && !found_lr)
815 {
816 found_lr = 1;
817 prolog_pc = pc + 4;
818 }
ce50d78b
UW		 819
820 if (ra == SPU_RAW_SP_REGNUM
821 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
822 && !found_bc)
823 {
824 found_bc = 1;
825 prolog_pc = pc + 4;
826 }
771b4502
UW		 827 }
828
829 /* _start uses SELB to set up the stack pointer. */
830 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
831 {
832 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
833 found_sp = 1;
834 }
835
836 /* We terminate if we find a branch. */
837 else if (is_branch (insn, &immed, &ra))
838 break;
839 }
840
841
842 /* If we successfully parsed until here, and didn't find any instruction
843 modifying SP, we assume we have a frameless function. */
844 if (!found_sp)
845 data->size = 0;
846
847 /* Return cooked instead of raw SP. */
848 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
849 data->cfa_reg = SPU_SP_REGNUM;
850
851 return prolog_pc;
852}
853
854/* Return the first instruction after the prologue starting at PC. */
855static CORE_ADDR
6093d2eb 856spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 857{
858 struct spu_prologue_data data;
e17a4113 859 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 860}
861
862/* Return the frame pointer in use at address PC. */
863static void
a54fba4c
MD		 864spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
865 int *reg, LONGEST *offset)
771b4502
UW		 866{
867 struct spu_prologue_data data;
e17a4113 868 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 869
870 if (data.size != -1 && data.cfa_reg != -1)
871 {
872 /* The 'frame pointer' address is CFA minus frame size. */
873 *reg = data.cfa_reg;
874 *offset = data.cfa_offset - data.size;
875 }
876 else
877 {
c378eb4e 878 /* ??? We don't really know ... */
771b4502
UW		 879 *reg = SPU_SP_REGNUM;
880 *offset = 0;
881 }
882}
883
c9cf6e20 884/* Implement the stack_frame_destroyed_p gdbarch method.
fe5febed
UW		 885
886 1) scan forward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer
888 or transfers control (except a return), execution is not in
889 an epilogue, return.
890 b) Stop scanning if you find a return instruction or reach the
891 end of the function or reach the hard limit for the size of
892 an epilogue.
893 2) scan backward from the point of execution:
894 a) If you find an instruction that modifies the stack pointer,
895 execution *is* in an epilogue, return.
896 b) Stop scanning if you reach an instruction that transfers
897 control or the beginning of the function or reach the hard
898 limit for the size of an epilogue. */
899
900static int
c9cf6e20 901spu_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
fe5febed 902{
e17a4113 903 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 904 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
905 bfd_byte buf[4];
906 unsigned int insn;
22e048c9 907 int rt, ra, rb, immed;
fe5febed
UW		 908
909 /* Find the search limits based on function boundaries and hard limit.
910 We assume the epilogue can be up to 64 instructions long. */
911
912 const int spu_max_epilogue_size = 64 * 4;
913
914 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
915 return 0;
916
917 if (pc - func_start < spu_max_epilogue_size)
918 epilogue_start = func_start;
919 else
920 epilogue_start = pc - spu_max_epilogue_size;
921
922 if (func_end - pc < spu_max_epilogue_size)
923 epilogue_end = func_end;
924 else
925 epilogue_end = pc + spu_max_epilogue_size;
926
927 /* Scan forward until next 'bi $0'. */
928
929 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
930 {
931 if (target_read_memory (scan_pc, buf, 4))
932 return 0;
e17a4113 933 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 934
935 if (is_branch (insn, &immed, &ra))
936 {
937 if (immed == 0 && ra == SPU_LR_REGNUM)
938 break;
939
940 return 0;
941 }
942
943 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
944 || is_rr (insn, op_a, &rt, &ra, &rb)
945 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
946 {
947 if (rt == SPU_RAW_SP_REGNUM)
948 return 0;
949 }
950 }
951
952 if (scan_pc >= epilogue_end)
953 return 0;
954
955 /* Scan backward until adjustment to stack pointer (R1). */
956
957 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
958 {
959 if (target_read_memory (scan_pc, buf, 4))
960 return 0;
e17a4113 961 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 962
963 if (is_branch (insn, &immed, &ra))
964 return 0;
965
966 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
967 || is_rr (insn, op_a, &rt, &ra, &rb)
968 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
969 {
970 if (rt == SPU_RAW_SP_REGNUM)
971 return 1;
972 }
973 }
974
975 return 0;
976}
977
978
771b4502
UW		 979/* Normal stack frames. */
980
981struct spu_unwind_cache
982{
983 CORE_ADDR func;
984 CORE_ADDR frame_base;
985 CORE_ADDR local_base;
986
987 struct trad_frame_saved_reg *saved_regs;
988};
989
990static struct spu_unwind_cache *
8d998b8f 991spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 992 void **this_prologue_cache)
993{
e17a4113 994 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 995 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 996 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 997 struct spu_unwind_cache *info;
998 struct spu_prologue_data data;
85e747d2 999 CORE_ADDR id = tdep->id;
dcf52cd8 1000 gdb_byte buf[16];
771b4502
UW		 1001
1002 if (*this_prologue_cache)
1003 return *this_prologue_cache;
1004
1005 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
1006 *this_prologue_cache = info;
8d998b8f 1007 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 1008 info->frame_base = 0;
1009 info->local_base = 0;
1010
1011 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 1012 info->func = get_frame_func (this_frame);
771b4502
UW		 1013 if (info->func == 0)
1014 {
1015 /* Fall back to using the current PC as frame ID. */
8d998b8f 1016 info->func = get_frame_pc (this_frame);
771b4502
UW		 1017 data.size = -1;
1018 }
1019 else
e17a4113
UW		 1020 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
1021 &data);
771b4502
UW		 1022
1023 /* If successful, use prologue analysis data. */
1024 if (data.size != -1 && data.cfa_reg != -1)
1025 {
1026 CORE_ADDR cfa;
1027 int i;
771b4502
UW		 1028
1029 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 1030 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 1031 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 1032 cfa = SPUADDR (id, cfa);
771b4502
UW		 1033
1034 /* Call-saved register slots. */
1035 for (i = 0; i < SPU_NUM_GPRS; i++)
1036 if (i == SPU_LR_REGNUM
1037 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
1038 if (data.reg_offset[i] != -1)
1039 info->saved_regs[i].addr = cfa - data.reg_offset[i];
1040
771b4502
UW		 1041 /* Frame bases. */
1042 info->frame_base = cfa;
1043 info->local_base = cfa - data.size;
1044 }
1045
1046 /* Otherwise, fall back to reading the backchain link. */
1047 else
1048 {
cdc9523a
UW		 1049 CORE_ADDR reg;
1050 LONGEST backchain;
13def385 1051 ULONGEST lslr;
cdc9523a 1052 int status;
771b4502 1053
13def385
UW		 1054 /* Get local store limit. */
1055 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1056 if (!lslr)
1057 lslr = (ULONGEST) -1;
1058
771b4502 1059 /* Get the backchain. */
8d998b8f 1060 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 1061 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1062 &backchain);
771b4502
UW		 1063
1064 /* A zero backchain terminates the frame chain. Also, sanity
1065 check against the local store size limit. */
13def385 1066 if (status && backchain > 0 && backchain <= lslr)
771b4502
UW		 1067 {
1068 /* Assume the link register is saved into its slot. */
13def385 1069 if (backchain + 16 <= lslr)
c378eb4e
MS		 1070 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1071 backchain + 16);
771b4502 1072
771b4502 1073 /* Frame bases. */
85e747d2
UW		 1074 info->frame_base = SPUADDR (id, backchain);
1075 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1076 }
1077 }
dcf52cd8 1078
c4891da7
UW		 1079 /* If we didn't find a frame, we cannot determine SP / return address. */
1080 if (info->frame_base == 0)
1081 return info;
1082
dcf52cd8 1083 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1084 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1085 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1086
0a44cb36
UW		 1087 /* Read full contents of the unwound link register in order to
1088 be able to determine the return address. */
dcf52cd8
UW		 1089 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1090 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1091 else
8d998b8f 1092 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1093
0a44cb36
UW		 1094 /* Normally, the return address is contained in the slot 0 of the
1095 link register, and slots 1-3 are zero. For an overlay return,
1096 slot 0 contains the address of the overlay manager return stub,
1097 slot 1 contains the partition number of the overlay section to
1098 be returned to, and slot 2 contains the return address within
1099 that section. Return the latter address in that case. */
e17a4113 1100 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1101 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1102 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1103 else
1104 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1105 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1106
1107 return info;
1108}
1109
1110static void
8d998b8f 1111spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1112 void **this_prologue_cache, struct frame_id *this_id)
1113{
1114 struct spu_unwind_cache *info =
8d998b8f 1115 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1116
1117 if (info->frame_base == 0)
1118 return;
1119
1120 *this_id = frame_id_build (info->frame_base, info->func);
1121}
1122
8d998b8f
UW		 1123static struct value *
1124spu_frame_prev_register (struct frame_info *this_frame,
1125 void **this_prologue_cache, int regnum)
771b4502
UW		 1126{
1127 struct spu_unwind_cache *info
8d998b8f 1128 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1129
1130 /* Special-case the stack pointer. */
1131 if (regnum == SPU_RAW_SP_REGNUM)
1132 regnum = SPU_SP_REGNUM;
1133
8d998b8f 1134 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1135}
1136
1137static const struct frame_unwind spu_frame_unwind = {
1138 NORMAL_FRAME,
8fbca658 1139 default_frame_unwind_stop_reason,
771b4502 1140 spu_frame_this_id,
8d998b8f
UW		 1141 spu_frame_prev_register,
1142 NULL,
1143 default_frame_sniffer
771b4502
UW		 1144};
1145
771b4502 1146static CORE_ADDR
8d998b8f 1147spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1148{
1149 struct spu_unwind_cache *info
8d998b8f 1150 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1151 return info->local_base;
1152}
1153
1154static const struct frame_base spu_frame_base = {
1155 &spu_frame_unwind,
1156 spu_frame_base_address,
1157 spu_frame_base_address,
1158 spu_frame_base_address
1159};
1160
1161static CORE_ADDR
1162spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1163{
85e747d2 1164 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1165 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1166 /* Mask off interrupt enable bit. */
85e747d2 1167 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1168}
1169
1170static CORE_ADDR
1171spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1172{
85e747d2
UW		 1173 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1174 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1175 return SPUADDR (tdep->id, sp);
771b4502
UW		 1176}
1177
118dfbaf 1178static CORE_ADDR
61a1198a 1179spu_read_pc (struct regcache *regcache)
118dfbaf 1180{
85e747d2 1181 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1182 ULONGEST pc;
1183 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1184 /* Mask off interrupt enable bit. */
85e747d2 1185 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1186}
1187
1188static void
61a1198a 1189spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1190{
1191 /* Keep interrupt enabled state unchanged. */
61a1198a 1192 ULONGEST old_pc;
30bcb456 1193
61a1198a
UW		 1194 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1195 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1196 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1197}
1198
771b4502 1199
cc5f0d61
UW		 1200/* Cell/B.E. cross-architecture unwinder support. */
1201
1202struct spu2ppu_cache
1203{
1204 struct frame_id frame_id;
1205 struct regcache *regcache;
1206};
1207
1208static struct gdbarch *
1209spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1210{
1211 struct spu2ppu_cache *cache = *this_cache;
1212 return get_regcache_arch (cache->regcache);
1213}
1214
1215static void
1216spu2ppu_this_id (struct frame_info *this_frame,
1217 void **this_cache, struct frame_id *this_id)
1218{
1219 struct spu2ppu_cache *cache = *this_cache;
1220 *this_id = cache->frame_id;
1221}
1222
1223static struct value *
1224spu2ppu_prev_register (struct frame_info *this_frame,
1225 void **this_cache, int regnum)
1226{
1227 struct spu2ppu_cache *cache = *this_cache;
1228 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1229 gdb_byte *buf;
1230
1231 buf = alloca (register_size (gdbarch, regnum));
1232 regcache_cooked_read (cache->regcache, regnum, buf);
1233 return frame_unwind_got_bytes (this_frame, regnum, buf);
1234}
1235
1236static int
1237spu2ppu_sniffer (const struct frame_unwind *self,
1238 struct frame_info *this_frame, void **this_prologue_cache)
1239{
1240 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1241 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1242 CORE_ADDR base, func, backchain;
1243 gdb_byte buf[4];
1244
f5656ead 1245 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_spu)
cc5f0d61
UW		 1246 return 0;
1247
1248 base = get_frame_sp (this_frame);
1249 func = get_frame_pc (this_frame);
1250 if (target_read_memory (base, buf, 4))
1251 return 0;
1252 backchain = extract_unsigned_integer (buf, 4, byte_order);
1253
1254 if (!backchain)
1255 {
1256 struct frame_info *fi;
1257
1258 struct spu2ppu_cache *cache
1259 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1260
1261 cache->frame_id = frame_id_build (base + 16, func);
1262
1263 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1264 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1265 break;
1266
1267 if (fi)
1268 {
1269 cache->regcache = frame_save_as_regcache (fi);
1270 *this_prologue_cache = cache;
1271 return 1;
1272 }
1273 else
1274 {
1275 struct regcache *regcache;
f5656ead 1276 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch ());
cc5f0d61
UW		 1277 cache->regcache = regcache_dup (regcache);
1278 *this_prologue_cache = cache;
1279 return 1;
1280 }
1281 }
1282
1283 return 0;
1284}
1285
1286static void
1287spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1288{
1289 struct spu2ppu_cache *cache = this_cache;
1290 regcache_xfree (cache->regcache);
1291}
1292
1293static const struct frame_unwind spu2ppu_unwind = {
1294 ARCH_FRAME,
8fbca658 1295 default_frame_unwind_stop_reason,
cc5f0d61
UW		 1296 spu2ppu_this_id,
1297 spu2ppu_prev_register,
1298 NULL,
1299 spu2ppu_sniffer,
1300 spu2ppu_dealloc_cache,
1301 spu2ppu_prev_arch,
1302};
1303
1304
771b4502
UW		 1305/* Function calling convention. */
1306
7b3dc0b7
UW		 1307static CORE_ADDR
1308spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1309{
1310 return sp & ~15;
1311}
1312
87805e63
UW		 1313static CORE_ADDR
1314spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1315 struct value **args, int nargs, struct type *value_type,
1316 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1317 struct regcache *regcache)
1318{
1319 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1320 sp = (sp - 4) & ~15;
1321 /* Store the address of that breakpoint */
1322 *bp_addr = sp;
1323 /* The call starts at the callee's entry point. */
1324 *real_pc = funaddr;
1325
1326 return sp;
1327}
1328
771b4502
UW		 1329static int
1330spu_scalar_value_p (struct type *type)
1331{
1332 switch (TYPE_CODE (type))
1333 {
1334 case TYPE_CODE_INT:
1335 case TYPE_CODE_ENUM:
1336 case TYPE_CODE_RANGE:
1337 case TYPE_CODE_CHAR:
1338 case TYPE_CODE_BOOL:
1339 case TYPE_CODE_PTR:
1340 case TYPE_CODE_REF:
1341 return TYPE_LENGTH (type) <= 16;
1342
1343 default:
1344 return 0;
1345 }
1346}
1347
1348static void
1349spu_value_to_regcache (struct regcache *regcache, int regnum,
1350 struct type *type, const gdb_byte *in)
1351{
1352 int len = TYPE_LENGTH (type);
1353
1354 if (spu_scalar_value_p (type))
1355 {
1356 int preferred_slot = len < 4 ? 4 - len : 0;
1357 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1358 }
1359 else
1360 {
1361 while (len >= 16)
1362 {
1363 regcache_cooked_write (regcache, regnum++, in);
1364 in += 16;
1365 len -= 16;
1366 }
1367
1368 if (len > 0)
1369 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1370 }
1371}
1372
1373static void
1374spu_regcache_to_value (struct regcache *regcache, int regnum,
1375 struct type *type, gdb_byte *out)
1376{
1377 int len = TYPE_LENGTH (type);
1378
1379 if (spu_scalar_value_p (type))
1380 {
1381 int preferred_slot = len < 4 ? 4 - len : 0;
1382 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1383 }
1384 else
1385 {
1386 while (len >= 16)
1387 {
1388 regcache_cooked_read (regcache, regnum++, out);
1389 out += 16;
1390 len -= 16;
1391 }
1392
1393 if (len > 0)
1394 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1395 }
1396}
1397
1398static CORE_ADDR
1399spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1400 struct regcache *regcache, CORE_ADDR bp_addr,
1401 int nargs, struct value **args, CORE_ADDR sp,
1402 int struct_return, CORE_ADDR struct_addr)
1403{
e17a4113 1404 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1405 CORE_ADDR sp_delta;
771b4502
UW		 1406 int i;
1407 int regnum = SPU_ARG1_REGNUM;
1408 int stack_arg = -1;
1409 gdb_byte buf[16];
1410
1411 /* Set the return address. */
1412 memset (buf, 0, sizeof buf);
85e747d2 1413 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1414 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1415
1416 /* If STRUCT_RETURN is true, then the struct return address (in
1417 STRUCT_ADDR) will consume the first argument-passing register.
1418 Both adjust the register count and store that value. */
1419 if (struct_return)
1420 {
1421 memset (buf, 0, sizeof buf);
85e747d2 1422 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1423 regcache_cooked_write (regcache, regnum++, buf);
1424 }
1425
1426 /* Fill in argument registers. */
1427 for (i = 0; i < nargs; i++)
1428 {
1429 struct value *arg = args[i];
1430 struct type *type = check_typedef (value_type (arg));
1431 const gdb_byte *contents = value_contents (arg);
354ecfd5 1432 int n_regs = align_up (TYPE_LENGTH (type), 16) / 16;
771b4502
UW		 1433
1434 /* If the argument doesn't wholly fit into registers, it and
1435 all subsequent arguments go to the stack. */
1436 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1437 {
1438 stack_arg = i;
1439 break;
1440 }
1441
1442 spu_value_to_regcache (regcache, regnum, type, contents);
1443 regnum += n_regs;
1444 }
1445
1446 /* Overflow arguments go to the stack. */
1447 if (stack_arg != -1)
1448 {
1449 CORE_ADDR ap;
1450
1451 /* Allocate all required stack size. */
1452 for (i = stack_arg; i < nargs; i++)
1453 {
1454 struct type *type = check_typedef (value_type (args[i]));
1455 sp -= align_up (TYPE_LENGTH (type), 16);
1456 }
1457
1458 /* Fill in stack arguments. */
1459 ap = sp;
1460 for (i = stack_arg; i < nargs; i++)
1461 {
1462 struct value *arg = args[i];
1463 struct type *type = check_typedef (value_type (arg));
1464 int len = TYPE_LENGTH (type);
1465 int preferred_slot;
1466
1467 if (spu_scalar_value_p (type))
1468 preferred_slot = len < 4 ? 4 - len : 0;
1469 else
1470 preferred_slot = 0;
1471
1472 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1473 ap += align_up (TYPE_LENGTH (type), 16);
1474 }
1475 }
1476
1477 /* Allocate stack frame header. */
1478 sp -= 32;
1479
ee82e879
UW		 1480 /* Store stack back chain. */
1481 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1482 target_write_memory (sp, buf, 16);
1483
9ff3afda 1484 /* Finally, update all slots of the SP register. */
e17a4113 1485 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1486 for (i = 0; i < 4; i++)
1487 {
e17a4113
UW		 1488 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1489 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1490 }
1491 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1492
1493 return sp;
1494}
1495
1496static struct frame_id
8d998b8f 1497spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1498{
85e747d2 1499 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1500 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1501 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1502 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1503}
1504
1505/* Function return value access. */
1506
1507static enum return_value_convention
6a3a010b 1508spu_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101
CV		 1509 struct type *type, struct regcache *regcache,
1510 gdb_byte *out, const gdb_byte *in)
771b4502 1511{
6a3a010b 1512 struct type *func_type = function ? value_type (function) : NULL;
771b4502 1513 enum return_value_convention rvc;
54fcddd0
UW		 1514 int opencl_vector = 0;
1515
598cfb71
UW		 1516 if (func_type)
1517 {
1518 func_type = check_typedef (func_type);
1519
1520 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1521 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1522
1523 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1524 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1525 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1526 && TYPE_VECTOR (type))
1527 opencl_vector = 1;
1528 }
771b4502
UW		 1529
1530 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1531 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1532 else
1533 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1534
1535 if (in)
1536 {
1537 switch (rvc)
1538 {
1539 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1540 if (opencl_vector && TYPE_LENGTH (type) == 2)
1541 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1542 else
1543 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
771b4502
UW		 1544 break;
1545
1546 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1547 error (_("Cannot set function return value."));
771b4502
UW		 1548 break;
1549 }
1550 }
1551 else if (out)
1552 {
1553 switch (rvc)
1554 {
1555 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1556 if (opencl_vector && TYPE_LENGTH (type) == 2)
1557 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1558 else
1559 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
771b4502
UW		 1560 break;
1561
1562 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1563 error (_("Function return value unknown."));
771b4502
UW		 1564 break;
1565 }
1566 }
1567
1568 return rvc;
1569}
1570
1571
1572/* Breakpoints. */
1573
1574static const gdb_byte *
c378eb4e
MS		 1575spu_breakpoint_from_pc (struct gdbarch *gdbarch,
1576 CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1577{
1578 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1579
1580 *lenptr = sizeof breakpoint;
1581 return breakpoint;
1582}
1583
d03285ec
UW		 1584static int
1585spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1586 struct bp_target_info *bp_tgt)
1587{
1588 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1589 that in a combined application, we have some breakpoints inserted in SPU
1590 code, and now the application forks (on the PPU side). GDB common code
1591 will assume that the fork system call copied all breakpoints into the new
1592 process' address space, and that all those copies now need to be removed
1593 (see breakpoint.c:detach_breakpoints).
1594
1595 While this is certainly true for PPU side breakpoints, it is not true
1596 for SPU side breakpoints. fork will clone the SPU context file
1597 descriptors, so that all the existing SPU contexts are in accessible
1598 in the new process. However, the contents of the SPU contexts themselves
1599 are *not* cloned. Therefore the effect of detach_breakpoints is to
1600 remove SPU breakpoints from the *original* SPU context's local store
1601 -- this is not the correct behaviour.
1602
1603 The workaround is to check whether the PID we are asked to remove this
1604 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1605 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1606 true in the context of detach_breakpoints. If so, we simply do nothing.
1607 [ Note that for the fork child process, it does not matter if breakpoints
1608 remain inserted, because those SPU contexts are not runnable anyway --
1609 the Linux kernel allows only the original process to invoke spu_run. */
1610
1611 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1612 return 0;
1613
1614 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1615}
1616
771b4502
UW		 1617
1618/* Software single-stepping support. */
1619
63807e1d 1620static int
0b1b3e42 1621spu_software_single_step (struct frame_info *frame)
771b4502 1622{
a6d9a66e 1623 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1624 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1625 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1626 CORE_ADDR pc, next_pc;
1627 unsigned int insn;
1628 int offset, reg;
1629 gdb_byte buf[4];
13def385 1630 ULONGEST lslr;
771b4502 1631
0b1b3e42 1632 pc = get_frame_pc (frame);
771b4502 1633
e0cd558a
UW		 1634 if (target_read_memory (pc, buf, 4))
1635 return 1;
e17a4113 1636 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1637
13def385
UW		 1638 /* Get local store limit. */
1639 lslr = get_frame_register_unsigned (frame, SPU_LSLR_REGNUM);
1640 if (!lslr)
1641 lslr = (ULONGEST) -1;
1642
e0cd558a
UW		 1643 /* Next sequential instruction is at PC + 4, except if the current
1644 instruction is a PPE-assisted call, in which case it is at PC + 8.
1645 Wrap around LS limit to be on the safe side. */
1646 if ((insn & 0xffffff00) == 0x00002100)
13def385 1647 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
e0cd558a 1648 else
13def385 1649 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
771b4502 1650
6c95b8df
PA		 1651 insert_single_step_breakpoint (gdbarch,
1652 aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1653
e0cd558a
UW		 1654 if (is_branch (insn, &offset, &reg))
1655 {
1656 CORE_ADDR target = offset;
771b4502 1657
e0cd558a 1658 if (reg == SPU_PC_REGNUM)
85e747d2 1659 target += SPUADDR_ADDR (pc);
e0cd558a
UW		 1660 else if (reg != -1)
1661 {
8dccd430
PA		 1662 int optim, unavail;
1663
1664 if (get_frame_register_bytes (frame, reg, 0, 4, buf,
1665 &optim, &unavail))
1666 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
1667 else
1668 {
1669 if (optim)
710409a2
PA		 1670 throw_error (OPTIMIZED_OUT_ERROR,
1671 _("Could not determine address of "
1672 "single-step breakpoint."));
8dccd430
PA		 1673 if (unavail)
1674 throw_error (NOT_AVAILABLE_ERROR,
1675 _("Could not determine address of "
1676 "single-step breakpoint."));
1677 }
771b4502 1678 }
e0cd558a 1679
13def385 1680 target = target & lslr;
e0cd558a 1681 if (target != next_pc)
6c95b8df 1682 insert_single_step_breakpoint (gdbarch, aspace,
85e747d2 1683 SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1684 }
e6590a1b
UW		 1685
1686 return 1;
771b4502
UW		 1687}
1688
6e3f70d7
UW		 1689
1690/* Longjmp support. */
1691
1692static int
1693spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1694{
e17a4113 1695 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1696 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1697 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1698 gdb_byte buf[4];
1699 CORE_ADDR jb_addr;
8dccd430 1700 int optim, unavail;
6e3f70d7
UW		 1701
1702 /* Jump buffer is pointed to by the argument register $r3. */
8dccd430
PA		 1703 if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1704 &optim, &unavail))
1705 return 0;
1706
e17a4113 1707 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1708 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1709 return 0;
1710
e17a4113 1711 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1712 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1713 return 1;
1714}
1715
1716
85e747d2
UW		 1717/* Disassembler. */
1718
1719struct spu_dis_asm_data
1720{
1721 struct gdbarch *gdbarch;
1722 int id;
1723};
1724
1725static void
1726spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1727{
1728 struct spu_dis_asm_data *data = info->application_data;
1729 print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1730}
1731
1732static int
1733gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1734{
c378eb4e
MS		 1735 /* The opcodes disassembler does 18-bit address arithmetic. Make
1736 sure the SPU ID encoded in the high bits is added back when we
1737 call print_address. */
85e747d2
UW		 1738 struct disassemble_info spu_info = *info;
1739 struct spu_dis_asm_data data;
1740 data.gdbarch = info->application_data;
1741 data.id = SPUADDR_SPU (memaddr);
1742
1743 spu_info.application_data = &data;
1744 spu_info.print_address_func = spu_dis_asm_print_address;
1745 return print_insn_spu (memaddr, &spu_info);
1746}
1747
1748
dcf52cd8
UW		 1749/* Target overlays for the SPU overlay manager.
1750
1751 See the documentation of simple_overlay_update for how the
1752 interface is supposed to work.
1753
1754 Data structures used by the overlay manager:
1755
1756 struct ovly_table
1757 {
1758 u32 vma;
1759 u32 size;
1760 u32 pos;
1761 u32 buf;
1762 } _ovly_table[]; -- one entry per overlay section
1763
1764 struct ovly_buf_table
1765 {
1766 u32 mapped;
1767 } _ovly_buf_table[]; -- one entry per overlay buffer
1768
1769 _ovly_table should never change.
1770
c378eb4e
MS		 1771 Both tables are aligned to a 16-byte boundary, the symbols
1772 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1773 size set to the size of the respective array. buf in _ovly_table is
1774 an index into _ovly_buf_table.
dcf52cd8 1775
c378eb4e 1776 mapped is an index into _ovly_table. Both the mapped and buf indices start
dcf52cd8
UW		 1777 from one to reference the first entry in their respective tables. */
1778
1779/* Using the per-objfile private data mechanism, we store for each
1780 objfile an array of "struct spu_overlay_table" structures, one
1781 for each obj_section of the objfile. This structure holds two
1782 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1783 is *not* an overlay section. If it is non-zero, it represents
1784 a target address. The overlay section is mapped iff the target
1785 integer at this location equals MAPPED_VAL. */
1786
1787static const struct objfile_data *spu_overlay_data;
1788
1789struct spu_overlay_table
1790 {
1791 CORE_ADDR mapped_ptr;
1792 CORE_ADDR mapped_val;
1793 };
1794
1795/* Retrieve the overlay table for OBJFILE. If not already cached, read
1796 the _ovly_table data structure from the target and initialize the
1797 spu_overlay_table data structure from it. */
1798static struct spu_overlay_table *
1799spu_get_overlay_table (struct objfile *objfile)
1800{
e17a4113
UW		 1801 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1802 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3b7344d5 1803 struct bound_minimal_symbol ovly_table_msym, ovly_buf_table_msym;
dcf52cd8
UW		 1804 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1805 unsigned ovly_table_size, ovly_buf_table_size;
1806 struct spu_overlay_table *tbl;
1807 struct obj_section *osect;
948f8e3d 1808 gdb_byte *ovly_table;
dcf52cd8
UW		 1809 int i;
1810
1811 tbl = objfile_data (objfile, spu_overlay_data);
1812 if (tbl)
1813 return tbl;
1814
1815 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
3b7344d5 1816 if (!ovly_table_msym.minsym)
dcf52cd8
UW		 1817 return NULL;
1818
c378eb4e
MS		 1819 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1820 NULL, objfile);
3b7344d5 1821 if (!ovly_buf_table_msym.minsym)
dcf52cd8
UW		 1822 return NULL;
1823
77e371c0 1824 ovly_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_table_msym);
3b7344d5 1825 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym.minsym);
dcf52cd8 1826
77e371c0 1827 ovly_buf_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
3b7344d5 1828 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym.minsym);
dcf52cd8
UW		 1829
1830 ovly_table = xmalloc (ovly_table_size);
1831 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1832
1833 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1834 objfile->sections_end - objfile->sections,
1835 struct spu_overlay_table);
1836
1837 for (i = 0; i < ovly_table_size / 16; i++)
1838 {
e17a4113
UW		 1839 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1840 4, byte_order);
1841 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1842 4, byte_order);
1843 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1844 4, byte_order);
1845 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1846 4, byte_order);
dcf52cd8
UW		 1847
1848 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1849 continue;
1850
1851 ALL_OBJFILE_OSECTIONS (objfile, osect)
1852 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1853 && pos == osect->the_bfd_section->filepos)
1854 {
1855 int ndx = osect - objfile->sections;
1856 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1857 tbl[ndx].mapped_val = i + 1;
1858 break;
1859 }
1860 }
1861
1862 xfree (ovly_table);
1863 set_objfile_data (objfile, spu_overlay_data, tbl);
1864 return tbl;
1865}
1866
1867/* Read _ovly_buf_table entry from the target to dermine whether
1868 OSECT is currently mapped, and update the mapped state. */
1869static void
1870spu_overlay_update_osect (struct obj_section *osect)
1871{
e17a4113
UW		 1872 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1873 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1874 struct spu_overlay_table *ovly_table;
85e747d2 1875 CORE_ADDR id, val;
dcf52cd8
UW		 1876
1877 ovly_table = spu_get_overlay_table (osect->objfile);
1878 if (!ovly_table)
1879 return;
1880
1881 ovly_table += osect - osect->objfile->sections;
1882 if (ovly_table->mapped_ptr == 0)
1883 return;
1884
85e747d2
UW		 1885 id = SPUADDR_SPU (obj_section_addr (osect));
1886 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1887 4, byte_order);
dcf52cd8
UW		 1888 osect->ovly_mapped = (val == ovly_table->mapped_val);
1889}
1890
1891/* If OSECT is NULL, then update all sections' mapped state.
1892 If OSECT is non-NULL, then update only OSECT's mapped state. */
1893static void
1894spu_overlay_update (struct obj_section *osect)
1895{
1896 /* Just one section. */
1897 if (osect)
1898 spu_overlay_update_osect (osect);
1899
1900 /* All sections. */
1901 else
1902 {
1903 struct objfile *objfile;
1904
1905 ALL_OBJSECTIONS (objfile, osect)
714835d5 1906 if (section_is_overlay (osect))
dcf52cd8
UW		 1907 spu_overlay_update_osect (osect);
1908 }
1909}
1910
1911/* Whenever a new objfile is loaded, read the target's _ovly_table.
1912 If there is one, go through all sections and make sure for non-
1913 overlay sections LMA equals VMA, while for overlay sections LMA
d2ed6730 1914 is larger than SPU_OVERLAY_LMA. */
dcf52cd8
UW		 1915static void
1916spu_overlay_new_objfile (struct objfile *objfile)
1917{
1918 struct spu_overlay_table *ovly_table;
1919 struct obj_section *osect;
1920
1921 /* If we've already touched this file, do nothing. */
1922 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1923 return;
1924
0391f248
UW		 1925 /* Consider only SPU objfiles. */
1926 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1927 return;
1928
dcf52cd8
UW		 1929 /* Check if this objfile has overlays. */
1930 ovly_table = spu_get_overlay_table (objfile);
1931 if (!ovly_table)
1932 return;
1933
1934 /* Now go and fiddle with all the LMAs. */
1935 ALL_OBJFILE_OSECTIONS (objfile, osect)
1936 {
1937 bfd *obfd = objfile->obfd;
1938 asection *bsect = osect->the_bfd_section;
1939 int ndx = osect - objfile->sections;
1940
1941 if (ovly_table[ndx].mapped_ptr == 0)
1942 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1943 else
d2ed6730 1944 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
dcf52cd8
UW		 1945 }
1946}
1947
771b4502 1948
3285f3fe
UW		 1949/* Insert temporary breakpoint on "main" function of newly loaded
1950 SPE context OBJFILE. */
1951static void
1952spu_catch_start (struct objfile *objfile)
1953{
3b7344d5 1954 struct bound_minimal_symbol minsym;
43f3e411 1955 struct compunit_symtab *cust;
3285f3fe
UW		 1956 CORE_ADDR pc;
1957 char buf[32];
1958
1959 /* Do this only if requested by "set spu stop-on-load on". */
1960 if (!spu_stop_on_load_p)
1961 return;
1962
1963 /* Consider only SPU objfiles. */
1964 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1965 return;
1966
1967 /* The main objfile is handled differently. */
1968 if (objfile == symfile_objfile)
1969 return;
1970
1971 /* There can be multiple symbols named "main". Search for the
1972 "main" in *this* objfile. */
1973 minsym = lookup_minimal_symbol ("main", NULL, objfile);
3b7344d5 1974 if (!minsym.minsym)
3285f3fe
UW		 1975 return;
1976
1977 /* If we have debugging information, try to use it -- this
1978 will allow us to properly skip the prologue. */
77e371c0 1979 pc = BMSYMBOL_VALUE_ADDRESS (minsym);
43f3e411
DE		 1980 cust
1981 = find_pc_sect_compunit_symtab (pc, MSYMBOL_OBJ_SECTION (minsym.objfile,
1982 minsym.minsym));
1983 if (cust != NULL)
3285f3fe 1984 {
43f3e411 1985 const struct blockvector *bv = COMPUNIT_BLOCKVECTOR (cust);
3285f3fe
UW		 1986 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1987 struct symbol *sym;
1988 struct symtab_and_line sal;
1989
16b2eaa1 1990 sym = block_lookup_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1991 if (sym)
1992 {
1993 fixup_symbol_section (sym, objfile);
1994 sal = find_function_start_sal (sym, 1);
1995 pc = sal.pc;
1996 }
1997 }
1998
1999 /* Use a numerical address for the set_breakpoint command to avoid having
2000 the breakpoint re-set incorrectly. */
2001 xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
d8c09fb5
JK		 2002 create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
2003 NULL /* cond_string */, -1 /* thread */,
6a609e58 2004 NULL /* extra_string */,
d8c09fb5 2005 0 /* parse_condition_and_thread */, 1 /* tempflag */,
bddaafad 2006 bp_breakpoint /* type_wanted */,
d8c09fb5
JK		 2007 0 /* ignore_count */,
2008 AUTO_BOOLEAN_FALSE /* pending_break_support */,
931bb47f 2009 &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
44f238bb 2010 1 /* enabled */, 0 /* internal */, 0);
3285f3fe
UW		 2011}
2012
2013
ff1a52c6
UW		 2014/* Look up OBJFILE loaded into FRAME's SPU context. */
2015static struct objfile *
2016spu_objfile_from_frame (struct frame_info *frame)
2017{
2018 struct gdbarch *gdbarch = get_frame_arch (frame);
2019 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2020 struct objfile *obj;
2021
2022 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2023 return NULL;
2024
2025 ALL_OBJFILES (obj)
2026 {
2027 if (obj->sections != obj->sections_end
2028 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
2029 return obj;
2030 }
2031
2032 return NULL;
2033}
2034
2035/* Flush cache for ea pointer access if available. */
2036static void
2037flush_ea_cache (void)
2038{
3b7344d5 2039 struct bound_minimal_symbol msymbol;
ff1a52c6
UW		 2040 struct objfile *obj;
2041
2042 if (!has_stack_frames ())
2043 return;
2044
2045 obj = spu_objfile_from_frame (get_current_frame ());
2046 if (obj == NULL)
2047 return;
2048
2049 /* Lookup inferior function __cache_flush. */
2050 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
3b7344d5 2051 if (msymbol.minsym != NULL)
ff1a52c6
UW		 2052 {
2053 struct type *type;
2054 CORE_ADDR addr;
2055
2056 type = objfile_type (obj)->builtin_void;
2057 type = lookup_function_type (type);
2058 type = lookup_pointer_type (type);
77e371c0 2059 addr = BMSYMBOL_VALUE_ADDRESS (msymbol);
ff1a52c6
UW		 2060
2061 call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
2062 }
2063}
2064
2065/* This handler is called when the inferior has stopped. If it is stopped in
2066 SPU architecture then flush the ea cache if used. */
2067static void
2068spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2069{
2070 if (!spu_auto_flush_cache_p)
2071 return;
2072
2073 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2074 re-entering this function when __cache_flush stops. */
2075 spu_auto_flush_cache_p = 0;
2076 flush_ea_cache ();
2077 spu_auto_flush_cache_p = 1;
2078}
2079
2080
23d964e7
UW		 2081/* "info spu" commands. */
2082
2083static void
2084info_spu_event_command (char *args, int from_tty)
2085{
2086 struct frame_info *frame = get_selected_frame (NULL);
2087 ULONGEST event_status = 0;
2088 ULONGEST event_mask = 0;
2089 struct cleanup *chain;
2090 gdb_byte buf[100];
2091 char annex[32];
2092 LONGEST len;
22e048c9 2093 int id;
23d964e7 2094
0391f248
UW		 2095 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2096 error (_("\"info spu\" is only supported on the SPU architecture."));
2097
23d964e7
UW		 2098 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2099
2100 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2101 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2102 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2103 if (len <= 0)
2104 error (_("Could not read event_status."));
9971ac47 2105 buf[len] = '\0';
001f13d8 2106 event_status = strtoulst ((char *) buf, NULL, 16);
23d964e7
UW		 2107
2108 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2109 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2110 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2111 if (len <= 0)
2112 error (_("Could not read event_mask."));
9971ac47 2113 buf[len] = '\0';
001f13d8 2114 event_mask = strtoulst ((char *) buf, NULL, 16);
23d964e7 2115
31a0ae49 2116 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoEvent");
23d964e7 2117
31a0ae49 2118 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2119 {
31a0ae49 2120 ui_out_field_fmt (current_uiout, "event_status",
23d964e7 2121 "0x%s", phex_nz (event_status, 4));
31a0ae49 2122 ui_out_field_fmt (current_uiout, "event_mask",
23d964e7
UW		 2123 "0x%s", phex_nz (event_mask, 4));
2124 }
2125 else
2126 {
2127 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2128 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2129 }
2130
2131 do_cleanups (chain);
2132}
2133
2134static void
2135info_spu_signal_command (char *args, int from_tty)
2136{
2137 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2138 struct gdbarch *gdbarch = get_frame_arch (frame);
2139 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2140 ULONGEST signal1 = 0;
2141 ULONGEST signal1_type = 0;
2142 int signal1_pending = 0;
2143 ULONGEST signal2 = 0;
2144 ULONGEST signal2_type = 0;
2145 int signal2_pending = 0;
2146 struct cleanup *chain;
2147 char annex[32];
2148 gdb_byte buf[100];
2149 LONGEST len;
22e048c9 2150 int id;
23d964e7 2151
e17a4113 2152 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2153 error (_("\"info spu\" is only supported on the SPU architecture."));
2154
23d964e7
UW		 2155 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2156
2157 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2158 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2159 if (len < 0)
2160 error (_("Could not read signal1."));
2161 else if (len == 4)
2162 {
e17a4113 2163 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2164 signal1_pending = 1;
2165 }
2166
2167 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2168 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2169 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2170 if (len <= 0)
2171 error (_("Could not read signal1_type."));
9971ac47 2172 buf[len] = '\0';
001f13d8 2173 signal1_type = strtoulst ((char *) buf, NULL, 16);
23d964e7
UW		 2174
2175 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2176 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2177 if (len < 0)
2178 error (_("Could not read signal2."));
2179 else if (len == 4)
2180 {
e17a4113 2181 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2182 signal2_pending = 1;
2183 }
2184
2185 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2186 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2187 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2188 if (len <= 0)
2189 error (_("Could not read signal2_type."));
9971ac47 2190 buf[len] = '\0';
001f13d8 2191 signal2_type = strtoulst ((char *) buf, NULL, 16);
23d964e7 2192
31a0ae49 2193 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoSignal");
23d964e7 2194
31a0ae49 2195 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2196 {
31a0ae49
JK		 2197 ui_out_field_int (current_uiout, "signal1_pending", signal1_pending);
2198 ui_out_field_fmt (current_uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2199 ui_out_field_int (current_uiout, "signal1_type", signal1_type);
2200 ui_out_field_int (current_uiout, "signal2_pending", signal2_pending);
2201 ui_out_field_fmt (current_uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2202 ui_out_field_int (current_uiout, "signal2_type", signal2_type);
23d964e7
UW		 2203 }
2204 else
2205 {
2206 if (signal1_pending)
2207 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2208 else
2209 printf_filtered (_("Signal 1 not pending "));
2210
2211 if (signal1_type)
23d964e7 2212 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2213 else
2214 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2215
2216 if (signal2_pending)
2217 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2218 else
2219 printf_filtered (_("Signal 2 not pending "));
2220
2221 if (signal2_type)
23d964e7 2222 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2223 else
2224 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2225 }
2226
2227 do_cleanups (chain);
2228}
2229
2230static void
e17a4113 2231info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2232 const char *field, const char *msg)
2233{
2234 struct cleanup *chain;
2235 int i;
2236
2237 if (nr <= 0)
2238 return;
2239
31a0ae49 2240 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 1, nr, "mbox");
23d964e7 2241
31a0ae49
JK		 2242 ui_out_table_header (current_uiout, 32, ui_left, field, msg);
2243 ui_out_table_body (current_uiout);
23d964e7
UW		 2244
2245 for (i = 0; i < nr; i++)
2246 {
2247 struct cleanup *val_chain;
2248 ULONGEST val;
31a0ae49 2249 val_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "mbox");
e17a4113 2250 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
31a0ae49 2251 ui_out_field_fmt (current_uiout, field, "0x%s", phex (val, 4));
23d964e7
UW		 2252 do_cleanups (val_chain);
2253
31a0ae49 2254 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2255 printf_filtered ("\n");
2256 }
2257
2258 do_cleanups (chain);
2259}
2260
2261static void
2262info_spu_mailbox_command (char *args, int from_tty)
2263{
2264 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2265 struct gdbarch *gdbarch = get_frame_arch (frame);
2266 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2267 struct cleanup *chain;
2268 char annex[32];
2269 gdb_byte buf[1024];
2270 LONGEST len;
22e048c9 2271 int id;
23d964e7 2272
e17a4113 2273 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2274 error (_("\"info spu\" is only supported on the SPU architecture."));
2275
23d964e7
UW		 2276 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2277
31a0ae49 2278 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoMailbox");
23d964e7
UW		 2279
2280 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2281 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2282 buf, 0, sizeof buf);
2283 if (len < 0)
2284 error (_("Could not read mbox_info."));
2285
e17a4113
UW		 2286 info_spu_mailbox_list (buf, len / 4, byte_order,
2287 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2288
2289 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2290 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2291 buf, 0, sizeof buf);
2292 if (len < 0)
2293 error (_("Could not read ibox_info."));
2294
e17a4113
UW		 2295 info_spu_mailbox_list (buf, len / 4, byte_order,
2296 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2297
2298 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2299 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2300 buf, 0, sizeof buf);
2301 if (len < 0)
2302 error (_("Could not read wbox_info."));
2303
e17a4113
UW		 2304 info_spu_mailbox_list (buf, len / 4, byte_order,
2305 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2306
2307 do_cleanups (chain);
2308}
2309
2310static ULONGEST
2311spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2312{
2313 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2314 return (word >> (63 - last)) & mask;
2315}
2316
2317static void
e17a4113 2318info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7
UW		 2319{
2320 static char *spu_mfc_opcode[256] =
2321 {
2322 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2323 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2324 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2325 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2326 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2327 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2328 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2329 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2330 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2331 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2332 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2333 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2334 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2335 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2336 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2337 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2338 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2339 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2340 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2341 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2342 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2343 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2344 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2345 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2346 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2347 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2348 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2349 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2350 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2351 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2352 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2353 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2354 };
2355
12ab8a60
UW		 2356 int *seq = alloca (nr * sizeof (int));
2357 int done = 0;
23d964e7 2358 struct cleanup *chain;
12ab8a60
UW		 2359 int i, j;
2360
2361
2362 /* Determine sequence in which to display (valid) entries. */
2363 for (i = 0; i < nr; i++)
2364 {
2365 /* Search for the first valid entry all of whose
2366 dependencies are met. */
2367 for (j = 0; j < nr; j++)
2368 {
2369 ULONGEST mfc_cq_dw3;
2370 ULONGEST dependencies;
2371
2372 if (done & (1 << (nr - 1 - j)))
2373 continue;
2374
e17a4113
UW		 2375 mfc_cq_dw3
2376 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2377 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2378 continue;
2379
2380 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2381 if ((dependencies & done) != dependencies)
2382 continue;
2383
2384 seq[i] = j;
2385 done |= 1 << (nr - 1 - j);
2386 break;
2387 }
2388
2389 if (j == nr)
2390 break;
2391 }
2392
2393 nr = i;
2394
23d964e7 2395
31a0ae49
JK		 2396 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 10, nr,
2397 "dma_cmd");
23d964e7 2398
31a0ae49
JK		 2399 ui_out_table_header (current_uiout, 7, ui_left, "opcode", "Opcode");
2400 ui_out_table_header (current_uiout, 3, ui_left, "tag", "Tag");
2401 ui_out_table_header (current_uiout, 3, ui_left, "tid", "TId");
2402 ui_out_table_header (current_uiout, 3, ui_left, "rid", "RId");
2403 ui_out_table_header (current_uiout, 18, ui_left, "ea", "EA");
2404 ui_out_table_header (current_uiout, 7, ui_left, "lsa", "LSA");
2405 ui_out_table_header (current_uiout, 7, ui_left, "size", "Size");
2406 ui_out_table_header (current_uiout, 7, ui_left, "lstaddr", "LstAddr");
2407 ui_out_table_header (current_uiout, 7, ui_left, "lstsize", "LstSize");
2408 ui_out_table_header (current_uiout, 1, ui_left, "error_p", "E");
23d964e7 2409
31a0ae49 2410 ui_out_table_body (current_uiout);
23d964e7
UW		 2411
2412 for (i = 0; i < nr; i++)
2413 {
2414 struct cleanup *cmd_chain;
2415 ULONGEST mfc_cq_dw0;
2416 ULONGEST mfc_cq_dw1;
2417 ULONGEST mfc_cq_dw2;
23d964e7 2418 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
22e048c9 2419 int list_lsa, list_size, mfc_lsa, mfc_size;
23d964e7
UW		 2420 ULONGEST mfc_ea;
2421 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2422
2423 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2424 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2425
e17a4113
UW		 2426 mfc_cq_dw0
2427 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2428 mfc_cq_dw1
2429 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2430 mfc_cq_dw2
2431 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2432
2433 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2434 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2435 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2436 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2437 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2438 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2439 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2440
2441 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2442 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2443
2444 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2445 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2446 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2447 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2448 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2449 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2450
31a0ae49 2451 cmd_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "cmd");
23d964e7
UW		 2452
2453 if (spu_mfc_opcode[mfc_cmd_opcode])
31a0ae49 2454 ui_out_field_string (current_uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
23d964e7 2455 else
31a0ae49 2456 ui_out_field_int (current_uiout, "opcode", mfc_cmd_opcode);
23d964e7 2457
31a0ae49
JK		 2458 ui_out_field_int (current_uiout, "tag", mfc_cmd_tag);
2459 ui_out_field_int (current_uiout, "tid", tclass_id);
2460 ui_out_field_int (current_uiout, "rid", rclass_id);
23d964e7
UW		 2461
2462 if (ea_valid_p)
31a0ae49 2463 ui_out_field_fmt (current_uiout, "ea", "0x%s", phex (mfc_ea, 8));
23d964e7 2464 else
31a0ae49 2465 ui_out_field_skip (current_uiout, "ea");
23d964e7 2466
31a0ae49 2467 ui_out_field_fmt (current_uiout, "lsa", "0x%05x", mfc_lsa << 4);
23d964e7 2468 if (qw_valid_p)
31a0ae49 2469 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size << 4);
23d964e7 2470 else
31a0ae49 2471 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size);
23d964e7
UW		 2472
2473 if (list_valid_p)
2474 {
31a0ae49
JK		 2475 ui_out_field_fmt (current_uiout, "lstaddr", "0x%05x", list_lsa << 3);
2476 ui_out_field_fmt (current_uiout, "lstsize", "0x%05x", list_size << 3);
23d964e7
UW		 2477 }
2478 else
2479 {
31a0ae49
JK		 2480 ui_out_field_skip (current_uiout, "lstaddr");
2481 ui_out_field_skip (current_uiout, "lstsize");
23d964e7
UW		 2482 }
2483
2484 if (cmd_error_p)
31a0ae49 2485 ui_out_field_string (current_uiout, "error_p", "*");
23d964e7 2486 else
31a0ae49 2487 ui_out_field_skip (current_uiout, "error_p");
23d964e7
UW		 2488
2489 do_cleanups (cmd_chain);
2490
31a0ae49 2491 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2492 printf_filtered ("\n");
2493 }
2494
2495 do_cleanups (chain);
2496}
2497
2498static void
2499info_spu_dma_command (char *args, int from_tty)
2500{
2501 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2502 struct gdbarch *gdbarch = get_frame_arch (frame);
2503 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2504 ULONGEST dma_info_type;
2505 ULONGEST dma_info_mask;
2506 ULONGEST dma_info_status;
2507 ULONGEST dma_info_stall_and_notify;
2508 ULONGEST dma_info_atomic_command_status;
2509 struct cleanup *chain;
2510 char annex[32];
2511 gdb_byte buf[1024];
2512 LONGEST len;
22e048c9 2513 int id;
23d964e7 2514
0391f248
UW		 2515 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2516 error (_("\"info spu\" is only supported on the SPU architecture."));
2517
23d964e7
UW		 2518 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2519
2520 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2521 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2522 buf, 0, 40 + 16 * 32);
2523 if (len <= 0)
2524 error (_("Could not read dma_info."));
2525
e17a4113
UW		 2526 dma_info_type
2527 = extract_unsigned_integer (buf, 8, byte_order);
2528 dma_info_mask
2529 = extract_unsigned_integer (buf + 8, 8, byte_order);
2530 dma_info_status
2531 = extract_unsigned_integer (buf + 16, 8, byte_order);
2532 dma_info_stall_and_notify
2533 = extract_unsigned_integer (buf + 24, 8, byte_order);
2534 dma_info_atomic_command_status
2535 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7 2536
31a0ae49 2537 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoDMA");
23d964e7 2538
31a0ae49 2539 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2540 {
31a0ae49 2541 ui_out_field_fmt (current_uiout, "dma_info_type", "0x%s",
23d964e7 2542 phex_nz (dma_info_type, 4));
31a0ae49 2543 ui_out_field_fmt (current_uiout, "dma_info_mask", "0x%s",
23d964e7 2544 phex_nz (dma_info_mask, 4));
31a0ae49 2545 ui_out_field_fmt (current_uiout, "dma_info_status", "0x%s",
23d964e7 2546 phex_nz (dma_info_status, 4));
31a0ae49 2547 ui_out_field_fmt (current_uiout, "dma_info_stall_and_notify", "0x%s",
23d964e7 2548 phex_nz (dma_info_stall_and_notify, 4));
31a0ae49 2549 ui_out_field_fmt (current_uiout, "dma_info_atomic_command_status", "0x%s",
23d964e7
UW		 2550 phex_nz (dma_info_atomic_command_status, 4));
2551 }
2552 else
2553 {
8fbde58b 2554 const char *query_msg = _("no query pending");
23d964e7 2555
8fbde58b
UW		 2556 if (dma_info_type & 4)
2557 switch (dma_info_type & 3)
2558 {
2559 case 1: query_msg = _("'any' query pending"); break;
2560 case 2: query_msg = _("'all' query pending"); break;
2561 default: query_msg = _("undefined query type"); break;
2562 }
23d964e7
UW		 2563
2564 printf_filtered (_("Tag-Group Status 0x%s\n"),
2565 phex (dma_info_status, 4));
2566 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2567 phex (dma_info_mask, 4), query_msg);
2568 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2569 phex (dma_info_stall_and_notify, 4));
2570 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2571 phex (dma_info_atomic_command_status, 4));
2572 printf_filtered ("\n");
2573 }
2574
e17a4113 2575 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2576 do_cleanups (chain);
2577}
2578
2579static void
2580info_spu_proxydma_command (char *args, int from_tty)
2581{
2582 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2583 struct gdbarch *gdbarch = get_frame_arch (frame);
2584 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2585 ULONGEST dma_info_type;
2586 ULONGEST dma_info_mask;
2587 ULONGEST dma_info_status;
2588 struct cleanup *chain;
2589 char annex[32];
2590 gdb_byte buf[1024];
2591 LONGEST len;
22e048c9 2592 int id;
23d964e7 2593
e17a4113 2594 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2595 error (_("\"info spu\" is only supported on the SPU architecture."));
2596
23d964e7
UW		 2597 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2598
2599 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2600 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2601 buf, 0, 24 + 8 * 32);
2602 if (len <= 0)
2603 error (_("Could not read proxydma_info."));
2604
e17a4113
UW		 2605 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2606 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2607 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7 2608
31a0ae49
JK		 2609 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout,
2610 "SPUInfoProxyDMA");
23d964e7 2611
31a0ae49 2612 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2613 {
31a0ae49 2614 ui_out_field_fmt (current_uiout, "proxydma_info_type", "0x%s",
23d964e7 2615 phex_nz (dma_info_type, 4));
31a0ae49 2616 ui_out_field_fmt (current_uiout, "proxydma_info_mask", "0x%s",
23d964e7 2617 phex_nz (dma_info_mask, 4));
31a0ae49 2618 ui_out_field_fmt (current_uiout, "proxydma_info_status", "0x%s",
23d964e7
UW		 2619 phex_nz (dma_info_status, 4));
2620 }
2621 else
2622 {
2623 const char *query_msg;
2624
8fbde58b 2625 switch (dma_info_type & 3)
23d964e7
UW		 2626 {
2627 case 0: query_msg = _("no query pending"); break;
2628 case 1: query_msg = _("'any' query pending"); break;
2629 case 2: query_msg = _("'all' query pending"); break;
2630 default: query_msg = _("undefined query type"); break;
2631 }
2632
2633 printf_filtered (_("Tag-Group Status 0x%s\n"),
2634 phex (dma_info_status, 4));
2635 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2636 phex (dma_info_mask, 4), query_msg);
2637 printf_filtered ("\n");
2638 }
2639
e17a4113 2640 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2641 do_cleanups (chain);
2642}
2643
2644static void
2645info_spu_command (char *args, int from_tty)
2646{
c378eb4e
MS		 2647 printf_unfiltered (_("\"info spu\" must be followed by "
2648 "the name of an SPU facility.\n"));
635c7e8a 2649 help_list (infospucmdlist, "info spu ", all_commands, gdb_stdout);
23d964e7
UW		 2650}
2651
2652
3285f3fe
UW		 2653/* Root of all "set spu "/"show spu " commands. */
2654
2655static void
2656show_spu_command (char *args, int from_tty)
2657{
2658 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2659}
2660
2661static void
2662set_spu_command (char *args, int from_tty)
2663{
2664 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2665}
2666
2667static void
2668show_spu_stop_on_load (struct ui_file *file, int from_tty,
2669 struct cmd_list_element *c, const char *value)
2670{
2671 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2672 value);
2673}
2674
ff1a52c6
UW		 2675static void
2676show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2677 struct cmd_list_element *c, const char *value)
2678{
2679 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2680 value);
2681}
2682
3285f3fe 2683
771b4502
UW		 2684/* Set up gdbarch struct. */
2685
2686static struct gdbarch *
2687spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2688{
2689 struct gdbarch *gdbarch;
794ac428 2690 struct gdbarch_tdep *tdep;
85e747d2
UW		 2691 int id = -1;
2692
2693 /* Which spufs ID was requested as address space? */
2694 if (info.tdep_info)
2695 id = *(int *)info.tdep_info;
2696 /* For objfile architectures of SPU solibs, decode the ID from the name.
2697 This assumes the filename convention employed by solib-spu.c. */
2698 else if (info.abfd)
2699 {
53e78085 2700 const char *name = strrchr (info.abfd->filename, '@');
85e747d2
UW		 2701 if (name)
2702 sscanf (name, "@0x%*x <%d>", &id);
2703 }
771b4502 2704
85e747d2
UW		 2705 /* Find a candidate among extant architectures. */
2706 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2707 arches != NULL;
2708 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2709 {
2710 tdep = gdbarch_tdep (arches->gdbarch);
2711 if (tdep && tdep->id == id)
2712 return arches->gdbarch;
2713 }
771b4502 2714
85e747d2 2715 /* None found, so create a new architecture. */
fc270c35 2716 tdep = XCNEW (struct gdbarch_tdep);
85e747d2 2717 tdep->id = id;
794ac428 2718 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2719
2720 /* Disassembler. */
85e747d2 2721 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2722
2723 /* Registers. */
2724 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2725 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2726 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2727 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2728 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2729 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2730 set_gdbarch_register_name (gdbarch, spu_register_name);
2731 set_gdbarch_register_type (gdbarch, spu_register_type);
2732 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2733 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2734 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502 2735 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
7ce16bd4
UW		 2736 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, spu_dwarf_reg_to_regnum);
2737 set_gdbarch_ax_pseudo_register_collect
2738 (gdbarch, spu_ax_pseudo_register_collect);
2739 set_gdbarch_ax_pseudo_register_push_stack
2740 (gdbarch, spu_ax_pseudo_register_push_stack);
771b4502
UW		 2741
2742 /* Data types. */
2743 set_gdbarch_char_signed (gdbarch, 0);
2744 set_gdbarch_ptr_bit (gdbarch, 32);
2745 set_gdbarch_addr_bit (gdbarch, 32);
2746 set_gdbarch_short_bit (gdbarch, 16);
2747 set_gdbarch_int_bit (gdbarch, 32);
2748 set_gdbarch_long_bit (gdbarch, 32);
2749 set_gdbarch_long_long_bit (gdbarch, 64);
2750 set_gdbarch_float_bit (gdbarch, 32);
2751 set_gdbarch_double_bit (gdbarch, 64);
2752 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2753 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2754 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2755 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2756
ff1a52c6 2757 /* Address handling. */
85e747d2 2758 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2759 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2760 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2761 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2762 set_gdbarch_address_class_type_flags_to_name
2763 (gdbarch, spu_address_class_type_flags_to_name);
2764 set_gdbarch_address_class_name_to_type_flags
2765 (gdbarch, spu_address_class_name_to_type_flags);
2766
36acd84e 2767
771b4502 2768 /* Inferior function calls. */
7b3dc0b7
UW		 2769 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2770 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2771 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2772 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2773 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2774 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2775 set_gdbarch_return_value (gdbarch, spu_return_value);
2776
2777 /* Frame handling. */
2778 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7ce16bd4 2779 dwarf2_append_unwinders (gdbarch);
8d998b8f 2780 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2781 frame_base_set_default (gdbarch, &spu_frame_base);
2782 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2783 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2784 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2785 set_gdbarch_frame_args_skip (gdbarch, 0);
2786 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
c9cf6e20 2787 set_gdbarch_stack_frame_destroyed_p (gdbarch, spu_stack_frame_destroyed_p);
771b4502 2788
cc5f0d61
UW		 2789 /* Cell/B.E. cross-architecture unwinder support. */
2790 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2791
771b4502
UW		 2792 /* Breakpoints. */
2793 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2794 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
d03285ec 2795 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
771b4502 2796 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2797 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2798
dcf52cd8
UW		 2799 /* Overlays. */
2800 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2801
771b4502
UW		 2802 return gdbarch;
2803}
2804
63807e1d
PA		 2805/* Provide a prototype to silence -Wmissing-prototypes. */
2806extern initialize_file_ftype _initialize_spu_tdep;
2807
771b4502
UW		 2808void
2809_initialize_spu_tdep (void)
2810{
2811 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2812
dcf52cd8
UW		 2813 /* Add ourselves to objfile event chain. */
2814 observer_attach_new_objfile (spu_overlay_new_objfile);
2815 spu_overlay_data = register_objfile_data ();
23d964e7 2816
3285f3fe
UW		 2817 /* Install spu stop-on-load handler. */
2818 observer_attach_new_objfile (spu_catch_start);
2819
ff1a52c6
UW		 2820 /* Add ourselves to normal_stop event chain. */
2821 observer_attach_normal_stop (spu_attach_normal_stop);
2822
3285f3fe
UW		 2823 /* Add root prefix command for all "set spu"/"show spu" commands. */
2824 add_prefix_cmd ("spu", no_class, set_spu_command,
2825 _("Various SPU specific commands."),
2826 &setspucmdlist, "set spu ", 0, &setlist);
2827 add_prefix_cmd ("spu", no_class, show_spu_command,
2828 _("Various SPU specific commands."),
2829 &showspucmdlist, "show spu ", 0, &showlist);
2830
2831 /* Toggle whether or not to add a temporary breakpoint at the "main"
2832 function of new SPE contexts. */
2833 add_setshow_boolean_cmd ("stop-on-load", class_support,
2834 &spu_stop_on_load_p, _("\
2835Set whether to stop for new SPE threads."),
2836 _("\
2837Show whether to stop for new SPE threads."),
2838 _("\
2839Use \"on\" to give control to the user when a new SPE thread\n\
2840enters its \"main\" function.\n\
2841Use \"off\" to disable stopping for new SPE threads."),
2842 NULL,
2843 show_spu_stop_on_load,
2844 &setspucmdlist, &showspucmdlist);
2845
ff1a52c6
UW		 2846 /* Toggle whether or not to automatically flush the software-managed
2847 cache whenever SPE execution stops. */
2848 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2849 &spu_auto_flush_cache_p, _("\
2850Set whether to automatically flush the software-managed cache."),
2851 _("\
2852Show whether to automatically flush the software-managed cache."),
2853 _("\
2854Use \"on\" to automatically flush the software-managed cache\n\
2855whenever SPE execution stops.\n\
2856Use \"off\" to never automatically flush the software-managed cache."),
2857 NULL,
2858 show_spu_auto_flush_cache,
2859 &setspucmdlist, &showspucmdlist);
2860
23d964e7
UW		 2861 /* Add root prefix command for all "info spu" commands. */
2862 add_prefix_cmd ("spu", class_info, info_spu_command,
2863 _("Various SPU specific commands."),
2864 &infospucmdlist, "info spu ", 0, &infolist);
2865
2866 /* Add various "info spu" commands. */
2867 add_cmd ("event", class_info, info_spu_event_command,
2868 _("Display SPU event facility status.\n"),
2869 &infospucmdlist);
2870 add_cmd ("signal", class_info, info_spu_signal_command,
2871 _("Display SPU signal notification facility status.\n"),
2872 &infospucmdlist);
2873 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2874 _("Display SPU mailbox facility status.\n"),
2875 &infospucmdlist);
2876 add_cmd ("dma", class_info, info_spu_dma_command,
2877 _("Display MFC DMA status.\n"),
2878 &infospucmdlist);
2879 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2880 _("Display MFC Proxy-DMA status.\n"),
2881 &infospucmdlist);
771b4502 2882}
GDB Binutils - Deliverables
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