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[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
4c38e0a4 2 Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
27#include "gdb_string.h"
28#include "gdb_assert.h"
29#include "frame.h"
30#include "frame-unwind.h"
31#include "frame-base.h"
32#include "trad-frame.h"
33#include "symtab.h"
34#include "symfile.h"
35#include "value.h"
36#include "inferior.h"
37#include "dis-asm.h"
38#include "objfiles.h"
39#include "language.h"
40#include "regcache.h"
41#include "reggroups.h"
42#include "floatformat.h"
3285f3fe 43#include "block.h"
dcf52cd8 44#include "observer.h"
ff1a52c6 45#include "infcall.h"
771b4502
UW		 46
47#include "spu-tdep.h"
48
794ac428 49
3285f3fe
UW		 50/* The list of available "set spu " and "show spu " commands. */
51static struct cmd_list_element *setspucmdlist = NULL;
52static struct cmd_list_element *showspucmdlist = NULL;
53
54/* Whether to stop for new SPE contexts. */
55static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 56/* Whether to automatically flush the SW-managed cache. */
57static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 58
59
794ac428
UW		 60/* The tdep structure. */
61struct gdbarch_tdep
62{
85e747d2
UW		 63 /* The spufs ID identifying our address space. */
64 int id;
65
794ac428
UW		 66 /* SPU-specific vector type. */
67 struct type *spu_builtin_type_vec128;
68};
69
70
f2d43c2c 71/* SPU-specific vector type. */
794ac428
UW		 72static struct type *
73spu_builtin_type_vec128 (struct gdbarch *gdbarch)
74{
75 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
76
77 if (!tdep->spu_builtin_type_vec128)
78 {
df4df182 79 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 80 struct type *t;
81
e9bb382b
UW		 82 t = arch_composite_type (gdbarch,
83 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 84 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 85 append_composite_type_field (t, "v2_int64",
df4df182 86 init_vector_type (bt->builtin_int64, 2));
794ac428 87 append_composite_type_field (t, "v4_int32",
df4df182 88 init_vector_type (bt->builtin_int32, 4));
794ac428 89 append_composite_type_field (t, "v8_int16",
df4df182 90 init_vector_type (bt->builtin_int16, 8));
794ac428 91 append_composite_type_field (t, "v16_int8",
df4df182 92 init_vector_type (bt->builtin_int8, 16));
794ac428 93 append_composite_type_field (t, "v2_double",
df4df182 94 init_vector_type (bt->builtin_double, 2));
794ac428 95 append_composite_type_field (t, "v4_float",
df4df182 96 init_vector_type (bt->builtin_float, 4));
794ac428 97
876cecd0 98 TYPE_VECTOR (t) = 1;
794ac428
UW		 99 TYPE_NAME (t) = "spu_builtin_type_vec128";
100
101 tdep->spu_builtin_type_vec128 = t;
102 }
103
104 return tdep->spu_builtin_type_vec128;
105}
106
771b4502 107
23d964e7
UW		 108/* The list of available "info spu " commands. */
109static struct cmd_list_element *infospucmdlist = NULL;
110
771b4502
UW		 111/* Registers. */
112
113static const char *
d93859e2 114spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 115{
116 static char *register_names[] =
117 {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
122 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
123 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
124 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
125 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
126 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
127 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
128 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
129 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
130 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
131 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
132 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
133 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 134 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 135 };
136
137 if (reg_nr < 0)
138 return NULL;
139 if (reg_nr >= sizeof register_names / sizeof *register_names)
140 return NULL;
141
142 return register_names[reg_nr];
143}
144
145static struct type *
146spu_register_type (struct gdbarch *gdbarch, int reg_nr)
147{
148 if (reg_nr < SPU_NUM_GPRS)
794ac428 149 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 150
151 switch (reg_nr)
152 {
153 case SPU_ID_REGNUM:
df4df182 154 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 155
156 case SPU_PC_REGNUM:
0dfff4cb 157 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 158
159 case SPU_SP_REGNUM:
0dfff4cb 160 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 161
23d964e7 162 case SPU_FPSCR_REGNUM:
df4df182 163 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 164
165 case SPU_SRR0_REGNUM:
df4df182 166 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 167
168 case SPU_LSLR_REGNUM:
df4df182 169 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 170
171 case SPU_DECR_REGNUM:
df4df182 172 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 173
174 case SPU_DECR_STATUS_REGNUM:
df4df182 175 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 176
771b4502
UW		 177 default:
178 internal_error (__FILE__, __LINE__, "invalid regnum");
179 }
180}
181
182/* Pseudo registers for preferred slots - stack pointer. */
183
23d964e7
UW		 184static void
185spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
186 gdb_byte *buf)
187{
e17a4113
UW		 188 struct gdbarch *gdbarch = get_regcache_arch (regcache);
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 190 gdb_byte reg[32];
191 char annex[32];
192 ULONGEST id;
193
194 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
195 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
196 memset (reg, 0, sizeof reg);
197 target_read (&current_target, TARGET_OBJECT_SPU, annex,
198 reg, 0, sizeof reg);
199
e17a4113 200 store_unsigned_integer (buf, 4, byte_order, strtoulst (reg, NULL, 16));
23d964e7
UW		 201}
202
771b4502
UW		 203static void
204spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
205 int regnum, gdb_byte *buf)
206{
207 gdb_byte reg[16];
23d964e7
UW		 208 char annex[32];
209 ULONGEST id;
771b4502
UW		 210
211 switch (regnum)
212 {
213 case SPU_SP_REGNUM:
214 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
215 memcpy (buf, reg, 4);
216 break;
217
23d964e7
UW		 218 case SPU_FPSCR_REGNUM:
219 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
220 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
221 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
222 break;
223
224 case SPU_SRR0_REGNUM:
225 spu_pseudo_register_read_spu (regcache, "srr0", buf);
226 break;
227
228 case SPU_LSLR_REGNUM:
229 spu_pseudo_register_read_spu (regcache, "lslr", buf);
230 break;
231
232 case SPU_DECR_REGNUM:
233 spu_pseudo_register_read_spu (regcache, "decr", buf);
234 break;
235
236 case SPU_DECR_STATUS_REGNUM:
237 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
238 break;
239
771b4502
UW		 240 default:
241 internal_error (__FILE__, __LINE__, _("invalid regnum"));
242 }
243}
244
23d964e7
UW		 245static void
246spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
247 const gdb_byte *buf)
248{
e17a4113
UW		 249 struct gdbarch *gdbarch = get_regcache_arch (regcache);
250 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 251 gdb_byte reg[32];
252 char annex[32];
253 ULONGEST id;
254
255 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
256 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
257 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 258 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7
UW		 259 target_write (&current_target, TARGET_OBJECT_SPU, annex,
260 reg, 0, strlen (reg));
261}
262
771b4502
UW		 263static void
264spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
265 int regnum, const gdb_byte *buf)
266{
267 gdb_byte reg[16];
23d964e7
UW		 268 char annex[32];
269 ULONGEST id;
771b4502
UW		 270
271 switch (regnum)
272 {
273 case SPU_SP_REGNUM:
274 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
275 memcpy (reg, buf, 4);
276 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
277 break;
278
23d964e7
UW		 279 case SPU_FPSCR_REGNUM:
280 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
281 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
282 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
283 break;
284
285 case SPU_SRR0_REGNUM:
286 spu_pseudo_register_write_spu (regcache, "srr0", buf);
287 break;
288
289 case SPU_LSLR_REGNUM:
290 spu_pseudo_register_write_spu (regcache, "lslr", buf);
291 break;
292
293 case SPU_DECR_REGNUM:
294 spu_pseudo_register_write_spu (regcache, "decr", buf);
295 break;
296
297 case SPU_DECR_STATUS_REGNUM:
298 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
299 break;
300
771b4502
UW		 301 default:
302 internal_error (__FILE__, __LINE__, _("invalid regnum"));
303 }
304}
305
306/* Value conversion -- access scalar values at the preferred slot. */
307
9acbedc0
UW		 308static struct value *
309spu_value_from_register (struct type *type, int regnum,
310 struct frame_info *frame)
771b4502 311{
9acbedc0
UW		 312 struct value *value = default_value_from_register (type, regnum, frame);
313 int len = TYPE_LENGTH (type);
771b4502 314
9acbedc0
UW		 315 if (regnum < SPU_NUM_GPRS && len < 16)
316 {
317 int preferred_slot = len < 4 ? 4 - len : 0;
318 set_value_offset (value, preferred_slot);
319 }
771b4502 320
9acbedc0 321 return value;
771b4502
UW		 322}
323
324/* Register groups. */
325
326static int
327spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
328 struct reggroup *group)
329{
330 /* Registers displayed via 'info regs'. */
331 if (group == general_reggroup)
332 return 1;
333
334 /* Registers displayed via 'info float'. */
335 if (group == float_reggroup)
336 return 0;
337
338 /* Registers that need to be saved/restored in order to
339 push or pop frames. */
340 if (group == save_reggroup || group == restore_reggroup)
341 return 1;
342
343 return default_register_reggroup_p (gdbarch, regnum, group);
344}
345
ff1a52c6
UW		 346
347/* Address handling. */
36acd84e 348
85e747d2
UW		 349static int
350spu_gdbarch_id (struct gdbarch *gdbarch)
351{
352 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
353 int id = tdep->id;
354
355 /* The objfile architecture of a standalone SPU executable does not
356 provide an SPU ID. Retrieve it from the the objfile's relocated
357 address range in this special case. */
358 if (id == -1
359 && symfile_objfile && symfile_objfile->obfd
360 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
361 && symfile_objfile->sections != symfile_objfile->sections_end)
362 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
363
364 return id;
365}
366
ff1a52c6
UW		 367static int
368spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
369{
370 if (dwarf2_addr_class == 1)
371 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
372 else
373 return 0;
374}
375
376static const char *
377spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
378{
379 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
380 return "__ea";
381 else
382 return NULL;
383}
384
385static int
386spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
387 const char *name, int *type_flags_ptr)
388{
389 if (strcmp (name, "__ea") == 0)
390 {
391 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
392 return 1;
393 }
394 else
395 return 0;
396}
397
85e747d2
UW		 398static void
399spu_address_to_pointer (struct gdbarch *gdbarch,
400 struct type *type, gdb_byte *buf, CORE_ADDR addr)
401{
402 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
403 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
404 SPUADDR_ADDR (addr));
405}
406
36acd84e 407static CORE_ADDR
9898f801
UW		 408spu_pointer_to_address (struct gdbarch *gdbarch,
409 struct type *type, const gdb_byte *buf)
36acd84e 410{
85e747d2 411 int id = spu_gdbarch_id (gdbarch);
e17a4113
UW		 412 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
413 ULONGEST addr
414 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 415
ff1a52c6
UW		 416 /* Do not convert __ea pointers. */
417 if (TYPE_ADDRESS_CLASS_1 (type))
418 return addr;
419
d2ed6730 420 return addr? SPUADDR (id, addr) : 0;
36acd84e
UW		 421}
422
423static CORE_ADDR
424spu_integer_to_address (struct gdbarch *gdbarch,
425 struct type *type, const gdb_byte *buf)
426{
85e747d2 427 int id = spu_gdbarch_id (gdbarch);
36acd84e 428 ULONGEST addr = unpack_long (type, buf);
36acd84e 429
d2ed6730 430 return SPUADDR (id, addr);
36acd84e
UW		 431}
432
771b4502
UW		 433
434/* Decoding SPU instructions. */
435
436enum
437 {
438 op_lqd = 0x34,
439 op_lqx = 0x3c4,
440 op_lqa = 0x61,
441 op_lqr = 0x67,
442 op_stqd = 0x24,
443 op_stqx = 0x144,
444 op_stqa = 0x41,
445 op_stqr = 0x47,
446
447 op_il = 0x081,
448 op_ila = 0x21,
449 op_a = 0x0c0,
450 op_ai = 0x1c,
451
452 op_selb = 0x4,
453
454 op_br = 0x64,
455 op_bra = 0x60,
456 op_brsl = 0x66,
457 op_brasl = 0x62,
458 op_brnz = 0x42,
459 op_brz = 0x40,
460 op_brhnz = 0x46,
461 op_brhz = 0x44,
462 op_bi = 0x1a8,
463 op_bisl = 0x1a9,
464 op_biz = 0x128,
465 op_binz = 0x129,
466 op_bihz = 0x12a,
467 op_bihnz = 0x12b,
468 };
469
470static int
471is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
472{
473 if ((insn >> 21) == op)
474 {
475 *rt = insn & 127;
476 *ra = (insn >> 7) & 127;
477 *rb = (insn >> 14) & 127;
478 return 1;
479 }
480
481 return 0;
482}
483
484static int
485is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
486{
487 if ((insn >> 28) == op)
488 {
489 *rt = (insn >> 21) & 127;
490 *ra = (insn >> 7) & 127;
491 *rb = (insn >> 14) & 127;
492 *rc = insn & 127;
493 return 1;
494 }
495
496 return 0;
497}
498
499static int
500is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
501{
502 if ((insn >> 21) == op)
503 {
504 *rt = insn & 127;
505 *ra = (insn >> 7) & 127;
506 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
507 return 1;
508 }
509
510 return 0;
511}
512
513static int
514is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
515{
516 if ((insn >> 24) == op)
517 {
518 *rt = insn & 127;
519 *ra = (insn >> 7) & 127;
520 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
521 return 1;
522 }
523
524 return 0;
525}
526
527static int
528is_ri16 (unsigned int insn, int op, int *rt, int *i16)
529{
530 if ((insn >> 23) == op)
531 {
532 *rt = insn & 127;
533 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
534 return 1;
535 }
536
537 return 0;
538}
539
540static int
541is_ri18 (unsigned int insn, int op, int *rt, int *i18)
542{
543 if ((insn >> 25) == op)
544 {
545 *rt = insn & 127;
546 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
547 return 1;
548 }
549
550 return 0;
551}
552
553static int
554is_branch (unsigned int insn, int *offset, int *reg)
555{
556 int rt, i7, i16;
557
558 if (is_ri16 (insn, op_br, &rt, &i16)
559 || is_ri16 (insn, op_brsl, &rt, &i16)
560 || is_ri16 (insn, op_brnz, &rt, &i16)
561 || is_ri16 (insn, op_brz, &rt, &i16)
562 || is_ri16 (insn, op_brhnz, &rt, &i16)
563 || is_ri16 (insn, op_brhz, &rt, &i16))
564 {
565 *reg = SPU_PC_REGNUM;
566 *offset = i16 << 2;
567 return 1;
568 }
569
570 if (is_ri16 (insn, op_bra, &rt, &i16)
571 || is_ri16 (insn, op_brasl, &rt, &i16))
572 {
573 *reg = -1;
574 *offset = i16 << 2;
575 return 1;
576 }
577
578 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
579 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
580 || is_ri7 (insn, op_biz, &rt, reg, &i7)
581 || is_ri7 (insn, op_binz, &rt, reg, &i7)
582 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
583 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
584 {
585 *offset = 0;
586 return 1;
587 }
588
589 return 0;
590}
591
592
593/* Prolog parsing. */
594
595struct spu_prologue_data
596 {
597 /* Stack frame size. -1 if analysis was unsuccessful. */
598 int size;
599
600 /* How to find the CFA. The CFA is equal to SP at function entry. */
601 int cfa_reg;
602 int cfa_offset;
603
604 /* Offset relative to CFA where a register is saved. -1 if invalid. */
605 int reg_offset[SPU_NUM_GPRS];
606 };
607
608static CORE_ADDR
e17a4113
UW		 609spu_analyze_prologue (struct gdbarch *gdbarch,
610 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 611 struct spu_prologue_data *data)
612{
e17a4113 613 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 614 int found_sp = 0;
615 int found_fp = 0;
616 int found_lr = 0;
ce50d78b 617 int found_bc = 0;
771b4502
UW		 618 int reg_immed[SPU_NUM_GPRS];
619 gdb_byte buf[16];
620 CORE_ADDR prolog_pc = start_pc;
621 CORE_ADDR pc;
622 int i;
623
624
625 /* Initialize DATA to default values. */
626 data->size = -1;
627
628 data->cfa_reg = SPU_RAW_SP_REGNUM;
629 data->cfa_offset = 0;
630
631 for (i = 0; i < SPU_NUM_GPRS; i++)
632 data->reg_offset[i] = -1;
633
634 /* Set up REG_IMMED array. This is non-zero for a register if we know its
635 preferred slot currently holds this immediate value. */
636 for (i = 0; i < SPU_NUM_GPRS; i++)
637 reg_immed[i] = 0;
638
639 /* Scan instructions until the first branch.
640
641 The following instructions are important prolog components:
642
643 - The first instruction to set up the stack pointer.
644 - The first instruction to set up the frame pointer.
645 - The first instruction to save the link register.
ce50d78b 646 - The first instruction to save the backchain.
771b4502 647
ce50d78b 648 We return the instruction after the latest of these four,
771b4502
UW		 649 or the incoming PC if none is found. The first instruction
650 to set up the stack pointer also defines the frame size.
651
652 Note that instructions saving incoming arguments to their stack
653 slots are not counted as important, because they are hard to
654 identify with certainty. This should not matter much, because
655 arguments are relevant only in code compiled with debug data,
656 and in such code the GDB core will advance until the first source
657 line anyway, using SAL data.
658
659 For purposes of stack unwinding, we analyze the following types
660 of instructions in addition:
661
662 - Any instruction adding to the current frame pointer.
663 - Any instruction loading an immediate constant into a register.
664 - Any instruction storing a register onto the stack.
665
666 These are used to compute the CFA and REG_OFFSET output. */
667
668 for (pc = start_pc; pc < end_pc; pc += 4)
669 {
670 unsigned int insn;
671 int rt, ra, rb, rc, immed;
672
673 if (target_read_memory (pc, buf, 4))
674 break;
e17a4113 675 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 676
677 /* AI is the typical instruction to set up a stack frame.
678 It is also used to initialize the frame pointer. */
679 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
680 {
681 if (rt == data->cfa_reg && ra == data->cfa_reg)
682 data->cfa_offset -= immed;
683
684 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
685 && !found_sp)
686 {
687 found_sp = 1;
688 prolog_pc = pc + 4;
689
690 data->size = -immed;
691 }
692 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
693 && !found_fp)
694 {
695 found_fp = 1;
696 prolog_pc = pc + 4;
697
698 data->cfa_reg = SPU_FP_REGNUM;
699 data->cfa_offset -= immed;
700 }
701 }
702
703 /* A is used to set up stack frames of size >= 512 bytes.
704 If we have tracked the contents of the addend register,
705 we can handle this as well. */
706 else if (is_rr (insn, op_a, &rt, &ra, &rb))
707 {
708 if (rt == data->cfa_reg && ra == data->cfa_reg)
709 {
710 if (reg_immed[rb] != 0)
711 data->cfa_offset -= reg_immed[rb];
712 else
713 data->cfa_reg = -1; /* We don't know the CFA any more. */
714 }
715
716 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
717 && !found_sp)
718 {
719 found_sp = 1;
720 prolog_pc = pc + 4;
721
722 if (reg_immed[rb] != 0)
723 data->size = -reg_immed[rb];
724 }
725 }
726
727 /* We need to track IL and ILA used to load immediate constants
728 in case they are later used as input to an A instruction. */
729 else if (is_ri16 (insn, op_il, &rt, &immed))
730 {
731 reg_immed[rt] = immed;
12102450
UW		 732
733 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
734 found_sp = 1;
771b4502
UW		 735 }
736
737 else if (is_ri18 (insn, op_ila, &rt, &immed))
738 {
739 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 740
741 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
742 found_sp = 1;
771b4502
UW		 743 }
744
745 /* STQD is used to save registers to the stack. */
746 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
747 {
748 if (ra == data->cfa_reg)
749 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
750
751 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
752 && !found_lr)
753 {
754 found_lr = 1;
755 prolog_pc = pc + 4;
756 }
ce50d78b
UW		 757
758 if (ra == SPU_RAW_SP_REGNUM
759 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
760 && !found_bc)
761 {
762 found_bc = 1;
763 prolog_pc = pc + 4;
764 }
771b4502
UW		 765 }
766
767 /* _start uses SELB to set up the stack pointer. */
768 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
769 {
770 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
771 found_sp = 1;
772 }
773
774 /* We terminate if we find a branch. */
775 else if (is_branch (insn, &immed, &ra))
776 break;
777 }
778
779
780 /* If we successfully parsed until here, and didn't find any instruction
781 modifying SP, we assume we have a frameless function. */
782 if (!found_sp)
783 data->size = 0;
784
785 /* Return cooked instead of raw SP. */
786 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
787 data->cfa_reg = SPU_SP_REGNUM;
788
789 return prolog_pc;
790}
791
792/* Return the first instruction after the prologue starting at PC. */
793static CORE_ADDR
6093d2eb 794spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 795{
796 struct spu_prologue_data data;
e17a4113 797 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 798}
799
800/* Return the frame pointer in use at address PC. */
801static void
a54fba4c
MD		 802spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
803 int *reg, LONGEST *offset)
771b4502
UW		 804{
805 struct spu_prologue_data data;
e17a4113 806 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 807
808 if (data.size != -1 && data.cfa_reg != -1)
809 {
810 /* The 'frame pointer' address is CFA minus frame size. */
811 *reg = data.cfa_reg;
812 *offset = data.cfa_offset - data.size;
813 }
814 else
815 {
816 /* ??? We don't really know ... */
817 *reg = SPU_SP_REGNUM;
818 *offset = 0;
819 }
820}
821
fe5febed
UW		 822/* Return true if we are in the function's epilogue, i.e. after the
823 instruction that destroyed the function's stack frame.
824
825 1) scan forward from the point of execution:
826 a) If you find an instruction that modifies the stack pointer
827 or transfers control (except a return), execution is not in
828 an epilogue, return.
829 b) Stop scanning if you find a return instruction or reach the
830 end of the function or reach the hard limit for the size of
831 an epilogue.
832 2) scan backward from the point of execution:
833 a) If you find an instruction that modifies the stack pointer,
834 execution *is* in an epilogue, return.
835 b) Stop scanning if you reach an instruction that transfers
836 control or the beginning of the function or reach the hard
837 limit for the size of an epilogue. */
838
839static int
840spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
841{
e17a4113 842 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 843 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
844 bfd_byte buf[4];
845 unsigned int insn;
846 int rt, ra, rb, rc, immed;
847
848 /* Find the search limits based on function boundaries and hard limit.
849 We assume the epilogue can be up to 64 instructions long. */
850
851 const int spu_max_epilogue_size = 64 * 4;
852
853 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
854 return 0;
855
856 if (pc - func_start < spu_max_epilogue_size)
857 epilogue_start = func_start;
858 else
859 epilogue_start = pc - spu_max_epilogue_size;
860
861 if (func_end - pc < spu_max_epilogue_size)
862 epilogue_end = func_end;
863 else
864 epilogue_end = pc + spu_max_epilogue_size;
865
866 /* Scan forward until next 'bi $0'. */
867
868 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
869 {
870 if (target_read_memory (scan_pc, buf, 4))
871 return 0;
e17a4113 872 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 873
874 if (is_branch (insn, &immed, &ra))
875 {
876 if (immed == 0 && ra == SPU_LR_REGNUM)
877 break;
878
879 return 0;
880 }
881
882 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
883 || is_rr (insn, op_a, &rt, &ra, &rb)
884 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
885 {
886 if (rt == SPU_RAW_SP_REGNUM)
887 return 0;
888 }
889 }
890
891 if (scan_pc >= epilogue_end)
892 return 0;
893
894 /* Scan backward until adjustment to stack pointer (R1). */
895
896 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
897 {
898 if (target_read_memory (scan_pc, buf, 4))
899 return 0;
e17a4113 900 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 901
902 if (is_branch (insn, &immed, &ra))
903 return 0;
904
905 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
906 || is_rr (insn, op_a, &rt, &ra, &rb)
907 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
908 {
909 if (rt == SPU_RAW_SP_REGNUM)
910 return 1;
911 }
912 }
913
914 return 0;
915}
916
917
771b4502
UW		 918/* Normal stack frames. */
919
920struct spu_unwind_cache
921{
922 CORE_ADDR func;
923 CORE_ADDR frame_base;
924 CORE_ADDR local_base;
925
926 struct trad_frame_saved_reg *saved_regs;
927};
928
929static struct spu_unwind_cache *
8d998b8f 930spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 931 void **this_prologue_cache)
932{
e17a4113 933 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 934 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 935 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 936 struct spu_unwind_cache *info;
937 struct spu_prologue_data data;
85e747d2 938 CORE_ADDR id = tdep->id;
dcf52cd8 939 gdb_byte buf[16];
771b4502
UW		 940
941 if (*this_prologue_cache)
942 return *this_prologue_cache;
943
944 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
945 *this_prologue_cache = info;
8d998b8f 946 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 947 info->frame_base = 0;
948 info->local_base = 0;
949
950 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 951 info->func = get_frame_func (this_frame);
771b4502
UW		 952 if (info->func == 0)
953 {
954 /* Fall back to using the current PC as frame ID. */
8d998b8f 955 info->func = get_frame_pc (this_frame);
771b4502
UW		 956 data.size = -1;
957 }
958 else
e17a4113
UW		 959 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
960 &data);
771b4502
UW		 961
962 /* If successful, use prologue analysis data. */
963 if (data.size != -1 && data.cfa_reg != -1)
964 {
965 CORE_ADDR cfa;
966 int i;
771b4502
UW		 967
968 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 969 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 970 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 971 cfa = SPUADDR (id, cfa);
771b4502
UW		 972
973 /* Call-saved register slots. */
974 for (i = 0; i < SPU_NUM_GPRS; i++)
975 if (i == SPU_LR_REGNUM
976 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
977 if (data.reg_offset[i] != -1)
978 info->saved_regs[i].addr = cfa - data.reg_offset[i];
979
771b4502
UW		 980 /* Frame bases. */
981 info->frame_base = cfa;
982 info->local_base = cfa - data.size;
983 }
984
985 /* Otherwise, fall back to reading the backchain link. */
986 else
987 {
cdc9523a
UW		 988 CORE_ADDR reg;
989 LONGEST backchain;
990 int status;
771b4502
UW		 991
992 /* Get the backchain. */
8d998b8f 993 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 994 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
995 &backchain);
771b4502
UW		 996
997 /* A zero backchain terminates the frame chain. Also, sanity
998 check against the local store size limit. */
cdc9523a 999 if (status && backchain > 0 && backchain < SPU_LS_SIZE)
771b4502
UW		 1000 {
1001 /* Assume the link register is saved into its slot. */
1002 if (backchain + 16 < SPU_LS_SIZE)
85e747d2 1003 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id, backchain + 16);
771b4502 1004
771b4502 1005 /* Frame bases. */
85e747d2
UW		 1006 info->frame_base = SPUADDR (id, backchain);
1007 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1008 }
1009 }
dcf52cd8 1010
c4891da7
UW		 1011 /* If we didn't find a frame, we cannot determine SP / return address. */
1012 if (info->frame_base == 0)
1013 return info;
1014
dcf52cd8 1015 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1016 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1017 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1018
0a44cb36
UW		 1019 /* Read full contents of the unwound link register in order to
1020 be able to determine the return address. */
dcf52cd8
UW		 1021 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1022 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1023 else
8d998b8f 1024 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1025
0a44cb36
UW		 1026 /* Normally, the return address is contained in the slot 0 of the
1027 link register, and slots 1-3 are zero. For an overlay return,
1028 slot 0 contains the address of the overlay manager return stub,
1029 slot 1 contains the partition number of the overlay section to
1030 be returned to, and slot 2 contains the return address within
1031 that section. Return the latter address in that case. */
e17a4113 1032 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1033 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1034 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1035 else
1036 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1037 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1038
1039 return info;
1040}
1041
1042static void
8d998b8f 1043spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1044 void **this_prologue_cache, struct frame_id *this_id)
1045{
1046 struct spu_unwind_cache *info =
8d998b8f 1047 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1048
1049 if (info->frame_base == 0)
1050 return;
1051
1052 *this_id = frame_id_build (info->frame_base, info->func);
1053}
1054
8d998b8f
UW		 1055static struct value *
1056spu_frame_prev_register (struct frame_info *this_frame,
1057 void **this_prologue_cache, int regnum)
771b4502
UW		 1058{
1059 struct spu_unwind_cache *info
8d998b8f 1060 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1061
1062 /* Special-case the stack pointer. */
1063 if (regnum == SPU_RAW_SP_REGNUM)
1064 regnum = SPU_SP_REGNUM;
1065
8d998b8f 1066 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1067}
1068
1069static const struct frame_unwind spu_frame_unwind = {
1070 NORMAL_FRAME,
1071 spu_frame_this_id,
8d998b8f
UW		 1072 spu_frame_prev_register,
1073 NULL,
1074 default_frame_sniffer
771b4502
UW		 1075};
1076
771b4502 1077static CORE_ADDR
8d998b8f 1078spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1079{
1080 struct spu_unwind_cache *info
8d998b8f 1081 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1082 return info->local_base;
1083}
1084
1085static const struct frame_base spu_frame_base = {
1086 &spu_frame_unwind,
1087 spu_frame_base_address,
1088 spu_frame_base_address,
1089 spu_frame_base_address
1090};
1091
1092static CORE_ADDR
1093spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1094{
85e747d2 1095 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1096 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1097 /* Mask off interrupt enable bit. */
85e747d2 1098 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1099}
1100
1101static CORE_ADDR
1102spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1103{
85e747d2
UW		 1104 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1105 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1106 return SPUADDR (tdep->id, sp);
771b4502
UW		 1107}
1108
118dfbaf 1109static CORE_ADDR
61a1198a 1110spu_read_pc (struct regcache *regcache)
118dfbaf 1111{
85e747d2 1112 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1113 ULONGEST pc;
1114 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1115 /* Mask off interrupt enable bit. */
85e747d2 1116 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1117}
1118
1119static void
61a1198a 1120spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1121{
1122 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1123 ULONGEST old_pc;
1124 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1125 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1126 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1127}
1128
771b4502 1129
cc5f0d61
UW		 1130/* Cell/B.E. cross-architecture unwinder support. */
1131
1132struct spu2ppu_cache
1133{
1134 struct frame_id frame_id;
1135 struct regcache *regcache;
1136};
1137
1138static struct gdbarch *
1139spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1140{
1141 struct spu2ppu_cache *cache = *this_cache;
1142 return get_regcache_arch (cache->regcache);
1143}
1144
1145static void
1146spu2ppu_this_id (struct frame_info *this_frame,
1147 void **this_cache, struct frame_id *this_id)
1148{
1149 struct spu2ppu_cache *cache = *this_cache;
1150 *this_id = cache->frame_id;
1151}
1152
1153static struct value *
1154spu2ppu_prev_register (struct frame_info *this_frame,
1155 void **this_cache, int regnum)
1156{
1157 struct spu2ppu_cache *cache = *this_cache;
1158 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1159 gdb_byte *buf;
1160
1161 buf = alloca (register_size (gdbarch, regnum));
1162 regcache_cooked_read (cache->regcache, regnum, buf);
1163 return frame_unwind_got_bytes (this_frame, regnum, buf);
1164}
1165
1166static int
1167spu2ppu_sniffer (const struct frame_unwind *self,
1168 struct frame_info *this_frame, void **this_prologue_cache)
1169{
1170 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1171 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1172 CORE_ADDR base, func, backchain;
1173 gdb_byte buf[4];
1174
1175 if (gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_spu)
1176 return 0;
1177
1178 base = get_frame_sp (this_frame);
1179 func = get_frame_pc (this_frame);
1180 if (target_read_memory (base, buf, 4))
1181 return 0;
1182 backchain = extract_unsigned_integer (buf, 4, byte_order);
1183
1184 if (!backchain)
1185 {
1186 struct frame_info *fi;
1187
1188 struct spu2ppu_cache *cache
1189 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1190
1191 cache->frame_id = frame_id_build (base + 16, func);
1192
1193 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1194 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1195 break;
1196
1197 if (fi)
1198 {
1199 cache->regcache = frame_save_as_regcache (fi);
1200 *this_prologue_cache = cache;
1201 return 1;
1202 }
1203 else
1204 {
1205 struct regcache *regcache;
1206 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch);
1207 cache->regcache = regcache_dup (regcache);
1208 *this_prologue_cache = cache;
1209 return 1;
1210 }
1211 }
1212
1213 return 0;
1214}
1215
1216static void
1217spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1218{
1219 struct spu2ppu_cache *cache = this_cache;
1220 regcache_xfree (cache->regcache);
1221}
1222
1223static const struct frame_unwind spu2ppu_unwind = {
1224 ARCH_FRAME,
1225 spu2ppu_this_id,
1226 spu2ppu_prev_register,
1227 NULL,
1228 spu2ppu_sniffer,
1229 spu2ppu_dealloc_cache,
1230 spu2ppu_prev_arch,
1231};
1232
1233
771b4502
UW		 1234/* Function calling convention. */
1235
7b3dc0b7
UW		 1236static CORE_ADDR
1237spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1238{
1239 return sp & ~15;
1240}
1241
87805e63
UW		 1242static CORE_ADDR
1243spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1244 struct value **args, int nargs, struct type *value_type,
1245 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1246 struct regcache *regcache)
1247{
1248 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1249 sp = (sp - 4) & ~15;
1250 /* Store the address of that breakpoint */
1251 *bp_addr = sp;
1252 /* The call starts at the callee's entry point. */
1253 *real_pc = funaddr;
1254
1255 return sp;
1256}
1257
771b4502
UW		 1258static int
1259spu_scalar_value_p (struct type *type)
1260{
1261 switch (TYPE_CODE (type))
1262 {
1263 case TYPE_CODE_INT:
1264 case TYPE_CODE_ENUM:
1265 case TYPE_CODE_RANGE:
1266 case TYPE_CODE_CHAR:
1267 case TYPE_CODE_BOOL:
1268 case TYPE_CODE_PTR:
1269 case TYPE_CODE_REF:
1270 return TYPE_LENGTH (type) <= 16;
1271
1272 default:
1273 return 0;
1274 }
1275}
1276
1277static void
1278spu_value_to_regcache (struct regcache *regcache, int regnum,
1279 struct type *type, const gdb_byte *in)
1280{
1281 int len = TYPE_LENGTH (type);
1282
1283 if (spu_scalar_value_p (type))
1284 {
1285 int preferred_slot = len < 4 ? 4 - len : 0;
1286 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1287 }
1288 else
1289 {
1290 while (len >= 16)
1291 {
1292 regcache_cooked_write (regcache, regnum++, in);
1293 in += 16;
1294 len -= 16;
1295 }
1296
1297 if (len > 0)
1298 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1299 }
1300}
1301
1302static void
1303spu_regcache_to_value (struct regcache *regcache, int regnum,
1304 struct type *type, gdb_byte *out)
1305{
1306 int len = TYPE_LENGTH (type);
1307
1308 if (spu_scalar_value_p (type))
1309 {
1310 int preferred_slot = len < 4 ? 4 - len : 0;
1311 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1312 }
1313 else
1314 {
1315 while (len >= 16)
1316 {
1317 regcache_cooked_read (regcache, regnum++, out);
1318 out += 16;
1319 len -= 16;
1320 }
1321
1322 if (len > 0)
1323 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1324 }
1325}
1326
1327static CORE_ADDR
1328spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1329 struct regcache *regcache, CORE_ADDR bp_addr,
1330 int nargs, struct value **args, CORE_ADDR sp,
1331 int struct_return, CORE_ADDR struct_addr)
1332{
e17a4113 1333 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1334 CORE_ADDR sp_delta;
771b4502
UW		 1335 int i;
1336 int regnum = SPU_ARG1_REGNUM;
1337 int stack_arg = -1;
1338 gdb_byte buf[16];
1339
1340 /* Set the return address. */
1341 memset (buf, 0, sizeof buf);
85e747d2 1342 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1343 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1344
1345 /* If STRUCT_RETURN is true, then the struct return address (in
1346 STRUCT_ADDR) will consume the first argument-passing register.
1347 Both adjust the register count and store that value. */
1348 if (struct_return)
1349 {
1350 memset (buf, 0, sizeof buf);
85e747d2 1351 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1352 regcache_cooked_write (regcache, regnum++, buf);
1353 }
1354
1355 /* Fill in argument registers. */
1356 for (i = 0; i < nargs; i++)
1357 {
1358 struct value *arg = args[i];
1359 struct type *type = check_typedef (value_type (arg));
1360 const gdb_byte *contents = value_contents (arg);
1361 int len = TYPE_LENGTH (type);
1362 int n_regs = align_up (len, 16) / 16;
1363
1364 /* If the argument doesn't wholly fit into registers, it and
1365 all subsequent arguments go to the stack. */
1366 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1367 {
1368 stack_arg = i;
1369 break;
1370 }
1371
1372 spu_value_to_regcache (regcache, regnum, type, contents);
1373 regnum += n_regs;
1374 }
1375
1376 /* Overflow arguments go to the stack. */
1377 if (stack_arg != -1)
1378 {
1379 CORE_ADDR ap;
1380
1381 /* Allocate all required stack size. */
1382 for (i = stack_arg; i < nargs; i++)
1383 {
1384 struct type *type = check_typedef (value_type (args[i]));
1385 sp -= align_up (TYPE_LENGTH (type), 16);
1386 }
1387
1388 /* Fill in stack arguments. */
1389 ap = sp;
1390 for (i = stack_arg; i < nargs; i++)
1391 {
1392 struct value *arg = args[i];
1393 struct type *type = check_typedef (value_type (arg));
1394 int len = TYPE_LENGTH (type);
1395 int preferred_slot;
1396
1397 if (spu_scalar_value_p (type))
1398 preferred_slot = len < 4 ? 4 - len : 0;
1399 else
1400 preferred_slot = 0;
1401
1402 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1403 ap += align_up (TYPE_LENGTH (type), 16);
1404 }
1405 }
1406
1407 /* Allocate stack frame header. */
1408 sp -= 32;
1409
ee82e879
UW		 1410 /* Store stack back chain. */
1411 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1412 target_write_memory (sp, buf, 16);
1413
9ff3afda 1414 /* Finally, update all slots of the SP register. */
e17a4113 1415 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1416 for (i = 0; i < 4; i++)
1417 {
e17a4113
UW		 1418 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1419 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1420 }
1421 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1422
1423 return sp;
1424}
1425
1426static struct frame_id
8d998b8f 1427spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1428{
85e747d2 1429 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1430 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1431 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1432 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1433}
1434
1435/* Function return value access. */
1436
1437static enum return_value_convention
c055b101
CV		 1438spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1439 struct type *type, struct regcache *regcache,
1440 gdb_byte *out, const gdb_byte *in)
771b4502
UW		 1441{
1442 enum return_value_convention rvc;
1443
1444 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1445 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1446 else
1447 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1448
1449 if (in)
1450 {
1451 switch (rvc)
1452 {
1453 case RETURN_VALUE_REGISTER_CONVENTION:
1454 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1455 break;
1456
1457 case RETURN_VALUE_STRUCT_CONVENTION:
1458 error ("Cannot set function return value.");
1459 break;
1460 }
1461 }
1462 else if (out)
1463 {
1464 switch (rvc)
1465 {
1466 case RETURN_VALUE_REGISTER_CONVENTION:
1467 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1468 break;
1469
1470 case RETURN_VALUE_STRUCT_CONVENTION:
1471 error ("Function return value unknown.");
1472 break;
1473 }
1474 }
1475
1476 return rvc;
1477}
1478
1479
1480/* Breakpoints. */
1481
1482static const gdb_byte *
67d57894 1483spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1484{
1485 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1486
1487 *lenptr = sizeof breakpoint;
1488 return breakpoint;
1489}
1490
1491
1492/* Software single-stepping support. */
1493
63807e1d 1494static int
0b1b3e42 1495spu_software_single_step (struct frame_info *frame)
771b4502 1496{
a6d9a66e 1497 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1498 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1499 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1500 CORE_ADDR pc, next_pc;
1501 unsigned int insn;
1502 int offset, reg;
1503 gdb_byte buf[4];
771b4502 1504
0b1b3e42 1505 pc = get_frame_pc (frame);
771b4502 1506
e0cd558a
UW		 1507 if (target_read_memory (pc, buf, 4))
1508 return 1;
e17a4113 1509 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1510
e0cd558a
UW		 1511 /* Next sequential instruction is at PC + 4, except if the current
1512 instruction is a PPE-assisted call, in which case it is at PC + 8.
1513 Wrap around LS limit to be on the safe side. */
1514 if ((insn & 0xffffff00) == 0x00002100)
85e747d2 1515 next_pc = (SPUADDR_ADDR (pc) + 8) & (SPU_LS_SIZE - 1);
e0cd558a 1516 else
85e747d2 1517 next_pc = (SPUADDR_ADDR (pc) + 4) & (SPU_LS_SIZE - 1);
771b4502 1518
6c95b8df
PA		 1519 insert_single_step_breakpoint (gdbarch,
1520 aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1521
e0cd558a
UW		 1522 if (is_branch (insn, &offset, &reg))
1523 {
1524 CORE_ADDR target = offset;
771b4502 1525
e0cd558a 1526 if (reg == SPU_PC_REGNUM)
85e747d2 1527 target += SPUADDR_ADDR (pc);
e0cd558a
UW		 1528 else if (reg != -1)
1529 {
0b1b3e42 1530 get_frame_register_bytes (frame, reg, 0, 4, buf);
e17a4113 1531 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
771b4502 1532 }
e0cd558a
UW		 1533
1534 target = target & (SPU_LS_SIZE - 1);
1535 if (target != next_pc)
6c95b8df 1536 insert_single_step_breakpoint (gdbarch, aspace,
85e747d2 1537 SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1538 }
e6590a1b
UW		 1539
1540 return 1;
771b4502
UW		 1541}
1542
6e3f70d7
UW		 1543
1544/* Longjmp support. */
1545
1546static int
1547spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1548{
e17a4113 1549 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1550 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1551 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1552 gdb_byte buf[4];
1553 CORE_ADDR jb_addr;
1554
1555 /* Jump buffer is pointed to by the argument register $r3. */
1556 get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf);
e17a4113 1557 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1558 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1559 return 0;
1560
e17a4113 1561 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1562 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1563 return 1;
1564}
1565
1566
85e747d2
UW		 1567/* Disassembler. */
1568
1569struct spu_dis_asm_data
1570{
1571 struct gdbarch *gdbarch;
1572 int id;
1573};
1574
1575static void
1576spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1577{
1578 struct spu_dis_asm_data *data = info->application_data;
1579 print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1580}
1581
1582static int
1583gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1584{
1585 /* The opcodes disassembler does 18-bit address arithmetic. Make sure the
1586 SPU ID encoded in the high bits is added back when we call print_address. */
1587 struct disassemble_info spu_info = *info;
1588 struct spu_dis_asm_data data;
1589 data.gdbarch = info->application_data;
1590 data.id = SPUADDR_SPU (memaddr);
1591
1592 spu_info.application_data = &data;
1593 spu_info.print_address_func = spu_dis_asm_print_address;
1594 return print_insn_spu (memaddr, &spu_info);
1595}
1596
1597
dcf52cd8
UW		 1598/* Target overlays for the SPU overlay manager.
1599
1600 See the documentation of simple_overlay_update for how the
1601 interface is supposed to work.
1602
1603 Data structures used by the overlay manager:
1604
1605 struct ovly_table
1606 {
1607 u32 vma;
1608 u32 size;
1609 u32 pos;
1610 u32 buf;
1611 } _ovly_table[]; -- one entry per overlay section
1612
1613 struct ovly_buf_table
1614 {
1615 u32 mapped;
1616 } _ovly_buf_table[]; -- one entry per overlay buffer
1617
1618 _ovly_table should never change.
1619
1620 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1621 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1622 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1623
1624 mapped is an index into _ovly_table. Both the mapped and buf indices start
1625 from one to reference the first entry in their respective tables. */
1626
1627/* Using the per-objfile private data mechanism, we store for each
1628 objfile an array of "struct spu_overlay_table" structures, one
1629 for each obj_section of the objfile. This structure holds two
1630 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1631 is *not* an overlay section. If it is non-zero, it represents
1632 a target address. The overlay section is mapped iff the target
1633 integer at this location equals MAPPED_VAL. */
1634
1635static const struct objfile_data *spu_overlay_data;
1636
1637struct spu_overlay_table
1638 {
1639 CORE_ADDR mapped_ptr;
1640 CORE_ADDR mapped_val;
1641 };
1642
1643/* Retrieve the overlay table for OBJFILE. If not already cached, read
1644 the _ovly_table data structure from the target and initialize the
1645 spu_overlay_table data structure from it. */
1646static struct spu_overlay_table *
1647spu_get_overlay_table (struct objfile *objfile)
1648{
e17a4113
UW		 1649 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1650 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8
UW		 1651 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1652 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1653 unsigned ovly_table_size, ovly_buf_table_size;
1654 struct spu_overlay_table *tbl;
1655 struct obj_section *osect;
1656 char *ovly_table;
1657 int i;
1658
1659 tbl = objfile_data (objfile, spu_overlay_data);
1660 if (tbl)
1661 return tbl;
1662
1663 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1664 if (!ovly_table_msym)
1665 return NULL;
1666
1667 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1668 if (!ovly_buf_table_msym)
1669 return NULL;
1670
1671 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1672 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1673
1674 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1675 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1676
1677 ovly_table = xmalloc (ovly_table_size);
1678 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1679
1680 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1681 objfile->sections_end - objfile->sections,
1682 struct spu_overlay_table);
1683
1684 for (i = 0; i < ovly_table_size / 16; i++)
1685 {
e17a4113
UW		 1686 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1687 4, byte_order);
1688 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1689 4, byte_order);
1690 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1691 4, byte_order);
1692 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1693 4, byte_order);
dcf52cd8
UW		 1694
1695 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1696 continue;
1697
1698 ALL_OBJFILE_OSECTIONS (objfile, osect)
1699 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1700 && pos == osect->the_bfd_section->filepos)
1701 {
1702 int ndx = osect - objfile->sections;
1703 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1704 tbl[ndx].mapped_val = i + 1;
1705 break;
1706 }
1707 }
1708
1709 xfree (ovly_table);
1710 set_objfile_data (objfile, spu_overlay_data, tbl);
1711 return tbl;
1712}
1713
1714/* Read _ovly_buf_table entry from the target to dermine whether
1715 OSECT is currently mapped, and update the mapped state. */
1716static void
1717spu_overlay_update_osect (struct obj_section *osect)
1718{
e17a4113
UW		 1719 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1720 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1721 struct spu_overlay_table *ovly_table;
85e747d2 1722 CORE_ADDR id, val;
dcf52cd8
UW		 1723
1724 ovly_table = spu_get_overlay_table (osect->objfile);
1725 if (!ovly_table)
1726 return;
1727
1728 ovly_table += osect - osect->objfile->sections;
1729 if (ovly_table->mapped_ptr == 0)
1730 return;
1731
85e747d2
UW		 1732 id = SPUADDR_SPU (obj_section_addr (osect));
1733 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1734 4, byte_order);
dcf52cd8
UW		 1735 osect->ovly_mapped = (val == ovly_table->mapped_val);
1736}
1737
1738/* If OSECT is NULL, then update all sections' mapped state.
1739 If OSECT is non-NULL, then update only OSECT's mapped state. */
1740static void
1741spu_overlay_update (struct obj_section *osect)
1742{
1743 /* Just one section. */
1744 if (osect)
1745 spu_overlay_update_osect (osect);
1746
1747 /* All sections. */
1748 else
1749 {
1750 struct objfile *objfile;
1751
1752 ALL_OBJSECTIONS (objfile, osect)
714835d5 1753 if (section_is_overlay (osect))
dcf52cd8
UW		 1754 spu_overlay_update_osect (osect);
1755 }
1756}
1757
1758/* Whenever a new objfile is loaded, read the target's _ovly_table.
1759 If there is one, go through all sections and make sure for non-
1760 overlay sections LMA equals VMA, while for overlay sections LMA
d2ed6730 1761 is larger than SPU_OVERLAY_LMA. */
dcf52cd8
UW		 1762static void
1763spu_overlay_new_objfile (struct objfile *objfile)
1764{
1765 struct spu_overlay_table *ovly_table;
1766 struct obj_section *osect;
1767
1768 /* If we've already touched this file, do nothing. */
1769 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1770 return;
1771
0391f248
UW		 1772 /* Consider only SPU objfiles. */
1773 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1774 return;
1775
dcf52cd8
UW		 1776 /* Check if this objfile has overlays. */
1777 ovly_table = spu_get_overlay_table (objfile);
1778 if (!ovly_table)
1779 return;
1780
1781 /* Now go and fiddle with all the LMAs. */
1782 ALL_OBJFILE_OSECTIONS (objfile, osect)
1783 {
1784 bfd *obfd = objfile->obfd;
1785 asection *bsect = osect->the_bfd_section;
1786 int ndx = osect - objfile->sections;
1787
1788 if (ovly_table[ndx].mapped_ptr == 0)
1789 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1790 else
d2ed6730 1791 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
dcf52cd8
UW		 1792 }
1793}
1794
771b4502 1795
3285f3fe
UW		 1796/* Insert temporary breakpoint on "main" function of newly loaded
1797 SPE context OBJFILE. */
1798static void
1799spu_catch_start (struct objfile *objfile)
1800{
1801 struct minimal_symbol *minsym;
1802 struct symtab *symtab;
1803 CORE_ADDR pc;
1804 char buf[32];
1805
1806 /* Do this only if requested by "set spu stop-on-load on". */
1807 if (!spu_stop_on_load_p)
1808 return;
1809
1810 /* Consider only SPU objfiles. */
1811 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1812 return;
1813
1814 /* The main objfile is handled differently. */
1815 if (objfile == symfile_objfile)
1816 return;
1817
1818 /* There can be multiple symbols named "main". Search for the
1819 "main" in *this* objfile. */
1820 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1821 if (!minsym)
1822 return;
1823
1824 /* If we have debugging information, try to use it -- this
1825 will allow us to properly skip the prologue. */
1826 pc = SYMBOL_VALUE_ADDRESS (minsym);
1827 symtab = find_pc_sect_symtab (pc, SYMBOL_OBJ_SECTION (minsym));
1828 if (symtab != NULL)
1829 {
1830 struct blockvector *bv = BLOCKVECTOR (symtab);
1831 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1832 struct symbol *sym;
1833 struct symtab_and_line sal;
1834
94af9270 1835 sym = lookup_block_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1836 if (sym)
1837 {
1838 fixup_symbol_section (sym, objfile);
1839 sal = find_function_start_sal (sym, 1);
1840 pc = sal.pc;
1841 }
1842 }
1843
1844 /* Use a numerical address for the set_breakpoint command to avoid having
1845 the breakpoint re-set incorrectly. */
1846 xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
d8c09fb5
JK		 1847 create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
1848 NULL /* cond_string */, -1 /* thread */,
1849 0 /* parse_condition_and_thread */, 1 /* tempflag */,
1850 0 /* hardwareflag */, 0 /* traceflag */,
1851 0 /* ignore_count */,
1852 AUTO_BOOLEAN_FALSE /* pending_break_support */,
1853 NULL /* ops */, 0 /* from_tty */, 1 /* enabled */);
3285f3fe
UW		 1854}
1855
1856
ff1a52c6
UW		 1857/* Look up OBJFILE loaded into FRAME's SPU context. */
1858static struct objfile *
1859spu_objfile_from_frame (struct frame_info *frame)
1860{
1861 struct gdbarch *gdbarch = get_frame_arch (frame);
1862 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1863 struct objfile *obj;
1864
1865 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
1866 return NULL;
1867
1868 ALL_OBJFILES (obj)
1869 {
1870 if (obj->sections != obj->sections_end
1871 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
1872 return obj;
1873 }
1874
1875 return NULL;
1876}
1877
1878/* Flush cache for ea pointer access if available. */
1879static void
1880flush_ea_cache (void)
1881{
1882 struct minimal_symbol *msymbol;
1883 struct objfile *obj;
1884
1885 if (!has_stack_frames ())
1886 return;
1887
1888 obj = spu_objfile_from_frame (get_current_frame ());
1889 if (obj == NULL)
1890 return;
1891
1892 /* Lookup inferior function __cache_flush. */
1893 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
1894 if (msymbol != NULL)
1895 {
1896 struct type *type;
1897 CORE_ADDR addr;
1898
1899 type = objfile_type (obj)->builtin_void;
1900 type = lookup_function_type (type);
1901 type = lookup_pointer_type (type);
1902 addr = SYMBOL_VALUE_ADDRESS (msymbol);
1903
1904 call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
1905 }
1906}
1907
1908/* This handler is called when the inferior has stopped. If it is stopped in
1909 SPU architecture then flush the ea cache if used. */
1910static void
1911spu_attach_normal_stop (struct bpstats *bs, int print_frame)
1912{
1913 if (!spu_auto_flush_cache_p)
1914 return;
1915
1916 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
1917 re-entering this function when __cache_flush stops. */
1918 spu_auto_flush_cache_p = 0;
1919 flush_ea_cache ();
1920 spu_auto_flush_cache_p = 1;
1921}
1922
1923
23d964e7
UW		 1924/* "info spu" commands. */
1925
1926static void
1927info_spu_event_command (char *args, int from_tty)
1928{
1929 struct frame_info *frame = get_selected_frame (NULL);
1930 ULONGEST event_status = 0;
1931 ULONGEST event_mask = 0;
1932 struct cleanup *chain;
1933 gdb_byte buf[100];
1934 char annex[32];
1935 LONGEST len;
1936 int rc, id;
1937
0391f248
UW		 1938 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1939 error (_("\"info spu\" is only supported on the SPU architecture."));
1940
23d964e7
UW		 1941 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1942
1943 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1944 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1945 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1946 if (len <= 0)
1947 error (_("Could not read event_status."));
9971ac47 1948 buf[len] = '\0';
23d964e7
UW		 1949 event_status = strtoulst (buf, NULL, 16);
1950
1951 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1952 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1953 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1954 if (len <= 0)
1955 error (_("Could not read event_mask."));
9971ac47 1956 buf[len] = '\0';
23d964e7
UW		 1957 event_mask = strtoulst (buf, NULL, 16);
1958
1959 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1960
1961 if (ui_out_is_mi_like_p (uiout))
1962 {
1963 ui_out_field_fmt (uiout, "event_status",
1964 "0x%s", phex_nz (event_status, 4));
1965 ui_out_field_fmt (uiout, "event_mask",
1966 "0x%s", phex_nz (event_mask, 4));
1967 }
1968 else
1969 {
1970 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1971 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1972 }
1973
1974 do_cleanups (chain);
1975}
1976
1977static void
1978info_spu_signal_command (char *args, int from_tty)
1979{
1980 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 1981 struct gdbarch *gdbarch = get_frame_arch (frame);
1982 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 1983 ULONGEST signal1 = 0;
1984 ULONGEST signal1_type = 0;
1985 int signal1_pending = 0;
1986 ULONGEST signal2 = 0;
1987 ULONGEST signal2_type = 0;
1988 int signal2_pending = 0;
1989 struct cleanup *chain;
1990 char annex[32];
1991 gdb_byte buf[100];
1992 LONGEST len;
1993 int rc, id;
1994
e17a4113 1995 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 1996 error (_("\"info spu\" is only supported on the SPU architecture."));
1997
23d964e7
UW		 1998 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1999
2000 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2001 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2002 if (len < 0)
2003 error (_("Could not read signal1."));
2004 else if (len == 4)
2005 {
e17a4113 2006 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2007 signal1_pending = 1;
2008 }
2009
2010 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2011 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2012 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2013 if (len <= 0)
2014 error (_("Could not read signal1_type."));
9971ac47 2015 buf[len] = '\0';
23d964e7
UW		 2016 signal1_type = strtoulst (buf, NULL, 16);
2017
2018 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2019 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2020 if (len < 0)
2021 error (_("Could not read signal2."));
2022 else if (len == 4)
2023 {
e17a4113 2024 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2025 signal2_pending = 1;
2026 }
2027
2028 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2029 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2030 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2031 if (len <= 0)
2032 error (_("Could not read signal2_type."));
9971ac47 2033 buf[len] = '\0';
23d964e7
UW		 2034 signal2_type = strtoulst (buf, NULL, 16);
2035
2036 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
2037
2038 if (ui_out_is_mi_like_p (uiout))
2039 {
2040 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
2041 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2042 ui_out_field_int (uiout, "signal1_type", signal1_type);
2043 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
2044 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2045 ui_out_field_int (uiout, "signal2_type", signal2_type);
2046 }
2047 else
2048 {
2049 if (signal1_pending)
2050 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2051 else
2052 printf_filtered (_("Signal 1 not pending "));
2053
2054 if (signal1_type)
23d964e7 2055 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2056 else
2057 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2058
2059 if (signal2_pending)
2060 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2061 else
2062 printf_filtered (_("Signal 2 not pending "));
2063
2064 if (signal2_type)
23d964e7 2065 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2066 else
2067 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2068 }
2069
2070 do_cleanups (chain);
2071}
2072
2073static void
e17a4113 2074info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2075 const char *field, const char *msg)
2076{
2077 struct cleanup *chain;
2078 int i;
2079
2080 if (nr <= 0)
2081 return;
2082
2083 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
2084
2085 ui_out_table_header (uiout, 32, ui_left, field, msg);
2086 ui_out_table_body (uiout);
2087
2088 for (i = 0; i < nr; i++)
2089 {
2090 struct cleanup *val_chain;
2091 ULONGEST val;
2092 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
e17a4113 2093 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
23d964e7
UW		 2094 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
2095 do_cleanups (val_chain);
2096
2097 if (!ui_out_is_mi_like_p (uiout))
2098 printf_filtered ("\n");
2099 }
2100
2101 do_cleanups (chain);
2102}
2103
2104static void
2105info_spu_mailbox_command (char *args, int from_tty)
2106{
2107 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2108 struct gdbarch *gdbarch = get_frame_arch (frame);
2109 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2110 struct cleanup *chain;
2111 char annex[32];
2112 gdb_byte buf[1024];
2113 LONGEST len;
2114 int i, id;
2115
e17a4113 2116 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2117 error (_("\"info spu\" is only supported on the SPU architecture."));
2118
23d964e7
UW		 2119 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2120
2121 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
2122
2123 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2124 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2125 buf, 0, sizeof buf);
2126 if (len < 0)
2127 error (_("Could not read mbox_info."));
2128
e17a4113
UW		 2129 info_spu_mailbox_list (buf, len / 4, byte_order,
2130 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2131
2132 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2133 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2134 buf, 0, sizeof buf);
2135 if (len < 0)
2136 error (_("Could not read ibox_info."));
2137
e17a4113
UW		 2138 info_spu_mailbox_list (buf, len / 4, byte_order,
2139 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2140
2141 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2142 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2143 buf, 0, sizeof buf);
2144 if (len < 0)
2145 error (_("Could not read wbox_info."));
2146
e17a4113
UW		 2147 info_spu_mailbox_list (buf, len / 4, byte_order,
2148 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2149
2150 do_cleanups (chain);
2151}
2152
2153static ULONGEST
2154spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2155{
2156 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2157 return (word >> (63 - last)) & mask;
2158}
2159
2160static void
e17a4113 2161info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7
UW		 2162{
2163 static char *spu_mfc_opcode[256] =
2164 {
2165 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2166 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2167 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2168 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2169 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2170 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2171 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2172 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2173 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2174 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2175 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2176 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2177 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2178 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2179 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2180 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2181 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2182 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2183 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2184 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2185 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2186 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2187 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2188 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2189 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2190 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2191 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2192 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2193 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2194 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2195 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2196 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2197 };
2198
12ab8a60
UW		 2199 int *seq = alloca (nr * sizeof (int));
2200 int done = 0;
23d964e7 2201 struct cleanup *chain;
12ab8a60
UW		 2202 int i, j;
2203
2204
2205 /* Determine sequence in which to display (valid) entries. */
2206 for (i = 0; i < nr; i++)
2207 {
2208 /* Search for the first valid entry all of whose
2209 dependencies are met. */
2210 for (j = 0; j < nr; j++)
2211 {
2212 ULONGEST mfc_cq_dw3;
2213 ULONGEST dependencies;
2214
2215 if (done & (1 << (nr - 1 - j)))
2216 continue;
2217
e17a4113
UW		 2218 mfc_cq_dw3
2219 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2220 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2221 continue;
2222
2223 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2224 if ((dependencies & done) != dependencies)
2225 continue;
2226
2227 seq[i] = j;
2228 done |= 1 << (nr - 1 - j);
2229 break;
2230 }
2231
2232 if (j == nr)
2233 break;
2234 }
2235
2236 nr = i;
2237
23d964e7
UW		 2238
2239 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
2240
2241 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
2242 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
2243 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
2244 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
2245 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
2246 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
2247 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
2248 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
2249 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
2250 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
2251
2252 ui_out_table_body (uiout);
2253
2254 for (i = 0; i < nr; i++)
2255 {
2256 struct cleanup *cmd_chain;
2257 ULONGEST mfc_cq_dw0;
2258 ULONGEST mfc_cq_dw1;
2259 ULONGEST mfc_cq_dw2;
23d964e7
UW		 2260 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
2261 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
2262 ULONGEST mfc_ea;
2263 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2264
2265 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2266 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2267
e17a4113
UW		 2268 mfc_cq_dw0
2269 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2270 mfc_cq_dw1
2271 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2272 mfc_cq_dw2
2273 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2274
2275 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2276 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2277 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2278 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2279 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2280 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2281 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2282
2283 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2284 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2285
2286 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2287 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2288 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2289 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2290 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2291 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2292
2293 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
2294
2295 if (spu_mfc_opcode[mfc_cmd_opcode])
2296 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
2297 else
2298 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
2299
2300 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
2301 ui_out_field_int (uiout, "tid", tclass_id);
2302 ui_out_field_int (uiout, "rid", rclass_id);
2303
2304 if (ea_valid_p)
2305 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
2306 else
2307 ui_out_field_skip (uiout, "ea");
2308
2309 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
2310 if (qw_valid_p)
2311 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
2312 else
2313 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
2314
2315 if (list_valid_p)
2316 {
2317 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
2318 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
2319 }
2320 else
2321 {
2322 ui_out_field_skip (uiout, "lstaddr");
2323 ui_out_field_skip (uiout, "lstsize");
2324 }
2325
2326 if (cmd_error_p)
2327 ui_out_field_string (uiout, "error_p", "*");
2328 else
2329 ui_out_field_skip (uiout, "error_p");
2330
2331 do_cleanups (cmd_chain);
2332
2333 if (!ui_out_is_mi_like_p (uiout))
2334 printf_filtered ("\n");
2335 }
2336
2337 do_cleanups (chain);
2338}
2339
2340static void
2341info_spu_dma_command (char *args, int from_tty)
2342{
2343 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2344 struct gdbarch *gdbarch = get_frame_arch (frame);
2345 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2346 ULONGEST dma_info_type;
2347 ULONGEST dma_info_mask;
2348 ULONGEST dma_info_status;
2349 ULONGEST dma_info_stall_and_notify;
2350 ULONGEST dma_info_atomic_command_status;
2351 struct cleanup *chain;
2352 char annex[32];
2353 gdb_byte buf[1024];
2354 LONGEST len;
2355 int i, id;
2356
0391f248
UW		 2357 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2358 error (_("\"info spu\" is only supported on the SPU architecture."));
2359
23d964e7
UW		 2360 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2361
2362 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2363 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2364 buf, 0, 40 + 16 * 32);
2365 if (len <= 0)
2366 error (_("Could not read dma_info."));
2367
e17a4113
UW		 2368 dma_info_type
2369 = extract_unsigned_integer (buf, 8, byte_order);
2370 dma_info_mask
2371 = extract_unsigned_integer (buf + 8, 8, byte_order);
2372 dma_info_status
2373 = extract_unsigned_integer (buf + 16, 8, byte_order);
2374 dma_info_stall_and_notify
2375 = extract_unsigned_integer (buf + 24, 8, byte_order);
2376 dma_info_atomic_command_status
2377 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7
UW		 2378
2379 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
2380
2381 if (ui_out_is_mi_like_p (uiout))
2382 {
2383 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
2384 phex_nz (dma_info_type, 4));
2385 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
2386 phex_nz (dma_info_mask, 4));
2387 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
2388 phex_nz (dma_info_status, 4));
2389 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
2390 phex_nz (dma_info_stall_and_notify, 4));
2391 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
2392 phex_nz (dma_info_atomic_command_status, 4));
2393 }
2394 else
2395 {
8fbde58b 2396 const char *query_msg = _("no query pending");
23d964e7 2397
8fbde58b
UW		 2398 if (dma_info_type & 4)
2399 switch (dma_info_type & 3)
2400 {
2401 case 1: query_msg = _("'any' query pending"); break;
2402 case 2: query_msg = _("'all' query pending"); break;
2403 default: query_msg = _("undefined query type"); break;
2404 }
23d964e7
UW		 2405
2406 printf_filtered (_("Tag-Group Status 0x%s\n"),
2407 phex (dma_info_status, 4));
2408 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2409 phex (dma_info_mask, 4), query_msg);
2410 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2411 phex (dma_info_stall_and_notify, 4));
2412 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2413 phex (dma_info_atomic_command_status, 4));
2414 printf_filtered ("\n");
2415 }
2416
e17a4113 2417 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2418 do_cleanups (chain);
2419}
2420
2421static void
2422info_spu_proxydma_command (char *args, int from_tty)
2423{
2424 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2425 struct gdbarch *gdbarch = get_frame_arch (frame);
2426 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2427 ULONGEST dma_info_type;
2428 ULONGEST dma_info_mask;
2429 ULONGEST dma_info_status;
2430 struct cleanup *chain;
2431 char annex[32];
2432 gdb_byte buf[1024];
2433 LONGEST len;
2434 int i, id;
2435
e17a4113 2436 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2437 error (_("\"info spu\" is only supported on the SPU architecture."));
2438
23d964e7
UW		 2439 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2440
2441 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2442 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2443 buf, 0, 24 + 8 * 32);
2444 if (len <= 0)
2445 error (_("Could not read proxydma_info."));
2446
e17a4113
UW		 2447 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2448 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2449 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7
UW		 2450
2451 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
2452
2453 if (ui_out_is_mi_like_p (uiout))
2454 {
2455 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
2456 phex_nz (dma_info_type, 4));
2457 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
2458 phex_nz (dma_info_mask, 4));
2459 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
2460 phex_nz (dma_info_status, 4));
2461 }
2462 else
2463 {
2464 const char *query_msg;
2465
8fbde58b 2466 switch (dma_info_type & 3)
23d964e7
UW		 2467 {
2468 case 0: query_msg = _("no query pending"); break;
2469 case 1: query_msg = _("'any' query pending"); break;
2470 case 2: query_msg = _("'all' query pending"); break;
2471 default: query_msg = _("undefined query type"); break;
2472 }
2473
2474 printf_filtered (_("Tag-Group Status 0x%s\n"),
2475 phex (dma_info_status, 4));
2476 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2477 phex (dma_info_mask, 4), query_msg);
2478 printf_filtered ("\n");
2479 }
2480
e17a4113 2481 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2482 do_cleanups (chain);
2483}
2484
2485static void
2486info_spu_command (char *args, int from_tty)
2487{
2488 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
2489 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2490}
2491
2492
3285f3fe
UW		 2493/* Root of all "set spu "/"show spu " commands. */
2494
2495static void
2496show_spu_command (char *args, int from_tty)
2497{
2498 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2499}
2500
2501static void
2502set_spu_command (char *args, int from_tty)
2503{
2504 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2505}
2506
2507static void
2508show_spu_stop_on_load (struct ui_file *file, int from_tty,
2509 struct cmd_list_element *c, const char *value)
2510{
2511 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2512 value);
2513}
2514
ff1a52c6
UW		 2515static void
2516show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2517 struct cmd_list_element *c, const char *value)
2518{
2519 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2520 value);
2521}
2522
3285f3fe 2523
771b4502
UW		 2524/* Set up gdbarch struct. */
2525
2526static struct gdbarch *
2527spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2528{
2529 struct gdbarch *gdbarch;
794ac428 2530 struct gdbarch_tdep *tdep;
85e747d2
UW		 2531 int id = -1;
2532
2533 /* Which spufs ID was requested as address space? */
2534 if (info.tdep_info)
2535 id = *(int *)info.tdep_info;
2536 /* For objfile architectures of SPU solibs, decode the ID from the name.
2537 This assumes the filename convention employed by solib-spu.c. */
2538 else if (info.abfd)
2539 {
2540 char *name = strrchr (info.abfd->filename, '@');
2541 if (name)
2542 sscanf (name, "@0x%*x <%d>", &id);
2543 }
771b4502 2544
85e747d2
UW		 2545 /* Find a candidate among extant architectures. */
2546 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2547 arches != NULL;
2548 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2549 {
2550 tdep = gdbarch_tdep (arches->gdbarch);
2551 if (tdep && tdep->id == id)
2552 return arches->gdbarch;
2553 }
771b4502 2554
85e747d2 2555 /* None found, so create a new architecture. */
794ac428 2556 tdep = XCALLOC (1, struct gdbarch_tdep);
85e747d2 2557 tdep->id = id;
794ac428 2558 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2559
2560 /* Disassembler. */
85e747d2 2561 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2562
2563 /* Registers. */
2564 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2565 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2566 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2567 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2568 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2569 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2570 set_gdbarch_register_name (gdbarch, spu_register_name);
2571 set_gdbarch_register_type (gdbarch, spu_register_type);
2572 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2573 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2574 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2575 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2576
2577 /* Data types. */
2578 set_gdbarch_char_signed (gdbarch, 0);
2579 set_gdbarch_ptr_bit (gdbarch, 32);
2580 set_gdbarch_addr_bit (gdbarch, 32);
2581 set_gdbarch_short_bit (gdbarch, 16);
2582 set_gdbarch_int_bit (gdbarch, 32);
2583 set_gdbarch_long_bit (gdbarch, 32);
2584 set_gdbarch_long_long_bit (gdbarch, 64);
2585 set_gdbarch_float_bit (gdbarch, 32);
2586 set_gdbarch_double_bit (gdbarch, 64);
2587 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2588 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2589 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2590 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2591
ff1a52c6 2592 /* Address handling. */
85e747d2 2593 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2594 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2595 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2596 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2597 set_gdbarch_address_class_type_flags_to_name
2598 (gdbarch, spu_address_class_type_flags_to_name);
2599 set_gdbarch_address_class_name_to_type_flags
2600 (gdbarch, spu_address_class_name_to_type_flags);
2601
36acd84e 2602
771b4502 2603 /* Inferior function calls. */
7b3dc0b7
UW		 2604 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2605 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2606 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2607 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2608 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2609 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2610 set_gdbarch_return_value (gdbarch, spu_return_value);
2611
2612 /* Frame handling. */
2613 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2614 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2615 frame_base_set_default (gdbarch, &spu_frame_base);
2616 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2617 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2618 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2619 set_gdbarch_frame_args_skip (gdbarch, 0);
2620 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2621 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502 2622
cc5f0d61
UW		 2623 /* Cell/B.E. cross-architecture unwinder support. */
2624 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2625
771b4502
UW		 2626 /* Breakpoints. */
2627 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2628 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2629 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2630 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2631 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2632
dcf52cd8
UW		 2633 /* Overlays. */
2634 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2635
771b4502
UW		 2636 return gdbarch;
2637}
2638
63807e1d
PA		 2639/* Provide a prototype to silence -Wmissing-prototypes. */
2640extern initialize_file_ftype _initialize_spu_tdep;
2641
771b4502
UW		 2642void
2643_initialize_spu_tdep (void)
2644{
2645 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2646
dcf52cd8
UW		 2647 /* Add ourselves to objfile event chain. */
2648 observer_attach_new_objfile (spu_overlay_new_objfile);
2649 spu_overlay_data = register_objfile_data ();
23d964e7 2650
3285f3fe
UW		 2651 /* Install spu stop-on-load handler. */
2652 observer_attach_new_objfile (spu_catch_start);
2653
ff1a52c6
UW		 2654 /* Add ourselves to normal_stop event chain. */
2655 observer_attach_normal_stop (spu_attach_normal_stop);
2656
3285f3fe
UW		 2657 /* Add root prefix command for all "set spu"/"show spu" commands. */
2658 add_prefix_cmd ("spu", no_class, set_spu_command,
2659 _("Various SPU specific commands."),
2660 &setspucmdlist, "set spu ", 0, &setlist);
2661 add_prefix_cmd ("spu", no_class, show_spu_command,
2662 _("Various SPU specific commands."),
2663 &showspucmdlist, "show spu ", 0, &showlist);
2664
2665 /* Toggle whether or not to add a temporary breakpoint at the "main"
2666 function of new SPE contexts. */
2667 add_setshow_boolean_cmd ("stop-on-load", class_support,
2668 &spu_stop_on_load_p, _("\
2669Set whether to stop for new SPE threads."),
2670 _("\
2671Show whether to stop for new SPE threads."),
2672 _("\
2673Use \"on\" to give control to the user when a new SPE thread\n\
2674enters its \"main\" function.\n\
2675Use \"off\" to disable stopping for new SPE threads."),
2676 NULL,
2677 show_spu_stop_on_load,
2678 &setspucmdlist, &showspucmdlist);
2679
ff1a52c6
UW		 2680 /* Toggle whether or not to automatically flush the software-managed
2681 cache whenever SPE execution stops. */
2682 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2683 &spu_auto_flush_cache_p, _("\
2684Set whether to automatically flush the software-managed cache."),
2685 _("\
2686Show whether to automatically flush the software-managed cache."),
2687 _("\
2688Use \"on\" to automatically flush the software-managed cache\n\
2689whenever SPE execution stops.\n\
2690Use \"off\" to never automatically flush the software-managed cache."),
2691 NULL,
2692 show_spu_auto_flush_cache,
2693 &setspucmdlist, &showspucmdlist);
2694
23d964e7
UW		 2695 /* Add root prefix command for all "info spu" commands. */
2696 add_prefix_cmd ("spu", class_info, info_spu_command,
2697 _("Various SPU specific commands."),
2698 &infospucmdlist, "info spu ", 0, &infolist);
2699
2700 /* Add various "info spu" commands. */
2701 add_cmd ("event", class_info, info_spu_event_command,
2702 _("Display SPU event facility status.\n"),
2703 &infospucmdlist);
2704 add_cmd ("signal", class_info, info_spu_signal_command,
2705 _("Display SPU signal notification facility status.\n"),
2706 &infospucmdlist);
2707 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2708 _("Display SPU mailbox facility status.\n"),
2709 &infospucmdlist);
2710 add_cmd ("dma", class_info, info_spu_dma_command,
2711 _("Display MFC DMA status.\n"),
2712 &infospucmdlist);
2713 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2714 _("Display MFC Proxy-DMA status.\n"),
2715 &infospucmdlist);
771b4502 2716}
GDB Binutils - Deliverables
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