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[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
ecd75fc8 2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
0e9f083f 27#include <string.h>
771b4502
UW		 28#include "gdb_assert.h"
29#include "frame.h"
30#include "frame-unwind.h"
31#include "frame-base.h"
32#include "trad-frame.h"
33#include "symtab.h"
34#include "symfile.h"
35#include "value.h"
36#include "inferior.h"
37#include "dis-asm.h"
38#include "objfiles.h"
39#include "language.h"
40#include "regcache.h"
41#include "reggroups.h"
42#include "floatformat.h"
3285f3fe 43#include "block.h"
dcf52cd8 44#include "observer.h"
ff1a52c6 45#include "infcall.h"
54fcddd0 46#include "dwarf2.h"
8dccd430 47#include "exceptions.h"
771b4502
UW		 48#include "spu-tdep.h"
49
794ac428 50
3285f3fe
UW		 51/* The list of available "set spu " and "show spu " commands. */
52static struct cmd_list_element *setspucmdlist = NULL;
53static struct cmd_list_element *showspucmdlist = NULL;
54
55/* Whether to stop for new SPE contexts. */
56static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 57/* Whether to automatically flush the SW-managed cache. */
58static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 59
60
794ac428
UW		 61/* The tdep structure. */
62struct gdbarch_tdep
63{
85e747d2
UW		 64 /* The spufs ID identifying our address space. */
65 int id;
66
794ac428
UW		 67 /* SPU-specific vector type. */
68 struct type *spu_builtin_type_vec128;
69};
70
71
f2d43c2c 72/* SPU-specific vector type. */
794ac428
UW		 73static struct type *
74spu_builtin_type_vec128 (struct gdbarch *gdbarch)
75{
76 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
77
78 if (!tdep->spu_builtin_type_vec128)
79 {
df4df182 80 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 81 struct type *t;
82
e9bb382b
UW		 83 t = arch_composite_type (gdbarch,
84 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 85 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 86 append_composite_type_field (t, "v2_int64",
df4df182 87 init_vector_type (bt->builtin_int64, 2));
794ac428 88 append_composite_type_field (t, "v4_int32",
df4df182 89 init_vector_type (bt->builtin_int32, 4));
794ac428 90 append_composite_type_field (t, "v8_int16",
df4df182 91 init_vector_type (bt->builtin_int16, 8));
794ac428 92 append_composite_type_field (t, "v16_int8",
df4df182 93 init_vector_type (bt->builtin_int8, 16));
794ac428 94 append_composite_type_field (t, "v2_double",
df4df182 95 init_vector_type (bt->builtin_double, 2));
794ac428 96 append_composite_type_field (t, "v4_float",
df4df182 97 init_vector_type (bt->builtin_float, 4));
794ac428 98
876cecd0 99 TYPE_VECTOR (t) = 1;
794ac428
UW		 100 TYPE_NAME (t) = "spu_builtin_type_vec128";
101
102 tdep->spu_builtin_type_vec128 = t;
103 }
104
105 return tdep->spu_builtin_type_vec128;
106}
107
771b4502 108
23d964e7
UW		 109/* The list of available "info spu " commands. */
110static struct cmd_list_element *infospucmdlist = NULL;
111
771b4502
UW		 112/* Registers. */
113
114static const char *
d93859e2 115spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 116{
117 static char *register_names[] =
118 {
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
122 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
123 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
124 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
125 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
126 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
127 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
128 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
129 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
130 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
131 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
132 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
133 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
134 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 135 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 136 };
137
138 if (reg_nr < 0)
139 return NULL;
140 if (reg_nr >= sizeof register_names / sizeof *register_names)
141 return NULL;
142
143 return register_names[reg_nr];
144}
145
146static struct type *
147spu_register_type (struct gdbarch *gdbarch, int reg_nr)
148{
149 if (reg_nr < SPU_NUM_GPRS)
794ac428 150 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 151
152 switch (reg_nr)
153 {
154 case SPU_ID_REGNUM:
df4df182 155 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 156
157 case SPU_PC_REGNUM:
0dfff4cb 158 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 159
160 case SPU_SP_REGNUM:
0dfff4cb 161 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 162
23d964e7 163 case SPU_FPSCR_REGNUM:
df4df182 164 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 165
166 case SPU_SRR0_REGNUM:
df4df182 167 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 168
169 case SPU_LSLR_REGNUM:
df4df182 170 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 171
172 case SPU_DECR_REGNUM:
df4df182 173 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 174
175 case SPU_DECR_STATUS_REGNUM:
df4df182 176 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 177
771b4502 178 default:
a73c6dcd 179 internal_error (__FILE__, __LINE__, _("invalid regnum"));
771b4502
UW		 180 }
181}
182
183/* Pseudo registers for preferred slots - stack pointer. */
184
05d1431c 185static enum register_status
23d964e7
UW		 186spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
187 gdb_byte *buf)
188{
e17a4113
UW		 189 struct gdbarch *gdbarch = get_regcache_arch (regcache);
190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
05d1431c 191 enum register_status status;
23d964e7
UW		 192 gdb_byte reg[32];
193 char annex[32];
194 ULONGEST id;
001f13d8 195 ULONGEST ul;
23d964e7 196
05d1431c
PA		 197 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
198 if (status != REG_VALID)
199 return status;
23d964e7
UW		 200 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
201 memset (reg, 0, sizeof reg);
202 target_read (&current_target, TARGET_OBJECT_SPU, annex,
203 reg, 0, sizeof reg);
204
001f13d8
PA		 205 ul = strtoulst ((char *) reg, NULL, 16);
206 store_unsigned_integer (buf, 4, byte_order, ul);
05d1431c 207 return REG_VALID;
23d964e7
UW		 208}
209
05d1431c 210static enum register_status
771b4502
UW		 211spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
212 int regnum, gdb_byte *buf)
213{
214 gdb_byte reg[16];
23d964e7
UW		 215 char annex[32];
216 ULONGEST id;
05d1431c 217 enum register_status status;
771b4502
UW		 218
219 switch (regnum)
220 {
221 case SPU_SP_REGNUM:
05d1431c
PA		 222 status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
223 if (status != REG_VALID)
224 return status;
771b4502 225 memcpy (buf, reg, 4);
05d1431c 226 return status;
771b4502 227
23d964e7 228 case SPU_FPSCR_REGNUM:
05d1431c
PA		 229 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
230 if (status != REG_VALID)
231 return status;
23d964e7
UW		 232 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
233 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
05d1431c 234 return status;
23d964e7
UW		 235
236 case SPU_SRR0_REGNUM:
05d1431c 237 return spu_pseudo_register_read_spu (regcache, "srr0", buf);
23d964e7
UW		 238
239 case SPU_LSLR_REGNUM:
05d1431c 240 return spu_pseudo_register_read_spu (regcache, "lslr", buf);
23d964e7
UW		 241
242 case SPU_DECR_REGNUM:
05d1431c 243 return spu_pseudo_register_read_spu (regcache, "decr", buf);
23d964e7
UW		 244
245 case SPU_DECR_STATUS_REGNUM:
05d1431c 246 return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
23d964e7 247
771b4502
UW		 248 default:
249 internal_error (__FILE__, __LINE__, _("invalid regnum"));
250 }
251}
252
23d964e7
UW		 253static void
254spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
255 const gdb_byte *buf)
256{
e17a4113
UW		 257 struct gdbarch *gdbarch = get_regcache_arch (regcache);
258 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
001f13d8 259 char reg[32];
23d964e7
UW		 260 char annex[32];
261 ULONGEST id;
262
263 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
264 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
265 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 266 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7 267 target_write (&current_target, TARGET_OBJECT_SPU, annex,
001f13d8 268 (gdb_byte *) reg, 0, strlen (reg));
23d964e7
UW		 269}
270
771b4502
UW		 271static void
272spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
273 int regnum, const gdb_byte *buf)
274{
275 gdb_byte reg[16];
23d964e7
UW		 276 char annex[32];
277 ULONGEST id;
771b4502
UW		 278
279 switch (regnum)
280 {
281 case SPU_SP_REGNUM:
282 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
283 memcpy (reg, buf, 4);
284 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
285 break;
286
23d964e7
UW		 287 case SPU_FPSCR_REGNUM:
288 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
289 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
290 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
291 break;
292
293 case SPU_SRR0_REGNUM:
294 spu_pseudo_register_write_spu (regcache, "srr0", buf);
295 break;
296
297 case SPU_LSLR_REGNUM:
298 spu_pseudo_register_write_spu (regcache, "lslr", buf);
299 break;
300
301 case SPU_DECR_REGNUM:
302 spu_pseudo_register_write_spu (regcache, "decr", buf);
303 break;
304
305 case SPU_DECR_STATUS_REGNUM:
306 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
307 break;
308
771b4502
UW		 309 default:
310 internal_error (__FILE__, __LINE__, _("invalid regnum"));
311 }
312}
313
314/* Value conversion -- access scalar values at the preferred slot. */
315
9acbedc0
UW		 316static struct value *
317spu_value_from_register (struct type *type, int regnum,
318 struct frame_info *frame)
771b4502 319{
9acbedc0 320 struct value *value = default_value_from_register (type, regnum, frame);
bad43aa5 321 int len = TYPE_LENGTH (type);
771b4502 322
bad43aa5 323 if (regnum < SPU_NUM_GPRS && len < 16)
9acbedc0 324 {
bad43aa5 325 int preferred_slot = len < 4 ? 4 - len : 0;
9acbedc0
UW		 326 set_value_offset (value, preferred_slot);
327 }
771b4502 328
9acbedc0 329 return value;
771b4502
UW		 330}
331
332/* Register groups. */
333
334static int
335spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
336 struct reggroup *group)
337{
338 /* Registers displayed via 'info regs'. */
339 if (group == general_reggroup)
340 return 1;
341
342 /* Registers displayed via 'info float'. */
343 if (group == float_reggroup)
344 return 0;
345
346 /* Registers that need to be saved/restored in order to
347 push or pop frames. */
348 if (group == save_reggroup || group == restore_reggroup)
349 return 1;
350
351 return default_register_reggroup_p (gdbarch, regnum, group);
352}
353
ff1a52c6
UW		 354
355/* Address handling. */
36acd84e 356
85e747d2
UW		 357static int
358spu_gdbarch_id (struct gdbarch *gdbarch)
359{
360 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
361 int id = tdep->id;
362
363 /* The objfile architecture of a standalone SPU executable does not
b021a221 364 provide an SPU ID. Retrieve it from the objfile's relocated
85e747d2
UW		 365 address range in this special case. */
366 if (id == -1
367 && symfile_objfile && symfile_objfile->obfd
368 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
369 && symfile_objfile->sections != symfile_objfile->sections_end)
370 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
371
372 return id;
373}
374
ff1a52c6
UW		 375static int
376spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
377{
378 if (dwarf2_addr_class == 1)
379 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
380 else
381 return 0;
382}
383
384static const char *
385spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
386{
387 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
388 return "__ea";
389 else
390 return NULL;
391}
392
393static int
394spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
395 const char *name, int *type_flags_ptr)
396{
397 if (strcmp (name, "__ea") == 0)
398 {
399 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
400 return 1;
401 }
402 else
403 return 0;
404}
405
85e747d2
UW		 406static void
407spu_address_to_pointer (struct gdbarch *gdbarch,
408 struct type *type, gdb_byte *buf, CORE_ADDR addr)
409{
410 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
411 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
412 SPUADDR_ADDR (addr));
413}
414
36acd84e 415static CORE_ADDR
9898f801
UW		 416spu_pointer_to_address (struct gdbarch *gdbarch,
417 struct type *type, const gdb_byte *buf)
36acd84e 418{
85e747d2 419 int id = spu_gdbarch_id (gdbarch);
e17a4113
UW		 420 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
421 ULONGEST addr
422 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 423
ff1a52c6
UW		 424 /* Do not convert __ea pointers. */
425 if (TYPE_ADDRESS_CLASS_1 (type))
426 return addr;
427
d2ed6730 428 return addr? SPUADDR (id, addr) : 0;
36acd84e
UW		 429}
430
431static CORE_ADDR
432spu_integer_to_address (struct gdbarch *gdbarch,
433 struct type *type, const gdb_byte *buf)
434{
85e747d2 435 int id = spu_gdbarch_id (gdbarch);
36acd84e 436 ULONGEST addr = unpack_long (type, buf);
36acd84e 437
d2ed6730 438 return SPUADDR (id, addr);
36acd84e
UW		 439}
440
771b4502
UW		 441
442/* Decoding SPU instructions. */
443
444enum
445 {
446 op_lqd = 0x34,
447 op_lqx = 0x3c4,
448 op_lqa = 0x61,
449 op_lqr = 0x67,
450 op_stqd = 0x24,
451 op_stqx = 0x144,
452 op_stqa = 0x41,
453 op_stqr = 0x47,
454
455 op_il = 0x081,
456 op_ila = 0x21,
457 op_a = 0x0c0,
458 op_ai = 0x1c,
459
a536c6d7 460 op_selb = 0x8,
771b4502
UW		 461
462 op_br = 0x64,
463 op_bra = 0x60,
464 op_brsl = 0x66,
465 op_brasl = 0x62,
466 op_brnz = 0x42,
467 op_brz = 0x40,
468 op_brhnz = 0x46,
469 op_brhz = 0x44,
470 op_bi = 0x1a8,
471 op_bisl = 0x1a9,
472 op_biz = 0x128,
473 op_binz = 0x129,
474 op_bihz = 0x12a,
475 op_bihnz = 0x12b,
476 };
477
478static int
479is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
480{
481 if ((insn >> 21) == op)
482 {
483 *rt = insn & 127;
484 *ra = (insn >> 7) & 127;
485 *rb = (insn >> 14) & 127;
486 return 1;
487 }
488
489 return 0;
490}
491
492static int
493is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
494{
495 if ((insn >> 28) == op)
496 {
497 *rt = (insn >> 21) & 127;
498 *ra = (insn >> 7) & 127;
499 *rb = (insn >> 14) & 127;
500 *rc = insn & 127;
501 return 1;
502 }
503
504 return 0;
505}
506
507static int
508is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
509{
510 if ((insn >> 21) == op)
511 {
512 *rt = insn & 127;
513 *ra = (insn >> 7) & 127;
514 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
515 return 1;
516 }
517
518 return 0;
519}
520
521static int
522is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
523{
524 if ((insn >> 24) == op)
525 {
526 *rt = insn & 127;
527 *ra = (insn >> 7) & 127;
528 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
529 return 1;
530 }
531
532 return 0;
533}
534
535static int
536is_ri16 (unsigned int insn, int op, int *rt, int *i16)
537{
538 if ((insn >> 23) == op)
539 {
540 *rt = insn & 127;
541 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
542 return 1;
543 }
544
545 return 0;
546}
547
548static int
549is_ri18 (unsigned int insn, int op, int *rt, int *i18)
550{
551 if ((insn >> 25) == op)
552 {
553 *rt = insn & 127;
554 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
555 return 1;
556 }
557
558 return 0;
559}
560
561static int
562is_branch (unsigned int insn, int *offset, int *reg)
563{
564 int rt, i7, i16;
565
566 if (is_ri16 (insn, op_br, &rt, &i16)
567 || is_ri16 (insn, op_brsl, &rt, &i16)
568 || is_ri16 (insn, op_brnz, &rt, &i16)
569 || is_ri16 (insn, op_brz, &rt, &i16)
570 || is_ri16 (insn, op_brhnz, &rt, &i16)
571 || is_ri16 (insn, op_brhz, &rt, &i16))
572 {
573 *reg = SPU_PC_REGNUM;
574 *offset = i16 << 2;
575 return 1;
576 }
577
578 if (is_ri16 (insn, op_bra, &rt, &i16)
579 || is_ri16 (insn, op_brasl, &rt, &i16))
580 {
581 *reg = -1;
582 *offset = i16 << 2;
583 return 1;
584 }
585
586 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
587 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
588 || is_ri7 (insn, op_biz, &rt, reg, &i7)
589 || is_ri7 (insn, op_binz, &rt, reg, &i7)
590 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
591 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
592 {
593 *offset = 0;
594 return 1;
595 }
596
597 return 0;
598}
599
600
601/* Prolog parsing. */
602
603struct spu_prologue_data
604 {
605 /* Stack frame size. -1 if analysis was unsuccessful. */
606 int size;
607
608 /* How to find the CFA. The CFA is equal to SP at function entry. */
609 int cfa_reg;
610 int cfa_offset;
611
612 /* Offset relative to CFA where a register is saved. -1 if invalid. */
613 int reg_offset[SPU_NUM_GPRS];
614 };
615
616static CORE_ADDR
e17a4113
UW		 617spu_analyze_prologue (struct gdbarch *gdbarch,
618 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 619 struct spu_prologue_data *data)
620{
e17a4113 621 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 622 int found_sp = 0;
623 int found_fp = 0;
624 int found_lr = 0;
ce50d78b 625 int found_bc = 0;
771b4502
UW		 626 int reg_immed[SPU_NUM_GPRS];
627 gdb_byte buf[16];
628 CORE_ADDR prolog_pc = start_pc;
629 CORE_ADDR pc;
630 int i;
631
632
633 /* Initialize DATA to default values. */
634 data->size = -1;
635
636 data->cfa_reg = SPU_RAW_SP_REGNUM;
637 data->cfa_offset = 0;
638
639 for (i = 0; i < SPU_NUM_GPRS; i++)
640 data->reg_offset[i] = -1;
641
642 /* Set up REG_IMMED array. This is non-zero for a register if we know its
643 preferred slot currently holds this immediate value. */
644 for (i = 0; i < SPU_NUM_GPRS; i++)
645 reg_immed[i] = 0;
646
647 /* Scan instructions until the first branch.
648
649 The following instructions are important prolog components:
650
651 - The first instruction to set up the stack pointer.
652 - The first instruction to set up the frame pointer.
653 - The first instruction to save the link register.
ce50d78b 654 - The first instruction to save the backchain.
771b4502 655
ce50d78b 656 We return the instruction after the latest of these four,
771b4502
UW		 657 or the incoming PC if none is found. The first instruction
658 to set up the stack pointer also defines the frame size.
659
660 Note that instructions saving incoming arguments to their stack
661 slots are not counted as important, because they are hard to
662 identify with certainty. This should not matter much, because
663 arguments are relevant only in code compiled with debug data,
664 and in such code the GDB core will advance until the first source
665 line anyway, using SAL data.
666
667 For purposes of stack unwinding, we analyze the following types
668 of instructions in addition:
669
670 - Any instruction adding to the current frame pointer.
671 - Any instruction loading an immediate constant into a register.
672 - Any instruction storing a register onto the stack.
673
674 These are used to compute the CFA and REG_OFFSET output. */
675
676 for (pc = start_pc; pc < end_pc; pc += 4)
677 {
678 unsigned int insn;
679 int rt, ra, rb, rc, immed;
680
681 if (target_read_memory (pc, buf, 4))
682 break;
e17a4113 683 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 684
685 /* AI is the typical instruction to set up a stack frame.
686 It is also used to initialize the frame pointer. */
687 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
688 {
689 if (rt == data->cfa_reg && ra == data->cfa_reg)
690 data->cfa_offset -= immed;
691
692 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
693 && !found_sp)
694 {
695 found_sp = 1;
696 prolog_pc = pc + 4;
697
698 data->size = -immed;
699 }
700 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
701 && !found_fp)
702 {
703 found_fp = 1;
704 prolog_pc = pc + 4;
705
706 data->cfa_reg = SPU_FP_REGNUM;
707 data->cfa_offset -= immed;
708 }
709 }
710
711 /* A is used to set up stack frames of size >= 512 bytes.
712 If we have tracked the contents of the addend register,
713 we can handle this as well. */
714 else if (is_rr (insn, op_a, &rt, &ra, &rb))
715 {
716 if (rt == data->cfa_reg && ra == data->cfa_reg)
717 {
718 if (reg_immed[rb] != 0)
719 data->cfa_offset -= reg_immed[rb];
720 else
721 data->cfa_reg = -1; /* We don't know the CFA any more. */
722 }
723
724 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
725 && !found_sp)
726 {
727 found_sp = 1;
728 prolog_pc = pc + 4;
729
730 if (reg_immed[rb] != 0)
731 data->size = -reg_immed[rb];
732 }
733 }
734
735 /* We need to track IL and ILA used to load immediate constants
736 in case they are later used as input to an A instruction. */
737 else if (is_ri16 (insn, op_il, &rt, &immed))
738 {
739 reg_immed[rt] = immed;
12102450
UW		 740
741 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
742 found_sp = 1;
771b4502
UW		 743 }
744
745 else if (is_ri18 (insn, op_ila, &rt, &immed))
746 {
747 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 748
749 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
750 found_sp = 1;
771b4502
UW		 751 }
752
753 /* STQD is used to save registers to the stack. */
754 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
755 {
756 if (ra == data->cfa_reg)
757 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
758
759 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
760 && !found_lr)
761 {
762 found_lr = 1;
763 prolog_pc = pc + 4;
764 }
ce50d78b
UW		 765
766 if (ra == SPU_RAW_SP_REGNUM
767 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
768 && !found_bc)
769 {
770 found_bc = 1;
771 prolog_pc = pc + 4;
772 }
771b4502
UW		 773 }
774
775 /* _start uses SELB to set up the stack pointer. */
776 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
777 {
778 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
779 found_sp = 1;
780 }
781
782 /* We terminate if we find a branch. */
783 else if (is_branch (insn, &immed, &ra))
784 break;
785 }
786
787
788 /* If we successfully parsed until here, and didn't find any instruction
789 modifying SP, we assume we have a frameless function. */
790 if (!found_sp)
791 data->size = 0;
792
793 /* Return cooked instead of raw SP. */
794 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
795 data->cfa_reg = SPU_SP_REGNUM;
796
797 return prolog_pc;
798}
799
800/* Return the first instruction after the prologue starting at PC. */
801static CORE_ADDR
6093d2eb 802spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 803{
804 struct spu_prologue_data data;
e17a4113 805 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 806}
807
808/* Return the frame pointer in use at address PC. */
809static void
a54fba4c
MD		 810spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
811 int *reg, LONGEST *offset)
771b4502
UW		 812{
813 struct spu_prologue_data data;
e17a4113 814 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 815
816 if (data.size != -1 && data.cfa_reg != -1)
817 {
818 /* The 'frame pointer' address is CFA minus frame size. */
819 *reg = data.cfa_reg;
820 *offset = data.cfa_offset - data.size;
821 }
822 else
823 {
c378eb4e 824 /* ??? We don't really know ... */
771b4502
UW		 825 *reg = SPU_SP_REGNUM;
826 *offset = 0;
827 }
828}
829
fe5febed
UW		 830/* Return true if we are in the function's epilogue, i.e. after the
831 instruction that destroyed the function's stack frame.
832
833 1) scan forward from the point of execution:
834 a) If you find an instruction that modifies the stack pointer
835 or transfers control (except a return), execution is not in
836 an epilogue, return.
837 b) Stop scanning if you find a return instruction or reach the
838 end of the function or reach the hard limit for the size of
839 an epilogue.
840 2) scan backward from the point of execution:
841 a) If you find an instruction that modifies the stack pointer,
842 execution *is* in an epilogue, return.
843 b) Stop scanning if you reach an instruction that transfers
844 control or the beginning of the function or reach the hard
845 limit for the size of an epilogue. */
846
847static int
848spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
849{
e17a4113 850 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 851 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
852 bfd_byte buf[4];
853 unsigned int insn;
22e048c9 854 int rt, ra, rb, immed;
fe5febed
UW		 855
856 /* Find the search limits based on function boundaries and hard limit.
857 We assume the epilogue can be up to 64 instructions long. */
858
859 const int spu_max_epilogue_size = 64 * 4;
860
861 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
862 return 0;
863
864 if (pc - func_start < spu_max_epilogue_size)
865 epilogue_start = func_start;
866 else
867 epilogue_start = pc - spu_max_epilogue_size;
868
869 if (func_end - pc < spu_max_epilogue_size)
870 epilogue_end = func_end;
871 else
872 epilogue_end = pc + spu_max_epilogue_size;
873
874 /* Scan forward until next 'bi $0'. */
875
876 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
877 {
878 if (target_read_memory (scan_pc, buf, 4))
879 return 0;
e17a4113 880 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 881
882 if (is_branch (insn, &immed, &ra))
883 {
884 if (immed == 0 && ra == SPU_LR_REGNUM)
885 break;
886
887 return 0;
888 }
889
890 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
891 || is_rr (insn, op_a, &rt, &ra, &rb)
892 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
893 {
894 if (rt == SPU_RAW_SP_REGNUM)
895 return 0;
896 }
897 }
898
899 if (scan_pc >= epilogue_end)
900 return 0;
901
902 /* Scan backward until adjustment to stack pointer (R1). */
903
904 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
905 {
906 if (target_read_memory (scan_pc, buf, 4))
907 return 0;
e17a4113 908 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 909
910 if (is_branch (insn, &immed, &ra))
911 return 0;
912
913 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
914 || is_rr (insn, op_a, &rt, &ra, &rb)
915 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
916 {
917 if (rt == SPU_RAW_SP_REGNUM)
918 return 1;
919 }
920 }
921
922 return 0;
923}
924
925
771b4502
UW		 926/* Normal stack frames. */
927
928struct spu_unwind_cache
929{
930 CORE_ADDR func;
931 CORE_ADDR frame_base;
932 CORE_ADDR local_base;
933
934 struct trad_frame_saved_reg *saved_regs;
935};
936
937static struct spu_unwind_cache *
8d998b8f 938spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 939 void **this_prologue_cache)
940{
e17a4113 941 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 942 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 943 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 944 struct spu_unwind_cache *info;
945 struct spu_prologue_data data;
85e747d2 946 CORE_ADDR id = tdep->id;
dcf52cd8 947 gdb_byte buf[16];
771b4502
UW		 948
949 if (*this_prologue_cache)
950 return *this_prologue_cache;
951
952 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
953 *this_prologue_cache = info;
8d998b8f 954 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 955 info->frame_base = 0;
956 info->local_base = 0;
957
958 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 959 info->func = get_frame_func (this_frame);
771b4502
UW		 960 if (info->func == 0)
961 {
962 /* Fall back to using the current PC as frame ID. */
8d998b8f 963 info->func = get_frame_pc (this_frame);
771b4502
UW		 964 data.size = -1;
965 }
966 else
e17a4113
UW		 967 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
968 &data);
771b4502
UW		 969
970 /* If successful, use prologue analysis data. */
971 if (data.size != -1 && data.cfa_reg != -1)
972 {
973 CORE_ADDR cfa;
974 int i;
771b4502
UW		 975
976 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 977 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 978 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 979 cfa = SPUADDR (id, cfa);
771b4502
UW		 980
981 /* Call-saved register slots. */
982 for (i = 0; i < SPU_NUM_GPRS; i++)
983 if (i == SPU_LR_REGNUM
984 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
985 if (data.reg_offset[i] != -1)
986 info->saved_regs[i].addr = cfa - data.reg_offset[i];
987
771b4502
UW		 988 /* Frame bases. */
989 info->frame_base = cfa;
990 info->local_base = cfa - data.size;
991 }
992
993 /* Otherwise, fall back to reading the backchain link. */
994 else
995 {
cdc9523a
UW		 996 CORE_ADDR reg;
997 LONGEST backchain;
13def385 998 ULONGEST lslr;
cdc9523a 999 int status;
771b4502 1000
13def385
UW		 1001 /* Get local store limit. */
1002 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1003 if (!lslr)
1004 lslr = (ULONGEST) -1;
1005
771b4502 1006 /* Get the backchain. */
8d998b8f 1007 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 1008 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1009 &backchain);
771b4502
UW		 1010
1011 /* A zero backchain terminates the frame chain. Also, sanity
1012 check against the local store size limit. */
13def385 1013 if (status && backchain > 0 && backchain <= lslr)
771b4502
UW		 1014 {
1015 /* Assume the link register is saved into its slot. */
13def385 1016 if (backchain + 16 <= lslr)
c378eb4e
MS		 1017 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1018 backchain + 16);
771b4502 1019
771b4502 1020 /* Frame bases. */
85e747d2
UW		 1021 info->frame_base = SPUADDR (id, backchain);
1022 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1023 }
1024 }
dcf52cd8 1025
c4891da7
UW		 1026 /* If we didn't find a frame, we cannot determine SP / return address. */
1027 if (info->frame_base == 0)
1028 return info;
1029
dcf52cd8 1030 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1031 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1032 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1033
0a44cb36
UW		 1034 /* Read full contents of the unwound link register in order to
1035 be able to determine the return address. */
dcf52cd8
UW		 1036 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1037 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1038 else
8d998b8f 1039 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1040
0a44cb36
UW		 1041 /* Normally, the return address is contained in the slot 0 of the
1042 link register, and slots 1-3 are zero. For an overlay return,
1043 slot 0 contains the address of the overlay manager return stub,
1044 slot 1 contains the partition number of the overlay section to
1045 be returned to, and slot 2 contains the return address within
1046 that section. Return the latter address in that case. */
e17a4113 1047 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1048 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1049 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1050 else
1051 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1052 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1053
1054 return info;
1055}
1056
1057static void
8d998b8f 1058spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1059 void **this_prologue_cache, struct frame_id *this_id)
1060{
1061 struct spu_unwind_cache *info =
8d998b8f 1062 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1063
1064 if (info->frame_base == 0)
1065 return;
1066
1067 *this_id = frame_id_build (info->frame_base, info->func);
1068}
1069
8d998b8f
UW		 1070static struct value *
1071spu_frame_prev_register (struct frame_info *this_frame,
1072 void **this_prologue_cache, int regnum)
771b4502
UW		 1073{
1074 struct spu_unwind_cache *info
8d998b8f 1075 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1076
1077 /* Special-case the stack pointer. */
1078 if (regnum == SPU_RAW_SP_REGNUM)
1079 regnum = SPU_SP_REGNUM;
1080
8d998b8f 1081 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1082}
1083
1084static const struct frame_unwind spu_frame_unwind = {
1085 NORMAL_FRAME,
8fbca658 1086 default_frame_unwind_stop_reason,
771b4502 1087 spu_frame_this_id,
8d998b8f
UW		 1088 spu_frame_prev_register,
1089 NULL,
1090 default_frame_sniffer
771b4502
UW		 1091};
1092
771b4502 1093static CORE_ADDR
8d998b8f 1094spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1095{
1096 struct spu_unwind_cache *info
8d998b8f 1097 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1098 return info->local_base;
1099}
1100
1101static const struct frame_base spu_frame_base = {
1102 &spu_frame_unwind,
1103 spu_frame_base_address,
1104 spu_frame_base_address,
1105 spu_frame_base_address
1106};
1107
1108static CORE_ADDR
1109spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1110{
85e747d2 1111 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1112 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1113 /* Mask off interrupt enable bit. */
85e747d2 1114 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1115}
1116
1117static CORE_ADDR
1118spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1119{
85e747d2
UW		 1120 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1121 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1122 return SPUADDR (tdep->id, sp);
771b4502
UW		 1123}
1124
118dfbaf 1125static CORE_ADDR
61a1198a 1126spu_read_pc (struct regcache *regcache)
118dfbaf 1127{
85e747d2 1128 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1129 ULONGEST pc;
1130 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1131 /* Mask off interrupt enable bit. */
85e747d2 1132 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1133}
1134
1135static void
61a1198a 1136spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1137{
1138 /* Keep interrupt enabled state unchanged. */
61a1198a 1139 ULONGEST old_pc;
30bcb456 1140
61a1198a
UW		 1141 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1142 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1143 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1144}
1145
771b4502 1146
cc5f0d61
UW		 1147/* Cell/B.E. cross-architecture unwinder support. */
1148
1149struct spu2ppu_cache
1150{
1151 struct frame_id frame_id;
1152 struct regcache *regcache;
1153};
1154
1155static struct gdbarch *
1156spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1157{
1158 struct spu2ppu_cache *cache = *this_cache;
1159 return get_regcache_arch (cache->regcache);
1160}
1161
1162static void
1163spu2ppu_this_id (struct frame_info *this_frame,
1164 void **this_cache, struct frame_id *this_id)
1165{
1166 struct spu2ppu_cache *cache = *this_cache;
1167 *this_id = cache->frame_id;
1168}
1169
1170static struct value *
1171spu2ppu_prev_register (struct frame_info *this_frame,
1172 void **this_cache, int regnum)
1173{
1174 struct spu2ppu_cache *cache = *this_cache;
1175 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1176 gdb_byte *buf;
1177
1178 buf = alloca (register_size (gdbarch, regnum));
1179 regcache_cooked_read (cache->regcache, regnum, buf);
1180 return frame_unwind_got_bytes (this_frame, regnum, buf);
1181}
1182
1183static int
1184spu2ppu_sniffer (const struct frame_unwind *self,
1185 struct frame_info *this_frame, void **this_prologue_cache)
1186{
1187 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1188 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1189 CORE_ADDR base, func, backchain;
1190 gdb_byte buf[4];
1191
f5656ead 1192 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_spu)
cc5f0d61
UW		 1193 return 0;
1194
1195 base = get_frame_sp (this_frame);
1196 func = get_frame_pc (this_frame);
1197 if (target_read_memory (base, buf, 4))
1198 return 0;
1199 backchain = extract_unsigned_integer (buf, 4, byte_order);
1200
1201 if (!backchain)
1202 {
1203 struct frame_info *fi;
1204
1205 struct spu2ppu_cache *cache
1206 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1207
1208 cache->frame_id = frame_id_build (base + 16, func);
1209
1210 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1211 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1212 break;
1213
1214 if (fi)
1215 {
1216 cache->regcache = frame_save_as_regcache (fi);
1217 *this_prologue_cache = cache;
1218 return 1;
1219 }
1220 else
1221 {
1222 struct regcache *regcache;
f5656ead 1223 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch ());
cc5f0d61
UW		 1224 cache->regcache = regcache_dup (regcache);
1225 *this_prologue_cache = cache;
1226 return 1;
1227 }
1228 }
1229
1230 return 0;
1231}
1232
1233static void
1234spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1235{
1236 struct spu2ppu_cache *cache = this_cache;
1237 regcache_xfree (cache->regcache);
1238}
1239
1240static const struct frame_unwind spu2ppu_unwind = {
1241 ARCH_FRAME,
8fbca658 1242 default_frame_unwind_stop_reason,
cc5f0d61
UW		 1243 spu2ppu_this_id,
1244 spu2ppu_prev_register,
1245 NULL,
1246 spu2ppu_sniffer,
1247 spu2ppu_dealloc_cache,
1248 spu2ppu_prev_arch,
1249};
1250
1251
771b4502
UW		 1252/* Function calling convention. */
1253
7b3dc0b7
UW		 1254static CORE_ADDR
1255spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1256{
1257 return sp & ~15;
1258}
1259
87805e63
UW		 1260static CORE_ADDR
1261spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1262 struct value **args, int nargs, struct type *value_type,
1263 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1264 struct regcache *regcache)
1265{
1266 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1267 sp = (sp - 4) & ~15;
1268 /* Store the address of that breakpoint */
1269 *bp_addr = sp;
1270 /* The call starts at the callee's entry point. */
1271 *real_pc = funaddr;
1272
1273 return sp;
1274}
1275
771b4502
UW		 1276static int
1277spu_scalar_value_p (struct type *type)
1278{
1279 switch (TYPE_CODE (type))
1280 {
1281 case TYPE_CODE_INT:
1282 case TYPE_CODE_ENUM:
1283 case TYPE_CODE_RANGE:
1284 case TYPE_CODE_CHAR:
1285 case TYPE_CODE_BOOL:
1286 case TYPE_CODE_PTR:
1287 case TYPE_CODE_REF:
1288 return TYPE_LENGTH (type) <= 16;
1289
1290 default:
1291 return 0;
1292 }
1293}
1294
1295static void
1296spu_value_to_regcache (struct regcache *regcache, int regnum,
1297 struct type *type, const gdb_byte *in)
1298{
1299 int len = TYPE_LENGTH (type);
1300
1301 if (spu_scalar_value_p (type))
1302 {
1303 int preferred_slot = len < 4 ? 4 - len : 0;
1304 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1305 }
1306 else
1307 {
1308 while (len >= 16)
1309 {
1310 regcache_cooked_write (regcache, regnum++, in);
1311 in += 16;
1312 len -= 16;
1313 }
1314
1315 if (len > 0)
1316 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1317 }
1318}
1319
1320static void
1321spu_regcache_to_value (struct regcache *regcache, int regnum,
1322 struct type *type, gdb_byte *out)
1323{
1324 int len = TYPE_LENGTH (type);
1325
1326 if (spu_scalar_value_p (type))
1327 {
1328 int preferred_slot = len < 4 ? 4 - len : 0;
1329 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1330 }
1331 else
1332 {
1333 while (len >= 16)
1334 {
1335 regcache_cooked_read (regcache, regnum++, out);
1336 out += 16;
1337 len -= 16;
1338 }
1339
1340 if (len > 0)
1341 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1342 }
1343}
1344
1345static CORE_ADDR
1346spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1347 struct regcache *regcache, CORE_ADDR bp_addr,
1348 int nargs, struct value **args, CORE_ADDR sp,
1349 int struct_return, CORE_ADDR struct_addr)
1350{
e17a4113 1351 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1352 CORE_ADDR sp_delta;
771b4502
UW		 1353 int i;
1354 int regnum = SPU_ARG1_REGNUM;
1355 int stack_arg = -1;
1356 gdb_byte buf[16];
1357
1358 /* Set the return address. */
1359 memset (buf, 0, sizeof buf);
85e747d2 1360 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1361 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1362
1363 /* If STRUCT_RETURN is true, then the struct return address (in
1364 STRUCT_ADDR) will consume the first argument-passing register.
1365 Both adjust the register count and store that value. */
1366 if (struct_return)
1367 {
1368 memset (buf, 0, sizeof buf);
85e747d2 1369 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1370 regcache_cooked_write (regcache, regnum++, buf);
1371 }
1372
1373 /* Fill in argument registers. */
1374 for (i = 0; i < nargs; i++)
1375 {
1376 struct value *arg = args[i];
1377 struct type *type = check_typedef (value_type (arg));
1378 const gdb_byte *contents = value_contents (arg);
354ecfd5 1379 int n_regs = align_up (TYPE_LENGTH (type), 16) / 16;
771b4502
UW		 1380
1381 /* If the argument doesn't wholly fit into registers, it and
1382 all subsequent arguments go to the stack. */
1383 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1384 {
1385 stack_arg = i;
1386 break;
1387 }
1388
1389 spu_value_to_regcache (regcache, regnum, type, contents);
1390 regnum += n_regs;
1391 }
1392
1393 /* Overflow arguments go to the stack. */
1394 if (stack_arg != -1)
1395 {
1396 CORE_ADDR ap;
1397
1398 /* Allocate all required stack size. */
1399 for (i = stack_arg; i < nargs; i++)
1400 {
1401 struct type *type = check_typedef (value_type (args[i]));
1402 sp -= align_up (TYPE_LENGTH (type), 16);
1403 }
1404
1405 /* Fill in stack arguments. */
1406 ap = sp;
1407 for (i = stack_arg; i < nargs; i++)
1408 {
1409 struct value *arg = args[i];
1410 struct type *type = check_typedef (value_type (arg));
1411 int len = TYPE_LENGTH (type);
1412 int preferred_slot;
1413
1414 if (spu_scalar_value_p (type))
1415 preferred_slot = len < 4 ? 4 - len : 0;
1416 else
1417 preferred_slot = 0;
1418
1419 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1420 ap += align_up (TYPE_LENGTH (type), 16);
1421 }
1422 }
1423
1424 /* Allocate stack frame header. */
1425 sp -= 32;
1426
ee82e879
UW		 1427 /* Store stack back chain. */
1428 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1429 target_write_memory (sp, buf, 16);
1430
9ff3afda 1431 /* Finally, update all slots of the SP register. */
e17a4113 1432 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1433 for (i = 0; i < 4; i++)
1434 {
e17a4113
UW		 1435 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1436 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1437 }
1438 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1439
1440 return sp;
1441}
1442
1443static struct frame_id
8d998b8f 1444spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1445{
85e747d2 1446 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1447 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1448 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1449 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1450}
1451
1452/* Function return value access. */
1453
1454static enum return_value_convention
6a3a010b 1455spu_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101
CV		 1456 struct type *type, struct regcache *regcache,
1457 gdb_byte *out, const gdb_byte *in)
771b4502 1458{
6a3a010b 1459 struct type *func_type = function ? value_type (function) : NULL;
771b4502 1460 enum return_value_convention rvc;
54fcddd0
UW		 1461 int opencl_vector = 0;
1462
598cfb71
UW		 1463 if (func_type)
1464 {
1465 func_type = check_typedef (func_type);
1466
1467 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1468 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1469
1470 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1471 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1472 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1473 && TYPE_VECTOR (type))
1474 opencl_vector = 1;
1475 }
771b4502
UW		 1476
1477 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1478 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1479 else
1480 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1481
1482 if (in)
1483 {
1484 switch (rvc)
1485 {
1486 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1487 if (opencl_vector && TYPE_LENGTH (type) == 2)
1488 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1489 else
1490 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
771b4502
UW		 1491 break;
1492
1493 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1494 error (_("Cannot set function return value."));
771b4502
UW		 1495 break;
1496 }
1497 }
1498 else if (out)
1499 {
1500 switch (rvc)
1501 {
1502 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1503 if (opencl_vector && TYPE_LENGTH (type) == 2)
1504 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1505 else
1506 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
771b4502
UW		 1507 break;
1508
1509 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1510 error (_("Function return value unknown."));
771b4502
UW		 1511 break;
1512 }
1513 }
1514
1515 return rvc;
1516}
1517
1518
1519/* Breakpoints. */
1520
1521static const gdb_byte *
c378eb4e
MS		 1522spu_breakpoint_from_pc (struct gdbarch *gdbarch,
1523 CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1524{
1525 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1526
1527 *lenptr = sizeof breakpoint;
1528 return breakpoint;
1529}
1530
d03285ec
UW		 1531static int
1532spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1533 struct bp_target_info *bp_tgt)
1534{
1535 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1536 that in a combined application, we have some breakpoints inserted in SPU
1537 code, and now the application forks (on the PPU side). GDB common code
1538 will assume that the fork system call copied all breakpoints into the new
1539 process' address space, and that all those copies now need to be removed
1540 (see breakpoint.c:detach_breakpoints).
1541
1542 While this is certainly true for PPU side breakpoints, it is not true
1543 for SPU side breakpoints. fork will clone the SPU context file
1544 descriptors, so that all the existing SPU contexts are in accessible
1545 in the new process. However, the contents of the SPU contexts themselves
1546 are *not* cloned. Therefore the effect of detach_breakpoints is to
1547 remove SPU breakpoints from the *original* SPU context's local store
1548 -- this is not the correct behaviour.
1549
1550 The workaround is to check whether the PID we are asked to remove this
1551 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1552 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1553 true in the context of detach_breakpoints. If so, we simply do nothing.
1554 [ Note that for the fork child process, it does not matter if breakpoints
1555 remain inserted, because those SPU contexts are not runnable anyway --
1556 the Linux kernel allows only the original process to invoke spu_run. */
1557
1558 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1559 return 0;
1560
1561 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1562}
1563
771b4502
UW		 1564
1565/* Software single-stepping support. */
1566
63807e1d 1567static int
0b1b3e42 1568spu_software_single_step (struct frame_info *frame)
771b4502 1569{
a6d9a66e 1570 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1571 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1572 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1573 CORE_ADDR pc, next_pc;
1574 unsigned int insn;
1575 int offset, reg;
1576 gdb_byte buf[4];
13def385 1577 ULONGEST lslr;
771b4502 1578
0b1b3e42 1579 pc = get_frame_pc (frame);
771b4502 1580
e0cd558a
UW		 1581 if (target_read_memory (pc, buf, 4))
1582 return 1;
e17a4113 1583 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1584
13def385
UW		 1585 /* Get local store limit. */
1586 lslr = get_frame_register_unsigned (frame, SPU_LSLR_REGNUM);
1587 if (!lslr)
1588 lslr = (ULONGEST) -1;
1589
e0cd558a
UW		 1590 /* Next sequential instruction is at PC + 4, except if the current
1591 instruction is a PPE-assisted call, in which case it is at PC + 8.
1592 Wrap around LS limit to be on the safe side. */
1593 if ((insn & 0xffffff00) == 0x00002100)
13def385 1594 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
e0cd558a 1595 else
13def385 1596 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
771b4502 1597
6c95b8df
PA		 1598 insert_single_step_breakpoint (gdbarch,
1599 aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1600
e0cd558a
UW		 1601 if (is_branch (insn, &offset, &reg))
1602 {
1603 CORE_ADDR target = offset;
771b4502 1604
e0cd558a 1605 if (reg == SPU_PC_REGNUM)
85e747d2 1606 target += SPUADDR_ADDR (pc);
e0cd558a
UW		 1607 else if (reg != -1)
1608 {
8dccd430
PA		 1609 int optim, unavail;
1610
1611 if (get_frame_register_bytes (frame, reg, 0, 4, buf,
1612 &optim, &unavail))
1613 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
1614 else
1615 {
1616 if (optim)
710409a2
PA		 1617 throw_error (OPTIMIZED_OUT_ERROR,
1618 _("Could not determine address of "
1619 "single-step breakpoint."));
8dccd430
PA		 1620 if (unavail)
1621 throw_error (NOT_AVAILABLE_ERROR,
1622 _("Could not determine address of "
1623 "single-step breakpoint."));
1624 }
771b4502 1625 }
e0cd558a 1626
13def385 1627 target = target & lslr;
e0cd558a 1628 if (target != next_pc)
6c95b8df 1629 insert_single_step_breakpoint (gdbarch, aspace,
85e747d2 1630 SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1631 }
e6590a1b
UW		 1632
1633 return 1;
771b4502
UW		 1634}
1635
6e3f70d7
UW		 1636
1637/* Longjmp support. */
1638
1639static int
1640spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1641{
e17a4113 1642 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1643 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1644 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1645 gdb_byte buf[4];
1646 CORE_ADDR jb_addr;
8dccd430 1647 int optim, unavail;
6e3f70d7
UW		 1648
1649 /* Jump buffer is pointed to by the argument register $r3. */
8dccd430
PA		 1650 if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1651 &optim, &unavail))
1652 return 0;
1653
e17a4113 1654 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1655 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1656 return 0;
1657
e17a4113 1658 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1659 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1660 return 1;
1661}
1662
1663
85e747d2
UW		 1664/* Disassembler. */
1665
1666struct spu_dis_asm_data
1667{
1668 struct gdbarch *gdbarch;
1669 int id;
1670};
1671
1672static void
1673spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1674{
1675 struct spu_dis_asm_data *data = info->application_data;
1676 print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1677}
1678
1679static int
1680gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1681{
c378eb4e
MS		 1682 /* The opcodes disassembler does 18-bit address arithmetic. Make
1683 sure the SPU ID encoded in the high bits is added back when we
1684 call print_address. */
85e747d2
UW		 1685 struct disassemble_info spu_info = *info;
1686 struct spu_dis_asm_data data;
1687 data.gdbarch = info->application_data;
1688 data.id = SPUADDR_SPU (memaddr);
1689
1690 spu_info.application_data = &data;
1691 spu_info.print_address_func = spu_dis_asm_print_address;
1692 return print_insn_spu (memaddr, &spu_info);
1693}
1694
1695
dcf52cd8
UW		 1696/* Target overlays for the SPU overlay manager.
1697
1698 See the documentation of simple_overlay_update for how the
1699 interface is supposed to work.
1700
1701 Data structures used by the overlay manager:
1702
1703 struct ovly_table
1704 {
1705 u32 vma;
1706 u32 size;
1707 u32 pos;
1708 u32 buf;
1709 } _ovly_table[]; -- one entry per overlay section
1710
1711 struct ovly_buf_table
1712 {
1713 u32 mapped;
1714 } _ovly_buf_table[]; -- one entry per overlay buffer
1715
1716 _ovly_table should never change.
1717
c378eb4e
MS		 1718 Both tables are aligned to a 16-byte boundary, the symbols
1719 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1720 size set to the size of the respective array. buf in _ovly_table is
1721 an index into _ovly_buf_table.
dcf52cd8 1722
c378eb4e 1723 mapped is an index into _ovly_table. Both the mapped and buf indices start
dcf52cd8
UW		 1724 from one to reference the first entry in their respective tables. */
1725
1726/* Using the per-objfile private data mechanism, we store for each
1727 objfile an array of "struct spu_overlay_table" structures, one
1728 for each obj_section of the objfile. This structure holds two
1729 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1730 is *not* an overlay section. If it is non-zero, it represents
1731 a target address. The overlay section is mapped iff the target
1732 integer at this location equals MAPPED_VAL. */
1733
1734static const struct objfile_data *spu_overlay_data;
1735
1736struct spu_overlay_table
1737 {
1738 CORE_ADDR mapped_ptr;
1739 CORE_ADDR mapped_val;
1740 };
1741
1742/* Retrieve the overlay table for OBJFILE. If not already cached, read
1743 the _ovly_table data structure from the target and initialize the
1744 spu_overlay_table data structure from it. */
1745static struct spu_overlay_table *
1746spu_get_overlay_table (struct objfile *objfile)
1747{
e17a4113
UW		 1748 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1749 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8
UW		 1750 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1751 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1752 unsigned ovly_table_size, ovly_buf_table_size;
1753 struct spu_overlay_table *tbl;
1754 struct obj_section *osect;
948f8e3d 1755 gdb_byte *ovly_table;
dcf52cd8
UW		 1756 int i;
1757
1758 tbl = objfile_data (objfile, spu_overlay_data);
1759 if (tbl)
1760 return tbl;
1761
1762 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1763 if (!ovly_table_msym)
1764 return NULL;
1765
c378eb4e
MS		 1766 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1767 NULL, objfile);
dcf52cd8
UW		 1768 if (!ovly_buf_table_msym)
1769 return NULL;
1770
1771 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1772 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1773
1774 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1775 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1776
1777 ovly_table = xmalloc (ovly_table_size);
1778 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1779
1780 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1781 objfile->sections_end - objfile->sections,
1782 struct spu_overlay_table);
1783
1784 for (i = 0; i < ovly_table_size / 16; i++)
1785 {
e17a4113
UW		 1786 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1787 4, byte_order);
1788 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1789 4, byte_order);
1790 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1791 4, byte_order);
1792 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1793 4, byte_order);
dcf52cd8
UW		 1794
1795 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1796 continue;
1797
1798 ALL_OBJFILE_OSECTIONS (objfile, osect)
1799 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1800 && pos == osect->the_bfd_section->filepos)
1801 {
1802 int ndx = osect - objfile->sections;
1803 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1804 tbl[ndx].mapped_val = i + 1;
1805 break;
1806 }
1807 }
1808
1809 xfree (ovly_table);
1810 set_objfile_data (objfile, spu_overlay_data, tbl);
1811 return tbl;
1812}
1813
1814/* Read _ovly_buf_table entry from the target to dermine whether
1815 OSECT is currently mapped, and update the mapped state. */
1816static void
1817spu_overlay_update_osect (struct obj_section *osect)
1818{
e17a4113
UW		 1819 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1820 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1821 struct spu_overlay_table *ovly_table;
85e747d2 1822 CORE_ADDR id, val;
dcf52cd8
UW		 1823
1824 ovly_table = spu_get_overlay_table (osect->objfile);
1825 if (!ovly_table)
1826 return;
1827
1828 ovly_table += osect - osect->objfile->sections;
1829 if (ovly_table->mapped_ptr == 0)
1830 return;
1831
85e747d2
UW		 1832 id = SPUADDR_SPU (obj_section_addr (osect));
1833 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1834 4, byte_order);
dcf52cd8
UW		 1835 osect->ovly_mapped = (val == ovly_table->mapped_val);
1836}
1837
1838/* If OSECT is NULL, then update all sections' mapped state.
1839 If OSECT is non-NULL, then update only OSECT's mapped state. */
1840static void
1841spu_overlay_update (struct obj_section *osect)
1842{
1843 /* Just one section. */
1844 if (osect)
1845 spu_overlay_update_osect (osect);
1846
1847 /* All sections. */
1848 else
1849 {
1850 struct objfile *objfile;
1851
1852 ALL_OBJSECTIONS (objfile, osect)
714835d5 1853 if (section_is_overlay (osect))
dcf52cd8
UW		 1854 spu_overlay_update_osect (osect);
1855 }
1856}
1857
1858/* Whenever a new objfile is loaded, read the target's _ovly_table.
1859 If there is one, go through all sections and make sure for non-
1860 overlay sections LMA equals VMA, while for overlay sections LMA
d2ed6730 1861 is larger than SPU_OVERLAY_LMA. */
dcf52cd8
UW		 1862static void
1863spu_overlay_new_objfile (struct objfile *objfile)
1864{
1865 struct spu_overlay_table *ovly_table;
1866 struct obj_section *osect;
1867
1868 /* If we've already touched this file, do nothing. */
1869 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1870 return;
1871
0391f248
UW		 1872 /* Consider only SPU objfiles. */
1873 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1874 return;
1875
dcf52cd8
UW		 1876 /* Check if this objfile has overlays. */
1877 ovly_table = spu_get_overlay_table (objfile);
1878 if (!ovly_table)
1879 return;
1880
1881 /* Now go and fiddle with all the LMAs. */
1882 ALL_OBJFILE_OSECTIONS (objfile, osect)
1883 {
1884 bfd *obfd = objfile->obfd;
1885 asection *bsect = osect->the_bfd_section;
1886 int ndx = osect - objfile->sections;
1887
1888 if (ovly_table[ndx].mapped_ptr == 0)
1889 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1890 else
d2ed6730 1891 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
dcf52cd8
UW		 1892 }
1893}
1894
771b4502 1895
3285f3fe
UW		 1896/* Insert temporary breakpoint on "main" function of newly loaded
1897 SPE context OBJFILE. */
1898static void
1899spu_catch_start (struct objfile *objfile)
1900{
1901 struct minimal_symbol *minsym;
1902 struct symtab *symtab;
1903 CORE_ADDR pc;
1904 char buf[32];
1905
1906 /* Do this only if requested by "set spu stop-on-load on". */
1907 if (!spu_stop_on_load_p)
1908 return;
1909
1910 /* Consider only SPU objfiles. */
1911 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1912 return;
1913
1914 /* The main objfile is handled differently. */
1915 if (objfile == symfile_objfile)
1916 return;
1917
1918 /* There can be multiple symbols named "main". Search for the
1919 "main" in *this* objfile. */
1920 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1921 if (!minsym)
1922 return;
1923
1924 /* If we have debugging information, try to use it -- this
1925 will allow us to properly skip the prologue. */
1926 pc = SYMBOL_VALUE_ADDRESS (minsym);
e27d198c 1927 symtab = find_pc_sect_symtab (pc, SYMBOL_OBJ_SECTION (objfile, minsym));
3285f3fe
UW		 1928 if (symtab != NULL)
1929 {
1930 struct blockvector *bv = BLOCKVECTOR (symtab);
1931 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1932 struct symbol *sym;
1933 struct symtab_and_line sal;
1934
94af9270 1935 sym = lookup_block_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1936 if (sym)
1937 {
1938 fixup_symbol_section (sym, objfile);
1939 sal = find_function_start_sal (sym, 1);
1940 pc = sal.pc;
1941 }
1942 }
1943
1944 /* Use a numerical address for the set_breakpoint command to avoid having
1945 the breakpoint re-set incorrectly. */
1946 xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
d8c09fb5
JK		 1947 create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
1948 NULL /* cond_string */, -1 /* thread */,
6a609e58 1949 NULL /* extra_string */,
d8c09fb5 1950 0 /* parse_condition_and_thread */, 1 /* tempflag */,
bddaafad 1951 bp_breakpoint /* type_wanted */,
d8c09fb5
JK		 1952 0 /* ignore_count */,
1953 AUTO_BOOLEAN_FALSE /* pending_break_support */,
931bb47f 1954 &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
44f238bb 1955 1 /* enabled */, 0 /* internal */, 0);
3285f3fe
UW		 1956}
1957
1958
ff1a52c6
UW		 1959/* Look up OBJFILE loaded into FRAME's SPU context. */
1960static struct objfile *
1961spu_objfile_from_frame (struct frame_info *frame)
1962{
1963 struct gdbarch *gdbarch = get_frame_arch (frame);
1964 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1965 struct objfile *obj;
1966
1967 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
1968 return NULL;
1969
1970 ALL_OBJFILES (obj)
1971 {
1972 if (obj->sections != obj->sections_end
1973 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
1974 return obj;
1975 }
1976
1977 return NULL;
1978}
1979
1980/* Flush cache for ea pointer access if available. */
1981static void
1982flush_ea_cache (void)
1983{
1984 struct minimal_symbol *msymbol;
1985 struct objfile *obj;
1986
1987 if (!has_stack_frames ())
1988 return;
1989
1990 obj = spu_objfile_from_frame (get_current_frame ());
1991 if (obj == NULL)
1992 return;
1993
1994 /* Lookup inferior function __cache_flush. */
1995 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
1996 if (msymbol != NULL)
1997 {
1998 struct type *type;
1999 CORE_ADDR addr;
2000
2001 type = objfile_type (obj)->builtin_void;
2002 type = lookup_function_type (type);
2003 type = lookup_pointer_type (type);
2004 addr = SYMBOL_VALUE_ADDRESS (msymbol);
2005
2006 call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
2007 }
2008}
2009
2010/* This handler is called when the inferior has stopped. If it is stopped in
2011 SPU architecture then flush the ea cache if used. */
2012static void
2013spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2014{
2015 if (!spu_auto_flush_cache_p)
2016 return;
2017
2018 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2019 re-entering this function when __cache_flush stops. */
2020 spu_auto_flush_cache_p = 0;
2021 flush_ea_cache ();
2022 spu_auto_flush_cache_p = 1;
2023}
2024
2025
23d964e7
UW		 2026/* "info spu" commands. */
2027
2028static void
2029info_spu_event_command (char *args, int from_tty)
2030{
2031 struct frame_info *frame = get_selected_frame (NULL);
2032 ULONGEST event_status = 0;
2033 ULONGEST event_mask = 0;
2034 struct cleanup *chain;
2035 gdb_byte buf[100];
2036 char annex[32];
2037 LONGEST len;
22e048c9 2038 int id;
23d964e7 2039
0391f248
UW		 2040 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2041 error (_("\"info spu\" is only supported on the SPU architecture."));
2042
23d964e7
UW		 2043 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2044
2045 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2046 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2047 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2048 if (len <= 0)
2049 error (_("Could not read event_status."));
9971ac47 2050 buf[len] = '\0';
001f13d8 2051 event_status = strtoulst ((char *) buf, NULL, 16);
23d964e7
UW		 2052
2053 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2054 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2055 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2056 if (len <= 0)
2057 error (_("Could not read event_mask."));
9971ac47 2058 buf[len] = '\0';
001f13d8 2059 event_mask = strtoulst ((char *) buf, NULL, 16);
23d964e7 2060
31a0ae49 2061 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoEvent");
23d964e7 2062
31a0ae49 2063 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2064 {
31a0ae49 2065 ui_out_field_fmt (current_uiout, "event_status",
23d964e7 2066 "0x%s", phex_nz (event_status, 4));
31a0ae49 2067 ui_out_field_fmt (current_uiout, "event_mask",
23d964e7
UW		 2068 "0x%s", phex_nz (event_mask, 4));
2069 }
2070 else
2071 {
2072 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2073 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2074 }
2075
2076 do_cleanups (chain);
2077}
2078
2079static void
2080info_spu_signal_command (char *args, int from_tty)
2081{
2082 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2083 struct gdbarch *gdbarch = get_frame_arch (frame);
2084 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2085 ULONGEST signal1 = 0;
2086 ULONGEST signal1_type = 0;
2087 int signal1_pending = 0;
2088 ULONGEST signal2 = 0;
2089 ULONGEST signal2_type = 0;
2090 int signal2_pending = 0;
2091 struct cleanup *chain;
2092 char annex[32];
2093 gdb_byte buf[100];
2094 LONGEST len;
22e048c9 2095 int id;
23d964e7 2096
e17a4113 2097 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2098 error (_("\"info spu\" is only supported on the SPU architecture."));
2099
23d964e7
UW		 2100 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2101
2102 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2103 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2104 if (len < 0)
2105 error (_("Could not read signal1."));
2106 else if (len == 4)
2107 {
e17a4113 2108 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2109 signal1_pending = 1;
2110 }
2111
2112 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2113 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2114 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2115 if (len <= 0)
2116 error (_("Could not read signal1_type."));
9971ac47 2117 buf[len] = '\0';
001f13d8 2118 signal1_type = strtoulst ((char *) buf, NULL, 16);
23d964e7
UW		 2119
2120 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2121 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2122 if (len < 0)
2123 error (_("Could not read signal2."));
2124 else if (len == 4)
2125 {
e17a4113 2126 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2127 signal2_pending = 1;
2128 }
2129
2130 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2131 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2132 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2133 if (len <= 0)
2134 error (_("Could not read signal2_type."));
9971ac47 2135 buf[len] = '\0';
001f13d8 2136 signal2_type = strtoulst ((char *) buf, NULL, 16);
23d964e7 2137
31a0ae49 2138 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoSignal");
23d964e7 2139
31a0ae49 2140 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2141 {
31a0ae49
JK		 2142 ui_out_field_int (current_uiout, "signal1_pending", signal1_pending);
2143 ui_out_field_fmt (current_uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2144 ui_out_field_int (current_uiout, "signal1_type", signal1_type);
2145 ui_out_field_int (current_uiout, "signal2_pending", signal2_pending);
2146 ui_out_field_fmt (current_uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2147 ui_out_field_int (current_uiout, "signal2_type", signal2_type);
23d964e7
UW		 2148 }
2149 else
2150 {
2151 if (signal1_pending)
2152 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2153 else
2154 printf_filtered (_("Signal 1 not pending "));
2155
2156 if (signal1_type)
23d964e7 2157 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2158 else
2159 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2160
2161 if (signal2_pending)
2162 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2163 else
2164 printf_filtered (_("Signal 2 not pending "));
2165
2166 if (signal2_type)
23d964e7 2167 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2168 else
2169 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2170 }
2171
2172 do_cleanups (chain);
2173}
2174
2175static void
e17a4113 2176info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2177 const char *field, const char *msg)
2178{
2179 struct cleanup *chain;
2180 int i;
2181
2182 if (nr <= 0)
2183 return;
2184
31a0ae49 2185 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 1, nr, "mbox");
23d964e7 2186
31a0ae49
JK		 2187 ui_out_table_header (current_uiout, 32, ui_left, field, msg);
2188 ui_out_table_body (current_uiout);
23d964e7
UW		 2189
2190 for (i = 0; i < nr; i++)
2191 {
2192 struct cleanup *val_chain;
2193 ULONGEST val;
31a0ae49 2194 val_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "mbox");
e17a4113 2195 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
31a0ae49 2196 ui_out_field_fmt (current_uiout, field, "0x%s", phex (val, 4));
23d964e7
UW		 2197 do_cleanups (val_chain);
2198
31a0ae49 2199 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2200 printf_filtered ("\n");
2201 }
2202
2203 do_cleanups (chain);
2204}
2205
2206static void
2207info_spu_mailbox_command (char *args, int from_tty)
2208{
2209 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2210 struct gdbarch *gdbarch = get_frame_arch (frame);
2211 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2212 struct cleanup *chain;
2213 char annex[32];
2214 gdb_byte buf[1024];
2215 LONGEST len;
22e048c9 2216 int id;
23d964e7 2217
e17a4113 2218 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2219 error (_("\"info spu\" is only supported on the SPU architecture."));
2220
23d964e7
UW		 2221 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2222
31a0ae49 2223 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoMailbox");
23d964e7
UW		 2224
2225 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2226 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2227 buf, 0, sizeof buf);
2228 if (len < 0)
2229 error (_("Could not read mbox_info."));
2230
e17a4113
UW		 2231 info_spu_mailbox_list (buf, len / 4, byte_order,
2232 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2233
2234 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2235 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2236 buf, 0, sizeof buf);
2237 if (len < 0)
2238 error (_("Could not read ibox_info."));
2239
e17a4113
UW		 2240 info_spu_mailbox_list (buf, len / 4, byte_order,
2241 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2242
2243 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2244 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2245 buf, 0, sizeof buf);
2246 if (len < 0)
2247 error (_("Could not read wbox_info."));
2248
e17a4113
UW		 2249 info_spu_mailbox_list (buf, len / 4, byte_order,
2250 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2251
2252 do_cleanups (chain);
2253}
2254
2255static ULONGEST
2256spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2257{
2258 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2259 return (word >> (63 - last)) & mask;
2260}
2261
2262static void
e17a4113 2263info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7
UW		 2264{
2265 static char *spu_mfc_opcode[256] =
2266 {
2267 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2268 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2269 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2270 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2271 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2272 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2273 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2274 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2275 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2276 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2277 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2278 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2279 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2280 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2281 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2282 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2283 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2284 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2285 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2286 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2287 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2288 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2289 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2290 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2291 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2292 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2293 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2294 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2295 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2296 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2297 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2298 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2299 };
2300
12ab8a60
UW		 2301 int *seq = alloca (nr * sizeof (int));
2302 int done = 0;
23d964e7 2303 struct cleanup *chain;
12ab8a60
UW		 2304 int i, j;
2305
2306
2307 /* Determine sequence in which to display (valid) entries. */
2308 for (i = 0; i < nr; i++)
2309 {
2310 /* Search for the first valid entry all of whose
2311 dependencies are met. */
2312 for (j = 0; j < nr; j++)
2313 {
2314 ULONGEST mfc_cq_dw3;
2315 ULONGEST dependencies;
2316
2317 if (done & (1 << (nr - 1 - j)))
2318 continue;
2319
e17a4113
UW		 2320 mfc_cq_dw3
2321 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2322 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2323 continue;
2324
2325 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2326 if ((dependencies & done) != dependencies)
2327 continue;
2328
2329 seq[i] = j;
2330 done |= 1 << (nr - 1 - j);
2331 break;
2332 }
2333
2334 if (j == nr)
2335 break;
2336 }
2337
2338 nr = i;
2339
23d964e7 2340
31a0ae49
JK		 2341 chain = make_cleanup_ui_out_table_begin_end (current_uiout, 10, nr,
2342 "dma_cmd");
23d964e7 2343
31a0ae49
JK		 2344 ui_out_table_header (current_uiout, 7, ui_left, "opcode", "Opcode");
2345 ui_out_table_header (current_uiout, 3, ui_left, "tag", "Tag");
2346 ui_out_table_header (current_uiout, 3, ui_left, "tid", "TId");
2347 ui_out_table_header (current_uiout, 3, ui_left, "rid", "RId");
2348 ui_out_table_header (current_uiout, 18, ui_left, "ea", "EA");
2349 ui_out_table_header (current_uiout, 7, ui_left, "lsa", "LSA");
2350 ui_out_table_header (current_uiout, 7, ui_left, "size", "Size");
2351 ui_out_table_header (current_uiout, 7, ui_left, "lstaddr", "LstAddr");
2352 ui_out_table_header (current_uiout, 7, ui_left, "lstsize", "LstSize");
2353 ui_out_table_header (current_uiout, 1, ui_left, "error_p", "E");
23d964e7 2354
31a0ae49 2355 ui_out_table_body (current_uiout);
23d964e7
UW		 2356
2357 for (i = 0; i < nr; i++)
2358 {
2359 struct cleanup *cmd_chain;
2360 ULONGEST mfc_cq_dw0;
2361 ULONGEST mfc_cq_dw1;
2362 ULONGEST mfc_cq_dw2;
23d964e7 2363 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
22e048c9 2364 int list_lsa, list_size, mfc_lsa, mfc_size;
23d964e7
UW		 2365 ULONGEST mfc_ea;
2366 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2367
2368 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2369 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2370
e17a4113
UW		 2371 mfc_cq_dw0
2372 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2373 mfc_cq_dw1
2374 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2375 mfc_cq_dw2
2376 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2377
2378 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2379 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2380 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2381 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2382 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2383 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2384 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2385
2386 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2387 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2388
2389 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2390 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2391 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2392 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2393 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2394 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2395
31a0ae49 2396 cmd_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "cmd");
23d964e7
UW		 2397
2398 if (spu_mfc_opcode[mfc_cmd_opcode])
31a0ae49 2399 ui_out_field_string (current_uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
23d964e7 2400 else
31a0ae49 2401 ui_out_field_int (current_uiout, "opcode", mfc_cmd_opcode);
23d964e7 2402
31a0ae49
JK		 2403 ui_out_field_int (current_uiout, "tag", mfc_cmd_tag);
2404 ui_out_field_int (current_uiout, "tid", tclass_id);
2405 ui_out_field_int (current_uiout, "rid", rclass_id);
23d964e7
UW		 2406
2407 if (ea_valid_p)
31a0ae49 2408 ui_out_field_fmt (current_uiout, "ea", "0x%s", phex (mfc_ea, 8));
23d964e7 2409 else
31a0ae49 2410 ui_out_field_skip (current_uiout, "ea");
23d964e7 2411
31a0ae49 2412 ui_out_field_fmt (current_uiout, "lsa", "0x%05x", mfc_lsa << 4);
23d964e7 2413 if (qw_valid_p)
31a0ae49 2414 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size << 4);
23d964e7 2415 else
31a0ae49 2416 ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size);
23d964e7
UW		 2417
2418 if (list_valid_p)
2419 {
31a0ae49
JK		 2420 ui_out_field_fmt (current_uiout, "lstaddr", "0x%05x", list_lsa << 3);
2421 ui_out_field_fmt (current_uiout, "lstsize", "0x%05x", list_size << 3);
23d964e7
UW		 2422 }
2423 else
2424 {
31a0ae49
JK		 2425 ui_out_field_skip (current_uiout, "lstaddr");
2426 ui_out_field_skip (current_uiout, "lstsize");
23d964e7
UW		 2427 }
2428
2429 if (cmd_error_p)
31a0ae49 2430 ui_out_field_string (current_uiout, "error_p", "*");
23d964e7 2431 else
31a0ae49 2432 ui_out_field_skip (current_uiout, "error_p");
23d964e7
UW		 2433
2434 do_cleanups (cmd_chain);
2435
31a0ae49 2436 if (!ui_out_is_mi_like_p (current_uiout))
23d964e7
UW		 2437 printf_filtered ("\n");
2438 }
2439
2440 do_cleanups (chain);
2441}
2442
2443static void
2444info_spu_dma_command (char *args, int from_tty)
2445{
2446 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2447 struct gdbarch *gdbarch = get_frame_arch (frame);
2448 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2449 ULONGEST dma_info_type;
2450 ULONGEST dma_info_mask;
2451 ULONGEST dma_info_status;
2452 ULONGEST dma_info_stall_and_notify;
2453 ULONGEST dma_info_atomic_command_status;
2454 struct cleanup *chain;
2455 char annex[32];
2456 gdb_byte buf[1024];
2457 LONGEST len;
22e048c9 2458 int id;
23d964e7 2459
0391f248
UW		 2460 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2461 error (_("\"info spu\" is only supported on the SPU architecture."));
2462
23d964e7
UW		 2463 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2464
2465 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2466 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2467 buf, 0, 40 + 16 * 32);
2468 if (len <= 0)
2469 error (_("Could not read dma_info."));
2470
e17a4113
UW		 2471 dma_info_type
2472 = extract_unsigned_integer (buf, 8, byte_order);
2473 dma_info_mask
2474 = extract_unsigned_integer (buf + 8, 8, byte_order);
2475 dma_info_status
2476 = extract_unsigned_integer (buf + 16, 8, byte_order);
2477 dma_info_stall_and_notify
2478 = extract_unsigned_integer (buf + 24, 8, byte_order);
2479 dma_info_atomic_command_status
2480 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7 2481
31a0ae49 2482 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoDMA");
23d964e7 2483
31a0ae49 2484 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2485 {
31a0ae49 2486 ui_out_field_fmt (current_uiout, "dma_info_type", "0x%s",
23d964e7 2487 phex_nz (dma_info_type, 4));
31a0ae49 2488 ui_out_field_fmt (current_uiout, "dma_info_mask", "0x%s",
23d964e7 2489 phex_nz (dma_info_mask, 4));
31a0ae49 2490 ui_out_field_fmt (current_uiout, "dma_info_status", "0x%s",
23d964e7 2491 phex_nz (dma_info_status, 4));
31a0ae49 2492 ui_out_field_fmt (current_uiout, "dma_info_stall_and_notify", "0x%s",
23d964e7 2493 phex_nz (dma_info_stall_and_notify, 4));
31a0ae49 2494 ui_out_field_fmt (current_uiout, "dma_info_atomic_command_status", "0x%s",
23d964e7
UW		 2495 phex_nz (dma_info_atomic_command_status, 4));
2496 }
2497 else
2498 {
8fbde58b 2499 const char *query_msg = _("no query pending");
23d964e7 2500
8fbde58b
UW		 2501 if (dma_info_type & 4)
2502 switch (dma_info_type & 3)
2503 {
2504 case 1: query_msg = _("'any' query pending"); break;
2505 case 2: query_msg = _("'all' query pending"); break;
2506 default: query_msg = _("undefined query type"); break;
2507 }
23d964e7
UW		 2508
2509 printf_filtered (_("Tag-Group Status 0x%s\n"),
2510 phex (dma_info_status, 4));
2511 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2512 phex (dma_info_mask, 4), query_msg);
2513 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2514 phex (dma_info_stall_and_notify, 4));
2515 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2516 phex (dma_info_atomic_command_status, 4));
2517 printf_filtered ("\n");
2518 }
2519
e17a4113 2520 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2521 do_cleanups (chain);
2522}
2523
2524static void
2525info_spu_proxydma_command (char *args, int from_tty)
2526{
2527 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2528 struct gdbarch *gdbarch = get_frame_arch (frame);
2529 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2530 ULONGEST dma_info_type;
2531 ULONGEST dma_info_mask;
2532 ULONGEST dma_info_status;
2533 struct cleanup *chain;
2534 char annex[32];
2535 gdb_byte buf[1024];
2536 LONGEST len;
22e048c9 2537 int id;
23d964e7 2538
e17a4113 2539 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2540 error (_("\"info spu\" is only supported on the SPU architecture."));
2541
23d964e7
UW		 2542 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2543
2544 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2545 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2546 buf, 0, 24 + 8 * 32);
2547 if (len <= 0)
2548 error (_("Could not read proxydma_info."));
2549
e17a4113
UW		 2550 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2551 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2552 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7 2553
31a0ae49
JK		 2554 chain = make_cleanup_ui_out_tuple_begin_end (current_uiout,
2555 "SPUInfoProxyDMA");
23d964e7 2556
31a0ae49 2557 if (ui_out_is_mi_like_p (current_uiout))
23d964e7 2558 {
31a0ae49 2559 ui_out_field_fmt (current_uiout, "proxydma_info_type", "0x%s",
23d964e7 2560 phex_nz (dma_info_type, 4));
31a0ae49 2561 ui_out_field_fmt (current_uiout, "proxydma_info_mask", "0x%s",
23d964e7 2562 phex_nz (dma_info_mask, 4));
31a0ae49 2563 ui_out_field_fmt (current_uiout, "proxydma_info_status", "0x%s",
23d964e7
UW		 2564 phex_nz (dma_info_status, 4));
2565 }
2566 else
2567 {
2568 const char *query_msg;
2569
8fbde58b 2570 switch (dma_info_type & 3)
23d964e7
UW		 2571 {
2572 case 0: query_msg = _("no query pending"); break;
2573 case 1: query_msg = _("'any' query pending"); break;
2574 case 2: query_msg = _("'all' query pending"); break;
2575 default: query_msg = _("undefined query type"); break;
2576 }
2577
2578 printf_filtered (_("Tag-Group Status 0x%s\n"),
2579 phex (dma_info_status, 4));
2580 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2581 phex (dma_info_mask, 4), query_msg);
2582 printf_filtered ("\n");
2583 }
2584
e17a4113 2585 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2586 do_cleanups (chain);
2587}
2588
2589static void
2590info_spu_command (char *args, int from_tty)
2591{
c378eb4e
MS		 2592 printf_unfiltered (_("\"info spu\" must be followed by "
2593 "the name of an SPU facility.\n"));
23d964e7
UW		 2594 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2595}
2596
2597
3285f3fe
UW		 2598/* Root of all "set spu "/"show spu " commands. */
2599
2600static void
2601show_spu_command (char *args, int from_tty)
2602{
2603 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2604}
2605
2606static void
2607set_spu_command (char *args, int from_tty)
2608{
2609 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2610}
2611
2612static void
2613show_spu_stop_on_load (struct ui_file *file, int from_tty,
2614 struct cmd_list_element *c, const char *value)
2615{
2616 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2617 value);
2618}
2619
ff1a52c6
UW		 2620static void
2621show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2622 struct cmd_list_element *c, const char *value)
2623{
2624 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2625 value);
2626}
2627
3285f3fe 2628
771b4502
UW		 2629/* Set up gdbarch struct. */
2630
2631static struct gdbarch *
2632spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2633{
2634 struct gdbarch *gdbarch;
794ac428 2635 struct gdbarch_tdep *tdep;
85e747d2
UW		 2636 int id = -1;
2637
2638 /* Which spufs ID was requested as address space? */
2639 if (info.tdep_info)
2640 id = *(int *)info.tdep_info;
2641 /* For objfile architectures of SPU solibs, decode the ID from the name.
2642 This assumes the filename convention employed by solib-spu.c. */
2643 else if (info.abfd)
2644 {
2645 char *name = strrchr (info.abfd->filename, '@');
2646 if (name)
2647 sscanf (name, "@0x%*x <%d>", &id);
2648 }
771b4502 2649
85e747d2
UW		 2650 /* Find a candidate among extant architectures. */
2651 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2652 arches != NULL;
2653 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2654 {
2655 tdep = gdbarch_tdep (arches->gdbarch);
2656 if (tdep && tdep->id == id)
2657 return arches->gdbarch;
2658 }
771b4502 2659
85e747d2 2660 /* None found, so create a new architecture. */
fc270c35 2661 tdep = XCNEW (struct gdbarch_tdep);
85e747d2 2662 tdep->id = id;
794ac428 2663 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2664
2665 /* Disassembler. */
85e747d2 2666 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2667
2668 /* Registers. */
2669 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2670 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2671 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2672 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2673 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2674 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2675 set_gdbarch_register_name (gdbarch, spu_register_name);
2676 set_gdbarch_register_type (gdbarch, spu_register_type);
2677 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2678 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2679 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2680 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2681
2682 /* Data types. */
2683 set_gdbarch_char_signed (gdbarch, 0);
2684 set_gdbarch_ptr_bit (gdbarch, 32);
2685 set_gdbarch_addr_bit (gdbarch, 32);
2686 set_gdbarch_short_bit (gdbarch, 16);
2687 set_gdbarch_int_bit (gdbarch, 32);
2688 set_gdbarch_long_bit (gdbarch, 32);
2689 set_gdbarch_long_long_bit (gdbarch, 64);
2690 set_gdbarch_float_bit (gdbarch, 32);
2691 set_gdbarch_double_bit (gdbarch, 64);
2692 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2693 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2694 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2695 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2696
ff1a52c6 2697 /* Address handling. */
85e747d2 2698 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2699 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2700 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2701 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2702 set_gdbarch_address_class_type_flags_to_name
2703 (gdbarch, spu_address_class_type_flags_to_name);
2704 set_gdbarch_address_class_name_to_type_flags
2705 (gdbarch, spu_address_class_name_to_type_flags);
2706
36acd84e 2707
771b4502 2708 /* Inferior function calls. */
7b3dc0b7
UW		 2709 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2710 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2711 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2712 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2713 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2714 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2715 set_gdbarch_return_value (gdbarch, spu_return_value);
2716
2717 /* Frame handling. */
2718 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2719 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2720 frame_base_set_default (gdbarch, &spu_frame_base);
2721 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2722 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2723 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2724 set_gdbarch_frame_args_skip (gdbarch, 0);
2725 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2726 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502 2727
cc5f0d61
UW		 2728 /* Cell/B.E. cross-architecture unwinder support. */
2729 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2730
771b4502
UW		 2731 /* Breakpoints. */
2732 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2733 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
d03285ec 2734 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
771b4502
UW		 2735 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2736 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2737 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2738
dcf52cd8
UW		 2739 /* Overlays. */
2740 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2741
771b4502
UW		 2742 return gdbarch;
2743}
2744
63807e1d
PA		 2745/* Provide a prototype to silence -Wmissing-prototypes. */
2746extern initialize_file_ftype _initialize_spu_tdep;
2747
771b4502
UW		 2748void
2749_initialize_spu_tdep (void)
2750{
2751 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2752
dcf52cd8
UW		 2753 /* Add ourselves to objfile event chain. */
2754 observer_attach_new_objfile (spu_overlay_new_objfile);
2755 spu_overlay_data = register_objfile_data ();
23d964e7 2756
3285f3fe
UW		 2757 /* Install spu stop-on-load handler. */
2758 observer_attach_new_objfile (spu_catch_start);
2759
ff1a52c6
UW		 2760 /* Add ourselves to normal_stop event chain. */
2761 observer_attach_normal_stop (spu_attach_normal_stop);
2762
3285f3fe
UW		 2763 /* Add root prefix command for all "set spu"/"show spu" commands. */
2764 add_prefix_cmd ("spu", no_class, set_spu_command,
2765 _("Various SPU specific commands."),
2766 &setspucmdlist, "set spu ", 0, &setlist);
2767 add_prefix_cmd ("spu", no_class, show_spu_command,
2768 _("Various SPU specific commands."),
2769 &showspucmdlist, "show spu ", 0, &showlist);
2770
2771 /* Toggle whether or not to add a temporary breakpoint at the "main"
2772 function of new SPE contexts. */
2773 add_setshow_boolean_cmd ("stop-on-load", class_support,
2774 &spu_stop_on_load_p, _("\
2775Set whether to stop for new SPE threads."),
2776 _("\
2777Show whether to stop for new SPE threads."),
2778 _("\
2779Use \"on\" to give control to the user when a new SPE thread\n\
2780enters its \"main\" function.\n\
2781Use \"off\" to disable stopping for new SPE threads."),
2782 NULL,
2783 show_spu_stop_on_load,
2784 &setspucmdlist, &showspucmdlist);
2785
ff1a52c6
UW		 2786 /* Toggle whether or not to automatically flush the software-managed
2787 cache whenever SPE execution stops. */
2788 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2789 &spu_auto_flush_cache_p, _("\
2790Set whether to automatically flush the software-managed cache."),
2791 _("\
2792Show whether to automatically flush the software-managed cache."),
2793 _("\
2794Use \"on\" to automatically flush the software-managed cache\n\
2795whenever SPE execution stops.\n\
2796Use \"off\" to never automatically flush the software-managed cache."),
2797 NULL,
2798 show_spu_auto_flush_cache,
2799 &setspucmdlist, &showspucmdlist);
2800
23d964e7
UW		 2801 /* Add root prefix command for all "info spu" commands. */
2802 add_prefix_cmd ("spu", class_info, info_spu_command,
2803 _("Various SPU specific commands."),
2804 &infospucmdlist, "info spu ", 0, &infolist);
2805
2806 /* Add various "info spu" commands. */
2807 add_cmd ("event", class_info, info_spu_event_command,
2808 _("Display SPU event facility status.\n"),
2809 &infospucmdlist);
2810 add_cmd ("signal", class_info, info_spu_signal_command,
2811 _("Display SPU signal notification facility status.\n"),
2812 &infospucmdlist);
2813 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2814 _("Display SPU mailbox facility status.\n"),
2815 &infospucmdlist);
2816 add_cmd ("dma", class_info, info_spu_dma_command,
2817 _("Display MFC DMA status.\n"),
2818 &infospucmdlist);
2819 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2820 _("Display MFC Proxy-DMA status.\n"),
2821 &infospucmdlist);
771b4502 2822}
GDB Binutils - Deliverables
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