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771b4502 | 1 | /* SPU target-dependent code for GDB, the GNU debugger. |
ecd75fc8 | 2 | Copyright (C) 2006-2014 Free Software Foundation, Inc. |
771b4502 UW |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
771b4502 UW |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
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18 | |
19 | #ifndef SPU_TDEP_H | |
20 | #define SPU_TDEP_H | |
21 | ||
22 | /* Number of registers. */ | |
23 | #define SPU_NUM_REGS 130 | |
23d964e7 | 24 | #define SPU_NUM_PSEUDO_REGS 6 |
771b4502 UW |
25 | #define SPU_NUM_GPRS 128 |
26 | ||
27 | /* Register numbers of various important registers. */ | |
28 | enum spu_regnum | |
29 | { | |
30 | /* SPU calling convention. */ | |
31 | SPU_LR_REGNUM = 0, /* Link register. */ | |
32 | SPU_RAW_SP_REGNUM = 1, /* Stack pointer (full register). */ | |
33 | SPU_ARG1_REGNUM = 3, /* First argument register. */ | |
34 | SPU_ARGN_REGNUM = 74, /* Last argument register. */ | |
35 | SPU_SAVED1_REGNUM = 80, /* First call-saved register. */ | |
36 | SPU_SAVEDN_REGNUM = 127, /* Last call-saved register. */ | |
37 | SPU_FP_REGNUM = 127, /* Frame pointer. */ | |
38 | ||
39 | /* Special registers. */ | |
40 | SPU_ID_REGNUM = 128, /* SPU ID register. */ | |
41 | SPU_PC_REGNUM = 129, /* Next program counter. */ | |
23d964e7 UW |
42 | SPU_SP_REGNUM = 130, /* Stack pointer (preferred slot). */ |
43 | SPU_FPSCR_REGNUM = 131, /* Floating point status/control register. */ | |
44 | SPU_SRR0_REGNUM = 132, /* SRR0 register. */ | |
45 | SPU_LSLR_REGNUM = 133, /* Local store limit register. */ | |
46 | SPU_DECR_REGNUM = 134, /* Decrementer value. */ | |
47 | SPU_DECR_STATUS_REGNUM = 135 /* Decrementer status. */ | |
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48 | }; |
49 | ||
d2ed6730 UW |
50 | /* Address conversions. |
51 | ||
52 | In a combined PPU/SPU debugging session, we have to consider multiple | |
53 | address spaces: the PPU 32- or 64-bit address space, and the 32-bit | |
54 | local store address space for each SPU context. As it is currently | |
55 | not yet possible to use the program_space / address_space mechanism | |
56 | to represent this, we encode all those addresses into one single | |
57 | 64-bit address for the whole process. For SPU programs using overlays, | |
58 | this address space must also include separate ranges reserved for the | |
59 | LMA of overlay sections. | |
60 | ||
61 | ||
62 | The following combinations are supported for combined debugging: | |
63 | ||
64 | PPU address (this relies on the fact that PPC 64-bit user space | |
65 | addresses can never have the highest-most bit set): | |
66 | ||
67 | +-+---------------------------------+ | |
68 | |0| ADDR [63] | | |
69 | +-+---------------------------------+ | |
70 | ||
71 | SPU address for SPU context with id SPU (this assumes that SPU | |
72 | IDs, which are file descriptors, are never larger than 2^30): | |
73 | ||
74 | +-+-+--------------+----------------+ | |
75 | |1|0| SPU [30] | ADDR [32] | | |
76 | +-+-+--------------+----------------+ | |
77 | ||
78 | SPU overlay section LMA for SPU context with id SPU: | |
79 | ||
80 | +-+-+--------------+----------------+ | |
81 | |1|1| SPU [30] | ADDR [32] | | |
82 | +-+-+--------------+----------------+ | |
83 | ||
84 | ||
85 | In SPU stand-alone debugging mode (using spu-linux-nat.c), | |
86 | the following combinations are supported: | |
87 | ||
88 | SPU address: | |
89 | ||
90 | +-+-+--------------+----------------+ | |
91 | |0|0| 0 | ADDR [32] | | |
92 | +-+-+--------------+----------------+ | |
93 | ||
94 | SPU overlay section LMA: | |
95 | ||
96 | +-+-+--------------+----------------+ | |
97 | |0|1| 0 | ADDR [32] | | |
98 | +-+-+--------------+----------------+ | |
99 | ||
100 | ||
101 | The following macros allow manipulation of addresses in the | |
102 | above formats. */ | |
103 | ||
85e747d2 UW |
104 | #define SPUADDR(spu, addr) \ |
105 | ((spu) != -1? (ULONGEST)1 << 63 | (ULONGEST)(spu) << 32 | (addr) : (addr)) | |
d2ed6730 | 106 | |
85e747d2 | 107 | #define SPUADDR_SPU(addr) \ |
768f0929 | 108 | (((addr) & (ULONGEST)1 << 63) \ |
d2ed6730 | 109 | ? (int) ((ULONGEST)(addr) >> 32 & 0x3fffffff) \ |
768f0929 | 110 | : -1) |
d2ed6730 | 111 | |
85e747d2 UW |
112 | #define SPUADDR_ADDR(addr) \ |
113 | (((addr) & (ULONGEST)1 << 63)? (ULONGEST)(addr) & 0xffffffff : (addr)) | |
114 | ||
d2ed6730 UW |
115 | #define SPU_OVERLAY_LMA ((ULONGEST)1 << 62) |
116 | ||
771b4502 | 117 | #endif |