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618f726f | 1 | # Copyright (C) 2008-2016 Free Software Foundation, Inc. |
604c2f83 LM |
2 | # |
3 | # This program is free software; you can redistribute it and/or modify | |
4 | # it under the terms of the GNU General Public License as published by | |
5 | # the Free Software Foundation; either version 3 of the License, or | |
6 | # (at your option) any later version. | |
7 | # | |
8 | # This program is distributed in the hope that it will be useful, | |
9 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | # GNU General Public License for more details. | |
12 | # | |
13 | # You should have received a copy of the GNU General Public License | |
14 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | # | |
604c2f83 | 16 | |
604c2f83 LM |
17 | # |
18 | # Test the use of VSX registers, for Powerpc. | |
19 | # | |
20 | ||
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21 | |
22 | if {![istarget "powerpc*"] || [skip_vsx_tests]} then { | |
23 | verbose "Skipping vsx register tests." | |
604c2f83 LM |
24 | return |
25 | } | |
26 | ||
20c2c024 | 27 | standard_testfile |
604c2f83 LM |
28 | |
29 | set compile_flags {debug nowarnings quiet} | |
4c93b1db | 30 | if [get_compiler_info] { |
604c2f83 LM |
31 | warning "get_compiler failed" |
32 | return -1 | |
33 | } | |
34 | ||
35 | if [test_compiler_info gcc*] { | |
36 | set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" | |
37 | } elseif [test_compiler_info xlc*] { | |
38 | set compile_flags "$compile_flags additional_flags=-qaltivec" | |
39 | } else { | |
40 | warning "unknown compiler" | |
41 | return -1 | |
42 | } | |
43 | ||
44 | if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { | |
5b362f04 | 45 | untested "failed to compile" |
604c2f83 LM |
46 | return -1 |
47 | } | |
48 | ||
49 | gdb_start | |
50 | gdb_reinitialize_dir $srcdir/$subdir | |
51 | gdb_load ${binfile} | |
52 | ||
53 | # Run to `main' where we begin our tests. | |
54 | ||
55 | if ![runto_main] then { | |
56 | gdb_suppress_tests | |
57 | } | |
58 | ||
084ee545 UW |
59 | set endianness "" |
60 | set msg "detect endianness" | |
61 | gdb_test_multiple "show endian" "$msg" { | |
62 | -re "(The target endianness is set automatically .currently )(big|little)( endian.*)$gdb_prompt $" { | |
63 | pass "$msg" | |
64 | set endianness $expect_out(2,string) | |
65 | } | |
66 | -re ".*$gdb_prompt $" { | |
67 | fail "$msg" | |
68 | } | |
69 | } | |
70 | ||
604c2f83 LM |
71 | # Data sets used throughout the test |
72 | ||
084ee545 UW |
73 | if {$endianness == "big"} { |
74 | set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." | |
75 | ||
76 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." | |
4572cbac | 77 | |
084ee545 | 78 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
d9492458 | 79 | |
084ee545 | 80 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
604c2f83 | 81 | |
084ee545 UW |
82 | set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
83 | ||
84 | set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." | |
85 | } else { | |
86 | set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." | |
d9492458 | 87 | |
084ee545 | 88 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." |
604c2f83 | 89 | |
084ee545 UW |
90 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." |
91 | ||
92 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." | |
93 | ||
94 | set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." | |
95 | ||
96 | set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." | |
97 | } | |
604c2f83 LM |
98 | |
99 | set float_register ".raw 0xdeadbeefdeadbeef." | |
100 | ||
101 | # First run the F0~F31/VS0~VS31 tests | |
102 | ||
103 | # 1: Set F0~F31 registers and check if it reflects on VS0~VS31. | |
104 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 105 | gdb_test_no_output "set \$f$i = 1\.3" |
604c2f83 LM |
106 | } |
107 | ||
108 | for {set i 0} {$i < 32} {incr i 1} { | |
109 | gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)" | |
110 | } | |
111 | ||
112 | # 2: Set VS0~VS31 registers and check if it reflects on F0~F31. | |
113 | for {set i 0} {$i < 32} {incr i 1} { | |
114 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 115 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" |
604c2f83 LM |
116 | } |
117 | } | |
118 | ||
119 | for {set i 0} {$i < 32} {incr i 1} { | |
120 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
121 | } | |
122 | ||
123 | for {set i 0} {$i < 32} {incr i 1} { | |
124 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)" | |
125 | } | |
126 | ||
127 | # Now run the VR0~VR31/VS32~VS63 tests | |
128 | ||
129 | # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. | |
130 | for {set i 0} {$i < 32} {incr i 1} { | |
131 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 132 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
133 | } |
134 | } | |
135 | ||
136 | for {set i 32} {$i < 64} {incr i 1} { | |
137 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i" | |
138 | } | |
139 | # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. | |
140 | for {set i 32} {$i < 64} {incr i 1} { | |
141 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 142 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
143 | } |
144 | } | |
145 | ||
146 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 147 | gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" |
604c2f83 LM |
148 | } |
149 | ||
d9492458 TJB |
150 | # Create a core file. We create the core file before the F32~F63/VR0~VR31 test |
151 | # below because then we'll have more interesting register values to verify | |
152 | # later when loading the core file (i.e., different register values for different | |
153 | # vector register banks). | |
154 | ||
16c85b5d | 155 | set corefile [standard_output_file vsx-core.test] |
fac51dd9 | 156 | set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"] |
604c2f83 | 157 | |
d9492458 TJB |
158 | # Now run the F32~F63/VR0~VR31 tests. |
159 | ||
160 | # 1: Set F32~F63 registers and check if it reflects on VR0~VR31. | |
161 | for {set i 32} {$i < 64} {incr i 1} { | |
162 | gdb_test_no_output "set \$f$i = 1\.3" | |
163 | } | |
164 | ||
165 | for {set i 0} {$i < 32} {incr i 1} { | |
166 | gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)" | |
167 | } | |
168 | ||
169 | # 2: Set VR0~VR31 registers and check if it reflects on F32~F63. | |
170 | for {set i 0} {$i < 32} {incr i 1} { | |
171 | for {set j 0} {$j < 4} {incr j 1} { | |
172 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef" | |
173 | } | |
174 | } | |
175 | ||
176 | for {set i 32} {$i < 64} {incr i 1} { | |
177 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
178 | } | |
179 | ||
180 | for {set i 0} {$i < 32} {incr i 1} { | |
181 | gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)" | |
182 | } | |
183 | ||
184 | # Test reading the core file. | |
185 | ||
604c2f83 LM |
186 | if {!$core_supported} { |
187 | return -1 | |
188 | } | |
189 | ||
190 | gdb_exit | |
191 | gdb_start | |
192 | gdb_reinitialize_dir $srcdir/$subdir | |
193 | gdb_load ${binfile} | |
194 | ||
fac51dd9 DE |
195 | set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"] |
196 | if { $core_loaded == -1 } { | |
197 | # No use proceeding from here. | |
198 | return | |
604c2f83 LM |
199 | } |
200 | ||
201 | for {set i 0} {$i < 32} {incr i 1} { | |
cdc7edd7 | 202 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file" |
604c2f83 LM |
203 | } |
204 | ||
205 | for {set i 32} {$i < 64} {incr i 1} { | |
cdc7edd7 | 206 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file" |
604c2f83 | 207 | } |