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32d0add0 | 1 | # Copyright 2009-2015 Free Software Foundation, Inc. |
1ea34204 UW |
2 | # |
3 | # This program is free software; you can redistribute it and/or modify | |
4 | # it under the terms of the GNU General Public License as published by | |
5 | # the Free Software Foundation; either version 3 of the License, or | |
6 | # (at your option) any later version. | |
7 | # | |
8 | # This program is distributed in the hope that it will be useful, | |
9 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | # GNU General Public License for more details. | |
12 | # | |
13 | # You should have received a copy of the GNU General Public License | |
14 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | # | |
16 | # Contributed by Markus Deuling <deuling@de.ibm.com>. | |
17 | # | |
18 | # Testsuite for Cell Broadband Engine combined debugger | |
19 | # Test ptype and print/set of SPU-side registers. | |
20 | ||
21 | load_lib cell.exp | |
22 | ||
23 | set ppu_file "break" | |
24 | set ppu_src ${srcdir}/${subdir}/${ppu_file}.c | |
25 | set ppu_bin ${objdir}/${subdir}/${ppu_file} | |
26 | set spu_file "break-spu" | |
27 | set spu_src ${srcdir}/${subdir}/${spu_file}.c | |
28 | set spu_bin ${objdir}/${subdir}/${spu_file} | |
29 | ||
30 | if {[skip_cell_tests]} { | |
31 | return 0 | |
32 | } | |
33 | ||
34 | # Compile SPU binary. | |
35 | if { [gdb_compile_cell_spu $spu_src $spu_bin executable {debug}] != "" } { | |
36 | unsupported "Compiling spu binary failed." | |
37 | return -1 | |
38 | } | |
39 | # Compile PPU binary. | |
40 | if { [gdb_cell_embedspu $spu_bin $spu_bin-embed.o {debug}] != "" } { | |
41 | unsupported "Embedding spu binary failed." | |
42 | return -1 | |
43 | } | |
44 | if { [gdb_compile_cell_ppu [list $ppu_src $spu_bin-embed.o] $ppu_bin executable {debug}] != "" } { | |
45 | unsupported "Compiling ppu binary failed." | |
46 | return -1 | |
47 | } | |
48 | ||
4c93b1db | 49 | if [get_compiler_info] { |
1ea34204 UW |
50 | return -1 |
51 | } | |
52 | ||
53 | gdb_exit | |
54 | gdb_start | |
55 | gdb_reinitialize_dir $srcdir/$subdir | |
56 | gdb_load ${ppu_bin} | |
57 | ||
58 | if ![runto_main] then { | |
59 | fail "Can't run to main" | |
60 | return 0 | |
61 | } | |
62 | ||
63 | # Continue to SPU | |
64 | cont_spu_main | |
65 | ||
66 | gdb_test "info registers r2" \ | |
67 | "r2.*\{uint128 =.*v2_int64 =.*v4_int32 =.*v8_int16 =.*v16_int8 =.*v2_double =.*v4_float =.*\}.*" \ | |
68 | "info registers r2" | |
69 | ||
70 | for {set check_reg 10} {$check_reg < 12} {incr check_reg} { | |
71 | gdb_test "print \$r$check_reg\.v4_int32" \ | |
72 | ".*= \{.*,.*,.*,.*\}" \ | |
73 | "print \$r$check_reg\.v4_int32" | |
74 | ||
75 | gdb_test "ptype \$r$check_reg" \ | |
76 | "type = union __spu_builtin_type_vec128.*\{.*int128_t uint128.* \ | |
77 | int64_t v2_int64.*int32_t v4_int32.*int16_t v8_int16.* \ | |
78 | int8_t v16_int8.*double v2_double.*float v4_float.*\}" \ | |
79 | "ptype \$r$check_reg" | |
80 | ||
81 | gdb_test "set \$r$check_reg\.v4_int32 = {1,2,3,4}" \ | |
82 | "" \ | |
83 | "set \$r$check_reg\.v4_int32 = {1,2,3,4}" | |
84 | ||
85 | gdb_test "print \$r$check_reg\.v4_int32" \ | |
86 | ".*= \{.*1, 2, 3, 4.*\}" \ | |
87 | "print \$r$check_reg\.v4_int32" | |
88 | ||
89 | gdb_test "print \$r$check_reg.v4_int32\[0\]" \ | |
90 | ".*= 1.*" \ | |
91 | "print \$r$check_reg.v4_int32\[0\]" | |
92 | ||
93 | gdb_test "print \$r$check_reg.v4_int32\[1\]" \ | |
94 | ".*= 2.*" \ | |
95 | "print \$r$check_reg.v4_int32\[1\]" | |
96 | ||
97 | gdb_test "print \$r$check_reg.v4_int32\[2\]" \ | |
98 | ".*= 3.*" \ | |
99 | "print \$r$check_reg.v4_int32\[2\]" | |
100 | ||
101 | gdb_test "print \$r$check_reg.v4_int32\[3\]" \ | |
102 | ".*= 4.*" \ | |
103 | "print \$r$check_reg.v4_int32\[3\]" | |
104 | ||
105 | gdb_test "print \$r$check_reg.v4_int32\[4\]" \ | |
106 | "no such vector element" \ | |
107 | "print \$r$check_reg.v4_int32\[4\]" | |
108 | ||
109 | # Set single array elements to other values and check the results. | |
110 | gdb_test "set \$r$check_reg\.v4_int32\[0\] = 5" \ | |
111 | "" \ | |
112 | "set \$r$check_reg\.v4_int32\[0\] = 5" | |
113 | gdb_test "print \$r$check_reg.v4_int32\[0\]" \ | |
114 | ".*= 5.*" \ | |
115 | "print \$r$check_reg.v4_int32\[0\]" | |
116 | ||
117 | gdb_test "set \$r$check_reg\.v4_int32\[1\] = 6" \ | |
118 | "" \ | |
119 | "set \$r$check_reg\.v4_int32\[1\] = 6" | |
120 | gdb_test "print \$r$check_reg.v4_int32\[1\]" \ | |
121 | ".*= 6.*" \ | |
122 | "print \$r$check_reg.v4_int32\[1\]" | |
123 | ||
124 | gdb_test "set \$r$check_reg\.v4_int32\[2\] = 7" \ | |
125 | "" \ | |
126 | "set \$r$check_reg\.v4_int32\[2\] = 7" | |
127 | gdb_test "print \$r$check_reg.v4_int32\[2\]" \ | |
128 | ".*= 7.*" \ | |
129 | "print \$r$check_reg.v4_int32\[2\]" | |
130 | ||
131 | gdb_test "set \$r$check_reg\.v4_int32\[3\] = 8" \ | |
132 | "" \ | |
133 | "set \$r$check_reg\.v4_int32\[3\] = 8" | |
134 | gdb_test "print \$r$check_reg.v4_int32\[3\]" \ | |
135 | ".*= 8.*" \ | |
136 | "print \$r$check_reg.v4_int32\[3\]" | |
137 | ||
138 | # Now there should be {5, 6, 7, 8} in that array. | |
139 | gdb_test "print \$r$check_reg\.v4_int32" \ | |
140 | ".*= \{.*5, 6, 7, 8.*\}" \ | |
141 | "print \$r$check_reg\.v4_int32" | |
142 | } | |
143 | ||
144 | gdb_exit | |
145 | return 0 |