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Make it simpler to add events to Python
[deliverable/binutils-gdb.git] / gdb / tic6x-tdep.c
CommitLineData
8cd64e00
YQ		 1/* Target dependent code for GDB on TI C6x systems.
2
61baf725 3 Copyright (C) 2010-2017 Free Software Foundation, Inc.
8cd64e00
YQ		 4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "frame.h"
24#include "frame-unwind.h"
25#include "frame-base.h"
26#include "trad-frame.h"
27#include "dwarf2-frame.h"
28#include "symtab.h"
29#include "inferior.h"
30#include "gdbtypes.h"
31#include "gdbcore.h"
32#include "gdbcmd.h"
33#include "target.h"
34#include "dis-asm.h"
35#include "regcache.h"
36#include "value.h"
37#include "symfile.h"
38#include "arch-utils.h"
39#include "floatformat.h"
40#include "glibc-tdep.h"
41#include "infcall.h"
42#include "regset.h"
43#include "tramp-frame.h"
44#include "linux-tdep.h"
45#include "solib.h"
46#include "objfiles.h"
8cd64e00
YQ		 47#include "osabi.h"
48#include "tic6x-tdep.h"
49#include "language.h"
50#include "target-descriptions.h"
325fac50 51#include <algorithm>
8cd64e00
YQ		 52
53#include "features/tic6x-c64xp.c"
54#include "features/tic6x-c64x.c"
55#include "features/tic6x-c62x.c"
56
57#define TIC6X_OPCODE_SIZE 4
58#define TIC6X_FETCH_PACKET_SIZE 32
59
60#define INST_S_BIT(INST) ((INST >> 1) & 1)
61#define INST_X_BIT(INST) ((INST >> 12) & 1)
62
85661b1e
YQ		 63const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 };
64const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 };
65
8cd64e00
YQ		 66struct tic6x_unwind_cache
67{
68 /* The frame's base, optionally used by the high-level debug info. */
69 CORE_ADDR base;
70
71 /* The previous frame's inner most stack address. Used as this
72 frame ID's stack_addr. */
73 CORE_ADDR cfa;
74
75 /* The address of the first instruction in this function */
76 CORE_ADDR pc;
77
78 /* Which register holds the return address for the frame. */
79 int return_regnum;
80
81 /* The offset of register saved on stack. If register is not saved, the
82 corresponding element is -1. */
83 CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS];
84};
85
86
87/* Name of TI C6x core registers. */
88static const char *const tic6x_register_names[] =
89{
90 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
91 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
92 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
93 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
94 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
95 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
96 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
97 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
98 "CSR", "PC", /* 32 33 */
99};
100
101/* This array maps the arguments to the register number which passes argument
102 in function call according to C6000 ELF ABI. */
103static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
104
105/* This is the implementation of gdbarch method register_name. */
106
107static const char *
108tic6x_register_name (struct gdbarch *gdbarch, int regno)
109{
110 if (regno < 0)
111 return NULL;
112
113 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
114 return tdesc_register_name (gdbarch, regno);
115 else if (regno >= ARRAY_SIZE (tic6x_register_names))
116 return "";
117 else
118 return tic6x_register_names[regno];
119}
120
121/* This is the implementation of gdbarch method register_type. */
122
123static struct type *
124tic6x_register_type (struct gdbarch *gdbarch, int regno)
125{
126
127 if (regno == TIC6X_PC_REGNUM)
128 return builtin_type (gdbarch)->builtin_func_ptr;
129 else
130 return builtin_type (gdbarch)->builtin_uint32;
131}
132
133static void
134tic6x_setup_default (struct tic6x_unwind_cache *cache)
135{
136 int i;
137
138 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
139 cache->reg_saved[i] = -1;
140}
141
142static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR);
143static int tic6x_register_number (int reg, int side, int crosspath);
144
145/* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
146 Bail out early if CURRENT_PC is reached. Returns the address of the first
147 instruction after the prologue. */
148
693be288 149static CORE_ADDR
8cd64e00
YQ		 150tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
151 const CORE_ADDR current_pc,
152 struct tic6x_unwind_cache *cache,
153 struct frame_info *this_frame)
154{
8cd64e00
YQ		 155 unsigned long inst;
156 unsigned int src_reg, base_reg, dst_reg;
157 int i;
158 CORE_ADDR pc = start_pc;
159 CORE_ADDR return_pc = start_pc;
160 int frame_base_offset_to_sp = 0;
161 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
162 int non_stw_insn_counter = 0;
163
164 if (start_pc >= current_pc)
165 return_pc = current_pc;
166
167 cache->base = 0;
168
169 /* The landmarks in prologue is one or two SUB instructions to SP.
170 Instructions on setting up dsbt are in the last part of prologue, if
171 needed. In maxim, prologue can be divided to three parts by two
172 `sub sp, xx, sp' insns. */
173
174 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
175 2nd one is optional. */
176 while (pc < current_pc)
177 {
8cd64e00
YQ		 178 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
179
180 if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0
181 || (inst & 0x0ffc) == 0x9c0)
182 {
183 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
184 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
185 INST_S_BIT (inst), 0);
186 unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f,
187 INST_S_BIT (inst), 0);
188
189 if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM)
190 {
191 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
192 offset. The constant offset is decoded in bit 13-17 in all
193 these three kinds of instructions. */
194 unsigned int ucst5 = (inst >> 13) & 0x1f;
195
196 if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */
197 frame_base_offset_to_sp += ucst5 << 2;
198 else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */
199 frame_base_offset_to_sp += ucst5 << 1;
200 else if ((inst & 0x0ffc) == 0x9c0) /* SUB */
201 frame_base_offset_to_sp += ucst5;
202 else
203 gdb_assert_not_reached ("unexpected instruction");
204
205 return_pc = pc + 4;
206 }
207 }
208 else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
209 {
210 /* The y bit determines which file base is read from. */
211 base_reg = tic6x_register_number ((inst >> 18) & 0x1f,
212 (inst >> 7) & 1, 0);
213
214 if (base_reg == TIC6X_SP_REGNUM)
215 {
216 src_reg = tic6x_register_number ((inst >> 23) & 0x1f,
217 INST_S_BIT (inst), 0);
218
219 cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2;
220
221 return_pc = pc + 4;
222 }
223 non_stw_insn_counter = 0;
224 }
225 else
226 {
227 non_stw_insn_counter++;
228 /* Following instruction sequence may be emitted in prologue:
229
230 <+0>: subah .D2 b15,28,b15
231 <+4>: or .L2X 0,a4,b0
232 <+8>: || stw .D2T2 b14,*+b15(56)
233 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
234 <+16>:|| stw .D2T1 a10,*+b15(48)
235 <+20>:stw .D2T2 b3,*+b15(52)
236 <+24>:stw .D2T1 a4,*+b15(40)
237
238 we should look forward for next instruction instead of breaking loop
239 here. So far, we allow almost two sequential non-stw instructions
240 in prologue. */
241 if (non_stw_insn_counter >= 2)
242 break;
243 }
244
245
246 pc += 4;
247 }
248 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
249 ldw .D2T2 *+b14(0),b14 */
250 inst = tic6x_fetch_instruction (gdbarch, pc);
251 /* The s bit determines which file dst will be loaded into, same effect as
252 other places. */
253 dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0);
254 /* The y bit (bit 7), instead of s bit, determines which file base be
255 used. */
256 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0);
257
258 if ((inst & 0x164) == 0x64 /* ldw */
259 && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */
260 && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */
261 {
262 return_pc = pc + 4;
263 }
264
265 if (this_frame)
266 {
267 cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
268
269 if (cache->reg_saved[TIC6X_FP_REGNUM] != -1)
270 {
271 /* If the FP now holds an offset from the CFA then this is a frame
272 which uses the frame pointer. */
273
274 cache->cfa = get_frame_register_unsigned (this_frame,
275 TIC6X_FP_REGNUM);
276 }
277 else
278 {
279 /* FP doesn't hold an offset from the CFA. If SP still holds an
280 offset from the CFA then we might be in a function which omits
281 the frame pointer. */
282
283 cache->cfa = cache->base + frame_base_offset_to_sp;
284 }
285 }
286
287 /* Adjust all the saved registers such that they contain addresses
288 instead of offsets. */
289 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
290 if (cache->reg_saved[i] != -1)
291 cache->reg_saved[i] = cache->base + cache->reg_saved[i];
292
293 return return_pc;
294}
295
296/* This is the implementation of gdbarch method skip_prologue. */
297
693be288 298static CORE_ADDR
8cd64e00
YQ		 299tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
300{
8cd64e00
YQ		 301 CORE_ADDR func_addr;
302 struct tic6x_unwind_cache cache;
303
304 /* See if we can determine the end of the prologue via the symbol table.
305 If so, then return either PC, or the PC after the prologue, whichever is
306 greater. */
307 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
308 {
309 CORE_ADDR post_prologue_pc
310 = skip_prologue_using_sal (gdbarch, func_addr);
311 if (post_prologue_pc != 0)
325fac50 312 return std::max (start_pc, post_prologue_pc);
8cd64e00
YQ		 313 }
314
315 /* Can't determine prologue from the symbol table, need to examine
316 instructions. */
317 return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache,
318 NULL);
319}
320
cd6c3b4f
YQ		 321/* Implement the breakpoint_kind_from_pc gdbarch method. */
322
d19280ad
YQ		 323static int
324tic6x_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
325{
326 return 4;
327}
8cd64e00 328
cd6c3b4f
YQ		 329/* Implement the sw_breakpoint_from_kind gdbarch method. */
330
948f8e3d 331static const gdb_byte *
d19280ad 332tic6x_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
8cd64e00
YQ		 333{
334 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
335
d19280ad 336 *size = kind;
8cd64e00
YQ		 337
338 if (tdep == NULL || tdep->breakpoint == NULL)
339 {
340 if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch))
341 return tic6x_bkpt_illegal_opcode_be;
342 else
343 return tic6x_bkpt_illegal_opcode_le;
344 }
345 else
346 return tdep->breakpoint;
347}
348
8cd64e00
YQ		 349static void
350tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
351 struct dwarf2_frame_state_reg *reg,
352 struct frame_info *this_frame)
353{
354 /* Mark the PC as the destination for the return address. */
355 if (regnum == gdbarch_pc_regnum (gdbarch))
356 reg->how = DWARF2_FRAME_REG_RA;
357
358 /* Mark the stack pointer as the call frame address. */
359 else if (regnum == gdbarch_sp_regnum (gdbarch))
360 reg->how = DWARF2_FRAME_REG_CFA;
361
362 /* The above was taken from the default init_reg in dwarf2-frame.c
363 while the below is c6x specific. */
364
365 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
366 callee-save. */
367 else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31))
368 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
369 else
370 /* All other registers are caller-save. */
371 reg->how = DWARF2_FRAME_REG_UNDEFINED;
372}
373
374/* This is the implementation of gdbarch method unwind_pc. */
375
376static CORE_ADDR
377tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
378{
379 gdb_byte buf[8];
380
381 frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf);
382 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
383}
384
385/* This is the implementation of gdbarch method unwind_sp. */
386
387static CORE_ADDR
388tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
389{
390 return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM);
391}
392
393
394/* Frame base handling. */
395
693be288 396static struct tic6x_unwind_cache*
8cd64e00
YQ		 397tic6x_frame_unwind_cache (struct frame_info *this_frame,
398 void **this_prologue_cache)
399{
400 struct gdbarch *gdbarch = get_frame_arch (this_frame);
401 CORE_ADDR current_pc;
402 struct tic6x_unwind_cache *cache;
8cd64e00
YQ		 403
404 if (*this_prologue_cache)
19ba03f4 405 return (struct tic6x_unwind_cache *) *this_prologue_cache;
8cd64e00
YQ		 406
407 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
408 (*this_prologue_cache) = cache;
409
410 cache->return_regnum = TIC6X_RA_REGNUM;
411
412 tic6x_setup_default (cache);
413
414 cache->pc = get_frame_func (this_frame);
415 current_pc = get_frame_pc (this_frame);
416
417 /* Prologue analysis does the rest... */
418 if (cache->pc != 0)
419 tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
420
421 return cache;
422}
423
424static void
425tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache,
426 struct frame_id *this_id)
427{
428 struct tic6x_unwind_cache *cache =
429 tic6x_frame_unwind_cache (this_frame, this_cache);
430
431 /* This marks the outermost frame. */
432 if (cache->base == 0)
433 return;
434
435 (*this_id) = frame_id_build (cache->cfa, cache->pc);
436}
437
438static struct value *
439tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache,
440 int regnum)
441{
442 struct tic6x_unwind_cache *cache =
443 tic6x_frame_unwind_cache (this_frame, this_cache);
444
445 gdb_assert (regnum >= 0);
446
447 /* The PC of the previous frame is stored in the RA register of
448 the current frame. Frob regnum so that we pull the value from
449 the correct place. */
450 if (regnum == TIC6X_PC_REGNUM)
451 regnum = cache->return_regnum;
452
453 if (regnum == TIC6X_SP_REGNUM && cache->cfa)
454 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
455
456 /* If we've worked out where a register is stored then load it from
457 there. */
458 if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1)
459 return frame_unwind_got_memory (this_frame, regnum,
460 cache->reg_saved[regnum]);
461
462 return frame_unwind_got_register (this_frame, regnum, regnum);
463}
464
465static CORE_ADDR
466tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache)
467{
468 struct tic6x_unwind_cache *info
469 = tic6x_frame_unwind_cache (this_frame, this_cache);
470 return info->base;
471}
472
473static const struct frame_unwind tic6x_frame_unwind =
474{
475 NORMAL_FRAME,
476 default_frame_unwind_stop_reason,
477 tic6x_frame_this_id,
478 tic6x_frame_prev_register,
479 NULL,
480 default_frame_sniffer
481};
482
483static const struct frame_base tic6x_frame_base =
484{
485 &tic6x_frame_unwind,
486 tic6x_frame_base_address,
487 tic6x_frame_base_address,
488 tic6x_frame_base_address
489};
490
491
492static struct tic6x_unwind_cache *
493tic6x_make_stub_cache (struct frame_info *this_frame)
494{
495 struct tic6x_unwind_cache *cache;
496
497 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
498
499 cache->return_regnum = TIC6X_RA_REGNUM;
500
501 tic6x_setup_default (cache);
502
503 cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
504
505 return cache;
506}
507
508static void
509tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache,
510 struct frame_id *this_id)
511{
512 struct tic6x_unwind_cache *cache;
513
514 if (*this_cache == NULL)
515 *this_cache = tic6x_make_stub_cache (this_frame);
19ba03f4 516 cache = (struct tic6x_unwind_cache *) *this_cache;
8cd64e00
YQ		 517
518 *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame));
519}
520
521static int
522tic6x_stub_unwind_sniffer (const struct frame_unwind *self,
523 struct frame_info *this_frame,
524 void **this_prologue_cache)
525{
526 CORE_ADDR addr_in_block;
527
528 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 529 if (in_plt_section (addr_in_block))
8cd64e00
YQ		 530 return 1;
531
532 return 0;
533}
534
535static const struct frame_unwind tic6x_stub_unwind =
536{
537 NORMAL_FRAME,
538 default_frame_unwind_stop_reason,
539 tic6x_stub_this_id,
540 tic6x_frame_prev_register,
541 NULL,
542 tic6x_stub_unwind_sniffer
543};
544
545/* Return the instruction on address PC. */
546
547static unsigned long
548tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc)
549{
550 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
551 return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order);
552}
553
554/* Compute the condition of INST if it is a conditional instruction. Always
555 return 1 if INST is not a conditional instruction. */
556
557static int
fb090cfa 558tic6x_condition_true (struct regcache *regcache, unsigned long inst)
8cd64e00
YQ		 559{
560 int register_number;
561 int register_value;
562 static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
563
564 register_number = register_numbers[(inst >> 29) & 7];
565 if (register_number == -1)
566 return 1;
567
fb090cfa 568 register_value = regcache_raw_get_signed (regcache, register_number);
8cd64e00
YQ		 569 if ((inst & 0x10000000) != 0)
570 return register_value == 0;
571 return register_value != 0;
572}
573
574/* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
575 instruction. */
576
577static int
578tic6x_register_number (int reg, int side, int crosspath)
579{
580 int r = (reg & 15) | ((crosspath ^ side) << 4);
581 if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */
582 r += 37;
583 return r;
584}
585
586static int
587tic6x_extract_signed_field (int value, int low_bit, int bits)
588{
589 int mask = (1 << bits) - 1;
590 int r = (value >> low_bit) & mask;
591 if ((r & (1 << (bits - 1))) != 0)
592 r -= mask + 1;
593 return r;
594}
595
596/* Determine where to set a single step breakpoint. */
597
598static CORE_ADDR
fb090cfa 599tic6x_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
8cd64e00 600{
fb090cfa 601 struct gdbarch *gdbarch = get_regcache_arch (regcache);
8cd64e00 602 unsigned long inst;
8cd64e00
YQ		 603 int register_number;
604 int last = 0;
605
606 do
607 {
608 inst = tic6x_fetch_instruction (gdbarch, pc);
609
610 last = !(inst & 1);
611
612 if (inst == TIC6X_INST_SWE)
613 {
614 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
615
616 if (tdep->syscall_next_pc != NULL)
fb090cfa 617 return tdep->syscall_next_pc (get_current_frame ());
8cd64e00
YQ		 618 }
619
fb090cfa 620 if (tic6x_condition_true (regcache, inst))
8cd64e00
YQ		 621 {
622 if ((inst & 0x0000007c) == 0x00000010)
623 {
624 /* B with displacement */
625 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
626 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
627 break;
628 }
629 if ((inst & 0x0f83effc) == 0x00000360)
630 {
631 /* B with register */
632
633 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
634 INST_S_BIT (inst),
635 INST_X_BIT (inst));
fb090cfa 636 pc = regcache_raw_get_unsigned (regcache, register_number);
8cd64e00
YQ		 637 break;
638 }
639 if ((inst & 0x00001ffc) == 0x00001020)
640 {
641 /* BDEC */
642 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
643 INST_S_BIT (inst), 0);
fb090cfa 644 if (regcache_raw_get_signed (regcache, register_number) >= 0)
8cd64e00
YQ		 645 {
646 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
647 pc += tic6x_extract_signed_field (inst, 7, 10) << 2;
648 }
649 break;
650 }
651 if ((inst & 0x00001ffc) == 0x00000120)
652 {
653 /* BNOP with displacement */
654 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
655 pc += tic6x_extract_signed_field (inst, 16, 12) << 2;
656 break;
657 }
658 if ((inst & 0x0f830ffe) == 0x00800362)
659 {
660 /* BNOP with register */
661 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
662 1, INST_X_BIT (inst));
fb090cfa 663 pc = regcache_raw_get_unsigned (regcache, register_number);
8cd64e00
YQ		 664 break;
665 }
666 if ((inst & 0x00001ffc) == 0x00000020)
667 {
668 /* BPOS */
669 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
670 INST_S_BIT (inst), 0);
fb090cfa 671 if (regcache_raw_get_signed (regcache, register_number) >= 0)
8cd64e00
YQ		 672 {
673 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
674 pc += tic6x_extract_signed_field (inst, 13, 10) << 2;
675 }
676 break;
677 }
678 if ((inst & 0xf000007c) == 0x10000010)
679 {
680 /* CALLP */
681 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
682 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
683 break;
684 }
685 }
686 pc += TIC6X_OPCODE_SIZE;
687 }
688 while (!last);
689 return pc;
690}
691
692/* This is the implementation of gdbarch method software_single_step. */
693
a0ff9e1a 694static std::vector<CORE_ADDR>
f5ea389a 695tic6x_software_single_step (struct regcache *regcache)
8cd64e00 696{
fb090cfa 697 CORE_ADDR next_pc = tic6x_get_next_pc (regcache, regcache_read_pc (regcache));
8cd64e00 698
a0ff9e1a 699 return {next_pc};
8cd64e00
YQ		 700}
701
702/* This is the implementation of gdbarch method frame_align. */
703
704static CORE_ADDR
705tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
706{
707 return align_down (addr, 8);
708}
709
8cd64e00
YQ		 710/* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
711 value into VALBUF. */
712
713static void
714tic6x_extract_return_value (struct type *valtype, struct regcache *regcache,
715 enum bfd_endian byte_order, gdb_byte *valbuf)
716{
717 int len = TYPE_LENGTH (valtype);
718
719 /* pointer types are returned in register A4,
720 up to 32-bit types in A4
721 up to 64-bit types in A5:A4 */
722 if (len <= 4)
723 {
724 /* In big-endian,
725 - one-byte structure or union occupies the LSB of single even register.
726 - for two-byte structure or union, the first byte occupies byte 1 of
727 register and the second byte occupies byte 0.
728 so, we read the contents in VAL from the LSBs of register. */
729 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
730 regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
731 valbuf);
732 else
733 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
734 }
735 else if (len <= 8)
736 {
737 /* For a 5-8 byte structure or union in big-endian, the first byte
738 occupies byte 3 (the MSB) of the upper (odd) register and the
739 remaining bytes fill the decreasingly significant bytes. 5-7
740 byte structures or unions have padding in the LSBs of the
741 lower (even) register. */
742 if (byte_order == BFD_ENDIAN_BIG)
743 {
744 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4);
745 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf);
746 }
747 else
748 {
749 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
750 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4);
751 }
752 }
753}
754
755/* Write into appropriate registers a function return value
756 of type TYPE, given in virtual format. */
757
758static void
759tic6x_store_return_value (struct type *valtype, struct regcache *regcache,
760 enum bfd_endian byte_order, const gdb_byte *valbuf)
761{
762 int len = TYPE_LENGTH (valtype);
763
764 /* return values of up to 8 bytes are returned in A5:A4 */
765
766 if (len <= 4)
767 {
768 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
769 regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
770 valbuf);
771 else
772 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
773 }
774 else if (len <= 8)
775 {
776 if (byte_order == BFD_ENDIAN_BIG)
777 {
778 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4);
779 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf);
780 }
781 else
782 {
783 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
784 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4);
785 }
786 }
787}
788
789/* This is the implementation of gdbarch method return_value. */
790
791static enum return_value_convention
6a3a010b 792tic6x_return_value (struct gdbarch *gdbarch, struct value *function,
8cd64e00
YQ		 793 struct type *type, struct regcache *regcache,
794 gdb_byte *readbuf, const gdb_byte *writebuf)
795{
18648a37
YQ		 796 /* In C++, when function returns an object, even its size is small
797 enough, it stii has to be passed via reference, pointed by register
798 A3. */
799 if (current_language->la_language == language_cplus)
800 {
801 if (type != NULL)
802 {
f168693b 803 type = check_typedef (type);
18648a37
YQ		 804 if (language_pass_by_reference (type))
805 return RETURN_VALUE_STRUCT_CONVENTION;
806 }
807 }
808
8cd64e00
YQ		 809 if (TYPE_LENGTH (type) > 8)
810 return RETURN_VALUE_STRUCT_CONVENTION;
811
812 if (readbuf)
813 tic6x_extract_return_value (type, regcache,
814 gdbarch_byte_order (gdbarch), readbuf);
815 if (writebuf)
816 tic6x_store_return_value (type, regcache,
817 gdbarch_byte_order (gdbarch), writebuf);
818
819 return RETURN_VALUE_REGISTER_CONVENTION;
820}
821
822/* This is the implementation of gdbarch method dummy_id. */
823
824static struct frame_id
825tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
826{
827 return frame_id_build
828 (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM),
829 get_frame_pc (this_frame));
830}
831
832/* Get the alignment requirement of TYPE. */
833
834static int
835tic6x_arg_type_alignment (struct type *type)
836{
837 int len = TYPE_LENGTH (check_typedef (type));
838 enum type_code typecode = TYPE_CODE (check_typedef (type));
839
840 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
841 {
842 /* The stack alignment of a structure (and union) passed by value is the
843 smallest power of two greater than or equal to its size.
844 This cannot exceed 8 bytes, which is the largest allowable size for
845 a structure passed by value. */
846
847 if (len <= 2)
848 return len;
849 else if (len <= 4)
850 return 4;
851 else if (len <= 8)
852 return 8;
853 else
854 gdb_assert_not_reached ("unexpected length of data");
855 }
856 else
857 {
858 if (len <= 4)
859 return 4;
860 else if (len == 8)
861 {
862 if (typecode == TYPE_CODE_COMPLEX)
863 return 4;
864 else
865 return 8;
866 }
867 else if (len == 16)
868 {
869 if (typecode == TYPE_CODE_COMPLEX)
870 return 8;
871 else
872 return 16;
873 }
874 else
875 internal_error (__FILE__, __LINE__, _("unexpected length %d of type"),
876 len);
877 }
878}
879
880/* This is the implementation of gdbarch method push_dummy_call. */
881
882static CORE_ADDR
883tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
884 struct regcache *regcache, CORE_ADDR bp_addr,
885 int nargs, struct value **args, CORE_ADDR sp,
886 int struct_return, CORE_ADDR struct_addr)
887{
888 int argreg = 0;
889 int argnum;
8cd64e00
YQ		 890 int stack_offset = 4;
891 int references_offset = 4;
892 CORE_ADDR func_addr = find_function_addr (function, NULL);
893 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
894 struct type *func_type = value_type (function);
895 /* The first arg passed on stack. Mostly the first 10 args are passed by
896 registers. */
897 int first_arg_on_stack = 10;
8cd64e00 898
8cd64e00
YQ		 899 /* Set the return address register to point to the entry point of
900 the program, where a breakpoint lies in wait. */
901 regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr);
902
903 /* The caller must pass an argument in A3 containing a destination address
904 for the returned value. The callee returns the object by copying it to
905 the address in A3. */
906 if (struct_return)
907 regcache_cooked_write_unsigned (regcache, 3, struct_addr);
8cd64e00
YQ		 908
909 /* Determine the type of this function. */
910 func_type = check_typedef (func_type);
911 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
912 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
913
914 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
915 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
916
917 /* For a variadic C function, the last explicitly declared argument and all
918 remaining arguments are passed on the stack. */
919 if (TYPE_VARARGS (func_type))
920 first_arg_on_stack = TYPE_NFIELDS (func_type) - 1;
921
18648a37
YQ		 922 /* Now make space on the stack for the args. */
923 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 924 {
925 int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
926 if (argnum >= 10 - argreg)
927 references_offset += len;
928 stack_offset += len;
929 }
930 sp -= stack_offset;
931 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
932 Stack Alignment. */
933 sp = align_down (sp, 8);
934 stack_offset = 4;
935
936 /* Now load as many as possible of the first arguments into
937 registers, and push the rest onto the stack. Loop through args
938 from first to last. */
18648a37 939 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 940 {
941 const gdb_byte *val;
942 struct value *arg = args[argnum];
943 struct type *arg_type = check_typedef (value_type (arg));
944 int len = TYPE_LENGTH (arg_type);
945 enum type_code typecode = TYPE_CODE (arg_type);
946
947 val = value_contents (arg);
948
949 /* Copy the argument to general registers or the stack in
950 register-sized pieces. */
951 if (argreg < first_arg_on_stack)
952 {
953 if (len <= 4)
954 {
955 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
956 {
957 /* In big-endian,
958 - one-byte structure or union occupies the LSB of single
959 even register.
960 - for two-byte structure or union, the first byte
961 occupies byte 1 of register and the second byte occupies
962 byte 0.
963 so, we write the contents in VAL to the lsp of
964 register. */
965 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
966 regcache_cooked_write_part (regcache, arg_regs[argreg],
967 4 - len, len, val);
968 else
969 regcache_cooked_write (regcache, arg_regs[argreg], val);
970 }
971 else
972 {
973 /* The argument is being passed by value in a single
974 register. */
975 CORE_ADDR regval = extract_unsigned_integer (val, len,
976 byte_order);
977
978 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
979 regval);
980 }
981 }
982 else
983 {
984 if (len <= 8)
985 {
986 if (typecode == TYPE_CODE_STRUCT
987 || typecode == TYPE_CODE_UNION)
988 {
989 /* For a 5-8 byte structure or union in big-endian, the
990 first byte occupies byte 3 (the MSB) of the upper (odd)
991 register and the remaining bytes fill the decreasingly
992 significant bytes. 5-7 byte structures or unions have
993 padding in the LSBs of the lower (even) register. */
994 if (byte_order == BFD_ENDIAN_BIG)
995 {
996 regcache_cooked_write (regcache,
997 arg_regs[argreg] + 1, val);
998 regcache_cooked_write_part (regcache,
999 arg_regs[argreg], 0,
1000 len - 4, val + 4);
1001 }
1002 else
1003 {
1004 regcache_cooked_write (regcache, arg_regs[argreg],
1005 val);
1006 regcache_cooked_write_part (regcache,
1007 arg_regs[argreg] + 1, 0,
1008 len - 4, val + 4);
1009 }
1010 }
1011 else
1012 {
1013 /* The argument is being passed by value in a pair of
1014 registers. */
1015 ULONGEST regval = extract_unsigned_integer (val, len,
1016 byte_order);
1017
1018 regcache_cooked_write_unsigned (regcache,
1019 arg_regs[argreg],
1020 regval);
1021 regcache_cooked_write_unsigned (regcache,
1022 arg_regs[argreg] + 1,
1023 regval >> 32);
1024 }
1025 }
1026 else
1027 {
1028 /* The argument is being passed by reference in a single
1029 register. */
1030 CORE_ADDR addr;
1031
1032 /* It is not necessary to adjust REFERENCES_OFFSET to
1033 8-byte aligned in some cases, in which 4-byte alignment
1034 is sufficient. For simplicity, we adjust
1035 REFERENCES_OFFSET to 8-byte aligned. */
1036 references_offset = align_up (references_offset, 8);
1037
1038 addr = sp + references_offset;
1039 write_memory (addr, val, len);
1040 references_offset += align_up (len, 4);
1041 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
1042 addr);
1043 }
1044 }
1045 argreg++;
1046 }
1047 else
1048 {
1049 /* The argument is being passed on the stack. */
1050 CORE_ADDR addr;
1051
1052 /* There are six different cases of alignment, and these rules can
1053 be found in tic6x_arg_type_alignment:
1054
1055 1) 4-byte aligned if size is less than or equal to 4 byte, such
1056 as short, int, struct, union etc.
1057 2) 8-byte aligned if size is less than or equal to 8-byte, such
1058 as double, long long,
1059 3) 4-byte aligned if it is of type _Complex float, even its size
1060 is 8-byte.
1061 4) 8-byte aligned if it is of type _Complex double or _Complex
1062 long double, even its size is 16-byte. Because, the address of
1063 variable is passed as reference.
1064 5) struct and union larger than 8-byte are passed by reference, so
1065 it is 4-byte aligned.
1066 6) struct and union of size between 4 byte and 8 byte varies.
1067 alignment of struct variable is the alignment of its first field,
1068 while alignment of union variable is the max of all its fields'
1069 alignment. */
1070
1071 if (len <= 4)
1072 ; /* Default is 4-byte aligned. Nothing to be done. */
1073 else if (len <= 8)
1074 stack_offset = align_up (stack_offset,
1075 tic6x_arg_type_alignment (arg_type));
1076 else if (len == 16)
1077 {
1078 /* _Complex double or _Complex long double */
1079 if (typecode == TYPE_CODE_COMPLEX)
1080 {
1081 /* The argument is being passed by reference on stack. */
1082 CORE_ADDR addr;
1083 references_offset = align_up (references_offset, 8);
1084
1085 addr = sp + references_offset;
1086 /* Store variable on stack. */
1087 write_memory (addr, val, len);
1088
1089 references_offset += align_up (len, 4);
1090
1091 /* Pass the address of variable on stack as reference. */
1092 store_unsigned_integer ((gdb_byte *) val, 4, byte_order,
1093 addr);
1094 len = 4;
1095
1096 }
1097 else
1098 internal_error (__FILE__, __LINE__,
1099 _("unexpected type %d of arg %d"),
1100 typecode, argnum);
1101 }
1102 else
1103 internal_error (__FILE__, __LINE__,
1104 _("unexpected length %d of arg %d"), len, argnum);
1105
1106 addr = sp + stack_offset;
1107 write_memory (addr, val, len);
1108 stack_offset += align_up (len, 4);
1109 }
1110 }
1111
1112 regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp);
1113
1114 /* Return adjusted stack pointer. */
1115 return sp;
1116}
1117
c9cf6e20 1118/* This is the implementation of gdbarch method stack_frame_destroyed_p. */
8cd64e00
YQ		 1119
1120static int
c9cf6e20 1121tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
8cd64e00
YQ		 1122{
1123 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
1124 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1125 if ((inst & 0x0f83effc) == 0x360)
1126 {
1127 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
1128 INST_S_BIT (inst),
1129 INST_X_BIT (inst));
1130 if (src2 == TIC6X_RA_REGNUM)
1131 return 1;
1132 }
1133
1134 return 0;
1135}
1136
1137/* This is the implementation of gdbarch method get_longjmp_target. */
1138
1139static int
1140tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1141{
1142 struct gdbarch *gdbarch = get_frame_arch (frame);
1143 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1144 CORE_ADDR jb_addr;
e362b510 1145 gdb_byte buf[4];
8cd64e00
YQ		 1146
1147 /* JMP_BUF is passed by reference in A4. */
1148 jb_addr = get_frame_register_unsigned (frame, 4);
1149
1150 /* JMP_BUF contains 13 elements of type int, and return address is stored
1151 in the last slot. */
1152 if (target_read_memory (jb_addr + 12 * 4, buf, 4))
1153 return 0;
1154
1155 *pc = extract_unsigned_integer (buf, 4, byte_order);
1156
1157 return 1;
1158}
1159
18648a37
YQ		 1160/* This is the implementation of gdbarch method
1161 return_in_first_hidden_param_p. */
1162
1163static int
1164tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
1165 struct type *type)
1166{
1167 return 0;
1168}
1169
8cd64e00
YQ		 1170static struct gdbarch *
1171tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1172{
1173 struct gdbarch *gdbarch;
1174 struct gdbarch_tdep *tdep;
1175 struct tdesc_arch_data *tdesc_data = NULL;
1176 const struct target_desc *tdesc = info.target_desc;
1177 int has_gp = 0;
1178
1179 /* Check any target description for validity. */
1180 if (tdesc_has_registers (tdesc))
1181 {
1182 const struct tdesc_feature *feature;
1183 int valid_p, i;
1184
1185 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core");
1186
1187 if (feature == NULL)
1188 return NULL;
1189
1190 tdesc_data = tdesc_data_alloc ();
1191
1192 valid_p = 1;
1193 for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */
1194 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1195 tic6x_register_names[i]);
1196
1197 /* CSR */
1198 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1199 tic6x_register_names[TIC6X_CSR_REGNUM]);
1200 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1201 tic6x_register_names[TIC6X_PC_REGNUM]);
1202
1203 if (!valid_p)
1204 {
1205 tdesc_data_cleanup (tdesc_data);
1206 return NULL;
1207 }
1208
1209 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp");
1210 if (feature)
1211 {
1212 int j = 0;
1213 static const char *const gp[] =
1214 {
1215 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1216 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1217 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1218 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1219 };
1220
1221 has_gp = 1;
1222 valid_p = 1;
1223 for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */
1224 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1225 gp[j]);
1226
1227 if (!valid_p)
1228 {
1229 tdesc_data_cleanup (tdesc_data);
1230 return NULL;
1231 }
1232 }
1233
1234 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp");
1235 if (feature)
1236 {
1237 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR");
1238 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC");
1239 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC");
1240
1241 if (!valid_p)
1242 {
1243 tdesc_data_cleanup (tdesc_data);
1244 return NULL;
1245 }
1246 }
1247
1248 }
1249
1250 /* Find a candidate among extant architectures. */
1251 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1252 arches != NULL;
1253 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1254 {
1255 tdep = gdbarch_tdep (arches->gdbarch);
1256
1257 if (has_gp != tdep->has_gp)
1258 continue;
1259
1260 if (tdep && tdep->breakpoint)
1261 return arches->gdbarch;
1262 }
1263
8d749320 1264 tdep = XCNEW (struct gdbarch_tdep);
8cd64e00
YQ		 1265
1266 tdep->has_gp = has_gp;
1267 gdbarch = gdbarch_alloc (&info, tdep);
1268
1269 /* Data type sizes. */
1270 set_gdbarch_ptr_bit (gdbarch, 32);
1271 set_gdbarch_addr_bit (gdbarch, 32);
1272 set_gdbarch_short_bit (gdbarch, 16);
1273 set_gdbarch_int_bit (gdbarch, 32);
1274 set_gdbarch_long_bit (gdbarch, 32);
1275 set_gdbarch_long_long_bit (gdbarch, 64);
1276 set_gdbarch_float_bit (gdbarch, 32);
1277 set_gdbarch_double_bit (gdbarch, 64);
1278
1279 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1280 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1281
1282 /* The register set. */
1283 set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS);
1284 set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM);
1285 set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM);
1286
1287 set_gdbarch_register_name (gdbarch, tic6x_register_name);
1288 set_gdbarch_register_type (gdbarch, tic6x_register_type);
1289
1290 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1291
1292 set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue);
04180708
YQ		 1293 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1294 tic6x_breakpoint_kind_from_pc);
1295 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1296 tic6x_sw_breakpoint_from_kind);
8cd64e00
YQ		 1297
1298 set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc);
1299 set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp);
1300
1301 /* Unwinding. */
1302 dwarf2_append_unwinders (gdbarch);
1303
1304 frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind);
1305 frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind);
195abc10 1306 frame_base_set_default (gdbarch, &tic6x_frame_base);
8cd64e00
YQ		 1307
1308 dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg);
1309
1310 /* Single stepping. */
1311 set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step);
1312
8cd64e00
YQ		 1313 /* Call dummy code. */
1314 set_gdbarch_frame_align (gdbarch, tic6x_frame_align);
1315
8cd64e00
YQ		 1316 set_gdbarch_return_value (gdbarch, tic6x_return_value);
1317
1318 set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id);
1319
1320 /* Enable inferior call support. */
1321 set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call);
1322
1323 set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target);
1324
c9cf6e20 1325 set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p);
8cd64e00 1326
18648a37
YQ		 1327 set_gdbarch_return_in_first_hidden_param_p (gdbarch,
1328 tic6x_return_in_first_hidden_param_p);
1329
8cd64e00
YQ		 1330 /* Hook in ABI-specific overrides, if they have been registered. */
1331 gdbarch_init_osabi (info, gdbarch);
1332
1333 if (tdesc_data)
1334 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
1335
1336 return gdbarch;
1337}
1338
1339void
1340_initialize_tic6x_tdep (void)
1341{
1342 register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init);
1343
1344 initialize_tdesc_tic6x_c64xp ();
1345 initialize_tdesc_tic6x_c64x ();
1346 initialize_tdesc_tic6x_c62x ();
1347}
GDB Binutils - Deliverables
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