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Identify verilog dump tests as such.
[deliverable/binutils-gdb.git] / gdb / tic6x-tdep.c
CommitLineData
8cd64e00
YQ		 1/* Target dependent code for GDB on TI C6x systems.
2
618f726f 3 Copyright (C) 2010-2016 Free Software Foundation, Inc.
8cd64e00
YQ		 4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "frame.h"
24#include "frame-unwind.h"
25#include "frame-base.h"
26#include "trad-frame.h"
27#include "dwarf2-frame.h"
28#include "symtab.h"
29#include "inferior.h"
30#include "gdbtypes.h"
31#include "gdbcore.h"
32#include "gdbcmd.h"
33#include "target.h"
34#include "dis-asm.h"
35#include "regcache.h"
36#include "value.h"
37#include "symfile.h"
38#include "arch-utils.h"
39#include "floatformat.h"
40#include "glibc-tdep.h"
41#include "infcall.h"
42#include "regset.h"
43#include "tramp-frame.h"
44#include "linux-tdep.h"
45#include "solib.h"
46#include "objfiles.h"
8cd64e00
YQ		 47#include "osabi.h"
48#include "tic6x-tdep.h"
49#include "language.h"
50#include "target-descriptions.h"
325fac50 51#include <algorithm>
8cd64e00
YQ		 52
53#include "features/tic6x-c64xp.c"
54#include "features/tic6x-c64x.c"
55#include "features/tic6x-c62x.c"
56
57#define TIC6X_OPCODE_SIZE 4
58#define TIC6X_FETCH_PACKET_SIZE 32
59
60#define INST_S_BIT(INST) ((INST >> 1) & 1)
61#define INST_X_BIT(INST) ((INST >> 12) & 1)
62
85661b1e
YQ		 63const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 };
64const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 };
65
8cd64e00
YQ		 66struct tic6x_unwind_cache
67{
68 /* The frame's base, optionally used by the high-level debug info. */
69 CORE_ADDR base;
70
71 /* The previous frame's inner most stack address. Used as this
72 frame ID's stack_addr. */
73 CORE_ADDR cfa;
74
75 /* The address of the first instruction in this function */
76 CORE_ADDR pc;
77
78 /* Which register holds the return address for the frame. */
79 int return_regnum;
80
81 /* The offset of register saved on stack. If register is not saved, the
82 corresponding element is -1. */
83 CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS];
84};
85
86
87/* Name of TI C6x core registers. */
88static const char *const tic6x_register_names[] =
89{
90 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
91 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
92 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
93 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
94 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
95 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
96 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
97 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
98 "CSR", "PC", /* 32 33 */
99};
100
101/* This array maps the arguments to the register number which passes argument
102 in function call according to C6000 ELF ABI. */
103static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
104
105/* This is the implementation of gdbarch method register_name. */
106
107static const char *
108tic6x_register_name (struct gdbarch *gdbarch, int regno)
109{
110 if (regno < 0)
111 return NULL;
112
113 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
114 return tdesc_register_name (gdbarch, regno);
115 else if (regno >= ARRAY_SIZE (tic6x_register_names))
116 return "";
117 else
118 return tic6x_register_names[regno];
119}
120
121/* This is the implementation of gdbarch method register_type. */
122
123static struct type *
124tic6x_register_type (struct gdbarch *gdbarch, int regno)
125{
126
127 if (regno == TIC6X_PC_REGNUM)
128 return builtin_type (gdbarch)->builtin_func_ptr;
129 else
130 return builtin_type (gdbarch)->builtin_uint32;
131}
132
133static void
134tic6x_setup_default (struct tic6x_unwind_cache *cache)
135{
136 int i;
137
138 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
139 cache->reg_saved[i] = -1;
140}
141
142static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR);
143static int tic6x_register_number (int reg, int side, int crosspath);
144
145/* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
146 Bail out early if CURRENT_PC is reached. Returns the address of the first
147 instruction after the prologue. */
148
693be288 149static CORE_ADDR
8cd64e00
YQ		 150tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
151 const CORE_ADDR current_pc,
152 struct tic6x_unwind_cache *cache,
153 struct frame_info *this_frame)
154{
8cd64e00
YQ		 155 unsigned long inst;
156 unsigned int src_reg, base_reg, dst_reg;
157 int i;
158 CORE_ADDR pc = start_pc;
159 CORE_ADDR return_pc = start_pc;
160 int frame_base_offset_to_sp = 0;
161 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
162 int non_stw_insn_counter = 0;
163
164 if (start_pc >= current_pc)
165 return_pc = current_pc;
166
167 cache->base = 0;
168
169 /* The landmarks in prologue is one or two SUB instructions to SP.
170 Instructions on setting up dsbt are in the last part of prologue, if
171 needed. In maxim, prologue can be divided to three parts by two
172 `sub sp, xx, sp' insns. */
173
174 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
175 2nd one is optional. */
176 while (pc < current_pc)
177 {
8cd64e00
YQ		 178 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
179
180 if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0
181 || (inst & 0x0ffc) == 0x9c0)
182 {
183 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
184 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
185 INST_S_BIT (inst), 0);
186 unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f,
187 INST_S_BIT (inst), 0);
188
189 if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM)
190 {
191 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
192 offset. The constant offset is decoded in bit 13-17 in all
193 these three kinds of instructions. */
194 unsigned int ucst5 = (inst >> 13) & 0x1f;
195
196 if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */
197 frame_base_offset_to_sp += ucst5 << 2;
198 else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */
199 frame_base_offset_to_sp += ucst5 << 1;
200 else if ((inst & 0x0ffc) == 0x9c0) /* SUB */
201 frame_base_offset_to_sp += ucst5;
202 else
203 gdb_assert_not_reached ("unexpected instruction");
204
205 return_pc = pc + 4;
206 }
207 }
208 else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
209 {
210 /* The y bit determines which file base is read from. */
211 base_reg = tic6x_register_number ((inst >> 18) & 0x1f,
212 (inst >> 7) & 1, 0);
213
214 if (base_reg == TIC6X_SP_REGNUM)
215 {
216 src_reg = tic6x_register_number ((inst >> 23) & 0x1f,
217 INST_S_BIT (inst), 0);
218
219 cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2;
220
221 return_pc = pc + 4;
222 }
223 non_stw_insn_counter = 0;
224 }
225 else
226 {
227 non_stw_insn_counter++;
228 /* Following instruction sequence may be emitted in prologue:
229
230 <+0>: subah .D2 b15,28,b15
231 <+4>: or .L2X 0,a4,b0
232 <+8>: || stw .D2T2 b14,*+b15(56)
233 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
234 <+16>:|| stw .D2T1 a10,*+b15(48)
235 <+20>:stw .D2T2 b3,*+b15(52)
236 <+24>:stw .D2T1 a4,*+b15(40)
237
238 we should look forward for next instruction instead of breaking loop
239 here. So far, we allow almost two sequential non-stw instructions
240 in prologue. */
241 if (non_stw_insn_counter >= 2)
242 break;
243 }
244
245
246 pc += 4;
247 }
248 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
249 ldw .D2T2 *+b14(0),b14 */
250 inst = tic6x_fetch_instruction (gdbarch, pc);
251 /* The s bit determines which file dst will be loaded into, same effect as
252 other places. */
253 dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0);
254 /* The y bit (bit 7), instead of s bit, determines which file base be
255 used. */
256 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0);
257
258 if ((inst & 0x164) == 0x64 /* ldw */
259 && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */
260 && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */
261 {
262 return_pc = pc + 4;
263 }
264
265 if (this_frame)
266 {
267 cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
268
269 if (cache->reg_saved[TIC6X_FP_REGNUM] != -1)
270 {
271 /* If the FP now holds an offset from the CFA then this is a frame
272 which uses the frame pointer. */
273
274 cache->cfa = get_frame_register_unsigned (this_frame,
275 TIC6X_FP_REGNUM);
276 }
277 else
278 {
279 /* FP doesn't hold an offset from the CFA. If SP still holds an
280 offset from the CFA then we might be in a function which omits
281 the frame pointer. */
282
283 cache->cfa = cache->base + frame_base_offset_to_sp;
284 }
285 }
286
287 /* Adjust all the saved registers such that they contain addresses
288 instead of offsets. */
289 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
290 if (cache->reg_saved[i] != -1)
291 cache->reg_saved[i] = cache->base + cache->reg_saved[i];
292
293 return return_pc;
294}
295
296/* This is the implementation of gdbarch method skip_prologue. */
297
693be288 298static CORE_ADDR
8cd64e00
YQ		 299tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
300{
8cd64e00
YQ		 301 CORE_ADDR func_addr;
302 struct tic6x_unwind_cache cache;
303
304 /* See if we can determine the end of the prologue via the symbol table.
305 If so, then return either PC, or the PC after the prologue, whichever is
306 greater. */
307 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
308 {
309 CORE_ADDR post_prologue_pc
310 = skip_prologue_using_sal (gdbarch, func_addr);
311 if (post_prologue_pc != 0)
325fac50 312 return std::max (start_pc, post_prologue_pc);
8cd64e00
YQ		 313 }
314
315 /* Can't determine prologue from the symbol table, need to examine
316 instructions. */
317 return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache,
318 NULL);
319}
320
cd6c3b4f
YQ		 321/* Implement the breakpoint_kind_from_pc gdbarch method. */
322
d19280ad
YQ		 323static int
324tic6x_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
325{
326 return 4;
327}
8cd64e00 328
cd6c3b4f
YQ		 329/* Implement the sw_breakpoint_from_kind gdbarch method. */
330
948f8e3d 331static const gdb_byte *
d19280ad 332tic6x_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
8cd64e00
YQ		 333{
334 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
335
d19280ad 336 *size = kind;
8cd64e00
YQ		 337
338 if (tdep == NULL || tdep->breakpoint == NULL)
339 {
340 if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch))
341 return tic6x_bkpt_illegal_opcode_be;
342 else
343 return tic6x_bkpt_illegal_opcode_le;
344 }
345 else
346 return tdep->breakpoint;
347}
348
349/* This is the implementation of gdbarch method print_insn. */
350
351static int
352tic6x_print_insn (bfd_vma memaddr, disassemble_info *info)
353{
354 return print_insn_tic6x (memaddr, info);
355}
356
357static void
358tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
359 struct dwarf2_frame_state_reg *reg,
360 struct frame_info *this_frame)
361{
362 /* Mark the PC as the destination for the return address. */
363 if (regnum == gdbarch_pc_regnum (gdbarch))
364 reg->how = DWARF2_FRAME_REG_RA;
365
366 /* Mark the stack pointer as the call frame address. */
367 else if (regnum == gdbarch_sp_regnum (gdbarch))
368 reg->how = DWARF2_FRAME_REG_CFA;
369
370 /* The above was taken from the default init_reg in dwarf2-frame.c
371 while the below is c6x specific. */
372
373 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
374 callee-save. */
375 else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31))
376 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
377 else
378 /* All other registers are caller-save. */
379 reg->how = DWARF2_FRAME_REG_UNDEFINED;
380}
381
382/* This is the implementation of gdbarch method unwind_pc. */
383
384static CORE_ADDR
385tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
386{
387 gdb_byte buf[8];
388
389 frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf);
390 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
391}
392
393/* This is the implementation of gdbarch method unwind_sp. */
394
395static CORE_ADDR
396tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
397{
398 return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM);
399}
400
401
402/* Frame base handling. */
403
693be288 404static struct tic6x_unwind_cache*
8cd64e00
YQ		 405tic6x_frame_unwind_cache (struct frame_info *this_frame,
406 void **this_prologue_cache)
407{
408 struct gdbarch *gdbarch = get_frame_arch (this_frame);
409 CORE_ADDR current_pc;
410 struct tic6x_unwind_cache *cache;
8cd64e00
YQ		 411
412 if (*this_prologue_cache)
19ba03f4 413 return (struct tic6x_unwind_cache *) *this_prologue_cache;
8cd64e00
YQ		 414
415 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
416 (*this_prologue_cache) = cache;
417
418 cache->return_regnum = TIC6X_RA_REGNUM;
419
420 tic6x_setup_default (cache);
421
422 cache->pc = get_frame_func (this_frame);
423 current_pc = get_frame_pc (this_frame);
424
425 /* Prologue analysis does the rest... */
426 if (cache->pc != 0)
427 tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
428
429 return cache;
430}
431
432static void
433tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache,
434 struct frame_id *this_id)
435{
436 struct tic6x_unwind_cache *cache =
437 tic6x_frame_unwind_cache (this_frame, this_cache);
438
439 /* This marks the outermost frame. */
440 if (cache->base == 0)
441 return;
442
443 (*this_id) = frame_id_build (cache->cfa, cache->pc);
444}
445
446static struct value *
447tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache,
448 int regnum)
449{
450 struct tic6x_unwind_cache *cache =
451 tic6x_frame_unwind_cache (this_frame, this_cache);
452
453 gdb_assert (regnum >= 0);
454
455 /* The PC of the previous frame is stored in the RA register of
456 the current frame. Frob regnum so that we pull the value from
457 the correct place. */
458 if (regnum == TIC6X_PC_REGNUM)
459 regnum = cache->return_regnum;
460
461 if (regnum == TIC6X_SP_REGNUM && cache->cfa)
462 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
463
464 /* If we've worked out where a register is stored then load it from
465 there. */
466 if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1)
467 return frame_unwind_got_memory (this_frame, regnum,
468 cache->reg_saved[regnum]);
469
470 return frame_unwind_got_register (this_frame, regnum, regnum);
471}
472
473static CORE_ADDR
474tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache)
475{
476 struct tic6x_unwind_cache *info
477 = tic6x_frame_unwind_cache (this_frame, this_cache);
478 return info->base;
479}
480
481static const struct frame_unwind tic6x_frame_unwind =
482{
483 NORMAL_FRAME,
484 default_frame_unwind_stop_reason,
485 tic6x_frame_this_id,
486 tic6x_frame_prev_register,
487 NULL,
488 default_frame_sniffer
489};
490
491static const struct frame_base tic6x_frame_base =
492{
493 &tic6x_frame_unwind,
494 tic6x_frame_base_address,
495 tic6x_frame_base_address,
496 tic6x_frame_base_address
497};
498
499
500static struct tic6x_unwind_cache *
501tic6x_make_stub_cache (struct frame_info *this_frame)
502{
503 struct tic6x_unwind_cache *cache;
504
505 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
506
507 cache->return_regnum = TIC6X_RA_REGNUM;
508
509 tic6x_setup_default (cache);
510
511 cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
512
513 return cache;
514}
515
516static void
517tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache,
518 struct frame_id *this_id)
519{
520 struct tic6x_unwind_cache *cache;
521
522 if (*this_cache == NULL)
523 *this_cache = tic6x_make_stub_cache (this_frame);
19ba03f4 524 cache = (struct tic6x_unwind_cache *) *this_cache;
8cd64e00
YQ		 525
526 *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame));
527}
528
529static int
530tic6x_stub_unwind_sniffer (const struct frame_unwind *self,
531 struct frame_info *this_frame,
532 void **this_prologue_cache)
533{
534 CORE_ADDR addr_in_block;
535
536 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 537 if (in_plt_section (addr_in_block))
8cd64e00
YQ		 538 return 1;
539
540 return 0;
541}
542
543static const struct frame_unwind tic6x_stub_unwind =
544{
545 NORMAL_FRAME,
546 default_frame_unwind_stop_reason,
547 tic6x_stub_this_id,
548 tic6x_frame_prev_register,
549 NULL,
550 tic6x_stub_unwind_sniffer
551};
552
553/* Return the instruction on address PC. */
554
555static unsigned long
556tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc)
557{
558 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
559 return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order);
560}
561
562/* Compute the condition of INST if it is a conditional instruction. Always
563 return 1 if INST is not a conditional instruction. */
564
565static int
566tic6x_condition_true (struct frame_info *frame, unsigned long inst)
567{
568 int register_number;
569 int register_value;
570 static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
571
572 register_number = register_numbers[(inst >> 29) & 7];
573 if (register_number == -1)
574 return 1;
575
576 register_value = get_frame_register_signed (frame, register_number);
577 if ((inst & 0x10000000) != 0)
578 return register_value == 0;
579 return register_value != 0;
580}
581
582/* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
583 instruction. */
584
585static int
586tic6x_register_number (int reg, int side, int crosspath)
587{
588 int r = (reg & 15) | ((crosspath ^ side) << 4);
589 if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */
590 r += 37;
591 return r;
592}
593
594static int
595tic6x_extract_signed_field (int value, int low_bit, int bits)
596{
597 int mask = (1 << bits) - 1;
598 int r = (value >> low_bit) & mask;
599 if ((r & (1 << (bits - 1))) != 0)
600 r -= mask + 1;
601 return r;
602}
603
604/* Determine where to set a single step breakpoint. */
605
606static CORE_ADDR
607tic6x_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
608{
609 struct gdbarch *gdbarch = get_frame_arch (frame);
610 unsigned long inst;
8cd64e00
YQ		 611 int register_number;
612 int last = 0;
613
614 do
615 {
616 inst = tic6x_fetch_instruction (gdbarch, pc);
617
618 last = !(inst & 1);
619
620 if (inst == TIC6X_INST_SWE)
621 {
622 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
623
624 if (tdep->syscall_next_pc != NULL)
625 return tdep->syscall_next_pc (frame);
626 }
627
628 if (tic6x_condition_true (frame, inst))
629 {
630 if ((inst & 0x0000007c) == 0x00000010)
631 {
632 /* B with displacement */
633 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
634 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
635 break;
636 }
637 if ((inst & 0x0f83effc) == 0x00000360)
638 {
639 /* B with register */
640
641 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
642 INST_S_BIT (inst),
643 INST_X_BIT (inst));
644 pc = get_frame_register_unsigned (frame, register_number);
645 break;
646 }
647 if ((inst & 0x00001ffc) == 0x00001020)
648 {
649 /* BDEC */
650 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
651 INST_S_BIT (inst), 0);
652 if (get_frame_register_signed (frame, register_number) >= 0)
653 {
654 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
655 pc += tic6x_extract_signed_field (inst, 7, 10) << 2;
656 }
657 break;
658 }
659 if ((inst & 0x00001ffc) == 0x00000120)
660 {
661 /* BNOP with displacement */
662 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
663 pc += tic6x_extract_signed_field (inst, 16, 12) << 2;
664 break;
665 }
666 if ((inst & 0x0f830ffe) == 0x00800362)
667 {
668 /* BNOP with register */
669 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
670 1, INST_X_BIT (inst));
671 pc = get_frame_register_unsigned (frame, register_number);
672 break;
673 }
674 if ((inst & 0x00001ffc) == 0x00000020)
675 {
676 /* BPOS */
677 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
678 INST_S_BIT (inst), 0);
679 if (get_frame_register_signed (frame, register_number) >= 0)
680 {
681 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
682 pc += tic6x_extract_signed_field (inst, 13, 10) << 2;
683 }
684 break;
685 }
686 if ((inst & 0xf000007c) == 0x10000010)
687 {
688 /* CALLP */
689 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
690 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
691 break;
692 }
693 }
694 pc += TIC6X_OPCODE_SIZE;
695 }
696 while (!last);
697 return pc;
698}
699
700/* This is the implementation of gdbarch method software_single_step. */
701
93f9a11f 702static VEC (CORE_ADDR) *
8cd64e00
YQ		 703tic6x_software_single_step (struct frame_info *frame)
704{
8cd64e00 705 CORE_ADDR next_pc = tic6x_get_next_pc (frame, get_frame_pc (frame));
93f9a11f 706 VEC (CORE_ADDR) *next_pcs = NULL;
8cd64e00 707
93f9a11f 708 VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
8cd64e00 709
93f9a11f 710 return next_pcs;
8cd64e00
YQ		 711}
712
713/* This is the implementation of gdbarch method frame_align. */
714
715static CORE_ADDR
716tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
717{
718 return align_down (addr, 8);
719}
720
8cd64e00
YQ		 721/* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
722 value into VALBUF. */
723
724static void
725tic6x_extract_return_value (struct type *valtype, struct regcache *regcache,
726 enum bfd_endian byte_order, gdb_byte *valbuf)
727{
728 int len = TYPE_LENGTH (valtype);
729
730 /* pointer types are returned in register A4,
731 up to 32-bit types in A4
732 up to 64-bit types in A5:A4 */
733 if (len <= 4)
734 {
735 /* In big-endian,
736 - one-byte structure or union occupies the LSB of single even register.
737 - for two-byte structure or union, the first byte occupies byte 1 of
738 register and the second byte occupies byte 0.
739 so, we read the contents in VAL from the LSBs of register. */
740 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
741 regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
742 valbuf);
743 else
744 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
745 }
746 else if (len <= 8)
747 {
748 /* For a 5-8 byte structure or union in big-endian, the first byte
749 occupies byte 3 (the MSB) of the upper (odd) register and the
750 remaining bytes fill the decreasingly significant bytes. 5-7
751 byte structures or unions have padding in the LSBs of the
752 lower (even) register. */
753 if (byte_order == BFD_ENDIAN_BIG)
754 {
755 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4);
756 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf);
757 }
758 else
759 {
760 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
761 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4);
762 }
763 }
764}
765
766/* Write into appropriate registers a function return value
767 of type TYPE, given in virtual format. */
768
769static void
770tic6x_store_return_value (struct type *valtype, struct regcache *regcache,
771 enum bfd_endian byte_order, const gdb_byte *valbuf)
772{
773 int len = TYPE_LENGTH (valtype);
774
775 /* return values of up to 8 bytes are returned in A5:A4 */
776
777 if (len <= 4)
778 {
779 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
780 regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
781 valbuf);
782 else
783 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
784 }
785 else if (len <= 8)
786 {
787 if (byte_order == BFD_ENDIAN_BIG)
788 {
789 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4);
790 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf);
791 }
792 else
793 {
794 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
795 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4);
796 }
797 }
798}
799
800/* This is the implementation of gdbarch method return_value. */
801
802static enum return_value_convention
6a3a010b 803tic6x_return_value (struct gdbarch *gdbarch, struct value *function,
8cd64e00
YQ		 804 struct type *type, struct regcache *regcache,
805 gdb_byte *readbuf, const gdb_byte *writebuf)
806{
18648a37
YQ		 807 /* In C++, when function returns an object, even its size is small
808 enough, it stii has to be passed via reference, pointed by register
809 A3. */
810 if (current_language->la_language == language_cplus)
811 {
812 if (type != NULL)
813 {
f168693b 814 type = check_typedef (type);
18648a37
YQ		 815 if (language_pass_by_reference (type))
816 return RETURN_VALUE_STRUCT_CONVENTION;
817 }
818 }
819
8cd64e00
YQ		 820 if (TYPE_LENGTH (type) > 8)
821 return RETURN_VALUE_STRUCT_CONVENTION;
822
823 if (readbuf)
824 tic6x_extract_return_value (type, regcache,
825 gdbarch_byte_order (gdbarch), readbuf);
826 if (writebuf)
827 tic6x_store_return_value (type, regcache,
828 gdbarch_byte_order (gdbarch), writebuf);
829
830 return RETURN_VALUE_REGISTER_CONVENTION;
831}
832
833/* This is the implementation of gdbarch method dummy_id. */
834
835static struct frame_id
836tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
837{
838 return frame_id_build
839 (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM),
840 get_frame_pc (this_frame));
841}
842
843/* Get the alignment requirement of TYPE. */
844
845static int
846tic6x_arg_type_alignment (struct type *type)
847{
848 int len = TYPE_LENGTH (check_typedef (type));
849 enum type_code typecode = TYPE_CODE (check_typedef (type));
850
851 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
852 {
853 /* The stack alignment of a structure (and union) passed by value is the
854 smallest power of two greater than or equal to its size.
855 This cannot exceed 8 bytes, which is the largest allowable size for
856 a structure passed by value. */
857
858 if (len <= 2)
859 return len;
860 else if (len <= 4)
861 return 4;
862 else if (len <= 8)
863 return 8;
864 else
865 gdb_assert_not_reached ("unexpected length of data");
866 }
867 else
868 {
869 if (len <= 4)
870 return 4;
871 else if (len == 8)
872 {
873 if (typecode == TYPE_CODE_COMPLEX)
874 return 4;
875 else
876 return 8;
877 }
878 else if (len == 16)
879 {
880 if (typecode == TYPE_CODE_COMPLEX)
881 return 8;
882 else
883 return 16;
884 }
885 else
886 internal_error (__FILE__, __LINE__, _("unexpected length %d of type"),
887 len);
888 }
889}
890
891/* This is the implementation of gdbarch method push_dummy_call. */
892
893static CORE_ADDR
894tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
895 struct regcache *regcache, CORE_ADDR bp_addr,
896 int nargs, struct value **args, CORE_ADDR sp,
897 int struct_return, CORE_ADDR struct_addr)
898{
899 int argreg = 0;
900 int argnum;
8cd64e00
YQ		 901 int stack_offset = 4;
902 int references_offset = 4;
903 CORE_ADDR func_addr = find_function_addr (function, NULL);
904 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
905 struct type *func_type = value_type (function);
906 /* The first arg passed on stack. Mostly the first 10 args are passed by
907 registers. */
908 int first_arg_on_stack = 10;
8cd64e00 909
8cd64e00
YQ		 910 /* Set the return address register to point to the entry point of
911 the program, where a breakpoint lies in wait. */
912 regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr);
913
914 /* The caller must pass an argument in A3 containing a destination address
915 for the returned value. The callee returns the object by copying it to
916 the address in A3. */
917 if (struct_return)
918 regcache_cooked_write_unsigned (regcache, 3, struct_addr);
8cd64e00
YQ		 919
920 /* Determine the type of this function. */
921 func_type = check_typedef (func_type);
922 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
923 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
924
925 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
926 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
927
928 /* For a variadic C function, the last explicitly declared argument and all
929 remaining arguments are passed on the stack. */
930 if (TYPE_VARARGS (func_type))
931 first_arg_on_stack = TYPE_NFIELDS (func_type) - 1;
932
18648a37
YQ		 933 /* Now make space on the stack for the args. */
934 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 935 {
936 int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
937 if (argnum >= 10 - argreg)
938 references_offset += len;
939 stack_offset += len;
940 }
941 sp -= stack_offset;
942 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
943 Stack Alignment. */
944 sp = align_down (sp, 8);
945 stack_offset = 4;
946
947 /* Now load as many as possible of the first arguments into
948 registers, and push the rest onto the stack. Loop through args
949 from first to last. */
18648a37 950 for (argnum = 0; argnum < nargs; argnum++)
8cd64e00
YQ		 951 {
952 const gdb_byte *val;
953 struct value *arg = args[argnum];
954 struct type *arg_type = check_typedef (value_type (arg));
955 int len = TYPE_LENGTH (arg_type);
956 enum type_code typecode = TYPE_CODE (arg_type);
957
958 val = value_contents (arg);
959
960 /* Copy the argument to general registers or the stack in
961 register-sized pieces. */
962 if (argreg < first_arg_on_stack)
963 {
964 if (len <= 4)
965 {
966 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
967 {
968 /* In big-endian,
969 - one-byte structure or union occupies the LSB of single
970 even register.
971 - for two-byte structure or union, the first byte
972 occupies byte 1 of register and the second byte occupies
973 byte 0.
974 so, we write the contents in VAL to the lsp of
975 register. */
976 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
977 regcache_cooked_write_part (regcache, arg_regs[argreg],
978 4 - len, len, val);
979 else
980 regcache_cooked_write (regcache, arg_regs[argreg], val);
981 }
982 else
983 {
984 /* The argument is being passed by value in a single
985 register. */
986 CORE_ADDR regval = extract_unsigned_integer (val, len,
987 byte_order);
988
989 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
990 regval);
991 }
992 }
993 else
994 {
995 if (len <= 8)
996 {
997 if (typecode == TYPE_CODE_STRUCT
998 || typecode == TYPE_CODE_UNION)
999 {
1000 /* For a 5-8 byte structure or union in big-endian, the
1001 first byte occupies byte 3 (the MSB) of the upper (odd)
1002 register and the remaining bytes fill the decreasingly
1003 significant bytes. 5-7 byte structures or unions have
1004 padding in the LSBs of the lower (even) register. */
1005 if (byte_order == BFD_ENDIAN_BIG)
1006 {
1007 regcache_cooked_write (regcache,
1008 arg_regs[argreg] + 1, val);
1009 regcache_cooked_write_part (regcache,
1010 arg_regs[argreg], 0,
1011 len - 4, val + 4);
1012 }
1013 else
1014 {
1015 regcache_cooked_write (regcache, arg_regs[argreg],
1016 val);
1017 regcache_cooked_write_part (regcache,
1018 arg_regs[argreg] + 1, 0,
1019 len - 4, val + 4);
1020 }
1021 }
1022 else
1023 {
1024 /* The argument is being passed by value in a pair of
1025 registers. */
1026 ULONGEST regval = extract_unsigned_integer (val, len,
1027 byte_order);
1028
1029 regcache_cooked_write_unsigned (regcache,
1030 arg_regs[argreg],
1031 regval);
1032 regcache_cooked_write_unsigned (regcache,
1033 arg_regs[argreg] + 1,
1034 regval >> 32);
1035 }
1036 }
1037 else
1038 {
1039 /* The argument is being passed by reference in a single
1040 register. */
1041 CORE_ADDR addr;
1042
1043 /* It is not necessary to adjust REFERENCES_OFFSET to
1044 8-byte aligned in some cases, in which 4-byte alignment
1045 is sufficient. For simplicity, we adjust
1046 REFERENCES_OFFSET to 8-byte aligned. */
1047 references_offset = align_up (references_offset, 8);
1048
1049 addr = sp + references_offset;
1050 write_memory (addr, val, len);
1051 references_offset += align_up (len, 4);
1052 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
1053 addr);
1054 }
1055 }
1056 argreg++;
1057 }
1058 else
1059 {
1060 /* The argument is being passed on the stack. */
1061 CORE_ADDR addr;
1062
1063 /* There are six different cases of alignment, and these rules can
1064 be found in tic6x_arg_type_alignment:
1065
1066 1) 4-byte aligned if size is less than or equal to 4 byte, such
1067 as short, int, struct, union etc.
1068 2) 8-byte aligned if size is less than or equal to 8-byte, such
1069 as double, long long,
1070 3) 4-byte aligned if it is of type _Complex float, even its size
1071 is 8-byte.
1072 4) 8-byte aligned if it is of type _Complex double or _Complex
1073 long double, even its size is 16-byte. Because, the address of
1074 variable is passed as reference.
1075 5) struct and union larger than 8-byte are passed by reference, so
1076 it is 4-byte aligned.
1077 6) struct and union of size between 4 byte and 8 byte varies.
1078 alignment of struct variable is the alignment of its first field,
1079 while alignment of union variable is the max of all its fields'
1080 alignment. */
1081
1082 if (len <= 4)
1083 ; /* Default is 4-byte aligned. Nothing to be done. */
1084 else if (len <= 8)
1085 stack_offset = align_up (stack_offset,
1086 tic6x_arg_type_alignment (arg_type));
1087 else if (len == 16)
1088 {
1089 /* _Complex double or _Complex long double */
1090 if (typecode == TYPE_CODE_COMPLEX)
1091 {
1092 /* The argument is being passed by reference on stack. */
1093 CORE_ADDR addr;
1094 references_offset = align_up (references_offset, 8);
1095
1096 addr = sp + references_offset;
1097 /* Store variable on stack. */
1098 write_memory (addr, val, len);
1099
1100 references_offset += align_up (len, 4);
1101
1102 /* Pass the address of variable on stack as reference. */
1103 store_unsigned_integer ((gdb_byte *) val, 4, byte_order,
1104 addr);
1105 len = 4;
1106
1107 }
1108 else
1109 internal_error (__FILE__, __LINE__,
1110 _("unexpected type %d of arg %d"),
1111 typecode, argnum);
1112 }
1113 else
1114 internal_error (__FILE__, __LINE__,
1115 _("unexpected length %d of arg %d"), len, argnum);
1116
1117 addr = sp + stack_offset;
1118 write_memory (addr, val, len);
1119 stack_offset += align_up (len, 4);
1120 }
1121 }
1122
1123 regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp);
1124
1125 /* Return adjusted stack pointer. */
1126 return sp;
1127}
1128
c9cf6e20 1129/* This is the implementation of gdbarch method stack_frame_destroyed_p. */
8cd64e00
YQ		 1130
1131static int
c9cf6e20 1132tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
8cd64e00
YQ		 1133{
1134 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
1135 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1136 if ((inst & 0x0f83effc) == 0x360)
1137 {
1138 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
1139 INST_S_BIT (inst),
1140 INST_X_BIT (inst));
1141 if (src2 == TIC6X_RA_REGNUM)
1142 return 1;
1143 }
1144
1145 return 0;
1146}
1147
1148/* This is the implementation of gdbarch method get_longjmp_target. */
1149
1150static int
1151tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1152{
1153 struct gdbarch *gdbarch = get_frame_arch (frame);
1154 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1155 CORE_ADDR jb_addr;
e362b510 1156 gdb_byte buf[4];
8cd64e00
YQ		 1157
1158 /* JMP_BUF is passed by reference in A4. */
1159 jb_addr = get_frame_register_unsigned (frame, 4);
1160
1161 /* JMP_BUF contains 13 elements of type int, and return address is stored
1162 in the last slot. */
1163 if (target_read_memory (jb_addr + 12 * 4, buf, 4))
1164 return 0;
1165
1166 *pc = extract_unsigned_integer (buf, 4, byte_order);
1167
1168 return 1;
1169}
1170
18648a37
YQ		 1171/* This is the implementation of gdbarch method
1172 return_in_first_hidden_param_p. */
1173
1174static int
1175tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
1176 struct type *type)
1177{
1178 return 0;
1179}
1180
8cd64e00
YQ		 1181static struct gdbarch *
1182tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1183{
1184 struct gdbarch *gdbarch;
1185 struct gdbarch_tdep *tdep;
1186 struct tdesc_arch_data *tdesc_data = NULL;
1187 const struct target_desc *tdesc = info.target_desc;
1188 int has_gp = 0;
1189
1190 /* Check any target description for validity. */
1191 if (tdesc_has_registers (tdesc))
1192 {
1193 const struct tdesc_feature *feature;
1194 int valid_p, i;
1195
1196 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core");
1197
1198 if (feature == NULL)
1199 return NULL;
1200
1201 tdesc_data = tdesc_data_alloc ();
1202
1203 valid_p = 1;
1204 for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */
1205 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1206 tic6x_register_names[i]);
1207
1208 /* CSR */
1209 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1210 tic6x_register_names[TIC6X_CSR_REGNUM]);
1211 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1212 tic6x_register_names[TIC6X_PC_REGNUM]);
1213
1214 if (!valid_p)
1215 {
1216 tdesc_data_cleanup (tdesc_data);
1217 return NULL;
1218 }
1219
1220 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp");
1221 if (feature)
1222 {
1223 int j = 0;
1224 static const char *const gp[] =
1225 {
1226 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1227 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1228 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1229 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1230 };
1231
1232 has_gp = 1;
1233 valid_p = 1;
1234 for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */
1235 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1236 gp[j]);
1237
1238 if (!valid_p)
1239 {
1240 tdesc_data_cleanup (tdesc_data);
1241 return NULL;
1242 }
1243 }
1244
1245 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp");
1246 if (feature)
1247 {
1248 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR");
1249 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC");
1250 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC");
1251
1252 if (!valid_p)
1253 {
1254 tdesc_data_cleanup (tdesc_data);
1255 return NULL;
1256 }
1257 }
1258
1259 }
1260
1261 /* Find a candidate among extant architectures. */
1262 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1263 arches != NULL;
1264 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1265 {
1266 tdep = gdbarch_tdep (arches->gdbarch);
1267
1268 if (has_gp != tdep->has_gp)
1269 continue;
1270
1271 if (tdep && tdep->breakpoint)
1272 return arches->gdbarch;
1273 }
1274
8d749320 1275 tdep = XCNEW (struct gdbarch_tdep);
8cd64e00
YQ		 1276
1277 tdep->has_gp = has_gp;
1278 gdbarch = gdbarch_alloc (&info, tdep);
1279
1280 /* Data type sizes. */
1281 set_gdbarch_ptr_bit (gdbarch, 32);
1282 set_gdbarch_addr_bit (gdbarch, 32);
1283 set_gdbarch_short_bit (gdbarch, 16);
1284 set_gdbarch_int_bit (gdbarch, 32);
1285 set_gdbarch_long_bit (gdbarch, 32);
1286 set_gdbarch_long_long_bit (gdbarch, 64);
1287 set_gdbarch_float_bit (gdbarch, 32);
1288 set_gdbarch_double_bit (gdbarch, 64);
1289
1290 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1291 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1292
1293 /* The register set. */
1294 set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS);
1295 set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM);
1296 set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM);
1297
1298 set_gdbarch_register_name (gdbarch, tic6x_register_name);
1299 set_gdbarch_register_type (gdbarch, tic6x_register_type);
1300
1301 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1302
1303 set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue);
04180708
YQ		 1304 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1305 tic6x_breakpoint_kind_from_pc);
1306 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1307 tic6x_sw_breakpoint_from_kind);
8cd64e00
YQ		 1308
1309 set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc);
1310 set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp);
1311
1312 /* Unwinding. */
1313 dwarf2_append_unwinders (gdbarch);
1314
1315 frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind);
1316 frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind);
195abc10 1317 frame_base_set_default (gdbarch, &tic6x_frame_base);
8cd64e00
YQ		 1318
1319 dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg);
1320
1321 /* Single stepping. */
1322 set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step);
1323
1324 set_gdbarch_print_insn (gdbarch, tic6x_print_insn);
1325
1326 /* Call dummy code. */
1327 set_gdbarch_frame_align (gdbarch, tic6x_frame_align);
1328
8cd64e00
YQ		 1329 set_gdbarch_return_value (gdbarch, tic6x_return_value);
1330
1331 set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id);
1332
1333 /* Enable inferior call support. */
1334 set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call);
1335
1336 set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target);
1337
c9cf6e20 1338 set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p);
8cd64e00 1339
18648a37
YQ		 1340 set_gdbarch_return_in_first_hidden_param_p (gdbarch,
1341 tic6x_return_in_first_hidden_param_p);
1342
8cd64e00
YQ		 1343 /* Hook in ABI-specific overrides, if they have been registered. */
1344 gdbarch_init_osabi (info, gdbarch);
1345
1346 if (tdesc_data)
1347 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
1348
1349 return gdbarch;
1350}
1351
693be288
JK		 1352/* -Wmissing-prototypes */
1353extern initialize_file_ftype _initialize_tic6x_tdep;
1354
8cd64e00
YQ		 1355void
1356_initialize_tic6x_tdep (void)
1357{
1358 register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init);
1359
1360 initialize_tdesc_tic6x_c64xp ();
1361 initialize_tdesc_tic6x_c64x ();
1362 initialize_tdesc_tic6x_c62x ();
1363}
GDB Binutils - Deliverables
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