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* tracepoint.c (trace_save): Call the writer's start method.
[deliverable/binutils-gdb.git] / gdb / v850-tdep.c
CommitLineData
181124bc
CV		 1/* Target-dependent code for the NEC V850 for GDB, the GNU debugger.
2
8acc9f48 3 Copyright (C) 1996-2013 Free Software Foundation, Inc.
181124bc
CV		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
181124bc
CV		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
181124bc
CV		 19
20#include "defs.h"
21#include "frame.h"
22#include "frame-base.h"
23#include "trad-frame.h"
24#include "frame-unwind.h"
25#include "dwarf2-frame.h"
26#include "gdbtypes.h"
27#include "inferior.h"
28#include "gdb_string.h"
29#include "gdb_assert.h"
30#include "gdbcore.h"
31#include "arch-utils.h"
32#include "regcache.h"
33#include "dis-asm.h"
34#include "osabi.h"
35
36enum
37 {
a2d13a0d 38 /* General purpose registers. */
181124bc
CV		 39 E_R0_REGNUM,
40 E_R1_REGNUM,
41 E_R2_REGNUM,
42 E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM,
43 E_R4_REGNUM,
44 E_R5_REGNUM,
45 E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM,
46 E_R7_REGNUM,
47 E_R8_REGNUM,
48 E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM,
49 E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM,
50 E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM,
51 E_R12_REGNUM,
52 E_R13_REGNUM,
53 E_R14_REGNUM,
54 E_R15_REGNUM,
55 E_R16_REGNUM,
56 E_R17_REGNUM,
57 E_R18_REGNUM,
58 E_R19_REGNUM,
59 E_R20_REGNUM,
60 E_R21_REGNUM,
61 E_R22_REGNUM,
62 E_R23_REGNUM,
63 E_R24_REGNUM,
64 E_R25_REGNUM,
65 E_R26_REGNUM,
66 E_R27_REGNUM,
67 E_R28_REGNUM,
68 E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM,
69 E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM,
70 E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM,
a2d13a0d
KB		 71
72 /* System registers - main banks. */
181124bc
CV		 73 E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM,
74 E_R33_REGNUM,
75 E_R34_REGNUM,
76 E_R35_REGNUM,
77 E_R36_REGNUM,
78 E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM,
79 E_R38_REGNUM,
80 E_R39_REGNUM,
81 E_R40_REGNUM,
82 E_R41_REGNUM,
83 E_R42_REGNUM,
84 E_R43_REGNUM,
85 E_R44_REGNUM,
86 E_R45_REGNUM,
87 E_R46_REGNUM,
88 E_R47_REGNUM,
89 E_R48_REGNUM,
90 E_R49_REGNUM,
91 E_R50_REGNUM,
92 E_R51_REGNUM,
93 E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM,
94 E_R53_REGNUM,
95 E_R54_REGNUM,
96 E_R55_REGNUM,
97 E_R56_REGNUM,
98 E_R57_REGNUM,
99 E_R58_REGNUM,
100 E_R59_REGNUM,
101 E_R60_REGNUM,
102 E_R61_REGNUM,
103 E_R62_REGNUM,
104 E_R63_REGNUM,
a2d13a0d
KB		 105
106 /* PC. */
181124bc 107 E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM,
55fa75c3
KB		 108 E_R65_REGNUM,
109 E_NUM_OF_V850_REGS,
110 E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS,
2aaed979 111
a2d13a0d 112 /* System registers - MPV (PROT00) bank. */
55fa75c3 113 E_R66_REGNUM = E_NUM_OF_V850_REGS,
2aaed979
KB		 114 E_R67_REGNUM,
115 E_R68_REGNUM,
116 E_R69_REGNUM,
117 E_R70_REGNUM,
118 E_R71_REGNUM,
119 E_R72_REGNUM,
120 E_R73_REGNUM,
121 E_R74_REGNUM,
122 E_R75_REGNUM,
123 E_R76_REGNUM,
124 E_R77_REGNUM,
125 E_R78_REGNUM,
126 E_R79_REGNUM,
127 E_R80_REGNUM,
128 E_R81_REGNUM,
129 E_R82_REGNUM,
130 E_R83_REGNUM,
131 E_R84_REGNUM,
132 E_R85_REGNUM,
133 E_R86_REGNUM,
134 E_R87_REGNUM,
135 E_R88_REGNUM,
136 E_R89_REGNUM,
137 E_R90_REGNUM,
138 E_R91_REGNUM,
139 E_R92_REGNUM,
140 E_R93_REGNUM,
141
a2d13a0d 142 /* System registers - MPU (PROT01) bank. */
2aaed979
KB		 143 E_R94_REGNUM,
144 E_R95_REGNUM,
145 E_R96_REGNUM,
146 E_R97_REGNUM,
147 E_R98_REGNUM,
148 E_R99_REGNUM,
149 E_R100_REGNUM,
150 E_R101_REGNUM,
151 E_R102_REGNUM,
152 E_R103_REGNUM,
153 E_R104_REGNUM,
154 E_R105_REGNUM,
155 E_R106_REGNUM,
156 E_R107_REGNUM,
157 E_R108_REGNUM,
158 E_R109_REGNUM,
159 E_R110_REGNUM,
160 E_R111_REGNUM,
161 E_R112_REGNUM,
162 E_R113_REGNUM,
163 E_R114_REGNUM,
164 E_R115_REGNUM,
165 E_R116_REGNUM,
166 E_R117_REGNUM,
167 E_R118_REGNUM,
168 E_R119_REGNUM,
169 E_R120_REGNUM,
170 E_R121_REGNUM,
171
a2d13a0d 172 /* FPU system registers. */
2aaed979
KB		 173 E_R122_REGNUM,
174 E_R123_REGNUM,
175 E_R124_REGNUM,
176 E_R125_REGNUM,
177 E_R126_REGNUM,
178 E_R127_REGNUM,
179 E_R128_REGNUM, E_FPSR_REGNUM = E_R128_REGNUM,
180 E_R129_REGNUM, E_FPEPC_REGNUM = E_R129_REGNUM,
181 E_R130_REGNUM, E_FPST_REGNUM = E_R130_REGNUM,
182 E_R131_REGNUM, E_FPCC_REGNUM = E_R131_REGNUM,
183 E_R132_REGNUM, E_FPCFG_REGNUM = E_R132_REGNUM,
184 E_R133_REGNUM,
185 E_R134_REGNUM,
186 E_R135_REGNUM,
187 E_R136_REGNUM,
188 E_R137_REGNUM,
189 E_R138_REGNUM,
190 E_R139_REGNUM,
191 E_R140_REGNUM,
192 E_R141_REGNUM,
193 E_R142_REGNUM,
194 E_R143_REGNUM,
195 E_R144_REGNUM,
196 E_R145_REGNUM,
197 E_R146_REGNUM,
198 E_R147_REGNUM,
199 E_R148_REGNUM,
181124bc
CV		 200 E_NUM_REGS
201 };
202
203enum
204{
205 v850_reg_size = 4
206};
207
208/* Size of return datatype which fits into all return registers. */
209enum
210{
211 E_MAX_RETTYPE_SIZE_IN_REGS = 2 * v850_reg_size
212};
213
214struct v850_frame_cache
215{
216 /* Base address. */
217 CORE_ADDR base;
218 LONGEST sp_offset;
219 CORE_ADDR pc;
220
221 /* Flag showing that a frame has been created in the prologue code. */
222 int uses_fp;
223
224 /* Saved registers. */
225 struct trad_frame_saved_reg *saved_regs;
226};
227
228/* Info gleaned from scanning a function's prologue. */
229struct pifsr /* Info about one saved register. */
230{
231 int offset; /* Offset from sp or fp. */
232 int cur_frameoffset; /* Current frameoffset. */
233 int reg; /* Saved register number. */
234};
235
236static const char *
d93859e2 237v850_register_name (struct gdbarch *gdbarch, int regnum)
181124bc
CV		 238{
239 static const char *v850_reg_names[] =
240 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
241 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
242 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
243 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
244 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
245 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
246 "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
247 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
248 "pc", "fp"
249 };
2aaed979 250 if (regnum < 0 || regnum > E_NUM_OF_V850_REGS)
181124bc
CV		 251 return NULL;
252 return v850_reg_names[regnum];
253}
254
255static const char *
d93859e2 256v850e_register_name (struct gdbarch *gdbarch, int regnum)
181124bc
CV		 257{
258 static const char *v850e_reg_names[] =
259 {
260 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
261 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
262 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
263 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
264 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
265 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
266 "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
267 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
268 "pc", "fp"
269 };
2aaed979 270 if (regnum < 0 || regnum > E_NUM_OF_V850E_REGS)
181124bc
CV		 271 return NULL;
272 return v850e_reg_names[regnum];
273}
274
2aaed979
KB		 275static const char *
276v850e2_register_name (struct gdbarch *gdbarch, int regnum)
277{
278 static const char *v850e2_reg_names[] =
279 {
a2d13a0d 280 /* General purpose registers. */
2aaed979
KB		 281 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
282 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
283 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
284 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
285
a2d13a0d
KB		 286 /* System registers - main banks. */
287 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg",
288 "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic",
289 "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "",
290 "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
291
292
293 /* PC. */
294 "pc", "",
2aaed979 295
a2d13a0d
KB		 296 /* System registers - MPV (PROT00) bank. */
297 "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "",
298 "vpecr", "vptid", "vpadr", "", "", "", "", "",
299 "", "", "", "", "", "", "", "",
300 "mca", "mcs", "mcc", "mcr",
2aaed979 301
a2d13a0d
KB		 302 /* System registers - MPU (PROT01) bank. */
303 "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u",
304 "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u",
305 "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u",
306 "dpa4l", "dpa4u", "dpa5l", "dpa5u",
2aaed979 307
a2d13a0d
KB		 308 /* FPU system registers. */
309 "", "", "", "", "", "", "fpsr", "fpepc",
310 "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
311 "", "", "", "", "", "", "", "",
312 "", "", "", "fpspc"
2aaed979
KB		 313 };
314 if (regnum < 0 || regnum >= E_NUM_REGS)
315 return NULL;
316 return v850e2_reg_names[regnum];
317}
318
181124bc
CV		 319/* Returns the default type for register N. */
320
321static struct type *
322v850_register_type (struct gdbarch *gdbarch, int regnum)
323{
324 if (regnum == E_PC_REGNUM)
0dfff4cb 325 return builtin_type (gdbarch)->builtin_func_ptr;
df4df182 326 return builtin_type (gdbarch)->builtin_int32;
181124bc
CV		 327}
328
329static int
330v850_type_is_scalar (struct type *t)
331{
332 return (TYPE_CODE (t) != TYPE_CODE_STRUCT
333 && TYPE_CODE (t) != TYPE_CODE_UNION
334 && TYPE_CODE (t) != TYPE_CODE_ARRAY);
335}
336
337/* Should call_function allocate stack space for a struct return? */
338static int
339v850_use_struct_convention (struct type *type)
340{
341 int i;
342 struct type *fld_type, *tgt_type;
343
344 /* 1. The value is greater than 8 bytes -> returned by copying. */
345 if (TYPE_LENGTH (type) > 8)
346 return 1;
347
348 /* 2. The value is a single basic type -> returned in register. */
349 if (v850_type_is_scalar (type))
350 return 0;
351
352 /* The value is a structure or union with a single element and that
353 element is either a single basic type or an array of a single basic
354 type whose size is greater than or equal to 4 -> returned in register. */
355 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
356 || TYPE_CODE (type) == TYPE_CODE_UNION)
357 && TYPE_NFIELDS (type) == 1)
358 {
359 fld_type = TYPE_FIELD_TYPE (type, 0);
360 if (v850_type_is_scalar (fld_type) && TYPE_LENGTH (fld_type) >= 4)
361 return 0;
362
363 if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY)
364 {
365 tgt_type = TYPE_TARGET_TYPE (fld_type);
366 if (v850_type_is_scalar (tgt_type) && TYPE_LENGTH (tgt_type) >= 4)
367 return 0;
368 }
369 }
370
371 /* The value is a structure whose first element is an integer or a float,
372 and which contains no arrays of more than two elements -> returned in
373 register. */
374 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
375 && v850_type_is_scalar (TYPE_FIELD_TYPE (type, 0))
376 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
377 {
378 for (i = 1; i < TYPE_NFIELDS (type); ++i)
379 {
380 fld_type = TYPE_FIELD_TYPE (type, 0);
381 if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY)
382 {
383 tgt_type = TYPE_TARGET_TYPE (fld_type);
384 if (TYPE_LENGTH (fld_type) >= 0 && TYPE_LENGTH (tgt_type) >= 0
385 && TYPE_LENGTH (fld_type) / TYPE_LENGTH (tgt_type) > 2)
386 return 1;
387 }
388 }
389 return 0;
390 }
391
581e13c1
MS		 392 /* The value is a union which contains at least one field which
393 would be returned in registers according to these rules ->
394 returned in register. */
181124bc
CV		 395 if (TYPE_CODE (type) == TYPE_CODE_UNION)
396 {
397 for (i = 0; i < TYPE_NFIELDS (type); ++i)
398 {
399 fld_type = TYPE_FIELD_TYPE (type, 0);
400 if (!v850_use_struct_convention (fld_type))
401 return 0;
402 }
403 }
404
405 return 1;
406}
407
408/* Structure for mapping bits in register lists to register numbers. */
409struct reg_list
410{
411 long mask;
412 int regno;
413};
414
415/* Helper function for v850_scan_prologue to handle prepare instruction. */
416
417static void
418v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
419 struct v850_frame_cache *pi, struct pifsr **pifsr_ptr)
420{
421 CORE_ADDR current_pc = *current_pc_ptr;
422 struct pifsr *pifsr = *pifsr_ptr;
423 long next = insn2 & 0xffff;
424 long list12 = ((insn & 1) << 16) + (next & 0xffe0);
425 long offset = (insn & 0x3e) << 1;
426 static struct reg_list reg_table[] =
427 {
428 {0x00800, 20}, /* r20 */
429 {0x00400, 21}, /* r21 */
430 {0x00200, 22}, /* r22 */
431 {0x00100, 23}, /* r23 */
432 {0x08000, 24}, /* r24 */
433 {0x04000, 25}, /* r25 */
434 {0x02000, 26}, /* r26 */
435 {0x01000, 27}, /* r27 */
436 {0x00080, 28}, /* r28 */
437 {0x00040, 29}, /* r29 */
438 {0x10000, 30}, /* ep */
439 {0x00020, 31}, /* lp */
440 {0, 0} /* end of table */
441 };
442 int i;
443
444 if ((next & 0x1f) == 0x0b) /* skip imm16 argument */
445 current_pc += 2;
446 else if ((next & 0x1f) == 0x13) /* skip imm16 argument */
447 current_pc += 2;
448 else if ((next & 0x1f) == 0x1b) /* skip imm32 argument */
449 current_pc += 4;
450
451 /* Calculate the total size of the saved registers, and add it to the
452 immediate value used to adjust SP. */
453 for (i = 0; reg_table[i].mask != 0; i++)
454 if (list12 & reg_table[i].mask)
455 offset += v850_reg_size;
456 pi->sp_offset -= offset;
457
458 /* Calculate the offsets of the registers relative to the value the SP
459 will have after the registers have been pushed and the imm5 value has
460 been subtracted from it. */
461 if (pifsr)
462 {
463 for (i = 0; reg_table[i].mask != 0; i++)
464 {
465 if (list12 & reg_table[i].mask)
466 {
467 int reg = reg_table[i].regno;
468 offset -= v850_reg_size;
469 pifsr->reg = reg;
470 pifsr->offset = offset;
471 pifsr->cur_frameoffset = pi->sp_offset;
472 pifsr++;
473 }
474 }
475 }
476
477 /* Set result parameters. */
478 *current_pc_ptr = current_pc;
479 *pifsr_ptr = pifsr;
480}
481
482
483/* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
484 The SR bit of the register list is not supported. gcc does not generate
485 this bit. */
486
487static void
488v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
489 struct pifsr **pifsr_ptr)
490{
491 struct pifsr *pifsr = *pifsr_ptr;
492 long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0);
493 long offset = 0;
494 static struct reg_list pushml_reg_table[] =
495 {
496 {0x80000, E_PS_REGNUM}, /* PSW */
497 {0x40000, 1}, /* r1 */
498 {0x20000, 2}, /* r2 */
499 {0x10000, 3}, /* r3 */
500 {0x00800, 4}, /* r4 */
501 {0x00400, 5}, /* r5 */
502 {0x00200, 6}, /* r6 */
503 {0x00100, 7}, /* r7 */
504 {0x08000, 8}, /* r8 */
505 {0x04000, 9}, /* r9 */
506 {0x02000, 10}, /* r10 */
507 {0x01000, 11}, /* r11 */
508 {0x00080, 12}, /* r12 */
509 {0x00040, 13}, /* r13 */
510 {0x00020, 14}, /* r14 */
511 {0x00010, 15}, /* r15 */
512 {0, 0} /* end of table */
513 };
514 static struct reg_list pushmh_reg_table[] =
515 {
516 {0x80000, 16}, /* r16 */
517 {0x40000, 17}, /* r17 */
518 {0x20000, 18}, /* r18 */
519 {0x10000, 19}, /* r19 */
520 {0x00800, 20}, /* r20 */
521 {0x00400, 21}, /* r21 */
522 {0x00200, 22}, /* r22 */
523 {0x00100, 23}, /* r23 */
524 {0x08000, 24}, /* r24 */
525 {0x04000, 25}, /* r25 */
526 {0x02000, 26}, /* r26 */
527 {0x01000, 27}, /* r27 */
528 {0x00080, 28}, /* r28 */
529 {0x00040, 29}, /* r29 */
530 {0x00010, 30}, /* r30 */
531 {0x00020, 31}, /* r31 */
532 {0, 0} /* end of table */
533 };
534 struct reg_list *reg_table;
535 int i;
536
537 /* Is this a pushml or a pushmh? */
538 if ((insn2 & 7) == 1)
539 reg_table = pushml_reg_table;
540 else
541 reg_table = pushmh_reg_table;
542
7a9dd1b2 543 /* Calculate the total size of the saved registers, and add it to the
181124bc
CV		 544 immediate value used to adjust SP. */
545 for (i = 0; reg_table[i].mask != 0; i++)
546 if (list12 & reg_table[i].mask)
547 offset += v850_reg_size;
548 pi->sp_offset -= offset;
549
550 /* Calculate the offsets of the registers relative to the value the SP
551 will have after the registers have been pushed and the imm5 value is
552 subtracted from it. */
553 if (pifsr)
554 {
555 for (i = 0; reg_table[i].mask != 0; i++)
556 {
557 if (list12 & reg_table[i].mask)
558 {
559 int reg = reg_table[i].regno;
560 offset -= v850_reg_size;
561 pifsr->reg = reg;
562 pifsr->offset = offset;
563 pifsr->cur_frameoffset = pi->sp_offset;
564 pifsr++;
565 }
566 }
567 }
568
569 /* Set result parameters. */
570 *pifsr_ptr = pifsr;
571}
572
573/* Helper function to evaluate if register is one of the "save" registers.
574 This allows to simplify conditionals in v850_analyze_prologue a lot. */
575
576static int
577v850_is_save_register (int reg)
578{
579 /* The caller-save registers are R2, R20 - R29 and R31. All other
580 registers are either special purpose (PC, SP), argument registers,
581e13c1 581 or just considered free for use in the caller. */
181124bc
CV		 582 return reg == E_R2_REGNUM
583 || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
584 || reg == E_R31_REGNUM;
585}
586
587/* Scan the prologue of the function that contains PC, and record what
588 we find in PI. Returns the pc after the prologue. Note that the
589 addresses saved in frame->saved_regs are just frame relative (negative
590 offsets from the frame pointer). This is because we don't know the
591 actual value of the frame pointer yet. In some circumstances, the
592 frame pointer can't be determined till after we have scanned the
593 prologue. */
594
595static CORE_ADDR
e17a4113
UW		 596v850_analyze_prologue (struct gdbarch *gdbarch,
597 CORE_ADDR func_addr, CORE_ADDR pc,
d2ca4222 598 struct v850_frame_cache *pi, ULONGEST ctbp)
181124bc 599{
e17a4113 600 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 601 CORE_ADDR prologue_end, current_pc;
602 struct pifsr pifsrs[E_NUM_REGS + 1];
603 struct pifsr *pifsr, *pifsr_tmp;
181124bc
CV		 604 int ep_used;
605 int reg;
606 CORE_ADDR save_pc, save_end;
607 int regsave_func_p;
608 int r12_tmp;
609
610 memset (&pifsrs, 0, sizeof pifsrs);
611 pifsr = &pifsrs[0];
612
613 prologue_end = pc;
614
615 /* Now, search the prologue looking for instructions that setup fp, save
616 rp, adjust sp and such. We also record the frame offset of any saved
617 registers. */
618
619 pi->sp_offset = 0;
620 pi->uses_fp = 0;
621 ep_used = 0;
622 regsave_func_p = 0;
623 save_pc = 0;
624 save_end = 0;
625 r12_tmp = 0;
626
627 for (current_pc = func_addr; current_pc < prologue_end;)
628 {
629 int insn;
630 int insn2 = -1; /* dummy value */
631
e17a4113 632 insn = read_memory_integer (current_pc, 2, byte_order);
181124bc 633 current_pc += 2;
581e13c1 634 if ((insn & 0x0780) >= 0x0600) /* Four byte instruction? */
181124bc 635 {
e17a4113 636 insn2 = read_memory_integer (current_pc, 2, byte_order);
181124bc
CV		 637 current_pc += 2;
638 }
639
640 if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p)
641 { /* jarl <func>,10 */
642 long low_disp = insn2 & ~(long) 1;
643 long disp = (((((insn & 0x3f) << 16) + low_disp)
644 & ~(long) 1) ^ 0x00200000) - 0x00200000;
645
646 save_pc = current_pc;
647 save_end = prologue_end;
648 regsave_func_p = 1;
649 current_pc += disp - 4;
650 prologue_end = (current_pc
651 + (2 * 3) /* moves to/from ep */
652 + 4 /* addi <const>,sp,sp */
653 + 2 /* jmp [r10] */
654 + (2 * 12) /* sst.w to save r2, r20-r29, r31 */
655 + 20); /* slop area */
656 }
657 else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p)
658 { /* callt <imm6> */
181124bc
CV		 659 long adr = ctbp + ((insn & 0x3f) << 1);
660
661 save_pc = current_pc;
662 save_end = prologue_end;
663 regsave_func_p = 1;
e17a4113
UW		 664 current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order)
665 & 0xffff);
181124bc
CV		 666 prologue_end = (current_pc
667 + (2 * 3) /* prepare list2,imm5,sp/imm */
668 + 4 /* ctret */
669 + 20); /* slop area */
670 continue;
671 }
672 else if ((insn & 0xffc0) == 0x0780) /* prepare list2,imm5 */
673 {
674 v850_handle_prepare (insn, insn2, &current_pc, pi, &pifsr);
675 continue;
676 }
677 else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144)
678 { /* ctret after processing register save. */
679 current_pc = save_pc;
680 prologue_end = save_end;
681 regsave_func_p = 0;
682 continue;
683 }
684 else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1)
685 { /* pushml, pushmh */
686 v850_handle_pushm (insn, insn2, pi, &pifsr);
687 continue;
688 }
689 else if ((insn & 0xffe0) == 0x0060 && regsave_func_p)
690 { /* jmp after processing register save. */
691 current_pc = save_pc;
692 prologue_end = save_end;
693 regsave_func_p = 0;
694 continue;
695 }
696 else if ((insn & 0x07c0) == 0x0780 /* jarl or jr */
697 || (insn & 0xffe0) == 0x0060 /* jmp */
698 || (insn & 0x0780) == 0x0580) /* branch */
699 {
581e13c1 700 break; /* Ran into end of prologue. */
181124bc
CV		 701 }
702
703 else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240))
704 /* add <imm>,sp */
705 pi->sp_offset += ((insn & 0x1f) ^ 0x10) - 0x10;
706 else if (insn == ((E_SP_REGNUM << 11) | 0x0600 | E_SP_REGNUM))
707 /* addi <imm>,sp,sp */
708 pi->sp_offset += insn2;
709 else if (insn == ((E_FP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
710 /* mov sp,fp */
711 pi->uses_fp = 1;
712 else if (insn == ((E_R12_REGNUM << 11) | 0x0640 | E_R0_REGNUM))
713 /* movhi hi(const),r0,r12 */
714 r12_tmp = insn2 << 16;
715 else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM))
716 /* movea lo(const),r12,r12 */
717 r12_tmp += insn2;
718 else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp)
719 /* add r12,sp */
720 pi->sp_offset += r12_tmp;
721 else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
722 /* mov sp,ep */
723 ep_used = 1;
724 else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM))
725 /* mov r1,ep */
726 ep_used = 0;
727 else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)
728 || (pi->uses_fp
729 && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
730 && pifsr
731 && v850_is_save_register (reg = (insn >> 11) & 0x1f))
732 {
733 /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
734 pifsr->reg = reg;
735 pifsr->offset = insn2 & ~1;
736 pifsr->cur_frameoffset = pi->sp_offset;
737 pifsr++;
738 }
739 else if (ep_used
740 && ((insn & 0x0781) == 0x0501)
741 && pifsr
742 && v850_is_save_register (reg = (insn >> 11) & 0x1f))
743 {
744 /* sst.w <reg>,<offset>[ep] */
745 pifsr->reg = reg;
746 pifsr->offset = (insn & 0x007e) << 1;
747 pifsr->cur_frameoffset = pi->sp_offset;
748 pifsr++;
749 }
750 }
751
752 /* Fix up any offsets to the final offset. If a frame pointer was created,
753 use it instead of the stack pointer. */
754 for (pifsr_tmp = pifsrs; pifsr_tmp != pifsr; pifsr_tmp++)
755 {
756 pifsr_tmp->offset -= pi->sp_offset - pifsr_tmp->cur_frameoffset;
757 pi->saved_regs[pifsr_tmp->reg].addr = pifsr_tmp->offset;
758 }
759
760 return current_pc;
761}
762
763/* Return the address of the first code past the prologue of the function. */
764
765static CORE_ADDR
6093d2eb 766v850_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
181124bc
CV		 767{
768 CORE_ADDR func_addr, func_end;
769
581e13c1 770 /* See what the symbol table says. */
181124bc
CV		 771
772 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
773 {
774 struct symtab_and_line sal;
775
776 sal = find_pc_line (func_addr, 0);
777 if (sal.line != 0 && sal.end < func_end)
778 return sal.end;
779
780 /* Either there's no line info, or the line after the prologue is after
781 the end of the function. In this case, there probably isn't a
782 prologue. */
783 return pc;
784 }
785
581e13c1
MS		 786 /* We can't find the start of this function, so there's nothing we
787 can do. */
181124bc
CV		 788 return pc;
789}
790
791static CORE_ADDR
792v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
793{
794 return sp & ~3;
795}
796
797/* Setup arguments and LP for a call to the target. First four args
798 go in R6->R9, subsequent args go into sp + 16 -> sp + ... Structs
799 are passed by reference. 64 bit quantities (doubles and long longs)
800 may be split between the regs and the stack. When calling a function
801 that returns a struct, a pointer to the struct is passed in as a secret
802 first argument (always in R6).
803
804 Stack space for the args has NOT been allocated: that job is up to us. */
805
806static CORE_ADDR
807v850_push_dummy_call (struct gdbarch *gdbarch,
808 struct value *function,
809 struct regcache *regcache,
810 CORE_ADDR bp_addr,
811 int nargs,
812 struct value **args,
813 CORE_ADDR sp,
814 int struct_return,
815 CORE_ADDR struct_addr)
816{
e17a4113 817 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 818 int argreg;
819 int argnum;
820 int len = 0;
821 int stack_offset;
822
823 /* The offset onto the stack at which we will start copying parameters
824 (after the registers are used up) begins at 16 rather than at zero.
825 That's how the ABI is defined, though there's no indication that these
826 16 bytes are used for anything, not even for saving incoming
827 argument registers. */
828 stack_offset = 16;
829
830 /* Now make space on the stack for the args. */
831 for (argnum = 0; argnum < nargs; argnum++)
832 len += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3);
833 sp -= len + stack_offset;
834
835 argreg = E_ARG0_REGNUM;
836 /* The struct_return pointer occupies the first parameter register. */
837 if (struct_return)
838 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
839
840 /* Now load as many as possible of the first arguments into
841 registers, and push the rest onto the stack. There are 16 bytes
842 in four registers available. Loop thru args from first to last. */
843 for (argnum = 0; argnum < nargs; argnum++)
844 {
845 int len;
846 gdb_byte *val;
847 gdb_byte valbuf[v850_reg_size];
848
849 if (!v850_type_is_scalar (value_type (*args))
850 && TYPE_LENGTH (value_type (*args)) > E_MAX_RETTYPE_SIZE_IN_REGS)
851 {
e17a4113
UW		 852 store_unsigned_integer (valbuf, 4, byte_order,
853 value_address (*args));
181124bc
CV		 854 len = 4;
855 val = valbuf;
856 }
857 else
858 {
859 len = TYPE_LENGTH (value_type (*args));
860 val = (gdb_byte *) value_contents (*args);
861 }
862
863 while (len > 0)
864 if (argreg <= E_ARGLAST_REGNUM)
865 {
866 CORE_ADDR regval;
867
e17a4113 868 regval = extract_unsigned_integer (val, v850_reg_size, byte_order);
181124bc
CV		 869 regcache_cooked_write_unsigned (regcache, argreg, regval);
870
871 len -= v850_reg_size;
872 val += v850_reg_size;
873 argreg++;
874 }
875 else
876 {
877 write_memory (sp + stack_offset, val, 4);
878
879 len -= 4;
880 val += 4;
881 stack_offset += 4;
882 }
883 args++;
884 }
885
886 /* Store return address. */
887 regcache_cooked_write_unsigned (regcache, E_LP_REGNUM, bp_addr);
888
889 /* Update stack pointer. */
890 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
891
892 return sp;
893}
894
895static void
896v850_extract_return_value (struct type *type, struct regcache *regcache,
897 gdb_byte *valbuf)
898{
e17a4113
UW		 899 struct gdbarch *gdbarch = get_regcache_arch (regcache);
900 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 901 int len = TYPE_LENGTH (type);
902
903 if (len <= v850_reg_size)
904 {
905 ULONGEST val;
906
907 regcache_cooked_read_unsigned (regcache, E_V0_REGNUM, &val);
e17a4113 908 store_unsigned_integer (valbuf, len, byte_order, val);
181124bc
CV		 909 }
910 else if (len <= 2 * v850_reg_size)
911 {
912 int i, regnum = E_V0_REGNUM;
913 gdb_byte buf[v850_reg_size];
914 for (i = 0; len > 0; i += 4, len -= 4)
915 {
916 regcache_raw_read (regcache, regnum++, buf);
917 memcpy (valbuf + i, buf, len > 4 ? 4 : len);
918 }
919 }
920}
921
922static void
923v850_store_return_value (struct type *type, struct regcache *regcache,
924 const gdb_byte *valbuf)
925{
e17a4113
UW		 926 struct gdbarch *gdbarch = get_regcache_arch (regcache);
927 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 928 int len = TYPE_LENGTH (type);
929
930 if (len <= v850_reg_size)
e17a4113
UW		 931 regcache_cooked_write_unsigned
932 (regcache, E_V0_REGNUM,
933 extract_unsigned_integer (valbuf, len, byte_order));
181124bc
CV		 934 else if (len <= 2 * v850_reg_size)
935 {
936 int i, regnum = E_V0_REGNUM;
937 for (i = 0; i < len; i += 4)
938 regcache_raw_write (regcache, regnum++, valbuf + i);
939 }
940}
941
942static enum return_value_convention
6a3a010b 943v850_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 944 struct type *type, struct regcache *regcache,
181124bc
CV		 945 gdb_byte *readbuf, const gdb_byte *writebuf)
946{
947 if (v850_use_struct_convention (type))
948 return RETURN_VALUE_STRUCT_CONVENTION;
949 if (writebuf)
950 v850_store_return_value (type, regcache, writebuf);
951 else if (readbuf)
952 v850_extract_return_value (type, regcache, readbuf);
953 return RETURN_VALUE_REGISTER_CONVENTION;
954}
955
956const static unsigned char *
67d57894 957v850_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
181124bc
CV		 958{
959 static unsigned char breakpoint[] = { 0x85, 0x05 };
960 *lenptr = sizeof (breakpoint);
961 return breakpoint;
962}
963
964static struct v850_frame_cache *
94afd7a6 965v850_alloc_frame_cache (struct frame_info *this_frame)
181124bc
CV		 966{
967 struct v850_frame_cache *cache;
181124bc
CV		 968
969 cache = FRAME_OBSTACK_ZALLOC (struct v850_frame_cache);
94afd7a6 970 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
181124bc
CV		 971
972 /* Base address. */
973 cache->base = 0;
974 cache->sp_offset = 0;
975 cache->pc = 0;
976
977 /* Frameless until proven otherwise. */
978 cache->uses_fp = 0;
979
980 return cache;
981}
982
983static struct v850_frame_cache *
94afd7a6 984v850_frame_cache (struct frame_info *this_frame, void **this_cache)
181124bc 985{
e17a4113 986 struct gdbarch *gdbarch = get_frame_arch (this_frame);
181124bc
CV		 987 struct v850_frame_cache *cache;
988 CORE_ADDR current_pc;
989 int i;
990
991 if (*this_cache)
992 return *this_cache;
993
94afd7a6 994 cache = v850_alloc_frame_cache (this_frame);
181124bc
CV		 995 *this_cache = cache;
996
997 /* In principle, for normal frames, fp holds the frame pointer,
998 which holds the base address for the current stack frame.
999 However, for functions that don't need it, the frame pointer is
1000 optional. For these "frameless" functions the frame pointer is
1001 actually the frame pointer of the calling frame. */
94afd7a6 1002 cache->base = get_frame_register_unsigned (this_frame, E_FP_REGNUM);
181124bc
CV		 1003 if (cache->base == 0)
1004 return cache;
1005
94afd7a6
UW		 1006 cache->pc = get_frame_func (this_frame);
1007 current_pc = get_frame_pc (this_frame);
181124bc 1008 if (cache->pc != 0)
d2ca4222
UW		 1009 {
1010 ULONGEST ctbp;
94afd7a6 1011 ctbp = get_frame_register_unsigned (this_frame, E_CTBP_REGNUM);
e17a4113 1012 v850_analyze_prologue (gdbarch, cache->pc, current_pc, cache, ctbp);
d2ca4222 1013 }
181124bc
CV		 1014
1015 if (!cache->uses_fp)
1016 {
1017 /* We didn't find a valid frame, which means that CACHE->base
1018 currently holds the frame pointer for our calling frame. If
1019 we're at the start of a function, or somewhere half-way its
1020 prologue, the function's frame probably hasn't been fully
1021 setup yet. Try to reconstruct the base address for the stack
1022 frame by looking at the stack pointer. For truly "frameless"
1023 functions this might work too. */
94afd7a6 1024 cache->base = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
181124bc
CV		 1025 }
1026
1027 /* Now that we have the base address for the stack frame we can
1028 calculate the value of sp in the calling frame. */
1029 trad_frame_set_value (cache->saved_regs, E_SP_REGNUM,
1030 cache->base - cache->sp_offset);
1031
1032 /* Adjust all the saved registers such that they contain addresses
1033 instead of offsets. */
55fa75c3 1034 for (i = 0; i < gdbarch_num_regs (gdbarch); i++)
181124bc
CV		 1035 if (trad_frame_addr_p (cache->saved_regs, i))
1036 cache->saved_regs[i].addr += cache->base;
1037
1038 /* The call instruction moves the caller's PC in the callee's LP.
1039 Since this is an unwind, do the reverse. Copy the location of LP
1040 into PC (the address / regnum) so that a request for PC will be
1041 converted into a request for the LP. */
1042
1043 cache->saved_regs[E_PC_REGNUM] = cache->saved_regs[E_LP_REGNUM];
1044
1045 return cache;
1046}
1047
1048
94afd7a6
UW		 1049static struct value *
1050v850_frame_prev_register (struct frame_info *this_frame,
1051 void **this_cache, int regnum)
181124bc 1052{
94afd7a6 1053 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 1054
1055 gdb_assert (regnum >= 0);
1056
94afd7a6 1057 return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
181124bc
CV		 1058}
1059
1060static void
94afd7a6 1061v850_frame_this_id (struct frame_info *this_frame, void **this_cache,
181124bc
CV		 1062 struct frame_id *this_id)
1063{
94afd7a6 1064 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 1065
1066 /* This marks the outermost frame. */
1067 if (cache->base == 0)
1068 return;
1069
1070 *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr, cache->pc);
1071}
1072
1073static const struct frame_unwind v850_frame_unwind = {
1074 NORMAL_FRAME,
8fbca658 1075 default_frame_unwind_stop_reason,
181124bc 1076 v850_frame_this_id,
94afd7a6
UW		 1077 v850_frame_prev_register,
1078 NULL,
1079 default_frame_sniffer
181124bc 1080};
181124bc
CV		 1081
1082static CORE_ADDR
1083v850_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1084{
3e8c568d 1085 return frame_unwind_register_unsigned (next_frame,
d93859e2 1086 gdbarch_sp_regnum (gdbarch));
181124bc
CV		 1087}
1088
1089static CORE_ADDR
1090v850_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1091{
3e8c568d 1092 return frame_unwind_register_unsigned (next_frame,
d93859e2 1093 gdbarch_pc_regnum (gdbarch));
181124bc
CV		 1094}
1095
1096static struct frame_id
94afd7a6 1097v850_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
181124bc 1098{
94afd7a6
UW		 1099 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
1100 gdbarch_sp_regnum (gdbarch));
1101 return frame_id_build (sp, get_frame_pc (this_frame));
181124bc
CV		 1102}
1103
1104static CORE_ADDR
94afd7a6 1105v850_frame_base_address (struct frame_info *this_frame, void **this_cache)
181124bc 1106{
94afd7a6 1107 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 1108
1109 return cache->base;
1110}
1111
1112static const struct frame_base v850_frame_base = {
1113 &v850_frame_unwind,
1114 v850_frame_base_address,
1115 v850_frame_base_address,
1116 v850_frame_base_address
1117};
1118
1119static struct gdbarch *
1120v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1121{
1122 struct gdbarch *gdbarch;
1123
1124 /* Change the register names based on the current machine type. */
1125 if (info.bfd_arch_info->arch != bfd_arch_v850)
1126 return NULL;
1127
1128 gdbarch = gdbarch_alloc (&info, NULL);
1129
1130 switch (info.bfd_arch_info->mach)
1131 {
1132 case bfd_mach_v850:
1133 set_gdbarch_register_name (gdbarch, v850_register_name);
55fa75c3 1134 set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850_REGS);
181124bc
CV		 1135 break;
1136 case bfd_mach_v850e:
1137 case bfd_mach_v850e1:
1138 set_gdbarch_register_name (gdbarch, v850e_register_name);
55fa75c3 1139 set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E_REGS);
181124bc 1140 break;
2aaed979
KB		 1141 case bfd_mach_v850e2:
1142 case bfd_mach_v850e2v3:
1143 set_gdbarch_register_name (gdbarch, v850e2_register_name);
55fa75c3 1144 set_gdbarch_num_regs (gdbarch, E_NUM_REGS);
2aaed979 1145 break;
181124bc
CV		 1146 }
1147
181124bc
CV		 1148 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1149 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
1150 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1151 set_gdbarch_fp0_regnum (gdbarch, -1);
1152
1153 set_gdbarch_register_type (gdbarch, v850_register_type);
1154
351a3e56 1155 set_gdbarch_char_signed (gdbarch, 1);
181124bc
CV		 1156 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1157 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1158 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1159 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1160
1161 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1162 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1163 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1164
1165 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1166 set_gdbarch_addr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1167
1168 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1169 set_gdbarch_breakpoint_from_pc (gdbarch, v850_breakpoint_from_pc);
1170
1171 set_gdbarch_return_value (gdbarch, v850_return_value);
1172 set_gdbarch_push_dummy_call (gdbarch, v850_push_dummy_call);
1173 set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue);
1174
1175 set_gdbarch_print_insn (gdbarch, print_insn_v850);
1176
1177 set_gdbarch_frame_align (gdbarch, v850_frame_align);
1178 set_gdbarch_unwind_sp (gdbarch, v850_unwind_sp);
1179 set_gdbarch_unwind_pc (gdbarch, v850_unwind_pc);
94afd7a6 1180 set_gdbarch_dummy_id (gdbarch, v850_dummy_id);
181124bc
CV		 1181 frame_base_set_default (gdbarch, &v850_frame_base);
1182
1183 /* Hook in ABI-specific overrides, if they have been registered. */
1184 gdbarch_init_osabi (info, gdbarch);
1185
94afd7a6
UW		 1186 dwarf2_append_unwinders (gdbarch);
1187 frame_unwind_append_unwinder (gdbarch, &v850_frame_unwind);
181124bc
CV		 1188
1189 return gdbarch;
1190}
1191
1192extern initialize_file_ftype _initialize_v850_tdep; /* -Wmissing-prototypes */
1193
1194void
1195_initialize_v850_tdep (void)
1196{
1197 register_gdbarch_init (bfd_arch_v850, v850_gdbarch_init);
1198}
GDB Binutils - Deliverables
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