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[deliverable/binutils-gdb.git] / gdb / v850-tdep.c
CommitLineData
181124bc
CV		 1/* Target-dependent code for the NEC V850 for GDB, the GNU debugger.
2
9b254dd1 3 Copyright (C) 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007,
7b6bb8da 4 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
181124bc
CV		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
181124bc
CV		 11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
181124bc
CV		 20
21#include "defs.h"
22#include "frame.h"
23#include "frame-base.h"
24#include "trad-frame.h"
25#include "frame-unwind.h"
26#include "dwarf2-frame.h"
27#include "gdbtypes.h"
28#include "inferior.h"
29#include "gdb_string.h"
30#include "gdb_assert.h"
31#include "gdbcore.h"
32#include "arch-utils.h"
33#include "regcache.h"
34#include "dis-asm.h"
35#include "osabi.h"
36
37enum
38 {
39 E_R0_REGNUM,
40 E_R1_REGNUM,
41 E_R2_REGNUM,
42 E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM,
43 E_R4_REGNUM,
44 E_R5_REGNUM,
45 E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM,
46 E_R7_REGNUM,
47 E_R8_REGNUM,
48 E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM,
49 E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM,
50 E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM,
51 E_R12_REGNUM,
52 E_R13_REGNUM,
53 E_R14_REGNUM,
54 E_R15_REGNUM,
55 E_R16_REGNUM,
56 E_R17_REGNUM,
57 E_R18_REGNUM,
58 E_R19_REGNUM,
59 E_R20_REGNUM,
60 E_R21_REGNUM,
61 E_R22_REGNUM,
62 E_R23_REGNUM,
63 E_R24_REGNUM,
64 E_R25_REGNUM,
65 E_R26_REGNUM,
66 E_R27_REGNUM,
67 E_R28_REGNUM,
68 E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM,
69 E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM,
70 E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM,
71 E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM,
72 E_R33_REGNUM,
73 E_R34_REGNUM,
74 E_R35_REGNUM,
75 E_R36_REGNUM,
76 E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM,
77 E_R38_REGNUM,
78 E_R39_REGNUM,
79 E_R40_REGNUM,
80 E_R41_REGNUM,
81 E_R42_REGNUM,
82 E_R43_REGNUM,
83 E_R44_REGNUM,
84 E_R45_REGNUM,
85 E_R46_REGNUM,
86 E_R47_REGNUM,
87 E_R48_REGNUM,
88 E_R49_REGNUM,
89 E_R50_REGNUM,
90 E_R51_REGNUM,
91 E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM,
92 E_R53_REGNUM,
93 E_R54_REGNUM,
94 E_R55_REGNUM,
95 E_R56_REGNUM,
96 E_R57_REGNUM,
97 E_R58_REGNUM,
98 E_R59_REGNUM,
99 E_R60_REGNUM,
100 E_R61_REGNUM,
101 E_R62_REGNUM,
102 E_R63_REGNUM,
103 E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM,
104 E_R65_REGNUM,
105 E_NUM_REGS
106 };
107
108enum
109{
110 v850_reg_size = 4
111};
112
113/* Size of return datatype which fits into all return registers. */
114enum
115{
116 E_MAX_RETTYPE_SIZE_IN_REGS = 2 * v850_reg_size
117};
118
119struct v850_frame_cache
120{
121 /* Base address. */
122 CORE_ADDR base;
123 LONGEST sp_offset;
124 CORE_ADDR pc;
125
126 /* Flag showing that a frame has been created in the prologue code. */
127 int uses_fp;
128
129 /* Saved registers. */
130 struct trad_frame_saved_reg *saved_regs;
131};
132
133/* Info gleaned from scanning a function's prologue. */
134struct pifsr /* Info about one saved register. */
135{
136 int offset; /* Offset from sp or fp. */
137 int cur_frameoffset; /* Current frameoffset. */
138 int reg; /* Saved register number. */
139};
140
141static const char *
d93859e2 142v850_register_name (struct gdbarch *gdbarch, int regnum)
181124bc
CV		 143{
144 static const char *v850_reg_names[] =
145 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
146 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
147 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
148 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
149 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
150 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
151 "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
152 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
153 "pc", "fp"
154 };
155 if (regnum < 0 || regnum >= E_NUM_REGS)
156 return NULL;
157 return v850_reg_names[regnum];
158}
159
160static const char *
d93859e2 161v850e_register_name (struct gdbarch *gdbarch, int regnum)
181124bc
CV		 162{
163 static const char *v850e_reg_names[] =
164 {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
168 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
169 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
170 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
171 "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
172 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
173 "pc", "fp"
174 };
175 if (regnum < 0 || regnum >= E_NUM_REGS)
176 return NULL;
177 return v850e_reg_names[regnum];
178}
179
180/* Returns the default type for register N. */
181
182static struct type *
183v850_register_type (struct gdbarch *gdbarch, int regnum)
184{
185 if (regnum == E_PC_REGNUM)
0dfff4cb 186 return builtin_type (gdbarch)->builtin_func_ptr;
df4df182 187 return builtin_type (gdbarch)->builtin_int32;
181124bc
CV		 188}
189
190static int
191v850_type_is_scalar (struct type *t)
192{
193 return (TYPE_CODE (t) != TYPE_CODE_STRUCT
194 && TYPE_CODE (t) != TYPE_CODE_UNION
195 && TYPE_CODE (t) != TYPE_CODE_ARRAY);
196}
197
198/* Should call_function allocate stack space for a struct return? */
199static int
200v850_use_struct_convention (struct type *type)
201{
202 int i;
203 struct type *fld_type, *tgt_type;
204
205 /* 1. The value is greater than 8 bytes -> returned by copying. */
206 if (TYPE_LENGTH (type) > 8)
207 return 1;
208
209 /* 2. The value is a single basic type -> returned in register. */
210 if (v850_type_is_scalar (type))
211 return 0;
212
213 /* The value is a structure or union with a single element and that
214 element is either a single basic type or an array of a single basic
215 type whose size is greater than or equal to 4 -> returned in register. */
216 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
217 || TYPE_CODE (type) == TYPE_CODE_UNION)
218 && TYPE_NFIELDS (type) == 1)
219 {
220 fld_type = TYPE_FIELD_TYPE (type, 0);
221 if (v850_type_is_scalar (fld_type) && TYPE_LENGTH (fld_type) >= 4)
222 return 0;
223
224 if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY)
225 {
226 tgt_type = TYPE_TARGET_TYPE (fld_type);
227 if (v850_type_is_scalar (tgt_type) && TYPE_LENGTH (tgt_type) >= 4)
228 return 0;
229 }
230 }
231
232 /* The value is a structure whose first element is an integer or a float,
233 and which contains no arrays of more than two elements -> returned in
234 register. */
235 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
236 && v850_type_is_scalar (TYPE_FIELD_TYPE (type, 0))
237 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
238 {
239 for (i = 1; i < TYPE_NFIELDS (type); ++i)
240 {
241 fld_type = TYPE_FIELD_TYPE (type, 0);
242 if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY)
243 {
244 tgt_type = TYPE_TARGET_TYPE (fld_type);
245 if (TYPE_LENGTH (fld_type) >= 0 && TYPE_LENGTH (tgt_type) >= 0
246 && TYPE_LENGTH (fld_type) / TYPE_LENGTH (tgt_type) > 2)
247 return 1;
248 }
249 }
250 return 0;
251 }
252
581e13c1
MS		 253 /* The value is a union which contains at least one field which
254 would be returned in registers according to these rules ->
255 returned in register. */
181124bc
CV		 256 if (TYPE_CODE (type) == TYPE_CODE_UNION)
257 {
258 for (i = 0; i < TYPE_NFIELDS (type); ++i)
259 {
260 fld_type = TYPE_FIELD_TYPE (type, 0);
261 if (!v850_use_struct_convention (fld_type))
262 return 0;
263 }
264 }
265
266 return 1;
267}
268
269/* Structure for mapping bits in register lists to register numbers. */
270struct reg_list
271{
272 long mask;
273 int regno;
274};
275
276/* Helper function for v850_scan_prologue to handle prepare instruction. */
277
278static void
279v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
280 struct v850_frame_cache *pi, struct pifsr **pifsr_ptr)
281{
282 CORE_ADDR current_pc = *current_pc_ptr;
283 struct pifsr *pifsr = *pifsr_ptr;
284 long next = insn2 & 0xffff;
285 long list12 = ((insn & 1) << 16) + (next & 0xffe0);
286 long offset = (insn & 0x3e) << 1;
287 static struct reg_list reg_table[] =
288 {
289 {0x00800, 20}, /* r20 */
290 {0x00400, 21}, /* r21 */
291 {0x00200, 22}, /* r22 */
292 {0x00100, 23}, /* r23 */
293 {0x08000, 24}, /* r24 */
294 {0x04000, 25}, /* r25 */
295 {0x02000, 26}, /* r26 */
296 {0x01000, 27}, /* r27 */
297 {0x00080, 28}, /* r28 */
298 {0x00040, 29}, /* r29 */
299 {0x10000, 30}, /* ep */
300 {0x00020, 31}, /* lp */
301 {0, 0} /* end of table */
302 };
303 int i;
304
305 if ((next & 0x1f) == 0x0b) /* skip imm16 argument */
306 current_pc += 2;
307 else if ((next & 0x1f) == 0x13) /* skip imm16 argument */
308 current_pc += 2;
309 else if ((next & 0x1f) == 0x1b) /* skip imm32 argument */
310 current_pc += 4;
311
312 /* Calculate the total size of the saved registers, and add it to the
313 immediate value used to adjust SP. */
314 for (i = 0; reg_table[i].mask != 0; i++)
315 if (list12 & reg_table[i].mask)
316 offset += v850_reg_size;
317 pi->sp_offset -= offset;
318
319 /* Calculate the offsets of the registers relative to the value the SP
320 will have after the registers have been pushed and the imm5 value has
321 been subtracted from it. */
322 if (pifsr)
323 {
324 for (i = 0; reg_table[i].mask != 0; i++)
325 {
326 if (list12 & reg_table[i].mask)
327 {
328 int reg = reg_table[i].regno;
329 offset -= v850_reg_size;
330 pifsr->reg = reg;
331 pifsr->offset = offset;
332 pifsr->cur_frameoffset = pi->sp_offset;
333 pifsr++;
334 }
335 }
336 }
337
338 /* Set result parameters. */
339 *current_pc_ptr = current_pc;
340 *pifsr_ptr = pifsr;
341}
342
343
344/* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
345 The SR bit of the register list is not supported. gcc does not generate
346 this bit. */
347
348static void
349v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
350 struct pifsr **pifsr_ptr)
351{
352 struct pifsr *pifsr = *pifsr_ptr;
353 long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0);
354 long offset = 0;
355 static struct reg_list pushml_reg_table[] =
356 {
357 {0x80000, E_PS_REGNUM}, /* PSW */
358 {0x40000, 1}, /* r1 */
359 {0x20000, 2}, /* r2 */
360 {0x10000, 3}, /* r3 */
361 {0x00800, 4}, /* r4 */
362 {0x00400, 5}, /* r5 */
363 {0x00200, 6}, /* r6 */
364 {0x00100, 7}, /* r7 */
365 {0x08000, 8}, /* r8 */
366 {0x04000, 9}, /* r9 */
367 {0x02000, 10}, /* r10 */
368 {0x01000, 11}, /* r11 */
369 {0x00080, 12}, /* r12 */
370 {0x00040, 13}, /* r13 */
371 {0x00020, 14}, /* r14 */
372 {0x00010, 15}, /* r15 */
373 {0, 0} /* end of table */
374 };
375 static struct reg_list pushmh_reg_table[] =
376 {
377 {0x80000, 16}, /* r16 */
378 {0x40000, 17}, /* r17 */
379 {0x20000, 18}, /* r18 */
380 {0x10000, 19}, /* r19 */
381 {0x00800, 20}, /* r20 */
382 {0x00400, 21}, /* r21 */
383 {0x00200, 22}, /* r22 */
384 {0x00100, 23}, /* r23 */
385 {0x08000, 24}, /* r24 */
386 {0x04000, 25}, /* r25 */
387 {0x02000, 26}, /* r26 */
388 {0x01000, 27}, /* r27 */
389 {0x00080, 28}, /* r28 */
390 {0x00040, 29}, /* r29 */
391 {0x00010, 30}, /* r30 */
392 {0x00020, 31}, /* r31 */
393 {0, 0} /* end of table */
394 };
395 struct reg_list *reg_table;
396 int i;
397
398 /* Is this a pushml or a pushmh? */
399 if ((insn2 & 7) == 1)
400 reg_table = pushml_reg_table;
401 else
402 reg_table = pushmh_reg_table;
403
404 /* Calculate the total size of the saved registers, and add it it to the
405 immediate value used to adjust SP. */
406 for (i = 0; reg_table[i].mask != 0; i++)
407 if (list12 & reg_table[i].mask)
408 offset += v850_reg_size;
409 pi->sp_offset -= offset;
410
411 /* Calculate the offsets of the registers relative to the value the SP
412 will have after the registers have been pushed and the imm5 value is
413 subtracted from it. */
414 if (pifsr)
415 {
416 for (i = 0; reg_table[i].mask != 0; i++)
417 {
418 if (list12 & reg_table[i].mask)
419 {
420 int reg = reg_table[i].regno;
421 offset -= v850_reg_size;
422 pifsr->reg = reg;
423 pifsr->offset = offset;
424 pifsr->cur_frameoffset = pi->sp_offset;
425 pifsr++;
426 }
427 }
428 }
429
430 /* Set result parameters. */
431 *pifsr_ptr = pifsr;
432}
433
434/* Helper function to evaluate if register is one of the "save" registers.
435 This allows to simplify conditionals in v850_analyze_prologue a lot. */
436
437static int
438v850_is_save_register (int reg)
439{
440 /* The caller-save registers are R2, R20 - R29 and R31. All other
441 registers are either special purpose (PC, SP), argument registers,
581e13c1 442 or just considered free for use in the caller. */
181124bc
CV		 443 return reg == E_R2_REGNUM
444 || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
445 || reg == E_R31_REGNUM;
446}
447
448/* Scan the prologue of the function that contains PC, and record what
449 we find in PI. Returns the pc after the prologue. Note that the
450 addresses saved in frame->saved_regs are just frame relative (negative
451 offsets from the frame pointer). This is because we don't know the
452 actual value of the frame pointer yet. In some circumstances, the
453 frame pointer can't be determined till after we have scanned the
454 prologue. */
455
456static CORE_ADDR
e17a4113
UW		 457v850_analyze_prologue (struct gdbarch *gdbarch,
458 CORE_ADDR func_addr, CORE_ADDR pc,
d2ca4222 459 struct v850_frame_cache *pi, ULONGEST ctbp)
181124bc 460{
e17a4113 461 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 462 CORE_ADDR prologue_end, current_pc;
463 struct pifsr pifsrs[E_NUM_REGS + 1];
464 struct pifsr *pifsr, *pifsr_tmp;
465 int fp_used;
466 int ep_used;
467 int reg;
468 CORE_ADDR save_pc, save_end;
469 int regsave_func_p;
470 int r12_tmp;
471
472 memset (&pifsrs, 0, sizeof pifsrs);
473 pifsr = &pifsrs[0];
474
475 prologue_end = pc;
476
477 /* Now, search the prologue looking for instructions that setup fp, save
478 rp, adjust sp and such. We also record the frame offset of any saved
479 registers. */
480
481 pi->sp_offset = 0;
482 pi->uses_fp = 0;
483 ep_used = 0;
484 regsave_func_p = 0;
485 save_pc = 0;
486 save_end = 0;
487 r12_tmp = 0;
488
489 for (current_pc = func_addr; current_pc < prologue_end;)
490 {
491 int insn;
492 int insn2 = -1; /* dummy value */
493
e17a4113 494 insn = read_memory_integer (current_pc, 2, byte_order);
181124bc 495 current_pc += 2;
581e13c1 496 if ((insn & 0x0780) >= 0x0600) /* Four byte instruction? */
181124bc 497 {
e17a4113 498 insn2 = read_memory_integer (current_pc, 2, byte_order);
181124bc
CV		 499 current_pc += 2;
500 }
501
502 if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p)
503 { /* jarl <func>,10 */
504 long low_disp = insn2 & ~(long) 1;
505 long disp = (((((insn & 0x3f) << 16) + low_disp)
506 & ~(long) 1) ^ 0x00200000) - 0x00200000;
507
508 save_pc = current_pc;
509 save_end = prologue_end;
510 regsave_func_p = 1;
511 current_pc += disp - 4;
512 prologue_end = (current_pc
513 + (2 * 3) /* moves to/from ep */
514 + 4 /* addi <const>,sp,sp */
515 + 2 /* jmp [r10] */
516 + (2 * 12) /* sst.w to save r2, r20-r29, r31 */
517 + 20); /* slop area */
518 }
519 else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p)
520 { /* callt <imm6> */
181124bc
CV		 521 long adr = ctbp + ((insn & 0x3f) << 1);
522
523 save_pc = current_pc;
524 save_end = prologue_end;
525 regsave_func_p = 1;
e17a4113
UW		 526 current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order)
527 & 0xffff);
181124bc
CV		 528 prologue_end = (current_pc
529 + (2 * 3) /* prepare list2,imm5,sp/imm */
530 + 4 /* ctret */
531 + 20); /* slop area */
532 continue;
533 }
534 else if ((insn & 0xffc0) == 0x0780) /* prepare list2,imm5 */
535 {
536 v850_handle_prepare (insn, insn2, &current_pc, pi, &pifsr);
537 continue;
538 }
539 else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144)
540 { /* ctret after processing register save. */
541 current_pc = save_pc;
542 prologue_end = save_end;
543 regsave_func_p = 0;
544 continue;
545 }
546 else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1)
547 { /* pushml, pushmh */
548 v850_handle_pushm (insn, insn2, pi, &pifsr);
549 continue;
550 }
551 else if ((insn & 0xffe0) == 0x0060 && regsave_func_p)
552 { /* jmp after processing register save. */
553 current_pc = save_pc;
554 prologue_end = save_end;
555 regsave_func_p = 0;
556 continue;
557 }
558 else if ((insn & 0x07c0) == 0x0780 /* jarl or jr */
559 || (insn & 0xffe0) == 0x0060 /* jmp */
560 || (insn & 0x0780) == 0x0580) /* branch */
561 {
581e13c1 562 break; /* Ran into end of prologue. */
181124bc
CV		 563 }
564
565 else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240))
566 /* add <imm>,sp */
567 pi->sp_offset += ((insn & 0x1f) ^ 0x10) - 0x10;
568 else if (insn == ((E_SP_REGNUM << 11) | 0x0600 | E_SP_REGNUM))
569 /* addi <imm>,sp,sp */
570 pi->sp_offset += insn2;
571 else if (insn == ((E_FP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
572 /* mov sp,fp */
573 pi->uses_fp = 1;
574 else if (insn == ((E_R12_REGNUM << 11) | 0x0640 | E_R0_REGNUM))
575 /* movhi hi(const),r0,r12 */
576 r12_tmp = insn2 << 16;
577 else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM))
578 /* movea lo(const),r12,r12 */
579 r12_tmp += insn2;
580 else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp)
581 /* add r12,sp */
582 pi->sp_offset += r12_tmp;
583 else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
584 /* mov sp,ep */
585 ep_used = 1;
586 else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM))
587 /* mov r1,ep */
588 ep_used = 0;
589 else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)
590 || (pi->uses_fp
591 && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
592 && pifsr
593 && v850_is_save_register (reg = (insn >> 11) & 0x1f))
594 {
595 /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
596 pifsr->reg = reg;
597 pifsr->offset = insn2 & ~1;
598 pifsr->cur_frameoffset = pi->sp_offset;
599 pifsr++;
600 }
601 else if (ep_used
602 && ((insn & 0x0781) == 0x0501)
603 && pifsr
604 && v850_is_save_register (reg = (insn >> 11) & 0x1f))
605 {
606 /* sst.w <reg>,<offset>[ep] */
607 pifsr->reg = reg;
608 pifsr->offset = (insn & 0x007e) << 1;
609 pifsr->cur_frameoffset = pi->sp_offset;
610 pifsr++;
611 }
612 }
613
614 /* Fix up any offsets to the final offset. If a frame pointer was created,
615 use it instead of the stack pointer. */
616 for (pifsr_tmp = pifsrs; pifsr_tmp != pifsr; pifsr_tmp++)
617 {
618 pifsr_tmp->offset -= pi->sp_offset - pifsr_tmp->cur_frameoffset;
619 pi->saved_regs[pifsr_tmp->reg].addr = pifsr_tmp->offset;
620 }
621
622 return current_pc;
623}
624
625/* Return the address of the first code past the prologue of the function. */
626
627static CORE_ADDR
6093d2eb 628v850_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
181124bc
CV		 629{
630 CORE_ADDR func_addr, func_end;
631
581e13c1 632 /* See what the symbol table says. */
181124bc
CV		 633
634 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
635 {
636 struct symtab_and_line sal;
637
638 sal = find_pc_line (func_addr, 0);
639 if (sal.line != 0 && sal.end < func_end)
640 return sal.end;
641
642 /* Either there's no line info, or the line after the prologue is after
643 the end of the function. In this case, there probably isn't a
644 prologue. */
645 return pc;
646 }
647
581e13c1
MS		 648 /* We can't find the start of this function, so there's nothing we
649 can do. */
181124bc
CV		 650 return pc;
651}
652
653static CORE_ADDR
654v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
655{
656 return sp & ~3;
657}
658
659/* Setup arguments and LP for a call to the target. First four args
660 go in R6->R9, subsequent args go into sp + 16 -> sp + ... Structs
661 are passed by reference. 64 bit quantities (doubles and long longs)
662 may be split between the regs and the stack. When calling a function
663 that returns a struct, a pointer to the struct is passed in as a secret
664 first argument (always in R6).
665
666 Stack space for the args has NOT been allocated: that job is up to us. */
667
668static CORE_ADDR
669v850_push_dummy_call (struct gdbarch *gdbarch,
670 struct value *function,
671 struct regcache *regcache,
672 CORE_ADDR bp_addr,
673 int nargs,
674 struct value **args,
675 CORE_ADDR sp,
676 int struct_return,
677 CORE_ADDR struct_addr)
678{
e17a4113 679 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 680 int argreg;
681 int argnum;
682 int len = 0;
683 int stack_offset;
684
685 /* The offset onto the stack at which we will start copying parameters
686 (after the registers are used up) begins at 16 rather than at zero.
687 That's how the ABI is defined, though there's no indication that these
688 16 bytes are used for anything, not even for saving incoming
689 argument registers. */
690 stack_offset = 16;
691
692 /* Now make space on the stack for the args. */
693 for (argnum = 0; argnum < nargs; argnum++)
694 len += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3);
695 sp -= len + stack_offset;
696
697 argreg = E_ARG0_REGNUM;
698 /* The struct_return pointer occupies the first parameter register. */
699 if (struct_return)
700 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
701
702 /* Now load as many as possible of the first arguments into
703 registers, and push the rest onto the stack. There are 16 bytes
704 in four registers available. Loop thru args from first to last. */
705 for (argnum = 0; argnum < nargs; argnum++)
706 {
707 int len;
708 gdb_byte *val;
709 gdb_byte valbuf[v850_reg_size];
710
711 if (!v850_type_is_scalar (value_type (*args))
712 && TYPE_LENGTH (value_type (*args)) > E_MAX_RETTYPE_SIZE_IN_REGS)
713 {
e17a4113
UW		 714 store_unsigned_integer (valbuf, 4, byte_order,
715 value_address (*args));
181124bc
CV		 716 len = 4;
717 val = valbuf;
718 }
719 else
720 {
721 len = TYPE_LENGTH (value_type (*args));
722 val = (gdb_byte *) value_contents (*args);
723 }
724
725 while (len > 0)
726 if (argreg <= E_ARGLAST_REGNUM)
727 {
728 CORE_ADDR regval;
729
e17a4113 730 regval = extract_unsigned_integer (val, v850_reg_size, byte_order);
181124bc
CV		 731 regcache_cooked_write_unsigned (regcache, argreg, regval);
732
733 len -= v850_reg_size;
734 val += v850_reg_size;
735 argreg++;
736 }
737 else
738 {
739 write_memory (sp + stack_offset, val, 4);
740
741 len -= 4;
742 val += 4;
743 stack_offset += 4;
744 }
745 args++;
746 }
747
748 /* Store return address. */
749 regcache_cooked_write_unsigned (regcache, E_LP_REGNUM, bp_addr);
750
751 /* Update stack pointer. */
752 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
753
754 return sp;
755}
756
757static void
758v850_extract_return_value (struct type *type, struct regcache *regcache,
759 gdb_byte *valbuf)
760{
e17a4113
UW		 761 struct gdbarch *gdbarch = get_regcache_arch (regcache);
762 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 763 int len = TYPE_LENGTH (type);
764
765 if (len <= v850_reg_size)
766 {
767 ULONGEST val;
768
769 regcache_cooked_read_unsigned (regcache, E_V0_REGNUM, &val);
e17a4113 770 store_unsigned_integer (valbuf, len, byte_order, val);
181124bc
CV		 771 }
772 else if (len <= 2 * v850_reg_size)
773 {
774 int i, regnum = E_V0_REGNUM;
775 gdb_byte buf[v850_reg_size];
776 for (i = 0; len > 0; i += 4, len -= 4)
777 {
778 regcache_raw_read (regcache, regnum++, buf);
779 memcpy (valbuf + i, buf, len > 4 ? 4 : len);
780 }
781 }
782}
783
784static void
785v850_store_return_value (struct type *type, struct regcache *regcache,
786 const gdb_byte *valbuf)
787{
e17a4113
UW		 788 struct gdbarch *gdbarch = get_regcache_arch (regcache);
789 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 790 int len = TYPE_LENGTH (type);
791
792 if (len <= v850_reg_size)
e17a4113
UW		 793 regcache_cooked_write_unsigned
794 (regcache, E_V0_REGNUM,
795 extract_unsigned_integer (valbuf, len, byte_order));
181124bc
CV		 796 else if (len <= 2 * v850_reg_size)
797 {
798 int i, regnum = E_V0_REGNUM;
799 for (i = 0; i < len; i += 4)
800 regcache_raw_write (regcache, regnum++, valbuf + i);
801 }
802}
803
804static enum return_value_convention
c055b101
CV		 805v850_return_value (struct gdbarch *gdbarch, struct type *func_type,
806 struct type *type, struct regcache *regcache,
181124bc
CV		 807 gdb_byte *readbuf, const gdb_byte *writebuf)
808{
809 if (v850_use_struct_convention (type))
810 return RETURN_VALUE_STRUCT_CONVENTION;
811 if (writebuf)
812 v850_store_return_value (type, regcache, writebuf);
813 else if (readbuf)
814 v850_extract_return_value (type, regcache, readbuf);
815 return RETURN_VALUE_REGISTER_CONVENTION;
816}
817
818const static unsigned char *
67d57894 819v850_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
181124bc
CV		 820{
821 static unsigned char breakpoint[] = { 0x85, 0x05 };
822 *lenptr = sizeof (breakpoint);
823 return breakpoint;
824}
825
826static struct v850_frame_cache *
94afd7a6 827v850_alloc_frame_cache (struct frame_info *this_frame)
181124bc
CV		 828{
829 struct v850_frame_cache *cache;
830 int i;
831
832 cache = FRAME_OBSTACK_ZALLOC (struct v850_frame_cache);
94afd7a6 833 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
181124bc
CV		 834
835 /* Base address. */
836 cache->base = 0;
837 cache->sp_offset = 0;
838 cache->pc = 0;
839
840 /* Frameless until proven otherwise. */
841 cache->uses_fp = 0;
842
843 return cache;
844}
845
846static struct v850_frame_cache *
94afd7a6 847v850_frame_cache (struct frame_info *this_frame, void **this_cache)
181124bc 848{
e17a4113 849 struct gdbarch *gdbarch = get_frame_arch (this_frame);
181124bc
CV		 850 struct v850_frame_cache *cache;
851 CORE_ADDR current_pc;
852 int i;
853
854 if (*this_cache)
855 return *this_cache;
856
94afd7a6 857 cache = v850_alloc_frame_cache (this_frame);
181124bc
CV		 858 *this_cache = cache;
859
860 /* In principle, for normal frames, fp holds the frame pointer,
861 which holds the base address for the current stack frame.
862 However, for functions that don't need it, the frame pointer is
863 optional. For these "frameless" functions the frame pointer is
864 actually the frame pointer of the calling frame. */
94afd7a6 865 cache->base = get_frame_register_unsigned (this_frame, E_FP_REGNUM);
181124bc
CV		 866 if (cache->base == 0)
867 return cache;
868
94afd7a6
UW		 869 cache->pc = get_frame_func (this_frame);
870 current_pc = get_frame_pc (this_frame);
181124bc 871 if (cache->pc != 0)
d2ca4222
UW		 872 {
873 ULONGEST ctbp;
94afd7a6 874 ctbp = get_frame_register_unsigned (this_frame, E_CTBP_REGNUM);
e17a4113 875 v850_analyze_prologue (gdbarch, cache->pc, current_pc, cache, ctbp);
d2ca4222 876 }
181124bc
CV		 877
878 if (!cache->uses_fp)
879 {
880 /* We didn't find a valid frame, which means that CACHE->base
881 currently holds the frame pointer for our calling frame. If
882 we're at the start of a function, or somewhere half-way its
883 prologue, the function's frame probably hasn't been fully
884 setup yet. Try to reconstruct the base address for the stack
885 frame by looking at the stack pointer. For truly "frameless"
886 functions this might work too. */
94afd7a6 887 cache->base = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
181124bc
CV		 888 }
889
890 /* Now that we have the base address for the stack frame we can
891 calculate the value of sp in the calling frame. */
892 trad_frame_set_value (cache->saved_regs, E_SP_REGNUM,
893 cache->base - cache->sp_offset);
894
895 /* Adjust all the saved registers such that they contain addresses
896 instead of offsets. */
897 for (i = 0; i < E_NUM_REGS; i++)
898 if (trad_frame_addr_p (cache->saved_regs, i))
899 cache->saved_regs[i].addr += cache->base;
900
901 /* The call instruction moves the caller's PC in the callee's LP.
902 Since this is an unwind, do the reverse. Copy the location of LP
903 into PC (the address / regnum) so that a request for PC will be
904 converted into a request for the LP. */
905
906 cache->saved_regs[E_PC_REGNUM] = cache->saved_regs[E_LP_REGNUM];
907
908 return cache;
909}
910
911
94afd7a6
UW		 912static struct value *
913v850_frame_prev_register (struct frame_info *this_frame,
914 void **this_cache, int regnum)
181124bc 915{
94afd7a6 916 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 917
918 gdb_assert (regnum >= 0);
919
94afd7a6 920 return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
181124bc
CV		 921}
922
923static void
94afd7a6 924v850_frame_this_id (struct frame_info *this_frame, void **this_cache,
181124bc
CV		 925 struct frame_id *this_id)
926{
94afd7a6 927 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 928
929 /* This marks the outermost frame. */
930 if (cache->base == 0)
931 return;
932
933 *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr, cache->pc);
934}
935
936static const struct frame_unwind v850_frame_unwind = {
937 NORMAL_FRAME,
8fbca658 938 default_frame_unwind_stop_reason,
181124bc 939 v850_frame_this_id,
94afd7a6
UW		 940 v850_frame_prev_register,
941 NULL,
942 default_frame_sniffer
181124bc 943};
181124bc
CV		 944
945static CORE_ADDR
946v850_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
947{
3e8c568d 948 return frame_unwind_register_unsigned (next_frame,
d93859e2 949 gdbarch_sp_regnum (gdbarch));
181124bc
CV		 950}
951
952static CORE_ADDR
953v850_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
954{
3e8c568d 955 return frame_unwind_register_unsigned (next_frame,
d93859e2 956 gdbarch_pc_regnum (gdbarch));
181124bc
CV		 957}
958
959static struct frame_id
94afd7a6 960v850_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
181124bc 961{
94afd7a6
UW		 962 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
963 gdbarch_sp_regnum (gdbarch));
964 return frame_id_build (sp, get_frame_pc (this_frame));
181124bc
CV		 965}
966
967static CORE_ADDR
94afd7a6 968v850_frame_base_address (struct frame_info *this_frame, void **this_cache)
181124bc 969{
94afd7a6 970 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 971
972 return cache->base;
973}
974
975static const struct frame_base v850_frame_base = {
976 &v850_frame_unwind,
977 v850_frame_base_address,
978 v850_frame_base_address,
979 v850_frame_base_address
980};
981
982static struct gdbarch *
983v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
984{
985 struct gdbarch *gdbarch;
986
987 /* Change the register names based on the current machine type. */
988 if (info.bfd_arch_info->arch != bfd_arch_v850)
989 return NULL;
990
991 gdbarch = gdbarch_alloc (&info, NULL);
992
993 switch (info.bfd_arch_info->mach)
994 {
995 case bfd_mach_v850:
996 set_gdbarch_register_name (gdbarch, v850_register_name);
997 break;
998 case bfd_mach_v850e:
999 case bfd_mach_v850e1:
1000 set_gdbarch_register_name (gdbarch, v850e_register_name);
1001 break;
1002 }
1003
1004 set_gdbarch_num_regs (gdbarch, E_NUM_REGS);
1005 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1006 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
1007 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1008 set_gdbarch_fp0_regnum (gdbarch, -1);
1009
1010 set_gdbarch_register_type (gdbarch, v850_register_type);
1011
351a3e56 1012 set_gdbarch_char_signed (gdbarch, 1);
181124bc
CV		 1013 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1014 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1015 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1016 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1017
1018 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1019 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1020 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1021
1022 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1023 set_gdbarch_addr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1024
1025 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1026 set_gdbarch_breakpoint_from_pc (gdbarch, v850_breakpoint_from_pc);
1027
1028 set_gdbarch_return_value (gdbarch, v850_return_value);
1029 set_gdbarch_push_dummy_call (gdbarch, v850_push_dummy_call);
1030 set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue);
1031
1032 set_gdbarch_print_insn (gdbarch, print_insn_v850);
1033
1034 set_gdbarch_frame_align (gdbarch, v850_frame_align);
1035 set_gdbarch_unwind_sp (gdbarch, v850_unwind_sp);
1036 set_gdbarch_unwind_pc (gdbarch, v850_unwind_pc);
94afd7a6 1037 set_gdbarch_dummy_id (gdbarch, v850_dummy_id);
181124bc
CV		 1038 frame_base_set_default (gdbarch, &v850_frame_base);
1039
1040 /* Hook in ABI-specific overrides, if they have been registered. */
1041 gdbarch_init_osabi (info, gdbarch);
1042
94afd7a6
UW		 1043 dwarf2_append_unwinders (gdbarch);
1044 frame_unwind_append_unwinder (gdbarch, &v850_frame_unwind);
181124bc
CV		 1045
1046 return gdbarch;
1047}
1048
1049extern initialize_file_ftype _initialize_v850_tdep; /* -Wmissing-prototypes */
1050
1051void
1052_initialize_v850_tdep (void)
1053{
1054 register_gdbarch_init (bfd_arch_v850, v850_gdbarch_init);
1055}
GDB Binutils - Deliverables
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