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* cli/cli-cmds.c (shell_escape): Silence warnings from old
[deliverable/binutils-gdb.git] / gdb / x86-64-tdep.c
CommitLineData
53e95fcf 1/* Target-dependent code for the x86-64 for GDB, the GNU debugger.
ce0eebec 2
51603483 3 Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
53e95fcf
JS		 4 Contributed by Jiri Smid, SuSE Labs.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23#include "defs.h"
c4f35dd8
MK		 24#include "arch-utils.h"
25#include "block.h"
26#include "dummy-frame.h"
27#include "frame.h"
28#include "frame-base.h"
29#include "frame-unwind.h"
53e95fcf 30#include "inferior.h"
53e95fcf 31#include "gdbcmd.h"
c4f35dd8
MK		 32#include "gdbcore.h"
33#include "objfiles.h"
53e95fcf
JS		 34#include "regcache.h"
35#include "symfile.h"
c4f35dd8 36
82dbc5f7 37#include "gdb_assert.h"
c4f35dd8
MK		 38
39#include "x86-64-tdep.h"
40#include "i387-tdep.h"
53e95fcf 41
53e95fcf 42/* Register numbers of various important registers. */
c4f35dd8
MK		 43
44#define X86_64_RAX_REGNUM 0 /* %rax */
45#define X86_64_RDX_REGNUM 3 /* %rdx */
46#define X86_64_RDI_REGNUM 5 /* %rdi */
47#define X86_64_RBP_REGNUM 6 /* %rbp */
48#define X86_64_RSP_REGNUM 7 /* %rsp */
49#define X86_64_RIP_REGNUM 16 /* %rip */
50#define X86_64_EFLAGS_REGNUM 17 /* %eflags */
51#define X86_64_ST0_REGNUM 22 /* %st0 */
52#define X86_64_XMM0_REGNUM 38 /* %xmm0 */
53#define X86_64_XMM1_REGNUM 39 /* %xmm1 */
54
55struct x86_64_register_info
de220d0f 56{
de220d0f
ML		 57 char *name;
58 struct type **type;
59};
53e95fcf 60
c4f35dd8
MK		 61static struct x86_64_register_info x86_64_register_info[] =
62{
63 { "rax", &builtin_type_int64 },
64 { "rbx", &builtin_type_int64 },
65 { "rcx", &builtin_type_int64 },
66 { "rdx", &builtin_type_int64 },
67 { "rsi", &builtin_type_int64 },
68 { "rdi", &builtin_type_int64 },
69 { "rbp", &builtin_type_void_data_ptr },
70 { "rsp", &builtin_type_void_data_ptr },
71
72 /* %r8 is indeed register number 8. */
73 { "r8", &builtin_type_int64 },
74 { "r9", &builtin_type_int64 },
75 { "r10", &builtin_type_int64 },
76 { "r11", &builtin_type_int64 },
77 { "r12", &builtin_type_int64 },
78 { "r13", &builtin_type_int64 },
79 { "r14", &builtin_type_int64 },
80 { "r15", &builtin_type_int64 },
81 { "rip", &builtin_type_void_func_ptr },
82 { "eflags", &builtin_type_int32 },
83 { "ds", &builtin_type_int32 },
84 { "es", &builtin_type_int32 },
85 { "fs", &builtin_type_int32 },
86 { "gs", &builtin_type_int32 },
87
88 /* %st0 is register number 22. */
89 { "st0", &builtin_type_i387_ext },
90 { "st1", &builtin_type_i387_ext },
91 { "st2", &builtin_type_i387_ext },
92 { "st3", &builtin_type_i387_ext },
93 { "st4", &builtin_type_i387_ext },
94 { "st5", &builtin_type_i387_ext },
95 { "st6", &builtin_type_i387_ext },
96 { "st7", &builtin_type_i387_ext },
97 { "fctrl", &builtin_type_int32 },
98 { "fstat", &builtin_type_int32 },
99 { "ftag", &builtin_type_int32 },
100 { "fiseg", &builtin_type_int32 },
101 { "fioff", &builtin_type_int32 },
102 { "foseg", &builtin_type_int32 },
103 { "fooff", &builtin_type_int32 },
104 { "fop", &builtin_type_int32 },
105
106 /* %xmm0 is register number 38. */
107 { "xmm0", &builtin_type_v4sf },
108 { "xmm1", &builtin_type_v4sf },
109 { "xmm2", &builtin_type_v4sf },
110 { "xmm3", &builtin_type_v4sf },
111 { "xmm4", &builtin_type_v4sf },
112 { "xmm5", &builtin_type_v4sf },
113 { "xmm6", &builtin_type_v4sf },
114 { "xmm7", &builtin_type_v4sf },
115 { "xmm8", &builtin_type_v4sf },
116 { "xmm9", &builtin_type_v4sf },
117 { "xmm10", &builtin_type_v4sf },
118 { "xmm11", &builtin_type_v4sf },
119 { "xmm12", &builtin_type_v4sf },
120 { "xmm13", &builtin_type_v4sf },
121 { "xmm14", &builtin_type_v4sf },
122 { "xmm15", &builtin_type_v4sf },
123 { "mxcsr", &builtin_type_int32 }
0e04a514
ML		 124};
125
c4f35dd8
MK		 126/* Total number of registers. */
127#define X86_64_NUM_REGS \
128 (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
de220d0f 129
c4f35dd8 130/* Return the name of register REGNUM. */
b6779aa2 131
c4f35dd8
MK		 132static const char *
133x86_64_register_name (int regnum)
53e95fcf 134{
c4f35dd8
MK		 135 if (regnum >= 0 && regnum < X86_64_NUM_REGS)
136 return x86_64_register_info[regnum].name;
53e95fcf 137
c4f35dd8 138 return NULL;
53e95fcf
JS		 139}
140
141/* Return the GDB type object for the "standard" data type of data in
c4f35dd8 142 register REGNUM. */
53e95fcf 143
c4f35dd8
MK		 144static struct type *
145x86_64_register_type (struct gdbarch *gdbarch, int regnum)
53e95fcf 146{
c4f35dd8 147 gdb_assert (regnum >= 0 && regnum < X86_64_NUM_REGS);
4657573b 148
c4f35dd8 149 return *x86_64_register_info[regnum].type;
53e95fcf
JS		 150}
151
c4f35dd8
MK		 152/* DWARF Register Number Mapping as defined in the System V psABI,
153 section 3.6. */
53e95fcf 154
c4f35dd8 155static int x86_64_dwarf_regmap[] =
0e04a514 156{
c4f35dd8
MK		 157 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
158 X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 3, 2,
159 4, X86_64_RDI_REGNUM,
160
161 /* Frame Pointer Register RBP. */
162 X86_64_RBP_REGNUM,
163
164 /* Stack Pointer Register RSP. */
165 X86_64_RSP_REGNUM,
166
167 /* Extended Integer Registers 8 - 15. */
168 8, 9, 10, 11, 12, 13, 14, 15,
169
170 /* Return Address RA. Not mapped. */
171 -1,
172
173 /* SSE Registers 0 - 7. */
174 X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
175 X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
176 X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
177 X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
178
179 /* Extended SSE Registers 8 - 15. */
180 X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9,
181 X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11,
182 X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13,
183 X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15,
184
185 /* Floating Point Registers 0-7. */
186 X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1,
187 X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3,
188 X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5,
189 X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7
190};
0e04a514 191
c4f35dd8
MK		 192static const int x86_64_dwarf_regmap_len =
193 (sizeof (x86_64_dwarf_regmap) / sizeof (x86_64_dwarf_regmap[0]));
0e04a514 194
c4f35dd8
MK		 195/* Convert DWARF register number REG to the appropriate register
196 number used by GDB. */
26abbdc4 197
c4f35dd8
MK		 198static int
199x86_64_dwarf_reg_to_regnum (int reg)
53e95fcf 200{
c4f35dd8 201 int regnum = -1;
53e95fcf 202
c4f35dd8
MK		 203 if (reg >= 0 || reg < x86_64_dwarf_regmap_len)
204 regnum = x86_64_dwarf_regmap[reg];
53e95fcf 205
c4f35dd8
MK		 206 if (regnum == -1)
207 warning ("Unmapped DWARF Register #%d encountered\n", reg);
208
209 return regnum;
53e95fcf 210}
d532c08f
MK		 211
212/* Return nonzero if a value of type TYPE stored in register REGNUM
213 needs any special handling. */
214
215static int
216x86_64_convert_register_p (int regnum, struct type *type)
217{
218 return i386_fp_regnum_p (regnum);
219}
53e95fcf
JS		 220\f
221
222/* The returning of values is done according to the special algorithm.
c4f35dd8
MK		 223 Some types are returned in registers an some (big structures) in
224 memory. See the System V psABI for details. */
53e95fcf
JS		 225
226#define MAX_CLASSES 4
227
228enum x86_64_reg_class
229{
230 X86_64_NO_CLASS,
231 X86_64_INTEGER_CLASS,
232 X86_64_INTEGERSI_CLASS,
233 X86_64_SSE_CLASS,
234 X86_64_SSESF_CLASS,
235 X86_64_SSEDF_CLASS,
236 X86_64_SSEUP_CLASS,
237 X86_64_X87_CLASS,
238 X86_64_X87UP_CLASS,
239 X86_64_MEMORY_CLASS
240};
241
242/* Return the union class of CLASS1 and CLASS2.
c4f35dd8 243 See the System V psABI for details. */
53e95fcf
JS		 244
245static enum x86_64_reg_class
246merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
247{
c4f35dd8 248 /* Rule (a): If both classes are equal, this is the resulting class. */
53e95fcf
JS		 249 if (class1 == class2)
250 return class1;
251
c4f35dd8 252 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
26abbdc4 253 is the other class. */
53e95fcf
JS		 254 if (class1 == X86_64_NO_CLASS)
255 return class2;
256 if (class2 == X86_64_NO_CLASS)
257 return class1;
258
c4f35dd8 259 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
53e95fcf
JS		 260 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
261 return X86_64_MEMORY_CLASS;
262
c4f35dd8 263 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
53e95fcf
JS		 264 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
265 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
266 return X86_64_INTEGERSI_CLASS;
267 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
268 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
269 return X86_64_INTEGER_CLASS;
270
c4f35dd8
MK		 271 /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is
272 used as class. */
53e95fcf
JS		 273 if (class1 == X86_64_X87_CLASS || class1 == X86_64_X87UP_CLASS
274 || class2 == X86_64_X87_CLASS || class2 == X86_64_X87UP_CLASS)
275 return X86_64_MEMORY_CLASS;
276
c4f35dd8 277 /* Rule (f): Otherwise class SSE is used. */
53e95fcf
JS		 278 return X86_64_SSE_CLASS;
279}
280
26abbdc4
MK		 281/* Classify the argument type. CLASSES will be filled by the register
282 class used to pass each word of the operand. The number of words
283 is returned. In case the parameter should be passed in memory, 0
284 is returned. As a special case for zero sized containers,
285 classes[0] will be NO_CLASS and 1 is returned.
53e95fcf 286
c4f35dd8 287 See the System V psABI for details. */
53e95fcf
JS		 288
289static int
290classify_argument (struct type *type,
291 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
292{
293 int bytes = TYPE_LENGTH (type);
294 int words = (bytes + 8 - 1) / 8;
295
296 switch (TYPE_CODE (type))
297 {
298 case TYPE_CODE_ARRAY:
299 case TYPE_CODE_STRUCT:
300 case TYPE_CODE_UNION:
301 {
302 int i;
303 enum x86_64_reg_class subclasses[MAX_CLASSES];
304
305 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
306 if (bytes > 16)
307 return 0;
308
309 for (i = 0; i < words; i++)
310 classes[i] = X86_64_NO_CLASS;
311
26abbdc4
MK		 312 /* Zero sized arrays or structures are NO_CLASS. We return 0
313 to signalize memory class, so handle it as special case. */
53e95fcf
JS		 314 if (!words)
315 {
316 classes[0] = X86_64_NO_CLASS;
317 return 1;
318 }
319 switch (TYPE_CODE (type))
320 {
321 case TYPE_CODE_STRUCT:
322 {
323 int j;
0004e5a2 324 for (j = 0; j < TYPE_NFIELDS (type); ++j)
53e95fcf 325 {
0004e5a2 326 int num = classify_argument (TYPE_FIELDS (type)[j].type,
53e95fcf 327 subclasses,
8dda9770
ML		 328 (TYPE_FIELDS (type)[j].loc.
329 bitpos + bit_offset) % 256);
53e95fcf
JS		 330 if (!num)
331 return 0;
332 for (i = 0; i < num; i++)
333 {
334 int pos =
8dda9770
ML		 335 (TYPE_FIELDS (type)[j].loc.bitpos +
336 bit_offset) / 8 / 8;
53e95fcf
JS		 337 classes[i + pos] =
338 merge_classes (subclasses[i], classes[i + pos]);
339 }
340 }
341 }
342 break;
343 case TYPE_CODE_ARRAY:
344 {
345 int num;
346
0004e5a2 347 num = classify_argument (TYPE_TARGET_TYPE (type),
53e95fcf
JS		 348 subclasses, bit_offset);
349 if (!num)
350 return 0;
351
352 /* The partial classes are now full classes. */
353 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
354 subclasses[0] = X86_64_SSE_CLASS;
355 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
356 subclasses[0] = X86_64_INTEGER_CLASS;
357
358 for (i = 0; i < words; i++)
359 classes[i] = subclasses[i % num];
360 }
361 break;
362 case TYPE_CODE_UNION:
363 {
364 int j;
365 {
0004e5a2 366 for (j = 0; j < TYPE_NFIELDS (type); ++j)
53e95fcf
JS		 367 {
368 int num;
0004e5a2 369 num = classify_argument (TYPE_FIELDS (type)[j].type,
53e95fcf
JS		 370 subclasses, bit_offset);
371 if (!num)
372 return 0;
373 for (i = 0; i < num; i++)
374 classes[i] = merge_classes (subclasses[i], classes[i]);
375 }
376 }
377 }
378 break;
4657573b
ML		 379 default:
380 break;
53e95fcf
JS		 381 }
382 /* Final merger cleanup. */
383 for (i = 0; i < words; i++)
384 {
385 /* If one class is MEMORY, everything should be passed in
386 memory. */
387 if (classes[i] == X86_64_MEMORY_CLASS)
388 return 0;
389
390 /* The X86_64_SSEUP_CLASS should be always preceeded by
391 X86_64_SSE_CLASS. */
392 if (classes[i] == X86_64_SSEUP_CLASS
393 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
394 classes[i] = X86_64_SSE_CLASS;
395
26abbdc4 396 /* X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS. */
53e95fcf
JS		 397 if (classes[i] == X86_64_X87UP_CLASS
398 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
399 classes[i] = X86_64_SSE_CLASS;
400 }
401 return words;
402 }
403 break;
404 case TYPE_CODE_FLT:
405 switch (bytes)
406 {
407 case 4:
408 if (!(bit_offset % 64))
409 classes[0] = X86_64_SSESF_CLASS;
410 else
411 classes[0] = X86_64_SSE_CLASS;
412 return 1;
413 case 8:
414 classes[0] = X86_64_SSEDF_CLASS;
415 return 1;
416 case 16:
417 classes[0] = X86_64_X87_CLASS;
418 classes[1] = X86_64_X87UP_CLASS;
419 return 2;
420 }
421 break;
50c46a0d
EZ		 422 case TYPE_CODE_ENUM:
423 case TYPE_CODE_REF:
53e95fcf
JS		 424 case TYPE_CODE_INT:
425 case TYPE_CODE_PTR:
426 switch (bytes)
427 {
428 case 1:
429 case 2:
430 case 4:
431 case 8:
432 if (bytes * 8 + bit_offset <= 32)
433 classes[0] = X86_64_INTEGERSI_CLASS;
434 else
435 classes[0] = X86_64_INTEGER_CLASS;
436 return 1;
437 case 16:
438 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
439 return 2;
440 default:
441 break;
442 }
443 case TYPE_CODE_VOID:
444 return 0;
8dda9770 445 default: /* Avoid warning. */
4657573b 446 break;
53e95fcf 447 }
ce0eebec
AC		 448 internal_error (__FILE__, __LINE__,
449 "classify_argument: unknown argument type");
53e95fcf
JS		 450}
451
26abbdc4
MK		 452/* Examine the argument and set *INT_NREGS and *SSE_NREGS to the
453 number of registers required based on the information passed in
454 CLASSES. Return 0 if parameter should be passed in memory. */
53e95fcf
JS		 455
456static int
457examine_argument (enum x86_64_reg_class classes[MAX_CLASSES],
458 int n, int *int_nregs, int *sse_nregs)
459{
460 *int_nregs = 0;
461 *sse_nregs = 0;
462 if (!n)
463 return 0;
464 for (n--; n >= 0; n--)
465 switch (classes[n])
466 {
467 case X86_64_INTEGER_CLASS:
468 case X86_64_INTEGERSI_CLASS:
469 (*int_nregs)++;
470 break;
471 case X86_64_SSE_CLASS:
472 case X86_64_SSESF_CLASS:
473 case X86_64_SSEDF_CLASS:
474 (*sse_nregs)++;
475 break;
476 case X86_64_NO_CLASS:
477 case X86_64_SSEUP_CLASS:
478 case X86_64_X87_CLASS:
479 case X86_64_X87UP_CLASS:
480 break;
481 case X86_64_MEMORY_CLASS:
ce0eebec
AC		 482 internal_error (__FILE__, __LINE__,
483 "examine_argument: unexpected memory class");
53e95fcf
JS		 484 }
485 return 1;
486}
487
488#define RET_INT_REGS 2
489#define RET_SSE_REGS 2
490
491/* Check if the structure in value_type is returned in registers or in
26abbdc4
MK		 492 memory. If this function returns 1, GDB will call
493 STORE_STRUCT_RETURN and EXTRACT_STRUCT_VALUE_ADDRESS else
494 STORE_RETURN_VALUE and EXTRACT_RETURN_VALUE will be used. */
c4f35dd8
MK		 495
496static int
53e95fcf
JS		 497x86_64_use_struct_convention (int gcc_p, struct type *value_type)
498{
499 enum x86_64_reg_class class[MAX_CLASSES];
500 int n = classify_argument (value_type, class, 0);
501 int needed_intregs;
502 int needed_sseregs;
503
504 return (!n ||
505 !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
506 needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS);
507}
508
53e95fcf
JS		 509/* Extract from an array REGBUF containing the (raw) register state, a
510 function return value of TYPE, and copy that, in virtual format,
511 into VALBUF. */
512
c4f35dd8 513static void
48037ead
ML		 514x86_64_extract_return_value (struct type *type, struct regcache *regcache,
515 void *valbuf)
53e95fcf
JS		 516{
517 enum x86_64_reg_class class[MAX_CLASSES];
518 int n = classify_argument (type, class, 0);
519 int needed_intregs;
520 int needed_sseregs;
521 int intreg = 0;
522 int ssereg = 0;
523 int offset = 0;
c4f35dd8
MK		 524 int ret_int_r[RET_INT_REGS] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM };
525 int ret_sse_r[RET_SSE_REGS] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM };
53e95fcf
JS		 526
527 if (!n ||
528 !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
529 needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS)
530 { /* memory class */
531 CORE_ADDR addr;
c4f35dd8 532 regcache_cooked_read (regcache, X86_64_RAX_REGNUM, &addr);
53e95fcf
JS		 533 read_memory (addr, valbuf, TYPE_LENGTH (type));
534 return;
535 }
536 else
537 {
538 int i;
539 for (i = 0; i < n; i++)
540 {
541 switch (class[i])
542 {
543 case X86_64_NO_CLASS:
544 break;
545 case X86_64_INTEGER_CLASS:
48037ead
ML		 546 regcache_cooked_read (regcache, ret_int_r[(intreg + 1) / 2],
547 (char *) valbuf + offset);
53e95fcf
JS		 548 offset += 8;
549 intreg += 2;
550 break;
551 case X86_64_INTEGERSI_CLASS:
48037ead
ML		 552 regcache_cooked_read_part (regcache, ret_int_r[intreg / 2],
553 0, 4, (char *) valbuf + offset);
53e95fcf
JS		 554 offset += 8;
555 intreg++;
556 break;
557 case X86_64_SSEDF_CLASS:
558 case X86_64_SSESF_CLASS:
559 case X86_64_SSE_CLASS:
48037ead
ML		 560 regcache_cooked_read_part (regcache,
561 ret_sse_r[(ssereg + 1) / 2], 0, 8,
562 (char *) valbuf + offset);
53e95fcf
JS		 563 offset += 8;
564 ssereg += 2;
565 break;
566 case X86_64_SSEUP_CLASS:
48037ead
ML		 567 regcache_cooked_read_part (regcache, ret_sse_r[ssereg / 2],
568 0, 8, (char *) valbuf + offset);
53e95fcf
JS		 569 offset += 8;
570 ssereg++;
571 break;
572 case X86_64_X87_CLASS:
c4f35dd8 573 regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM,
48037ead 574 0, 8, (char *) valbuf + offset);
53e95fcf
JS		 575 offset += 8;
576 break;
577 case X86_64_X87UP_CLASS:
c4f35dd8 578 regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM,
48037ead 579 8, 2, (char *) valbuf + offset);
53e95fcf
JS		 580 offset += 8;
581 break;
582 case X86_64_MEMORY_CLASS:
583 default:
584 internal_error (__FILE__, __LINE__,
585 "Unexpected argument class");
586 }
587 }
588 }
589}
590
53e95fcf 591#define INT_REGS 6
c4f35dd8 592#define SSE_REGS 8
53e95fcf 593
c4f35dd8
MK		 594static CORE_ADDR
595x86_64_push_arguments (struct regcache *regcache, int nargs,
596 struct value **args, CORE_ADDR sp)
53e95fcf
JS		 597{
598 int intreg = 0;
599 int ssereg = 0;
600 int i;
c4f35dd8
MK		 601 static int int_parameter_registers[INT_REGS] =
602 {
603 X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
604 X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
605 8, 9 /* %r8, %r9 */
ce0eebec 606 };
c4f35dd8
MK		 607 /* %xmm0 - %xmm7 */
608 static int sse_parameter_registers[SSE_REGS] =
609 {
610 X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
611 X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
612 X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
613 X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
ce0eebec
AC		 614 };
615 int stack_values_count = 0;
82dbc5f7 616 int *stack_values;
e9f30c21 617 stack_values = alloca (nargs * sizeof (int));
53e95fcf
JS		 618 for (i = 0; i < nargs; i++)
619 {
620 enum x86_64_reg_class class[MAX_CLASSES];
621 int n = classify_argument (args[i]->type, class, 0);
622 int needed_intregs;
623 int needed_sseregs;
624
625 if (!n ||
626 !examine_argument (class, n, &needed_intregs, &needed_sseregs)
82dbc5f7
AC		 627 || intreg / 2 + needed_intregs > INT_REGS
628 || ssereg / 2 + needed_sseregs > SSE_REGS)
ce0eebec
AC		 629 { /* memory class */
630 stack_values[stack_values_count++] = i;
53e95fcf
JS		 631 }
632 else
633 {
634 int j;
6b53acc6 635 int offset = 0;
53e95fcf
JS		 636 for (j = 0; j < n; j++)
637 {
53e95fcf
JS		 638 switch (class[j])
639 {
640 case X86_64_NO_CLASS:
641 break;
642 case X86_64_INTEGER_CLASS:
c4f35dd8
MK		 643 regcache_cooked_write
644 (regcache, int_parameter_registers[(intreg + 1) / 2],
645 VALUE_CONTENTS_ALL (args[i]) + offset);
53e95fcf
JS		 646 offset += 8;
647 intreg += 2;
648 break;
649 case X86_64_INTEGERSI_CLASS:
50c46a0d 650 {
c4f35dd8
MK		 651 LONGEST val = extract_signed_integer
652 (VALUE_CONTENTS_ALL (args[i]) + offset, 4);
653 regcache_cooked_write_signed
654 (regcache, int_parameter_registers[intreg / 2], val);
50c46a0d
EZ		 655
656 offset += 8;
657 intreg++;
658 break;
659 }
53e95fcf
JS		 660 case X86_64_SSEDF_CLASS:
661 case X86_64_SSESF_CLASS:
662 case X86_64_SSE_CLASS:
c4f35dd8
MK		 663 regcache_cooked_write
664 (regcache, sse_parameter_registers[(ssereg + 1) / 2],
665 VALUE_CONTENTS_ALL (args[i]) + offset);
53e95fcf
JS		 666 offset += 8;
667 ssereg += 2;
668 break;
669 case X86_64_SSEUP_CLASS:
c4f35dd8
MK		 670 regcache_cooked_write
671 (regcache, sse_parameter_registers[ssereg / 2],
672 VALUE_CONTENTS_ALL (args[i]) + offset);
53e95fcf
JS		 673 offset += 8;
674 ssereg++;
675 break;
676 case X86_64_X87_CLASS:
53e95fcf 677 case X86_64_MEMORY_CLASS:
ce0eebec 678 stack_values[stack_values_count++] = i;
82dbc5f7
AC		 679 break;
680 case X86_64_X87UP_CLASS:
53e95fcf
JS		 681 break;
682 default:
683 internal_error (__FILE__, __LINE__,
684 "Unexpected argument class");
685 }
686 intreg += intreg % 2;
687 ssereg += ssereg % 2;
688 }
689 }
690 }
c4f35dd8
MK		 691
692 /* Push any remaining arguments onto the stack. */
82dbc5f7
AC		 693 while (--stack_values_count >= 0)
694 {
e9f30c21 695 struct value *arg = args[stack_values[stack_values_count]];
82dbc5f7 696 int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
c4f35dd8
MK		 697
698 /* Make sure the stack stays eightbyte-aligned. */
699 sp -= (len + 7) & ~7;
82dbc5f7
AC		 700 write_memory (sp, VALUE_CONTENTS_ALL (arg), len);
701 }
c4f35dd8 702
53e95fcf
JS		 703 return sp;
704}
705
706/* Write into the appropriate registers a function return value stored
707 in VALBUF of type TYPE, given in virtual format. */
c4f35dd8
MK		 708
709static void
48037ead
ML		 710x86_64_store_return_value (struct type *type, struct regcache *regcache,
711 const void *valbuf)
53e95fcf
JS		 712{
713 int len = TYPE_LENGTH (type);
714
715 if (TYPE_CODE_FLT == TYPE_CODE (type))
716 {
c4f35dd8
MK		 717 ULONGEST fstat;
718 char buf[FPU_REG_RAW_SIZE];
719
720 /* Returning floating-point values is a bit tricky. Apart from
721 storing the return value in %st(0), we have to simulate the
722 state of the FPU at function return point. */
723
724 /* Convert the value found in VALBUF to the extended
725 floating-point format used by the FPU. This is probably
726 not exactly how it would happen on the target itself, but
727 it is the best we can do. */
728 convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext);
729 regcache_raw_write (regcache, X86_64_ST0_REGNUM, buf);
730
731 /* Set the top of the floating-point register stack to 7. The
732 actual value doesn't really matter, but 7 is what a normal
733 function return would end up with if the program started out
734 with a freshly initialized FPU. */
735 regcache_raw_read_unsigned (regcache, FSTAT_REGNUM, &fstat);
736 fstat |= (7 << 11);
737 regcache_raw_write_unsigned (regcache, FSTAT_REGNUM, fstat);
738
739 /* Mark %st(1) through %st(7) as empty. Since we set the top of
740 the floating-point register stack to 7, the appropriate value
741 for the tag word is 0x3fff. */
742 regcache_raw_write_unsigned (regcache, FTAG_REGNUM, 0x3fff);
53e95fcf
JS		 743 }
744 else
745 {
746 int low_size = REGISTER_RAW_SIZE (0);
747 int high_size = REGISTER_RAW_SIZE (1);
748
749 if (len <= low_size)
48037ead 750 regcache_cooked_write_part (regcache, 0, 0, len, valbuf);
53e95fcf
JS		 751 else if (len <= (low_size + high_size))
752 {
48037ead
ML		 753 regcache_cooked_write_part (regcache, 0, 0, low_size, valbuf);
754 regcache_cooked_write_part (regcache, 1, 0,
755 len - low_size,
756 (const char *) valbuf + low_size);
53e95fcf
JS		 757 }
758 else
759 internal_error (__FILE__, __LINE__,
760 "Cannot store return value of %d bytes long.", len);
761 }
762}
763\f
764
c4f35dd8 765static CORE_ADDR
10f93086
MK		 766x86_64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
767 struct regcache *regcache, CORE_ADDR bp_addr,
768 int nargs, struct value **args, CORE_ADDR sp,
769 int struct_return, CORE_ADDR struct_addr)
53e95fcf 770{
c4f35dd8
MK		 771 char buf[8];
772
773 /* Pass arguments. */
774 sp = x86_64_push_arguments (regcache, nargs, args, sp);
775
776 /* Pass "hidden" argument". */
777 if (struct_return)
778 {
779 store_unsigned_integer (buf, 8, struct_addr);
780 regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf);
781 }
782
783 /* Store return address. */
784 sp -= 8;
10f93086 785 store_unsigned_integer (buf, 8, bp_addr);
c4f35dd8
MK		 786 write_memory (sp, buf, 8);
787
788 /* Finally, update the stack pointer... */
789 store_unsigned_integer (buf, 8, sp);
790 regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf);
791
792 /* ...and fake a frame pointer. */
793 regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf);
794
3e210248 795 return sp + 16;
53e95fcf 796}
c4f35dd8
MK		 797\f
798
799/* The maximum number of saved registers. This should include %rip. */
2b5e0749 800#define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
c4f35dd8
MK		 801
802struct x86_64_frame_cache
803{
804 /* Base address. */
805 CORE_ADDR base;
806 CORE_ADDR sp_offset;
807 CORE_ADDR pc;
808
809 /* Saved registers. */
810 CORE_ADDR saved_regs[X86_64_NUM_SAVED_REGS];
811 CORE_ADDR saved_sp;
812
813 /* Do we have a frame? */
814 int frameless_p;
815};
8dda9770 816
c4f35dd8
MK		 817/* Allocate and initialize a frame cache. */
818
819static struct x86_64_frame_cache *
820x86_64_alloc_frame_cache (void)
8dda9770 821{
c4f35dd8
MK		 822 struct x86_64_frame_cache *cache;
823 int i;
824
825 cache = FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache);
8dda9770 826
c4f35dd8
MK		 827 /* Base address. */
828 cache->base = 0;
829 cache->sp_offset = -8;
830 cache->pc = 0;
831
832 /* Saved registers. We initialize these to -1 since zero is a valid
833 offset (that's where %rbp is supposed to be stored). */
834 for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
835 cache->saved_regs[i] = -1;
836 cache->saved_sp = 0;
837
838 /* Frameless until proven otherwise. */
839 cache->frameless_p = 1;
840
841 return cache;
8dda9770 842}
53e95fcf 843
c4f35dd8
MK		 844/* Do a limited analysis of the prologue at PC and update CACHE
845 accordingly. Bail out early if CURRENT_PC is reached. Return the
846 address where the analysis stopped.
847
848 We will handle only functions beginning with:
849
850 pushq %rbp 0x55
851 movq %rsp, %rbp 0x48 0x89 0xe5
852
853 Any function that doesn't start with this sequence will be assumed
854 to have no prologue and thus no valid frame pointer in %rbp. */
855
856static CORE_ADDR
857x86_64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
858 struct x86_64_frame_cache *cache)
53e95fcf 859{
c4f35dd8
MK		 860 static unsigned char proto[3] = { 0x48, 0x89, 0xe5 };
861 unsigned char buf[3];
862 unsigned char op;
863
864 if (current_pc <= pc)
865 return current_pc;
866
867 op = read_memory_unsigned_integer (pc, 1);
868
869 if (op == 0x55) /* pushq %rbp */
870 {
871 /* Take into account that we've executed the `pushq %rbp' that
872 starts this instruction sequence. */
873 cache->saved_regs[X86_64_RBP_REGNUM] = 0;
874 cache->sp_offset += 8;
875
876 /* If that's all, return now. */
877 if (current_pc <= pc + 1)
878 return current_pc;
879
880 /* Check for `movq %rsp, %rbp'. */
881 read_memory (pc + 1, buf, 3);
882 if (memcmp (buf, proto, 3) != 0)
883 return pc + 1;
884
885 /* OK, we actually have a frame. */
886 cache->frameless_p = 0;
887 return pc + 4;
888 }
889
890 return pc;
53e95fcf
JS		 891}
892
c4f35dd8
MK		 893/* Return PC of first real instruction. */
894
895static CORE_ADDR
896x86_64_skip_prologue (CORE_ADDR start_pc)
53e95fcf 897{
c4f35dd8
MK		 898 struct x86_64_frame_cache cache;
899 CORE_ADDR pc;
900
901 pc = x86_64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
902 if (cache.frameless_p)
903 return start_pc;
904
905 return pc;
53e95fcf 906}
c4f35dd8 907\f
53e95fcf 908
c4f35dd8
MK		 909/* Normal frames. */
910
911static struct x86_64_frame_cache *
912x86_64_frame_cache (struct frame_info *next_frame, void **this_cache)
6d686a84 913{
c4f35dd8
MK		 914 struct x86_64_frame_cache *cache;
915 char buf[8];
6d686a84 916 int i;
6d686a84 917
c4f35dd8
MK		 918 if (*this_cache)
919 return *this_cache;
6d686a84 920
c4f35dd8
MK		 921 cache = x86_64_alloc_frame_cache ();
922 *this_cache = cache;
923
924 frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
925 cache->base = extract_unsigned_integer (buf, 8);
926 if (cache->base == 0)
927 return cache;
928
929 /* For normal frames, %rip is stored at 8(%rbp). */
930 cache->saved_regs[X86_64_RIP_REGNUM] = 8;
931
932 cache->pc = frame_func_unwind (next_frame);
933 if (cache->pc != 0)
934 x86_64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
935
936 if (cache->frameless_p)
937 {
938 /* We didn't find a valid frame, which means that CACHE->base
939 currently holds the frame pointer for our calling frame. If
940 we're at the start of a function, or somewhere half-way its
941 prologue, the function's frame probably hasn't been fully
942 setup yet. Try to reconstruct the base address for the stack
943 frame by looking at the stack pointer. For truly "frameless"
944 functions this might work too. */
945
946 frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
947 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
948 }
949
950 /* Now that we have the base address for the stack frame we can
951 calculate the value of %rsp in the calling frame. */
952 cache->saved_sp = cache->base + 16;
953
954 /* Adjust all the saved registers such that they contain addresses
955 instead of offsets. */
956 for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
957 if (cache->saved_regs[i] != -1)
958 cache->saved_regs[i] += cache->base;
959
960 return cache;
6d686a84
ML		 961}
962
c4f35dd8
MK		 963static void
964x86_64_frame_this_id (struct frame_info *next_frame, void **this_cache,
965 struct frame_id *this_id)
966{
967 struct x86_64_frame_cache *cache =
968 x86_64_frame_cache (next_frame, this_cache);
969
970 /* This marks the outermost frame. */
971 if (cache->base == 0)
972 return;
973
974 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
975}
e76e1718 976
c4f35dd8
MK		 977static void
978x86_64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
979 int regnum, int *optimizedp,
980 enum lval_type *lvalp, CORE_ADDR *addrp,
981 int *realnump, void *valuep)
53e95fcf 982{
c4f35dd8
MK		 983 struct x86_64_frame_cache *cache =
984 x86_64_frame_cache (next_frame, this_cache);
e76e1718 985
c4f35dd8 986 gdb_assert (regnum >= 0);
b1ab997b 987
c4f35dd8
MK		 988 if (regnum == SP_REGNUM && cache->saved_sp)
989 {
990 *optimizedp = 0;
991 *lvalp = not_lval;
992 *addrp = 0;
993 *realnump = -1;
994 if (valuep)
995 {
996 /* Store the value. */
997 store_unsigned_integer (valuep, 8, cache->saved_sp);
998 }
999 return;
1000 }
e76e1718 1001
c4f35dd8
MK		 1002 if (regnum < X86_64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1003 {
1004 *optimizedp = 0;
1005 *lvalp = lval_memory;
1006 *addrp = cache->saved_regs[regnum];
1007 *realnump = -1;
1008 if (valuep)
1009 {
1010 /* Read the value in from memory. */
1011 read_memory (*addrp, valuep,
1012 register_size (current_gdbarch, regnum));
1013 }
1014 return;
1015 }
e76e1718 1016
c4f35dd8
MK		 1017 frame_register_unwind (next_frame, regnum,
1018 optimizedp, lvalp, addrp, realnump, valuep);
1019}
e76e1718 1020
c4f35dd8
MK		 1021static const struct frame_unwind x86_64_frame_unwind =
1022{
1023 NORMAL_FRAME,
1024 x86_64_frame_this_id,
1025 x86_64_frame_prev_register
1026};
e76e1718 1027
c4f35dd8
MK		 1028static const struct frame_unwind *
1029x86_64_frame_p (CORE_ADDR pc)
1030{
1031 return &x86_64_frame_unwind;
1032}
1033\f
e76e1718 1034
c4f35dd8
MK		 1035/* Signal trampolines. */
1036
1037/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
1038 64-bit variants. This would require using identical frame caches
1039 on both platforms. */
1040
1041static struct x86_64_frame_cache *
1042x86_64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1043{
1044 struct x86_64_frame_cache *cache;
1045 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1046 CORE_ADDR addr;
1047 char buf[8];
2b5e0749 1048 int i;
c4f35dd8
MK		 1049
1050 if (*this_cache)
1051 return *this_cache;
1052
1053 cache = x86_64_alloc_frame_cache ();
1054
1055 frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
1056 cache->base = extract_unsigned_integer (buf, 8) - 8;
1057
1058 addr = tdep->sigcontext_addr (next_frame);
2b5e0749
MK		 1059 gdb_assert (tdep->sc_reg_offset);
1060 gdb_assert (tdep->sc_num_regs <= X86_64_NUM_SAVED_REGS);
1061 for (i = 0; i < tdep->sc_num_regs; i++)
1062 if (tdep->sc_reg_offset[i] != -1)
1063 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8
MK		 1064
1065 *this_cache = cache;
1066 return cache;
53e95fcf
JS		 1067}
1068
c4f35dd8
MK		 1069static void
1070x86_64_sigtramp_frame_this_id (struct frame_info *next_frame,
1071 void **this_cache, struct frame_id *this_id)
1072{
1073 struct x86_64_frame_cache *cache =
1074 x86_64_sigtramp_frame_cache (next_frame, this_cache);
1075
1076 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
1077}
1078
1079static void
1080x86_64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1081 void **this_cache,
1082 int regnum, int *optimizedp,
1083 enum lval_type *lvalp, CORE_ADDR *addrp,
1084 int *realnump, void *valuep)
1085{
1086 /* Make sure we've initialized the cache. */
1087 x86_64_sigtramp_frame_cache (next_frame, this_cache);
1088
1089 x86_64_frame_prev_register (next_frame, this_cache, regnum,
1090 optimizedp, lvalp, addrp, realnump, valuep);
1091}
1092
1093static const struct frame_unwind x86_64_sigtramp_frame_unwind =
1094{
1095 SIGTRAMP_FRAME,
1096 x86_64_sigtramp_frame_this_id,
1097 x86_64_sigtramp_frame_prev_register
1098};
1099
1100static const struct frame_unwind *
1101x86_64_sigtramp_frame_p (CORE_ADDR pc)
1102{
1103 char *name;
1104
1105 find_pc_partial_function (pc, &name, NULL, NULL);
1106 if (PC_IN_SIGTRAMP (pc, name))
1c3545ae
MK		 1107 {
1108 gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr);
1109
1110 return &x86_64_sigtramp_frame_unwind;
1111 }
c4f35dd8
MK		 1112
1113 return NULL;
1114}
1115\f
1116
1117static CORE_ADDR
1118x86_64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1119{
1120 struct x86_64_frame_cache *cache =
1121 x86_64_frame_cache (next_frame, this_cache);
1122
1123 return cache->base;
1124}
1125
1126static const struct frame_base x86_64_frame_base =
1127{
1128 &x86_64_frame_unwind,
1129 x86_64_frame_base_address,
1130 x86_64_frame_base_address,
1131 x86_64_frame_base_address
1132};
1133
166f4c7b 1134static struct frame_id
c4f35dd8 1135x86_64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
166f4c7b 1136{
c4f35dd8
MK		 1137 char buf[8];
1138 CORE_ADDR fp;
1139
1140 frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
1141 fp = extract_unsigned_integer (buf, 8);
1142
1143 return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
166f4c7b
ML		 1144}
1145
2213a65d 1146void
0c1a73d6 1147x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
53e95fcf 1148{
0c1a73d6 1149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53e95fcf 1150
b83b026c 1151 /* The x86-64 has 16 SSE registers. */
0c1a73d6 1152 tdep->num_xmm_regs = 16;
53e95fcf 1153
0c1a73d6 1154 /* This is what all the fuss is about. */
53e95fcf
JS		 1155 set_gdbarch_long_bit (gdbarch, 64);
1156 set_gdbarch_long_long_bit (gdbarch, 64);
1157 set_gdbarch_ptr_bit (gdbarch, 64);
1158
b83b026c
MK		 1159 /* In contrast to the i386, on the x86-64 a `long double' actually
1160 takes up 128 bits, even though it's still based on the i387
1161 extended floating-point format which has only 80 significant bits. */
1162 set_gdbarch_long_double_bit (gdbarch, 128);
1163
53e95fcf 1164 set_gdbarch_num_regs (gdbarch, X86_64_NUM_REGS);
c4f35dd8
MK		 1165 set_gdbarch_register_name (gdbarch, x86_64_register_name);
1166 set_gdbarch_register_type (gdbarch, x86_64_register_type);
b83b026c
MK		 1167
1168 /* Register numbers of various important registers. */
c4f35dd8
MK		 1169 set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */
1170 set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */
1171 set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */
1172 set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */
b83b026c
MK		 1173
1174 /* The "default" register numbering scheme for the x86-64 is
c4f35dd8
MK		 1175 referred to as the "DWARF Register Number Mapping" in the System
1176 V psABI. The preferred debugging format for all known x86-64
1177 targets is actually DWARF2, and GCC doesn't seem to support DWARF
1178 (that is DWARF-1), but we provide the same mapping just in case.
1179 This mapping is also used for stabs, which GCC does support. */
1180 set_gdbarch_stab_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
1181 set_gdbarch_dwarf_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
1182 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
de220d0f 1183
c4f35dd8
MK		 1184 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1185 be in use on any of the supported x86-64 targets. */
53e95fcf 1186
c4f35dd8
MK		 1187 /* Call dummy code. */
1188 set_gdbarch_push_dummy_call (gdbarch, x86_64_push_dummy_call);
53e95fcf 1189
d532c08f
MK		 1190 set_gdbarch_convert_register_p (gdbarch, x86_64_convert_register_p);
1191 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1192 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1193
48037ead 1194 set_gdbarch_extract_return_value (gdbarch, x86_64_extract_return_value);
48037ead 1195 set_gdbarch_store_return_value (gdbarch, x86_64_store_return_value);
b83b026c
MK		 1196 /* Override, since this is handled by x86_64_extract_return_value. */
1197 set_gdbarch_extract_struct_value_address (gdbarch, NULL);
1198 set_gdbarch_use_struct_convention (gdbarch, x86_64_use_struct_convention);
53e95fcf 1199
b83b026c 1200 set_gdbarch_skip_prologue (gdbarch, x86_64_skip_prologue);
53e95fcf 1201
c4f35dd8 1202 /* Avoid wiring in the MMX registers for now. */
2213a65d
MK		 1203 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1204
c4f35dd8 1205 set_gdbarch_unwind_dummy_id (gdbarch, x86_64_unwind_dummy_id);
53e95fcf 1206
b83b026c
MK		 1207 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1208 since all supported x86-64 targets are ELF, but that might change
1209 in the future. */
8a8ab2b9 1210 set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section);
c4f35dd8
MK		 1211
1212 frame_unwind_append_predicate (gdbarch, x86_64_sigtramp_frame_p);
1213 frame_unwind_append_predicate (gdbarch, x86_64_frame_p);
1214 frame_base_set_default (gdbarch, &x86_64_frame_base);
1215}
1216\f
1217
1218#define I387_FISEG_REGNUM FISEG_REGNUM
1219#define I387_FOSEG_REGNUM FOSEG_REGNUM
1220
1221/* The 64-bit FXSAVE format differs from the 32-bit format in the
1222 sense that the instruction pointer and data pointer are simply
1223 64-bit offsets into the code segment and the data segment instead
1224 of a selector offset pair. The functions below store the upper 32
1225 bits of these pointers (instead of just the 16-bits of the segment
1226 selector). */
1227
1228/* Fill GDB's register array with the floating-point and SSE register
1229 values in *FXSAVE. This function masks off any of the reserved
1230 bits in *FXSAVE. */
1231
1232void
1233x86_64_supply_fxsave (char *fxsave)
1234{
1235 i387_supply_fxsave (fxsave);
1236
1237 if (fxsave)
1238 {
1239 supply_register (I387_FISEG_REGNUM, fxsave + 12);
1240 supply_register (I387_FOSEG_REGNUM, fxsave + 20);
1241 }
0c1a73d6
MK		 1242}
1243
c4f35dd8
MK		 1244/* Fill register REGNUM (if it is a floating-point or SSE register) in
1245 *FXSAVE with the value in GDB's register array. If REGNUM is -1, do
1246 this for all registers. This function doesn't touch any of the
1247 reserved bits in *FXSAVE. */
1248
53e95fcf 1249void
c4f35dd8 1250x86_64_fill_fxsave (char *fxsave, int regnum)
53e95fcf 1251{
c4f35dd8 1252 i387_fill_fxsave (fxsave, regnum);
53e95fcf 1253
c4f35dd8 1254 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
088ce440 1255 regcache_collect (I387_FISEG_REGNUM, fxsave + 12);
c4f35dd8 1256 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
088ce440 1257 regcache_collect (I387_FOSEG_REGNUM, fxsave + 20);
53e95fcf 1258}
GDB Binutils - Deliverables
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