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* elfxx-target.h: Remove PTR cast.
[deliverable/binutils-gdb.git] / gdb / x86-64-tdep.c
CommitLineData
53e95fcf 1/* Target-dependent code for the x86-64 for GDB, the GNU debugger.
ce0eebec 2
51603483 3 Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
53e95fcf
JS		 4 Contributed by Jiri Smid, SuSE Labs.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23#include "defs.h"
c4f35dd8
MK		 24#include "arch-utils.h"
25#include "block.h"
26#include "dummy-frame.h"
27#include "frame.h"
28#include "frame-base.h"
29#include "frame-unwind.h"
53e95fcf 30#include "inferior.h"
53e95fcf 31#include "gdbcmd.h"
c4f35dd8
MK		 32#include "gdbcore.h"
33#include "objfiles.h"
53e95fcf
JS		 34#include "regcache.h"
35#include "symfile.h"
c4f35dd8 36
82dbc5f7 37#include "gdb_assert.h"
c4f35dd8
MK		 38
39#include "x86-64-tdep.h"
40#include "i387-tdep.h"
53e95fcf 41
402ecd56 42/* Register information. */
c4f35dd8
MK		 43
44struct x86_64_register_info
de220d0f 45{
de220d0f
ML		 46 char *name;
47 struct type **type;
48};
53e95fcf 49
c4f35dd8
MK		 50static struct x86_64_register_info x86_64_register_info[] =
51{
52 { "rax", &builtin_type_int64 },
53 { "rbx", &builtin_type_int64 },
54 { "rcx", &builtin_type_int64 },
55 { "rdx", &builtin_type_int64 },
56 { "rsi", &builtin_type_int64 },
57 { "rdi", &builtin_type_int64 },
58 { "rbp", &builtin_type_void_data_ptr },
59 { "rsp", &builtin_type_void_data_ptr },
60
61 /* %r8 is indeed register number 8. */
62 { "r8", &builtin_type_int64 },
63 { "r9", &builtin_type_int64 },
64 { "r10", &builtin_type_int64 },
65 { "r11", &builtin_type_int64 },
66 { "r12", &builtin_type_int64 },
67 { "r13", &builtin_type_int64 },
68 { "r14", &builtin_type_int64 },
69 { "r15", &builtin_type_int64 },
70 { "rip", &builtin_type_void_func_ptr },
71 { "eflags", &builtin_type_int32 },
72 { "ds", &builtin_type_int32 },
73 { "es", &builtin_type_int32 },
74 { "fs", &builtin_type_int32 },
75 { "gs", &builtin_type_int32 },
76
77 /* %st0 is register number 22. */
78 { "st0", &builtin_type_i387_ext },
79 { "st1", &builtin_type_i387_ext },
80 { "st2", &builtin_type_i387_ext },
81 { "st3", &builtin_type_i387_ext },
82 { "st4", &builtin_type_i387_ext },
83 { "st5", &builtin_type_i387_ext },
84 { "st6", &builtin_type_i387_ext },
85 { "st7", &builtin_type_i387_ext },
86 { "fctrl", &builtin_type_int32 },
87 { "fstat", &builtin_type_int32 },
88 { "ftag", &builtin_type_int32 },
89 { "fiseg", &builtin_type_int32 },
90 { "fioff", &builtin_type_int32 },
91 { "foseg", &builtin_type_int32 },
92 { "fooff", &builtin_type_int32 },
93 { "fop", &builtin_type_int32 },
94
95 /* %xmm0 is register number 38. */
96 { "xmm0", &builtin_type_v4sf },
97 { "xmm1", &builtin_type_v4sf },
98 { "xmm2", &builtin_type_v4sf },
99 { "xmm3", &builtin_type_v4sf },
100 { "xmm4", &builtin_type_v4sf },
101 { "xmm5", &builtin_type_v4sf },
102 { "xmm6", &builtin_type_v4sf },
103 { "xmm7", &builtin_type_v4sf },
104 { "xmm8", &builtin_type_v4sf },
105 { "xmm9", &builtin_type_v4sf },
106 { "xmm10", &builtin_type_v4sf },
107 { "xmm11", &builtin_type_v4sf },
108 { "xmm12", &builtin_type_v4sf },
109 { "xmm13", &builtin_type_v4sf },
110 { "xmm14", &builtin_type_v4sf },
111 { "xmm15", &builtin_type_v4sf },
112 { "mxcsr", &builtin_type_int32 }
0e04a514
ML		 113};
114
c4f35dd8
MK		 115/* Total number of registers. */
116#define X86_64_NUM_REGS \
117 (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
de220d0f 118
c4f35dd8 119/* Return the name of register REGNUM. */
b6779aa2 120
c4f35dd8
MK		 121static const char *
122x86_64_register_name (int regnum)
53e95fcf 123{
c4f35dd8
MK		 124 if (regnum >= 0 && regnum < X86_64_NUM_REGS)
125 return x86_64_register_info[regnum].name;
53e95fcf 126
c4f35dd8 127 return NULL;
53e95fcf
JS		 128}
129
130/* Return the GDB type object for the "standard" data type of data in
c4f35dd8 131 register REGNUM. */
53e95fcf 132
c4f35dd8
MK		 133static struct type *
134x86_64_register_type (struct gdbarch *gdbarch, int regnum)
53e95fcf 135{
c4f35dd8 136 gdb_assert (regnum >= 0 && regnum < X86_64_NUM_REGS);
4657573b 137
c4f35dd8 138 return *x86_64_register_info[regnum].type;
53e95fcf
JS		 139}
140
c4f35dd8
MK		 141/* DWARF Register Number Mapping as defined in the System V psABI,
142 section 3.6. */
53e95fcf 143
c4f35dd8 144static int x86_64_dwarf_regmap[] =
0e04a514 145{
c4f35dd8 146 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
abd4220e 147 X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 2, 1,
c4f35dd8
MK		 148 4, X86_64_RDI_REGNUM,
149
150 /* Frame Pointer Register RBP. */
151 X86_64_RBP_REGNUM,
152
153 /* Stack Pointer Register RSP. */
154 X86_64_RSP_REGNUM,
155
156 /* Extended Integer Registers 8 - 15. */
157 8, 9, 10, 11, 12, 13, 14, 15,
158
159 /* Return Address RA. Not mapped. */
160 -1,
161
162 /* SSE Registers 0 - 7. */
163 X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
164 X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
165 X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
166 X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
167
168 /* Extended SSE Registers 8 - 15. */
169 X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9,
170 X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11,
171 X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13,
172 X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15,
173
174 /* Floating Point Registers 0-7. */
175 X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1,
176 X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3,
177 X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5,
178 X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7
179};
0e04a514 180
c4f35dd8
MK		 181static const int x86_64_dwarf_regmap_len =
182 (sizeof (x86_64_dwarf_regmap) / sizeof (x86_64_dwarf_regmap[0]));
0e04a514 183
c4f35dd8
MK		 184/* Convert DWARF register number REG to the appropriate register
185 number used by GDB. */
26abbdc4 186
c4f35dd8
MK		 187static int
188x86_64_dwarf_reg_to_regnum (int reg)
53e95fcf 189{
c4f35dd8 190 int regnum = -1;
53e95fcf 191
c4f35dd8
MK		 192 if (reg >= 0 || reg < x86_64_dwarf_regmap_len)
193 regnum = x86_64_dwarf_regmap[reg];
53e95fcf 194
c4f35dd8
MK		 195 if (regnum == -1)
196 warning ("Unmapped DWARF Register #%d encountered\n", reg);
197
198 return regnum;
53e95fcf 199}
d532c08f
MK		 200
201/* Return nonzero if a value of type TYPE stored in register REGNUM
202 needs any special handling. */
203
204static int
205x86_64_convert_register_p (int regnum, struct type *type)
206{
207 return i386_fp_regnum_p (regnum);
208}
53e95fcf
JS		 209\f
210
211/* The returning of values is done according to the special algorithm.
c4f35dd8
MK		 212 Some types are returned in registers an some (big structures) in
213 memory. See the System V psABI for details. */
53e95fcf
JS		 214
215#define MAX_CLASSES 4
216
217enum x86_64_reg_class
218{
219 X86_64_NO_CLASS,
220 X86_64_INTEGER_CLASS,
221 X86_64_INTEGERSI_CLASS,
222 X86_64_SSE_CLASS,
223 X86_64_SSESF_CLASS,
224 X86_64_SSEDF_CLASS,
225 X86_64_SSEUP_CLASS,
226 X86_64_X87_CLASS,
227 X86_64_X87UP_CLASS,
228 X86_64_MEMORY_CLASS
229};
230
231/* Return the union class of CLASS1 and CLASS2.
c4f35dd8 232 See the System V psABI for details. */
53e95fcf
JS		 233
234static enum x86_64_reg_class
235merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
236{
c4f35dd8 237 /* Rule (a): If both classes are equal, this is the resulting class. */
53e95fcf
JS		 238 if (class1 == class2)
239 return class1;
240
c4f35dd8 241 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
26abbdc4 242 is the other class. */
53e95fcf
JS		 243 if (class1 == X86_64_NO_CLASS)
244 return class2;
245 if (class2 == X86_64_NO_CLASS)
246 return class1;
247
c4f35dd8 248 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
53e95fcf
JS		 249 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
250 return X86_64_MEMORY_CLASS;
251
c4f35dd8 252 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
53e95fcf
JS		 253 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
254 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
255 return X86_64_INTEGERSI_CLASS;
256 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
257 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
258 return X86_64_INTEGER_CLASS;
259
c4f35dd8
MK		 260 /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is
261 used as class. */
53e95fcf
JS		 262 if (class1 == X86_64_X87_CLASS || class1 == X86_64_X87UP_CLASS
263 || class2 == X86_64_X87_CLASS || class2 == X86_64_X87UP_CLASS)
264 return X86_64_MEMORY_CLASS;
265
c4f35dd8 266 /* Rule (f): Otherwise class SSE is used. */
53e95fcf
JS		 267 return X86_64_SSE_CLASS;
268}
269
26abbdc4
MK		 270/* Classify the argument type. CLASSES will be filled by the register
271 class used to pass each word of the operand. The number of words
272 is returned. In case the parameter should be passed in memory, 0
273 is returned. As a special case for zero sized containers,
274 classes[0] will be NO_CLASS and 1 is returned.
53e95fcf 275
c4f35dd8 276 See the System V psABI for details. */
53e95fcf
JS		 277
278static int
279classify_argument (struct type *type,
280 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
281{
282 int bytes = TYPE_LENGTH (type);
283 int words = (bytes + 8 - 1) / 8;
284
285 switch (TYPE_CODE (type))
286 {
287 case TYPE_CODE_ARRAY:
288 case TYPE_CODE_STRUCT:
289 case TYPE_CODE_UNION:
290 {
291 int i;
292 enum x86_64_reg_class subclasses[MAX_CLASSES];
293
294 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
295 if (bytes > 16)
296 return 0;
297
298 for (i = 0; i < words; i++)
299 classes[i] = X86_64_NO_CLASS;
300
26abbdc4
MK		 301 /* Zero sized arrays or structures are NO_CLASS. We return 0
302 to signalize memory class, so handle it as special case. */
53e95fcf
JS		 303 if (!words)
304 {
305 classes[0] = X86_64_NO_CLASS;
306 return 1;
307 }
308 switch (TYPE_CODE (type))
309 {
310 case TYPE_CODE_STRUCT:
311 {
312 int j;
0004e5a2 313 for (j = 0; j < TYPE_NFIELDS (type); ++j)
53e95fcf 314 {
0004e5a2 315 int num = classify_argument (TYPE_FIELDS (type)[j].type,
53e95fcf 316 subclasses,
8dda9770
ML		 317 (TYPE_FIELDS (type)[j].loc.
318 bitpos + bit_offset) % 256);
53e95fcf
JS		 319 if (!num)
320 return 0;
321 for (i = 0; i < num; i++)
322 {
323 int pos =
8dda9770
ML		 324 (TYPE_FIELDS (type)[j].loc.bitpos +
325 bit_offset) / 8 / 8;
53e95fcf
JS		 326 classes[i + pos] =
327 merge_classes (subclasses[i], classes[i + pos]);
328 }
329 }
330 }
331 break;
332 case TYPE_CODE_ARRAY:
333 {
334 int num;
335
0004e5a2 336 num = classify_argument (TYPE_TARGET_TYPE (type),
53e95fcf
JS		 337 subclasses, bit_offset);
338 if (!num)
339 return 0;
340
341 /* The partial classes are now full classes. */
342 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
343 subclasses[0] = X86_64_SSE_CLASS;
344 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
345 subclasses[0] = X86_64_INTEGER_CLASS;
346
347 for (i = 0; i < words; i++)
348 classes[i] = subclasses[i % num];
349 }
350 break;
351 case TYPE_CODE_UNION:
352 {
353 int j;
354 {
0004e5a2 355 for (j = 0; j < TYPE_NFIELDS (type); ++j)
53e95fcf
JS		 356 {
357 int num;
0004e5a2 358 num = classify_argument (TYPE_FIELDS (type)[j].type,
53e95fcf
JS		 359 subclasses, bit_offset);
360 if (!num)
361 return 0;
362 for (i = 0; i < num; i++)
363 classes[i] = merge_classes (subclasses[i], classes[i]);
364 }
365 }
366 }
367 break;
4657573b
ML		 368 default:
369 break;
53e95fcf
JS		 370 }
371 /* Final merger cleanup. */
372 for (i = 0; i < words; i++)
373 {
374 /* If one class is MEMORY, everything should be passed in
375 memory. */
376 if (classes[i] == X86_64_MEMORY_CLASS)
377 return 0;
378
379 /* The X86_64_SSEUP_CLASS should be always preceeded by
380 X86_64_SSE_CLASS. */
381 if (classes[i] == X86_64_SSEUP_CLASS
382 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
383 classes[i] = X86_64_SSE_CLASS;
384
26abbdc4 385 /* X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS. */
53e95fcf
JS		 386 if (classes[i] == X86_64_X87UP_CLASS
387 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
388 classes[i] = X86_64_SSE_CLASS;
389 }
390 return words;
391 }
392 break;
393 case TYPE_CODE_FLT:
394 switch (bytes)
395 {
396 case 4:
397 if (!(bit_offset % 64))
398 classes[0] = X86_64_SSESF_CLASS;
399 else
400 classes[0] = X86_64_SSE_CLASS;
401 return 1;
402 case 8:
403 classes[0] = X86_64_SSEDF_CLASS;
404 return 1;
405 case 16:
406 classes[0] = X86_64_X87_CLASS;
407 classes[1] = X86_64_X87UP_CLASS;
408 return 2;
409 }
410 break;
50c46a0d
EZ		 411 case TYPE_CODE_ENUM:
412 case TYPE_CODE_REF:
53e95fcf
JS		 413 case TYPE_CODE_INT:
414 case TYPE_CODE_PTR:
415 switch (bytes)
416 {
417 case 1:
418 case 2:
419 case 4:
420 case 8:
421 if (bytes * 8 + bit_offset <= 32)
422 classes[0] = X86_64_INTEGERSI_CLASS;
423 else
424 classes[0] = X86_64_INTEGER_CLASS;
425 return 1;
426 case 16:
427 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
428 return 2;
429 default:
430 break;
431 }
432 case TYPE_CODE_VOID:
433 return 0;
8dda9770 434 default: /* Avoid warning. */
4657573b 435 break;
53e95fcf 436 }
ce0eebec
AC		 437 internal_error (__FILE__, __LINE__,
438 "classify_argument: unknown argument type");
53e95fcf
JS		 439}
440
26abbdc4
MK		 441/* Examine the argument and set *INT_NREGS and *SSE_NREGS to the
442 number of registers required based on the information passed in
443 CLASSES. Return 0 if parameter should be passed in memory. */
53e95fcf
JS		 444
445static int
446examine_argument (enum x86_64_reg_class classes[MAX_CLASSES],
447 int n, int *int_nregs, int *sse_nregs)
448{
449 *int_nregs = 0;
450 *sse_nregs = 0;
451 if (!n)
452 return 0;
453 for (n--; n >= 0; n--)
454 switch (classes[n])
455 {
456 case X86_64_INTEGER_CLASS:
457 case X86_64_INTEGERSI_CLASS:
458 (*int_nregs)++;
459 break;
460 case X86_64_SSE_CLASS:
461 case X86_64_SSESF_CLASS:
462 case X86_64_SSEDF_CLASS:
463 (*sse_nregs)++;
464 break;
465 case X86_64_NO_CLASS:
466 case X86_64_SSEUP_CLASS:
467 case X86_64_X87_CLASS:
468 case X86_64_X87UP_CLASS:
469 break;
470 case X86_64_MEMORY_CLASS:
ce0eebec
AC		 471 internal_error (__FILE__, __LINE__,
472 "examine_argument: unexpected memory class");
53e95fcf
JS		 473 }
474 return 1;
475}
476
477#define RET_INT_REGS 2
478#define RET_SSE_REGS 2
479
480/* Check if the structure in value_type is returned in registers or in
26abbdc4
MK		 481 memory. If this function returns 1, GDB will call
482 STORE_STRUCT_RETURN and EXTRACT_STRUCT_VALUE_ADDRESS else
483 STORE_RETURN_VALUE and EXTRACT_RETURN_VALUE will be used. */
c4f35dd8
MK		 484
485static int
53e95fcf
JS		 486x86_64_use_struct_convention (int gcc_p, struct type *value_type)
487{
488 enum x86_64_reg_class class[MAX_CLASSES];
489 int n = classify_argument (value_type, class, 0);
490 int needed_intregs;
491 int needed_sseregs;
492
493 return (!n ||
494 !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
495 needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS);
496}
497
53e95fcf
JS		 498/* Extract from an array REGBUF containing the (raw) register state, a
499 function return value of TYPE, and copy that, in virtual format,
500 into VALBUF. */
501
c4f35dd8 502static void
48037ead
ML		 503x86_64_extract_return_value (struct type *type, struct regcache *regcache,
504 void *valbuf)
53e95fcf
JS		 505{
506 enum x86_64_reg_class class[MAX_CLASSES];
507 int n = classify_argument (type, class, 0);
508 int needed_intregs;
509 int needed_sseregs;
510 int intreg = 0;
511 int ssereg = 0;
512 int offset = 0;
c4f35dd8
MK		 513 int ret_int_r[RET_INT_REGS] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM };
514 int ret_sse_r[RET_SSE_REGS] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM };
53e95fcf
JS		 515
516 if (!n ||
517 !examine_argument (class, n, &needed_intregs, &needed_sseregs) ||
518 needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS)
519 { /* memory class */
520 CORE_ADDR addr;
c4f35dd8 521 regcache_cooked_read (regcache, X86_64_RAX_REGNUM, &addr);
53e95fcf
JS		 522 read_memory (addr, valbuf, TYPE_LENGTH (type));
523 return;
524 }
525 else
526 {
527 int i;
528 for (i = 0; i < n; i++)
529 {
530 switch (class[i])
531 {
532 case X86_64_NO_CLASS:
533 break;
534 case X86_64_INTEGER_CLASS:
48037ead
ML		 535 regcache_cooked_read (regcache, ret_int_r[(intreg + 1) / 2],
536 (char *) valbuf + offset);
53e95fcf
JS		 537 offset += 8;
538 intreg += 2;
539 break;
540 case X86_64_INTEGERSI_CLASS:
48037ead
ML		 541 regcache_cooked_read_part (regcache, ret_int_r[intreg / 2],
542 0, 4, (char *) valbuf + offset);
53e95fcf
JS		 543 offset += 8;
544 intreg++;
545 break;
546 case X86_64_SSEDF_CLASS:
547 case X86_64_SSESF_CLASS:
548 case X86_64_SSE_CLASS:
48037ead
ML		 549 regcache_cooked_read_part (regcache,
550 ret_sse_r[(ssereg + 1) / 2], 0, 8,
551 (char *) valbuf + offset);
53e95fcf
JS		 552 offset += 8;
553 ssereg += 2;
554 break;
555 case X86_64_SSEUP_CLASS:
48037ead
ML		 556 regcache_cooked_read_part (regcache, ret_sse_r[ssereg / 2],
557 0, 8, (char *) valbuf + offset);
53e95fcf
JS		 558 offset += 8;
559 ssereg++;
560 break;
561 case X86_64_X87_CLASS:
c4f35dd8 562 regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM,
48037ead 563 0, 8, (char *) valbuf + offset);
53e95fcf
JS		 564 offset += 8;
565 break;
566 case X86_64_X87UP_CLASS:
c4f35dd8 567 regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM,
48037ead 568 8, 2, (char *) valbuf + offset);
53e95fcf
JS		 569 offset += 8;
570 break;
571 case X86_64_MEMORY_CLASS:
572 default:
573 internal_error (__FILE__, __LINE__,
574 "Unexpected argument class");
575 }
576 }
577 }
578}
579
53e95fcf 580#define INT_REGS 6
c4f35dd8 581#define SSE_REGS 8
53e95fcf 582
c4f35dd8
MK		 583static CORE_ADDR
584x86_64_push_arguments (struct regcache *regcache, int nargs,
585 struct value **args, CORE_ADDR sp)
53e95fcf
JS		 586{
587 int intreg = 0;
588 int ssereg = 0;
c1da67ba
AJ		 589 /* For varargs functions we have to pass the total number of SSE
590 registers used in %rax. So, let's count this number. */
8ffd9b1b
AJ		 591 int total_sse_args = 0;
592 /* Once an SSE/int argument is passed on the stack, all subsequent
593 arguments are passed there. */
594 int sse_stack = 0;
595 int int_stack = 0;
c1da67ba 596 unsigned total_sp;
53e95fcf 597 int i;
8ffd9b1b 598 char buf[8];
c4f35dd8
MK		 599 static int int_parameter_registers[INT_REGS] =
600 {
601 X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
602 X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
603 8, 9 /* %r8, %r9 */
ce0eebec 604 };
c4f35dd8
MK		 605 /* %xmm0 - %xmm7 */
606 static int sse_parameter_registers[SSE_REGS] =
607 {
608 X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
609 X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
610 X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
611 X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
ce0eebec
AC		 612 };
613 int stack_values_count = 0;
82dbc5f7 614 int *stack_values;
e9f30c21 615 stack_values = alloca (nargs * sizeof (int));
53e95fcf
JS		 616 for (i = 0; i < nargs; i++)
617 {
618 enum x86_64_reg_class class[MAX_CLASSES];
619 int n = classify_argument (args[i]->type, class, 0);
620 int needed_intregs;
621 int needed_sseregs;
622
623 if (!n ||
8ffd9b1b 624 !examine_argument (class, n, &needed_intregs, &needed_sseregs))
ce0eebec
AC		 625 { /* memory class */
626 stack_values[stack_values_count++] = i;
53e95fcf
JS		 627 }
628 else
629 {
630 int j;
6b53acc6 631 int offset = 0;
8ffd9b1b
AJ		 632
633 if (intreg / 2 + needed_intregs > INT_REGS)
634 int_stack = 1;
635 if (ssereg / 2 + needed_sseregs > SSE_REGS)
636 sse_stack = 1;
c1da67ba
AJ		 637 if (!sse_stack)
638 total_sse_args += needed_sseregs;
8ffd9b1b 639
53e95fcf
JS		 640 for (j = 0; j < n; j++)
641 {
53e95fcf
JS		 642 switch (class[j])
643 {
644 case X86_64_NO_CLASS:
645 break;
646 case X86_64_INTEGER_CLASS:
8ffd9b1b
AJ		 647 if (int_stack)
648 stack_values[stack_values_count++] = i;
649 else
650 {
651 regcache_cooked_write
652 (regcache, int_parameter_registers[(intreg + 1) / 2],
653 VALUE_CONTENTS_ALL (args[i]) + offset);
654 offset += 8;
655 intreg += 2;
656 }
53e95fcf
JS		 657 break;
658 case X86_64_INTEGERSI_CLASS:
8ffd9b1b
AJ		 659 if (int_stack)
660 stack_values[stack_values_count++] = i;
661 else
662 {
663 LONGEST val = extract_signed_integer
664 (VALUE_CONTENTS_ALL (args[i]) + offset, 4);
665 regcache_cooked_write_signed
666 (regcache, int_parameter_registers[intreg / 2], val);
667
668 offset += 8;
669 intreg++;
670 }
671 break;
53e95fcf
JS		 672 case X86_64_SSEDF_CLASS:
673 case X86_64_SSESF_CLASS:
674 case X86_64_SSE_CLASS:
8ffd9b1b
AJ		 675 if (sse_stack)
676 stack_values[stack_values_count++] = i;
677 else
678 {
679 regcache_cooked_write
680 (regcache, sse_parameter_registers[(ssereg + 1) / 2],
681 VALUE_CONTENTS_ALL (args[i]) + offset);
682 offset += 8;
683 ssereg += 2;
684 }
53e95fcf
JS		 685 break;
686 case X86_64_SSEUP_CLASS:
8ffd9b1b
AJ		 687 if (sse_stack)
688 stack_values[stack_values_count++] = i;
689 else
690 {
691 regcache_cooked_write
692 (regcache, sse_parameter_registers[ssereg / 2],
693 VALUE_CONTENTS_ALL (args[i]) + offset);
694 offset += 8;
695 ssereg++;
696 }
53e95fcf
JS		 697 break;
698 case X86_64_X87_CLASS:
53e95fcf 699 case X86_64_MEMORY_CLASS:
ce0eebec 700 stack_values[stack_values_count++] = i;
82dbc5f7
AC		 701 break;
702 case X86_64_X87UP_CLASS:
53e95fcf
JS		 703 break;
704 default:
705 internal_error (__FILE__, __LINE__,
706 "Unexpected argument class");
707 }
708 intreg += intreg % 2;
709 ssereg += ssereg % 2;
710 }
711 }
712 }
c4f35dd8 713
c1da67ba
AJ		 714 /* We have to make sure that the stack is 16-byte aligned after the
715 setup. Let's calculate size of arguments first, align stack and
716 then fill in the arguments. */
717 total_sp = 0;
718 for (i = 0; i < stack_values_count; i++)
719 {
720 struct value *arg = args[stack_values[i]];
721 int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
722 total_sp += (len + 7) & ~7;
723 }
724 /* total_sp is now a multiple of 8, if it is not a multiple of 16,
725 change the stack pointer so that it will be afterwards correctly
726 aligned. */
727 if (total_sp & 15)
728 sp -= 8;
729
c4f35dd8 730 /* Push any remaining arguments onto the stack. */
82dbc5f7
AC		 731 while (--stack_values_count >= 0)
732 {
e9f30c21 733 struct value *arg = args[stack_values[stack_values_count]];
82dbc5f7 734 int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
c4f35dd8 735
c1da67ba 736 /* Make sure the stack is 8-byte-aligned. */
c4f35dd8 737 sp -= (len + 7) & ~7;
82dbc5f7
AC		 738 write_memory (sp, VALUE_CONTENTS_ALL (arg), len);
739 }
c4f35dd8 740
8ffd9b1b
AJ		 741 /* Write number of SSE type arguments to RAX to take care of varargs
742 functions. */
743 store_unsigned_integer (buf, 8, total_sse_args);
744 regcache_cooked_write (regcache, X86_64_RAX_REGNUM, buf);
745
53e95fcf
JS		 746 return sp;
747}
748
749/* Write into the appropriate registers a function return value stored
750 in VALBUF of type TYPE, given in virtual format. */
c4f35dd8
MK		 751
752static void
48037ead
ML		 753x86_64_store_return_value (struct type *type, struct regcache *regcache,
754 const void *valbuf)
53e95fcf
JS		 755{
756 int len = TYPE_LENGTH (type);
757
8ffd9b1b
AJ		 758 /* First handle long doubles. */
759 if (TYPE_CODE_FLT == TYPE_CODE (type) && len == 16)
53e95fcf 760 {
c4f35dd8
MK		 761 ULONGEST fstat;
762 char buf[FPU_REG_RAW_SIZE];
763
764 /* Returning floating-point values is a bit tricky. Apart from
765 storing the return value in %st(0), we have to simulate the
766 state of the FPU at function return point. */
767
768 /* Convert the value found in VALBUF to the extended
769 floating-point format used by the FPU. This is probably
770 not exactly how it would happen on the target itself, but
771 it is the best we can do. */
772 convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext);
773 regcache_raw_write (regcache, X86_64_ST0_REGNUM, buf);
774
775 /* Set the top of the floating-point register stack to 7. The
776 actual value doesn't really matter, but 7 is what a normal
777 function return would end up with if the program started out
778 with a freshly initialized FPU. */
779 regcache_raw_read_unsigned (regcache, FSTAT_REGNUM, &fstat);
780 fstat |= (7 << 11);
781 regcache_raw_write_unsigned (regcache, FSTAT_REGNUM, fstat);
782
783 /* Mark %st(1) through %st(7) as empty. Since we set the top of
784 the floating-point register stack to 7, the appropriate value
785 for the tag word is 0x3fff. */
786 regcache_raw_write_unsigned (regcache, FTAG_REGNUM, 0x3fff);
53e95fcf 787 }
8ffd9b1b
AJ		 788 else if (TYPE_CODE_FLT == TYPE_CODE (type))
789 {
790 /* Handle double and float variables. */
249de4f6
MK		 791 regcache_cooked_write_part (regcache, X86_64_XMM0_REGNUM,
792 0, len, valbuf);
8ffd9b1b
AJ		 793 }
794 /* XXX: What about complex floating point types? */
53e95fcf
JS		 795 else
796 {
797 int low_size = REGISTER_RAW_SIZE (0);
798 int high_size = REGISTER_RAW_SIZE (1);
799
800 if (len <= low_size)
48037ead 801 regcache_cooked_write_part (regcache, 0, 0, len, valbuf);
53e95fcf
JS		 802 else if (len <= (low_size + high_size))
803 {
48037ead
ML		 804 regcache_cooked_write_part (regcache, 0, 0, low_size, valbuf);
805 regcache_cooked_write_part (regcache, 1, 0,
806 len - low_size,
807 (const char *) valbuf + low_size);
53e95fcf
JS		 808 }
809 else
810 internal_error (__FILE__, __LINE__,
811 "Cannot store return value of %d bytes long.", len);
812 }
813}
814\f
815
c4f35dd8 816static CORE_ADDR
10f93086
MK		 817x86_64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
818 struct regcache *regcache, CORE_ADDR bp_addr,
819 int nargs, struct value **args, CORE_ADDR sp,
820 int struct_return, CORE_ADDR struct_addr)
53e95fcf 821{
c4f35dd8
MK		 822 char buf[8];
823
824 /* Pass arguments. */
825 sp = x86_64_push_arguments (regcache, nargs, args, sp);
826
827 /* Pass "hidden" argument". */
828 if (struct_return)
829 {
830 store_unsigned_integer (buf, 8, struct_addr);
831 regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf);
832 }
833
834 /* Store return address. */
835 sp -= 8;
10f93086 836 store_unsigned_integer (buf, 8, bp_addr);
c4f35dd8
MK		 837 write_memory (sp, buf, 8);
838
839 /* Finally, update the stack pointer... */
840 store_unsigned_integer (buf, 8, sp);
841 regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf);
842
843 /* ...and fake a frame pointer. */
844 regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf);
845
3e210248 846 return sp + 16;
53e95fcf 847}
c4f35dd8
MK		 848\f
849
850/* The maximum number of saved registers. This should include %rip. */
2b5e0749 851#define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
c4f35dd8
MK		 852
853struct x86_64_frame_cache
854{
855 /* Base address. */
856 CORE_ADDR base;
857 CORE_ADDR sp_offset;
858 CORE_ADDR pc;
859
860 /* Saved registers. */
861 CORE_ADDR saved_regs[X86_64_NUM_SAVED_REGS];
862 CORE_ADDR saved_sp;
863
864 /* Do we have a frame? */
865 int frameless_p;
866};
8dda9770 867
c4f35dd8
MK		 868/* Allocate and initialize a frame cache. */
869
870static struct x86_64_frame_cache *
871x86_64_alloc_frame_cache (void)
8dda9770 872{
c4f35dd8
MK		 873 struct x86_64_frame_cache *cache;
874 int i;
875
876 cache = FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache);
8dda9770 877
c4f35dd8
MK		 878 /* Base address. */
879 cache->base = 0;
880 cache->sp_offset = -8;
881 cache->pc = 0;
882
883 /* Saved registers. We initialize these to -1 since zero is a valid
884 offset (that's where %rbp is supposed to be stored). */
885 for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
886 cache->saved_regs[i] = -1;
887 cache->saved_sp = 0;
888
889 /* Frameless until proven otherwise. */
890 cache->frameless_p = 1;
891
892 return cache;
8dda9770 893}
53e95fcf 894
c4f35dd8
MK		 895/* Do a limited analysis of the prologue at PC and update CACHE
896 accordingly. Bail out early if CURRENT_PC is reached. Return the
897 address where the analysis stopped.
898
899 We will handle only functions beginning with:
900
901 pushq %rbp 0x55
902 movq %rsp, %rbp 0x48 0x89 0xe5
903
904 Any function that doesn't start with this sequence will be assumed
905 to have no prologue and thus no valid frame pointer in %rbp. */
906
907static CORE_ADDR
908x86_64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
909 struct x86_64_frame_cache *cache)
53e95fcf 910{
c4f35dd8
MK		 911 static unsigned char proto[3] = { 0x48, 0x89, 0xe5 };
912 unsigned char buf[3];
913 unsigned char op;
914
915 if (current_pc <= pc)
916 return current_pc;
917
918 op = read_memory_unsigned_integer (pc, 1);
919
920 if (op == 0x55) /* pushq %rbp */
921 {
922 /* Take into account that we've executed the `pushq %rbp' that
923 starts this instruction sequence. */
924 cache->saved_regs[X86_64_RBP_REGNUM] = 0;
925 cache->sp_offset += 8;
926
927 /* If that's all, return now. */
928 if (current_pc <= pc + 1)
929 return current_pc;
930
931 /* Check for `movq %rsp, %rbp'. */
932 read_memory (pc + 1, buf, 3);
933 if (memcmp (buf, proto, 3) != 0)
934 return pc + 1;
935
936 /* OK, we actually have a frame. */
937 cache->frameless_p = 0;
938 return pc + 4;
939 }
940
941 return pc;
53e95fcf
JS		 942}
943
c4f35dd8
MK		 944/* Return PC of first real instruction. */
945
946static CORE_ADDR
947x86_64_skip_prologue (CORE_ADDR start_pc)
53e95fcf 948{
c4f35dd8
MK		 949 struct x86_64_frame_cache cache;
950 CORE_ADDR pc;
951
952 pc = x86_64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
953 if (cache.frameless_p)
954 return start_pc;
955
956 return pc;
53e95fcf 957}
c4f35dd8 958\f
53e95fcf 959
c4f35dd8
MK		 960/* Normal frames. */
961
962static struct x86_64_frame_cache *
963x86_64_frame_cache (struct frame_info *next_frame, void **this_cache)
6d686a84 964{
c4f35dd8
MK		 965 struct x86_64_frame_cache *cache;
966 char buf[8];
6d686a84 967 int i;
6d686a84 968
c4f35dd8
MK		 969 if (*this_cache)
970 return *this_cache;
6d686a84 971
c4f35dd8
MK		 972 cache = x86_64_alloc_frame_cache ();
973 *this_cache = cache;
974
975 frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
976 cache->base = extract_unsigned_integer (buf, 8);
977 if (cache->base == 0)
978 return cache;
979
980 /* For normal frames, %rip is stored at 8(%rbp). */
981 cache->saved_regs[X86_64_RIP_REGNUM] = 8;
982
983 cache->pc = frame_func_unwind (next_frame);
984 if (cache->pc != 0)
985 x86_64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
986
987 if (cache->frameless_p)
988 {
989 /* We didn't find a valid frame, which means that CACHE->base
990 currently holds the frame pointer for our calling frame. If
991 we're at the start of a function, or somewhere half-way its
992 prologue, the function's frame probably hasn't been fully
993 setup yet. Try to reconstruct the base address for the stack
994 frame by looking at the stack pointer. For truly "frameless"
995 functions this might work too. */
996
997 frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
998 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
999 }
1000
1001 /* Now that we have the base address for the stack frame we can
1002 calculate the value of %rsp in the calling frame. */
1003 cache->saved_sp = cache->base + 16;
1004
1005 /* Adjust all the saved registers such that they contain addresses
1006 instead of offsets. */
1007 for (i = 0; i < X86_64_NUM_SAVED_REGS; i++)
1008 if (cache->saved_regs[i] != -1)
1009 cache->saved_regs[i] += cache->base;
1010
1011 return cache;
6d686a84
ML		 1012}
1013
c4f35dd8
MK		 1014static void
1015x86_64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1016 struct frame_id *this_id)
1017{
1018 struct x86_64_frame_cache *cache =
1019 x86_64_frame_cache (next_frame, this_cache);
1020
1021 /* This marks the outermost frame. */
1022 if (cache->base == 0)
1023 return;
1024
1025 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
1026}
e76e1718 1027
c4f35dd8
MK		 1028static void
1029x86_64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1030 int regnum, int *optimizedp,
1031 enum lval_type *lvalp, CORE_ADDR *addrp,
1032 int *realnump, void *valuep)
53e95fcf 1033{
c4f35dd8
MK		 1034 struct x86_64_frame_cache *cache =
1035 x86_64_frame_cache (next_frame, this_cache);
e76e1718 1036
c4f35dd8 1037 gdb_assert (regnum >= 0);
b1ab997b 1038
c4f35dd8
MK		 1039 if (regnum == SP_REGNUM && cache->saved_sp)
1040 {
1041 *optimizedp = 0;
1042 *lvalp = not_lval;
1043 *addrp = 0;
1044 *realnump = -1;
1045 if (valuep)
1046 {
1047 /* Store the value. */
1048 store_unsigned_integer (valuep, 8, cache->saved_sp);
1049 }
1050 return;
1051 }
e76e1718 1052
c4f35dd8
MK		 1053 if (regnum < X86_64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
1054 {
1055 *optimizedp = 0;
1056 *lvalp = lval_memory;
1057 *addrp = cache->saved_regs[regnum];
1058 *realnump = -1;
1059 if (valuep)
1060 {
1061 /* Read the value in from memory. */
1062 read_memory (*addrp, valuep,
1063 register_size (current_gdbarch, regnum));
1064 }
1065 return;
1066 }
e76e1718 1067
c4f35dd8
MK		 1068 frame_register_unwind (next_frame, regnum,
1069 optimizedp, lvalp, addrp, realnump, valuep);
1070}
e76e1718 1071
c4f35dd8
MK		 1072static const struct frame_unwind x86_64_frame_unwind =
1073{
1074 NORMAL_FRAME,
1075 x86_64_frame_this_id,
1076 x86_64_frame_prev_register
1077};
e76e1718 1078
c4f35dd8 1079static const struct frame_unwind *
336d1bba 1080x86_64_frame_sniffer (struct frame_info *next_frame)
c4f35dd8
MK		 1081{
1082 return &x86_64_frame_unwind;
1083}
1084\f
e76e1718 1085
c4f35dd8
MK		 1086/* Signal trampolines. */
1087
1088/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
1089 64-bit variants. This would require using identical frame caches
1090 on both platforms. */
1091
1092static struct x86_64_frame_cache *
1093x86_64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1094{
1095 struct x86_64_frame_cache *cache;
1096 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1097 CORE_ADDR addr;
1098 char buf[8];
2b5e0749 1099 int i;
c4f35dd8
MK		 1100
1101 if (*this_cache)
1102 return *this_cache;
1103
1104 cache = x86_64_alloc_frame_cache ();
1105
1106 frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
1107 cache->base = extract_unsigned_integer (buf, 8) - 8;
1108
1109 addr = tdep->sigcontext_addr (next_frame);
2b5e0749
MK		 1110 gdb_assert (tdep->sc_reg_offset);
1111 gdb_assert (tdep->sc_num_regs <= X86_64_NUM_SAVED_REGS);
1112 for (i = 0; i < tdep->sc_num_regs; i++)
1113 if (tdep->sc_reg_offset[i] != -1)
1114 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8
MK		 1115
1116 *this_cache = cache;
1117 return cache;
53e95fcf
JS		 1118}
1119
c4f35dd8
MK		 1120static void
1121x86_64_sigtramp_frame_this_id (struct frame_info *next_frame,
1122 void **this_cache, struct frame_id *this_id)
1123{
1124 struct x86_64_frame_cache *cache =
1125 x86_64_sigtramp_frame_cache (next_frame, this_cache);
1126
1127 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
1128}
1129
1130static void
1131x86_64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1132 void **this_cache,
1133 int regnum, int *optimizedp,
1134 enum lval_type *lvalp, CORE_ADDR *addrp,
1135 int *realnump, void *valuep)
1136{
1137 /* Make sure we've initialized the cache. */
1138 x86_64_sigtramp_frame_cache (next_frame, this_cache);
1139
1140 x86_64_frame_prev_register (next_frame, this_cache, regnum,
1141 optimizedp, lvalp, addrp, realnump, valuep);
1142}
1143
1144static const struct frame_unwind x86_64_sigtramp_frame_unwind =
1145{
1146 SIGTRAMP_FRAME,
1147 x86_64_sigtramp_frame_this_id,
1148 x86_64_sigtramp_frame_prev_register
1149};
1150
1151static const struct frame_unwind *
336d1bba 1152x86_64_sigtramp_frame_sniffer (struct frame_info *next_frame)
c4f35dd8 1153{
336d1bba 1154 CORE_ADDR pc = frame_pc_unwind (next_frame);
c4f35dd8
MK		 1155 char *name;
1156
1157 find_pc_partial_function (pc, &name, NULL, NULL);
1158 if (PC_IN_SIGTRAMP (pc, name))
1c3545ae
MK		 1159 {
1160 gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr);
1161
1162 return &x86_64_sigtramp_frame_unwind;
1163 }
c4f35dd8
MK		 1164
1165 return NULL;
1166}
1167\f
1168
1169static CORE_ADDR
1170x86_64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1171{
1172 struct x86_64_frame_cache *cache =
1173 x86_64_frame_cache (next_frame, this_cache);
1174
1175 return cache->base;
1176}
1177
1178static const struct frame_base x86_64_frame_base =
1179{
1180 &x86_64_frame_unwind,
1181 x86_64_frame_base_address,
1182 x86_64_frame_base_address,
1183 x86_64_frame_base_address
1184};
1185
166f4c7b 1186static struct frame_id
c4f35dd8 1187x86_64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
166f4c7b 1188{
c4f35dd8
MK		 1189 char buf[8];
1190 CORE_ADDR fp;
1191
1192 frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
1193 fp = extract_unsigned_integer (buf, 8);
1194
1195 return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
166f4c7b
ML		 1196}
1197
2213a65d 1198void
0c1a73d6 1199x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
53e95fcf 1200{
0c1a73d6 1201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53e95fcf 1202
b83b026c 1203 /* The x86-64 has 16 SSE registers. */
0c1a73d6 1204 tdep->num_xmm_regs = 16;
53e95fcf 1205
0c1a73d6 1206 /* This is what all the fuss is about. */
53e95fcf
JS		 1207 set_gdbarch_long_bit (gdbarch, 64);
1208 set_gdbarch_long_long_bit (gdbarch, 64);
1209 set_gdbarch_ptr_bit (gdbarch, 64);
1210
b83b026c
MK		 1211 /* In contrast to the i386, on the x86-64 a `long double' actually
1212 takes up 128 bits, even though it's still based on the i387
1213 extended floating-point format which has only 80 significant bits. */
1214 set_gdbarch_long_double_bit (gdbarch, 128);
1215
53e95fcf 1216 set_gdbarch_num_regs (gdbarch, X86_64_NUM_REGS);
c4f35dd8
MK		 1217 set_gdbarch_register_name (gdbarch, x86_64_register_name);
1218 set_gdbarch_register_type (gdbarch, x86_64_register_type);
b83b026c
MK		 1219
1220 /* Register numbers of various important registers. */
c4f35dd8
MK		 1221 set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */
1222 set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */
1223 set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */
1224 set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */
b83b026c
MK		 1225
1226 /* The "default" register numbering scheme for the x86-64 is
c4f35dd8
MK		 1227 referred to as the "DWARF Register Number Mapping" in the System
1228 V psABI. The preferred debugging format for all known x86-64
1229 targets is actually DWARF2, and GCC doesn't seem to support DWARF
1230 (that is DWARF-1), but we provide the same mapping just in case.
1231 This mapping is also used for stabs, which GCC does support. */
1232 set_gdbarch_stab_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
1233 set_gdbarch_dwarf_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
1234 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum);
de220d0f 1235
c4f35dd8
MK		 1236 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1237 be in use on any of the supported x86-64 targets. */
53e95fcf 1238
c4f35dd8
MK		 1239 /* Call dummy code. */
1240 set_gdbarch_push_dummy_call (gdbarch, x86_64_push_dummy_call);
53e95fcf 1241
d532c08f
MK		 1242 set_gdbarch_convert_register_p (gdbarch, x86_64_convert_register_p);
1243 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1244 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1245
48037ead 1246 set_gdbarch_extract_return_value (gdbarch, x86_64_extract_return_value);
48037ead 1247 set_gdbarch_store_return_value (gdbarch, x86_64_store_return_value);
b83b026c
MK		 1248 /* Override, since this is handled by x86_64_extract_return_value. */
1249 set_gdbarch_extract_struct_value_address (gdbarch, NULL);
1250 set_gdbarch_use_struct_convention (gdbarch, x86_64_use_struct_convention);
53e95fcf 1251
b83b026c 1252 set_gdbarch_skip_prologue (gdbarch, x86_64_skip_prologue);
53e95fcf 1253
c4f35dd8 1254 /* Avoid wiring in the MMX registers for now. */
2213a65d
MK		 1255 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1256
c4f35dd8 1257 set_gdbarch_unwind_dummy_id (gdbarch, x86_64_unwind_dummy_id);
53e95fcf 1258
b83b026c
MK		 1259 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1260 since all supported x86-64 targets are ELF, but that might change
1261 in the future. */
8a8ab2b9 1262 set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section);
c4f35dd8 1263
336d1bba
AC		 1264 frame_unwind_append_sniffer (gdbarch, x86_64_sigtramp_frame_sniffer);
1265 frame_unwind_append_sniffer (gdbarch, x86_64_frame_sniffer);
c4f35dd8
MK		 1266 frame_base_set_default (gdbarch, &x86_64_frame_base);
1267}
1268\f
1269
1270#define I387_FISEG_REGNUM FISEG_REGNUM
1271#define I387_FOSEG_REGNUM FOSEG_REGNUM
1272
1273/* The 64-bit FXSAVE format differs from the 32-bit format in the
1274 sense that the instruction pointer and data pointer are simply
1275 64-bit offsets into the code segment and the data segment instead
1276 of a selector offset pair. The functions below store the upper 32
1277 bits of these pointers (instead of just the 16-bits of the segment
1278 selector). */
1279
1280/* Fill GDB's register array with the floating-point and SSE register
1281 values in *FXSAVE. This function masks off any of the reserved
1282 bits in *FXSAVE. */
1283
1284void
1285x86_64_supply_fxsave (char *fxsave)
1286{
1287 i387_supply_fxsave (fxsave);
1288
1289 if (fxsave)
1290 {
1291 supply_register (I387_FISEG_REGNUM, fxsave + 12);
1292 supply_register (I387_FOSEG_REGNUM, fxsave + 20);
1293 }
0c1a73d6
MK		 1294}
1295
c4f35dd8
MK		 1296/* Fill register REGNUM (if it is a floating-point or SSE register) in
1297 *FXSAVE with the value in GDB's register array. If REGNUM is -1, do
1298 this for all registers. This function doesn't touch any of the
1299 reserved bits in *FXSAVE. */
1300
53e95fcf 1301void
c4f35dd8 1302x86_64_fill_fxsave (char *fxsave, int regnum)
53e95fcf 1303{
c4f35dd8 1304 i387_fill_fxsave (fxsave, regnum);
53e95fcf 1305
c4f35dd8 1306 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
088ce440 1307 regcache_collect (I387_FISEG_REGNUM, fxsave + 12);
c4f35dd8 1308 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
088ce440 1309 regcache_collect (I387_FOSEG_REGNUM, fxsave + 20);
53e95fcf 1310}
GDB Binutils - Deliverables
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