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ca3bf3bd DJ |
1 | /* Configuration for the Xtensa architecture for GDB, the GNU debugger. |
2 | ||
3 | Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
20 | Boston, MA 02110-1301, USA. */ | |
21 | ||
22 | #include "xtensa-config.h" | |
23 | #include "defs.h" | |
24 | #include "gdbarch.h" | |
25 | #include "xtensa-tdep.h" | |
26 | #include "gdbtypes.h" | |
27 | ||
28 | /* Check version of configuration file. */ | |
29 | #define XTENSA_CONFIG_VERSION 0x60 | |
30 | #if XTENSA_TDEP_VERSION != XTENSA_CONFIG_VERSION | |
31 | #warning "xtensa-config.c version mismatch!" | |
32 | #endif | |
33 | ||
34 | ||
35 | /* Return the byte order from the configuration. | |
36 | We need this function, because the byte order is needed even | |
37 | before the target structure (tdep) has been set up. */ | |
38 | ||
39 | int | |
40 | xtensa_config_byte_order (void) | |
41 | { | |
42 | return XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; | |
43 | } | |
44 | ||
45 | ||
46 | /* This routine returns the predefined architecture-dependent | |
47 | parameter structure (tdep) and register map. */ | |
48 | ||
49 | struct gdbarch_tdep xtensa_tdep; | |
50 | ||
51 | struct gdbarch_tdep * | |
52 | xtensa_config_tdep (struct gdbarch_info *info) | |
53 | { | |
54 | return &xtensa_tdep; | |
55 | } | |
56 | ||
57 | ||
58 | /* Masked registers. */ | |
59 | const int mask0[] = { 1, 96, 0, 4 }; | |
60 | const int mask1[] = { 1, 96, 5, 1 }; | |
61 | const int mask2[] = { 1, 96, 18, 1 }; | |
62 | const int mask3[] = { 1, 96, 6, 2 }; | |
63 | const int mask4[] = { 1, 96, 4, 1 }; | |
64 | const int mask5[] = { 1, 96, 16, 2 }; | |
65 | const int mask6[] = { 1, 96, 8, 4 }; | |
66 | const int mask7[] = { 1, 95, 12, 20 }; | |
67 | const int mask8[] = { 1, 95, 0, 1 }; | |
68 | const int mask9[] = { 1, 108, 8, 4 }; | |
69 | const int mask10[] = { 1, 109, 24, 8 }; | |
70 | const int mask11[] = { 1, 109, 16, 8 }; | |
71 | const int mask12[] = { 1, 109, 8, 8 }; | |
72 | const int mask13[] = { 1, 110, 16, 2 }; | |
73 | const int mask14[] = { 1, 111, 16, 2 }; | |
74 | const int mask15[] = { 1, 67, 22, 10 }; | |
75 | ||
76 | ||
77 | /* Register map. */ | |
78 | xtensa_register_t rmap[] = | |
79 | { | |
80 | { /* 0000 */ "ar0", 0, xtRegisterTypeArRegfile, 0x2, 0, | |
81 | 32, 4, 4, 0x00000100, 0x0006, 0, | |
82 | 0, 0 }, | |
83 | { /* 0001 */ "ar1", 4, xtRegisterTypeArRegfile, 0x2, 0, | |
84 | 32, 4, 4, 0x00000101, 0x0006, 0, | |
85 | 0, 0 }, | |
86 | { /* 0002 */ "ar2", 8, xtRegisterTypeArRegfile, 0x2, 0, | |
87 | 32, 4, 4, 0x00000102, 0x0006, 0, | |
88 | 0, 0 }, | |
89 | { /* 0003 */ "ar3", 12, xtRegisterTypeArRegfile, 0x2, 0, | |
90 | 32, 4, 4, 0x00000103, 0x0006, 0, | |
91 | 0, 0 }, | |
92 | { /* 0004 */ "ar4", 16, xtRegisterTypeArRegfile, 0x2, 0, | |
93 | 32, 4, 4, 0x00000104, 0x0006, 0, | |
94 | 0, 0 }, | |
95 | { /* 0005 */ "ar5", 20, xtRegisterTypeArRegfile, 0x2, 0, | |
96 | 32, 4, 4, 0x00000105, 0x0006, 0, | |
97 | 0, 0 }, | |
98 | { /* 0006 */ "ar6", 24, xtRegisterTypeArRegfile, 0x2, 0, | |
99 | 32, 4, 4, 0x00000106, 0x0006, 0, | |
100 | 0, 0 }, | |
101 | { /* 0007 */ "ar7", 28, xtRegisterTypeArRegfile, 0x2, 0, | |
102 | 32, 4, 4, 0x00000107, 0x0006, 0, | |
103 | 0, 0 }, | |
104 | { /* 0008 */ "ar8", 32, xtRegisterTypeArRegfile, 0x2, 0, | |
105 | 32, 4, 4, 0x00000108, 0x0006, 0, | |
106 | 0, 0 }, | |
107 | { /* 0009 */ "ar9", 36, xtRegisterTypeArRegfile, 0x2, 0, | |
108 | 32, 4, 4, 0x00000109, 0x0006, 0, | |
109 | 0, 0 }, | |
110 | { /* 0010 */ "ar10", 40, xtRegisterTypeArRegfile, 0x2, 0, | |
111 | 32, 4, 4, 0x0000010a, 0x0006, 0, | |
112 | 0, 0 }, | |
113 | { /* 0011 */ "ar11", 44, xtRegisterTypeArRegfile, 0x2, 0, | |
114 | 32, 4, 4, 0x0000010b, 0x0006, 0, | |
115 | 0, 0 }, | |
116 | { /* 0012 */ "ar12", 48, xtRegisterTypeArRegfile, 0x2, 0, | |
117 | 32, 4, 4, 0x0000010c, 0x0006, 0, | |
118 | 0, 0 }, | |
119 | { /* 0013 */ "ar13", 52, xtRegisterTypeArRegfile, 0x2, 0, | |
120 | 32, 4, 4, 0x0000010d, 0x0006, 0, | |
121 | 0, 0 }, | |
122 | { /* 0014 */ "ar14", 56, xtRegisterTypeArRegfile, 0x2, 0, | |
123 | 32, 4, 4, 0x0000010e, 0x0006, 0, | |
124 | 0, 0 }, | |
125 | { /* 0015 */ "ar15", 60, xtRegisterTypeArRegfile, 0x2, 0, | |
126 | 32, 4, 4, 0x0000010f, 0x0006, 0, | |
127 | 0, 0 }, | |
128 | { /* 0016 */ "ar16", 64, xtRegisterTypeArRegfile, 0x2, 0, | |
129 | 32, 4, 4, 0x00000110, 0x0006, 0, | |
130 | 0, 0 }, | |
131 | { /* 0017 */ "ar17", 68, xtRegisterTypeArRegfile, 0x2, 0, | |
132 | 32, 4, 4, 0x00000111, 0x0006, 0, | |
133 | 0, 0 }, | |
134 | { /* 0018 */ "ar18", 72, xtRegisterTypeArRegfile, 0x2, 0, | |
135 | 32, 4, 4, 0x00000112, 0x0006, 0, | |
136 | 0, 0 }, | |
137 | { /* 0019 */ "ar19", 76, xtRegisterTypeArRegfile, 0x2, 0, | |
138 | 32, 4, 4, 0x00000113, 0x0006, 0, | |
139 | 0, 0 }, | |
140 | { /* 0020 */ "ar20", 80, xtRegisterTypeArRegfile, 0x2, 0, | |
141 | 32, 4, 4, 0x00000114, 0x0006, 0, | |
142 | 0, 0 }, | |
143 | { /* 0021 */ "ar21", 84, xtRegisterTypeArRegfile, 0x2, 0, | |
144 | 32, 4, 4, 0x00000115, 0x0006, 0, | |
145 | 0, 0 }, | |
146 | { /* 0022 */ "ar22", 88, xtRegisterTypeArRegfile, 0x2, 0, | |
147 | 32, 4, 4, 0x00000116, 0x0006, 0, | |
148 | 0, 0 }, | |
149 | { /* 0023 */ "ar23", 92, xtRegisterTypeArRegfile, 0x2, 0, | |
150 | 32, 4, 4, 0x00000117, 0x0006, 0, | |
151 | 0, 0 }, | |
152 | { /* 0024 */ "ar24", 96, xtRegisterTypeArRegfile, 0x2, 0, | |
153 | 32, 4, 4, 0x00000118, 0x0006, 0, | |
154 | 0, 0 }, | |
155 | { /* 0025 */ "ar25", 100, xtRegisterTypeArRegfile, 0x2, 0, | |
156 | 32, 4, 4, 0x00000119, 0x0006, 0, | |
157 | 0, 0 }, | |
158 | { /* 0026 */ "ar26", 104, xtRegisterTypeArRegfile, 0x2, 0, | |
159 | 32, 4, 4, 0x0000011a, 0x0006, 0, | |
160 | 0, 0 }, | |
161 | { /* 0027 */ "ar27", 108, xtRegisterTypeArRegfile, 0x2, 0, | |
162 | 32, 4, 4, 0x0000011b, 0x0006, 0, | |
163 | 0, 0 }, | |
164 | { /* 0028 */ "ar28", 112, xtRegisterTypeArRegfile, 0x2, 0, | |
165 | 32, 4, 4, 0x0000011c, 0x0006, 0, | |
166 | 0, 0 }, | |
167 | { /* 0029 */ "ar29", 116, xtRegisterTypeArRegfile, 0x2, 0, | |
168 | 32, 4, 4, 0x0000011d, 0x0006, 0, | |
169 | 0, 0 }, | |
170 | { /* 0030 */ "ar30", 120, xtRegisterTypeArRegfile, 0x2, 0, | |
171 | 32, 4, 4, 0x0000011e, 0x0006, 0, | |
172 | 0, 0 }, | |
173 | { /* 0031 */ "ar31", 124, xtRegisterTypeArRegfile, 0x2, 0, | |
174 | 32, 4, 4, 0x0000011f, 0x0006, 0, | |
175 | 0, 0 }, | |
176 | { /* 0032 */ "ar32", 128, xtRegisterTypeArRegfile, 0x2, 0, | |
177 | 32, 4, 4, 0x00000120, 0x0006, 0, | |
178 | 0, 0 }, | |
179 | { /* 0033 */ "ar33", 132, xtRegisterTypeArRegfile, 0x2, 0, | |
180 | 32, 4, 4, 0x00000121, 0x0006, 0, | |
181 | 0, 0 }, | |
182 | { /* 0034 */ "ar34", 136, xtRegisterTypeArRegfile, 0x2, 0, | |
183 | 32, 4, 4, 0x00000122, 0x0006, 0, | |
184 | 0, 0 }, | |
185 | { /* 0035 */ "ar35", 140, xtRegisterTypeArRegfile, 0x2, 0, | |
186 | 32, 4, 4, 0x00000123, 0x0006, 0, | |
187 | 0, 0 }, | |
188 | { /* 0036 */ "ar36", 144, xtRegisterTypeArRegfile, 0x2, 0, | |
189 | 32, 4, 4, 0x00000124, 0x0006, 0, | |
190 | 0, 0 }, | |
191 | { /* 0037 */ "ar37", 148, xtRegisterTypeArRegfile, 0x2, 0, | |
192 | 32, 4, 4, 0x00000125, 0x0006, 0, | |
193 | 0, 0 }, | |
194 | { /* 0038 */ "ar38", 152, xtRegisterTypeArRegfile, 0x2, 0, | |
195 | 32, 4, 4, 0x00000126, 0x0006, 0, | |
196 | 0, 0 }, | |
197 | { /* 0039 */ "ar39", 156, xtRegisterTypeArRegfile, 0x2, 0, | |
198 | 32, 4, 4, 0x00000127, 0x0006, 0, | |
199 | 0, 0 }, | |
200 | { /* 0040 */ "ar40", 160, xtRegisterTypeArRegfile, 0x2, 0, | |
201 | 32, 4, 4, 0x00000128, 0x0006, 0, | |
202 | 0, 0 }, | |
203 | { /* 0041 */ "ar41", 164, xtRegisterTypeArRegfile, 0x2, 0, | |
204 | 32, 4, 4, 0x00000129, 0x0006, 0, | |
205 | 0, 0 }, | |
206 | { /* 0042 */ "ar42", 168, xtRegisterTypeArRegfile, 0x2, 0, | |
207 | 32, 4, 4, 0x0000012a, 0x0006, 0, | |
208 | 0, 0 }, | |
209 | { /* 0043 */ "ar43", 172, xtRegisterTypeArRegfile, 0x2, 0, | |
210 | 32, 4, 4, 0x0000012b, 0x0006, 0, | |
211 | 0, 0 }, | |
212 | { /* 0044 */ "ar44", 176, xtRegisterTypeArRegfile, 0x2, 0, | |
213 | 32, 4, 4, 0x0000012c, 0x0006, 0, | |
214 | 0, 0 }, | |
215 | { /* 0045 */ "ar45", 180, xtRegisterTypeArRegfile, 0x2, 0, | |
216 | 32, 4, 4, 0x0000012d, 0x0006, 0, | |
217 | 0, 0 }, | |
218 | { /* 0046 */ "ar46", 184, xtRegisterTypeArRegfile, 0x2, 0, | |
219 | 32, 4, 4, 0x0000012e, 0x0006, 0, | |
220 | 0, 0 }, | |
221 | { /* 0047 */ "ar47", 188, xtRegisterTypeArRegfile, 0x2, 0, | |
222 | 32, 4, 4, 0x0000012f, 0x0006, 0, | |
223 | 0, 0 }, | |
224 | { /* 0048 */ "ar48", 192, xtRegisterTypeArRegfile, 0x2, 0, | |
225 | 32, 4, 4, 0x00000130, 0x0006, 0, | |
226 | 0, 0 }, | |
227 | { /* 0049 */ "ar49", 196, xtRegisterTypeArRegfile, 0x2, 0, | |
228 | 32, 4, 4, 0x00000131, 0x0006, 0, | |
229 | 0, 0 }, | |
230 | { /* 0050 */ "ar50", 200, xtRegisterTypeArRegfile, 0x2, 0, | |
231 | 32, 4, 4, 0x00000132, 0x0006, 0, | |
232 | 0, 0 }, | |
233 | { /* 0051 */ "ar51", 204, xtRegisterTypeArRegfile, 0x2, 0, | |
234 | 32, 4, 4, 0x00000133, 0x0006, 0, | |
235 | 0, 0 }, | |
236 | { /* 0052 */ "ar52", 208, xtRegisterTypeArRegfile, 0x2, 0, | |
237 | 32, 4, 4, 0x00000134, 0x0006, 0, | |
238 | 0, 0 }, | |
239 | { /* 0053 */ "ar53", 212, xtRegisterTypeArRegfile, 0x2, 0, | |
240 | 32, 4, 4, 0x00000135, 0x0006, 0, | |
241 | 0, 0 }, | |
242 | { /* 0054 */ "ar54", 216, xtRegisterTypeArRegfile, 0x2, 0, | |
243 | 32, 4, 4, 0x00000136, 0x0006, 0, | |
244 | 0, 0 }, | |
245 | { /* 0055 */ "ar55", 220, xtRegisterTypeArRegfile, 0x2, 0, | |
246 | 32, 4, 4, 0x00000137, 0x0006, 0, | |
247 | 0, 0 }, | |
248 | { /* 0056 */ "ar56", 224, xtRegisterTypeArRegfile, 0x2, 0, | |
249 | 32, 4, 4, 0x00000138, 0x0006, 0, | |
250 | 0, 0 }, | |
251 | { /* 0057 */ "ar57", 228, xtRegisterTypeArRegfile, 0x2, 0, | |
252 | 32, 4, 4, 0x00000139, 0x0006, 0, | |
253 | 0, 0 }, | |
254 | { /* 0058 */ "ar58", 232, xtRegisterTypeArRegfile, 0x2, 0, | |
255 | 32, 4, 4, 0x0000013a, 0x0006, 0, | |
256 | 0, 0 }, | |
257 | { /* 0059 */ "ar59", 236, xtRegisterTypeArRegfile, 0x2, 0, | |
258 | 32, 4, 4, 0x0000013b, 0x0006, 0, | |
259 | 0, 0 }, | |
260 | { /* 0060 */ "ar60", 240, xtRegisterTypeArRegfile, 0x2, 0, | |
261 | 32, 4, 4, 0x0000013c, 0x0006, 0, | |
262 | 0, 0 }, | |
263 | { /* 0061 */ "ar61", 244, xtRegisterTypeArRegfile, 0x2, 0, | |
264 | 32, 4, 4, 0x0000013d, 0x0006, 0, | |
265 | 0, 0 }, | |
266 | { /* 0062 */ "ar62", 248, xtRegisterTypeArRegfile, 0x2, 0, | |
267 | 32, 4, 4, 0x0000013e, 0x0006, 0, | |
268 | 0, 0 }, | |
269 | { /* 0063 */ "ar63", 252, xtRegisterTypeArRegfile, 0x2, 0, | |
270 | 32, 4, 4, 0x0000013f, 0x0006, 0, | |
271 | 0, 0 }, | |
272 | { /* 0064 */ "lbeg", 256, xtRegisterTypeSpecialReg, 0x1100, 0, | |
273 | 32, 4, 4, 0x00000200, 0x0006, 0, | |
274 | 0, 0 }, | |
275 | { /* 0065 */ "lend", 260, xtRegisterTypeSpecialReg, 0x1100, 0, | |
276 | 32, 4, 4, 0x00000201, 0x0006, 0, | |
277 | 0, 0 }, | |
278 | { /* 0066 */ "lcount", 264, xtRegisterTypeSpecialReg, 0x1100, 0, | |
279 | 32, 4, 4, 0x00000202, 0x0006, 0, | |
280 | 0, 0 }, | |
281 | { /* 0067 */ "ptevaddr", 268, xtRegisterTypeSpecialReg, 0x1000, 0, | |
282 | 32, 4, 4, 0x00000253, 0x0007, 0, | |
283 | 0, 0 }, | |
284 | { /* 0068 */ "ddr", 272, xtRegisterTypeSpecialReg, 0x1000, 0, | |
285 | 32, 4, 4, 0x00000268, 0x0007, 0, | |
286 | 0, 0 }, | |
287 | { /* 0069 */ "interrupt", 276, xtRegisterTypeSpecialReg, 0x1000, 0, | |
288 | 17, 4, 4, 0x000002e2, 0x000b, 0, | |
289 | 0, 0 }, | |
290 | { /* 0070 */ "intset", 280, xtRegisterTypeSpecialReg, 0x1000, 0, | |
291 | 17, 4, 4, 0x000002e2, 0x000d, 0, | |
292 | 0, 0 }, | |
293 | { /* 0071 */ "intclear", 284, xtRegisterTypeSpecialReg, 0x1000, 0, | |
294 | 17, 4, 4, 0x000002e3, 0x000d, 0, | |
295 | 0, 0 }, | |
296 | { /* 0072 */ "ccount", 288, xtRegisterTypeSpecialReg, 0x1000, 0, | |
297 | 32, 4, 4, 0x000002ea, 0x000f, 0, | |
298 | 0, 0 }, | |
299 | { /* 0073 */ "prid", 292, xtRegisterTypeSpecialReg, 0x1000, 0, | |
300 | 32, 4, 4, 0x000002eb, 0x0003, 0, | |
301 | 0, 0 }, | |
302 | { /* 0074 */ "icount", 296, xtRegisterTypeSpecialReg, 0x1000, 0, | |
303 | 32, 4, 4, 0x000002ec, 0x000f, 0, | |
304 | 0, 0 }, | |
305 | { /* 0075 */ "ccompare0", 300, xtRegisterTypeSpecialReg, 0x1000, 0, | |
306 | 32, 4, 4, 0x000002f0, 0x000f, 0, | |
307 | 0, 0 }, | |
308 | { /* 0076 */ "ccompare1", 304, xtRegisterTypeSpecialReg, 0x1000, 0, | |
309 | 32, 4, 4, 0x000002f1, 0x000f, 0, | |
310 | 0, 0 }, | |
311 | { /* 0077 */ "ccompare2", 308, xtRegisterTypeSpecialReg, 0x1000, 0, | |
312 | 32, 4, 4, 0x000002f2, 0x000f, 0, | |
313 | 0, 0 }, | |
314 | { /* 0078 */ "epc1", 312, xtRegisterTypeSpecialReg, 0x1000, 0, | |
315 | 32, 4, 4, 0x000002b1, 0x0007, 0, | |
316 | 0, 0 }, | |
317 | { /* 0079 */ "epc2", 316, xtRegisterTypeSpecialReg, 0x1000, 0, | |
318 | 32, 4, 4, 0x000002b2, 0x0007, 0, | |
319 | 0, 0 }, | |
320 | { /* 0080 */ "epc3", 320, xtRegisterTypeSpecialReg, 0x1000, 0, | |
321 | 32, 4, 4, 0x000002b3, 0x0007, 0, | |
322 | 0, 0 }, | |
323 | { /* 0081 */ "epc4", 324, xtRegisterTypeSpecialReg, 0x1000, 0, | |
324 | 32, 4, 4, 0x000002b4, 0x0007, 0, | |
325 | 0, 0 }, | |
326 | { /* 0082 */ "excsave1", 328, xtRegisterTypeSpecialReg, 0x1000, 0, | |
327 | 32, 4, 4, 0x000002d1, 0x0007, 0, | |
328 | 0, 0 }, | |
329 | { /* 0083 */ "excsave2", 332, xtRegisterTypeSpecialReg, 0x1000, 0, | |
330 | 32, 4, 4, 0x000002d2, 0x0007, 0, | |
331 | 0, 0 }, | |
332 | { /* 0084 */ "excsave3", 336, xtRegisterTypeSpecialReg, 0x1000, 0, | |
333 | 32, 4, 4, 0x000002d3, 0x0007, 0, | |
334 | 0, 0 }, | |
335 | { /* 0085 */ "excsave4", 340, xtRegisterTypeSpecialReg, 0x1000, 0, | |
336 | 32, 4, 4, 0x000002d4, 0x0007, 0, | |
337 | 0, 0 }, | |
338 | { /* 0086 */ "eps2", 344, xtRegisterTypeSpecialReg, 0x1000, 0, | |
339 | 19, 4, 4, 0x000002c2, 0x0007, 0, | |
340 | 0, 0 }, | |
341 | { /* 0087 */ "eps3", 348, xtRegisterTypeSpecialReg, 0x1000, 0, | |
342 | 19, 4, 4, 0x000002c3, 0x0007, 0, | |
343 | 0, 0 }, | |
344 | { /* 0088 */ "eps4", 352, xtRegisterTypeSpecialReg, 0x1000, 0, | |
345 | 19, 4, 4, 0x000002c4, 0x0007, 0, | |
346 | 0, 0 }, | |
347 | { /* 0089 */ "exccause", 356, xtRegisterTypeSpecialReg, 0x1000, 0, | |
348 | 6, 4, 4, 0x000002e8, 0x0007, 0, | |
349 | 0, 0 }, | |
350 | { /* 0090 */ "depc", 360, xtRegisterTypeSpecialReg, 0x1000, 0, | |
351 | 32, 4, 4, 0x000002c0, 0x0007, 0, | |
352 | 0, 0 }, | |
353 | { /* 0091 */ "excvaddr", 364, xtRegisterTypeSpecialReg, 0x1000, 0, | |
354 | 32, 4, 4, 0x000002ee, 0x0007, 0, | |
355 | 0, 0 }, | |
356 | { /* 0092 */ "windowbase", 368, xtRegisterTypeSpecialReg, 0x1002, 0, | |
357 | 4, 4, 4, 0x00000248, 0x0007, 0, | |
358 | 0, 0 }, | |
359 | { /* 0093 */ "windowstart", 372, xtRegisterTypeSpecialReg, 0x1002, 0, | |
360 | 16, 4, 4, 0x00000249, 0x0007, 0, | |
361 | 0, 0 }, | |
362 | { /* 0094 */ "sar", 376, xtRegisterTypeSpecialReg, 0x1100, 0, | |
363 | 6, 4, 4, 0x00000203, 0x0006, 0, | |
364 | 0, 0 }, | |
365 | { /* 0095 */ "litbase", 380, xtRegisterTypeSpecialReg, 0x1100, 0, | |
366 | 32, 4, 4, 0x00000205, 0x0006, 0, | |
367 | 0, 0 }, | |
368 | { /* 0096 */ "ps", 384, xtRegisterTypeSpecialReg, 0x1100, 0, | |
369 | 19, 4, 4, 0x000002e6, 0x0007, 0, | |
370 | 0, 0 }, | |
371 | { /* 0097 */ "misc0", 388, xtRegisterTypeSpecialReg, 0x1000, 0, | |
372 | 32, 4, 4, 0x000002f4, 0x0007, 0, | |
373 | 0, 0 }, | |
374 | { /* 0098 */ "misc1", 392, xtRegisterTypeSpecialReg, 0x1000, 0, | |
375 | 32, 4, 4, 0x000002f5, 0x0007, 0, | |
376 | 0, 0 }, | |
377 | { /* 0099 */ "intenable", 396, xtRegisterTypeSpecialReg, 0x1000, 0, | |
378 | 17, 4, 4, 0x000002e4, 0x0007, 0, | |
379 | 0, 0 }, | |
380 | { /* 0100 */ "dbreaka0", 400, xtRegisterTypeSpecialReg, 0x1000, 0, | |
381 | 32, 4, 4, 0x00000290, 0x0007, 0, | |
382 | 0, 0 }, | |
383 | { /* 0101 */ "dbreakc0", 404, xtRegisterTypeSpecialReg, 0x1000, 0, | |
384 | 32, 4, 4, 0x000002a0, 0x0007, 0, | |
385 | 0, 0 }, | |
386 | { /* 0102 */ "dbreaka1", 408, xtRegisterTypeSpecialReg, 0x1000, 0, | |
387 | 32, 4, 4, 0x00000291, 0x0007, 0, | |
388 | 0, 0 }, | |
389 | { /* 0103 */ "dbreakc1", 412, xtRegisterTypeSpecialReg, 0x1000, 0, | |
390 | 32, 4, 4, 0x000002a1, 0x0007, 0, | |
391 | 0, 0 }, | |
392 | { /* 0104 */ "ibreaka0", 416, xtRegisterTypeSpecialReg, 0x1000, 0, | |
393 | 32, 4, 4, 0x00000280, 0x0007, 0, | |
394 | 0, 0 }, | |
395 | { /* 0105 */ "ibreaka1", 420, xtRegisterTypeSpecialReg, 0x1000, 0, | |
396 | 32, 4, 4, 0x00000281, 0x0007, 0, | |
397 | 0, 0 }, | |
398 | { /* 0106 */ "ibreakenable", 424, xtRegisterTypeSpecialReg, 0x1000, 0, | |
399 | 2, 4, 4, 0x00000260, 0x0007, 0, | |
400 | 0, 0 }, | |
401 | { /* 0107 */ "icountlevel", 428, xtRegisterTypeSpecialReg, 0x1000, 0, | |
402 | 4, 4, 4, 0x000002ed, 0x0007, 0, | |
403 | 0, 0 }, | |
404 | { /* 0108 */ "debugcause", 432, xtRegisterTypeSpecialReg, 0x1000, 0, | |
405 | 12, 4, 4, 0x000002e9, 0x0003, 0, | |
406 | 0, 0 }, | |
407 | { /* 0109 */ "rasid", 436, xtRegisterTypeSpecialReg, 0x1000, 0, | |
408 | 32, 4, 4, 0x0000025a, 0x0007, 0, | |
409 | 0, 0 }, | |
410 | { /* 0110 */ "itlbcfg", 440, xtRegisterTypeSpecialReg, 0x1000, 0, | |
411 | 18, 4, 4, 0x0000025b, 0x0007, 0, | |
412 | 0, 0 }, | |
413 | { /* 0111 */ "dtlbcfg", 444, xtRegisterTypeSpecialReg, 0x1000, 0, | |
414 | 18, 4, 4, 0x0000025c, 0x0007, 0, | |
415 | 0, 0 }, | |
416 | { /* 0112 */ "threadptr", 448, xtRegisterTypeUserReg, 0x110, 0, | |
417 | 32, 4, 4, 0x000003e7, 0x0006, 0, | |
418 | 0, 0 }, | |
419 | { /* 0113 */ "pc", 452, xtRegisterTypeVirtual, 0x100, 0, | |
420 | 32, 4, 4, 0x00000020, 0x0006, 0, | |
421 | 0, 0 }, | |
422 | { /* 0114 */ "a0", 456, xtRegisterTypeWindow, 0x100, 0, | |
423 | 32, 4, 4, 0x00000000, 0x0006, 0, | |
424 | 0, 0 }, | |
425 | { /* 0115 */ "a1", 460, xtRegisterTypeWindow, 0x100, 0, | |
426 | 32, 4, 4, 0x00000001, 0x0006, 0, | |
427 | 0, 0 }, | |
428 | { /* 0116 */ "a2", 464, xtRegisterTypeWindow, 0x100, 0, | |
429 | 32, 4, 4, 0x00000002, 0x0006, 0, | |
430 | 0, 0 }, | |
431 | { /* 0117 */ "a3", 468, xtRegisterTypeWindow, 0x100, 0, | |
432 | 32, 4, 4, 0x00000003, 0x0006, 0, | |
433 | 0, 0 }, | |
434 | { /* 0118 */ "a4", 472, xtRegisterTypeWindow, 0x100, 0, | |
435 | 32, 4, 4, 0x00000004, 0x0006, 0, | |
436 | 0, 0 }, | |
437 | { /* 0119 */ "a5", 476, xtRegisterTypeWindow, 0x100, 0, | |
438 | 32, 4, 4, 0x00000005, 0x0006, 0, | |
439 | 0, 0 }, | |
440 | { /* 0120 */ "a6", 480, xtRegisterTypeWindow, 0x100, 0, | |
441 | 32, 4, 4, 0x00000006, 0x0006, 0, | |
442 | 0, 0 }, | |
443 | { /* 0121 */ "a7", 484, xtRegisterTypeWindow, 0x100, 0, | |
444 | 32, 4, 4, 0x00000007, 0x0006, 0, | |
445 | 0, 0 }, | |
446 | { /* 0122 */ "a8", 488, xtRegisterTypeWindow, 0x100, 0, | |
447 | 32, 4, 4, 0x00000008, 0x0006, 0, | |
448 | 0, 0 }, | |
449 | { /* 0123 */ "a9", 492, xtRegisterTypeWindow, 0x100, 0, | |
450 | 32, 4, 4, 0x00000009, 0x0006, 0, | |
451 | 0, 0 }, | |
452 | { /* 0124 */ "a10", 496, xtRegisterTypeWindow, 0x100, 0, | |
453 | 32, 4, 4, 0x0000000a, 0x0006, 0, | |
454 | 0, 0 }, | |
455 | { /* 0125 */ "a11", 500, xtRegisterTypeWindow, 0x100, 0, | |
456 | 32, 4, 4, 0x0000000b, 0x0006, 0, | |
457 | 0, 0 }, | |
458 | { /* 0126 */ "a12", 504, xtRegisterTypeWindow, 0x100, 0, | |
459 | 32, 4, 4, 0x0000000c, 0x0006, 0, | |
460 | 0, 0 }, | |
461 | { /* 0127 */ "a13", 508, xtRegisterTypeWindow, 0x100, 0, | |
462 | 32, 4, 4, 0x0000000d, 0x0006, 0, | |
463 | 0, 0 }, | |
464 | { /* 0128 */ "a14", 512, xtRegisterTypeWindow, 0x100, 0, | |
465 | 32, 4, 4, 0x0000000e, 0x0006, 0, | |
466 | 0, 0 }, | |
467 | { /* 0129 */ "a15", 516, xtRegisterTypeWindow, 0x100, 0, | |
468 | 32, 4, 4, 0x0000000f, 0x0006, 0, | |
469 | 0, 0 }, | |
470 | { /* 0130 */ "psintlevel", 520, xtRegisterTypeMapped, 0x1010, 0, | |
471 | 4, 4, 4, 0x00002004, 0x0006, (xtensa_mask_t *) mask0, | |
472 | 0, 0 }, | |
473 | { /* 0131 */ "psum", 524, xtRegisterTypeMapped, 0x1010, 0, | |
474 | 1, 4, 4, 0x00002005, 0x0006, (xtensa_mask_t *) mask1, | |
475 | 0, 0 }, | |
476 | { /* 0132 */ "pswoe", 528, xtRegisterTypeMapped, 0x1010, 0, | |
477 | 1, 4, 4, 0x00002006, 0x0006, (xtensa_mask_t *) mask2, | |
478 | 0, 0 }, | |
479 | { /* 0133 */ "psring", 532, xtRegisterTypeMapped, 0x1010, 0, | |
480 | 2, 4, 4, 0x00002007, 0x0006, (xtensa_mask_t *) mask3, | |
481 | 0, 0 }, | |
482 | { /* 0134 */ "psexcm", 536, xtRegisterTypeMapped, 0x1010, 0, | |
483 | 1, 4, 4, 0x00002008, 0x0006, (xtensa_mask_t *) mask4, | |
484 | 0, 0 }, | |
485 | { /* 0135 */ "pscallinc", 540, xtRegisterTypeMapped, 0x1010, 0, | |
486 | 2, 4, 4, 0x00002009, 0x0006, (xtensa_mask_t *) mask5, | |
487 | 0, 0 }, | |
488 | { /* 0136 */ "psowb", 544, xtRegisterTypeMapped, 0x1010, 0, | |
489 | 4, 4, 4, 0x0000200a, 0x0006, (xtensa_mask_t *) mask6, | |
490 | 0, 0 }, | |
491 | { /* 0137 */ "litbaddr", 548, xtRegisterTypeMapped, 0x1010, 0, | |
492 | 20, 4, 4, 0x0000200b, 0x0006, (xtensa_mask_t *) mask7, | |
493 | 0, 0 }, | |
494 | { /* 0138 */ "litben", 552, xtRegisterTypeMapped, 0x1010, 0, | |
495 | 1, 4, 4, 0x0000200c, 0x0006, (xtensa_mask_t *) mask8, | |
496 | 0, 0 }, | |
497 | { /* 0139 */ "dbnum", 556, xtRegisterTypeMapped, 0x1010, 0, | |
498 | 4, 4, 4, 0x00002011, 0x0006, (xtensa_mask_t *) mask9, | |
499 | 0, 0 }, | |
500 | { /* 0140 */ "asid3", 560, xtRegisterTypeMapped, 0x1010, 0, | |
501 | 8, 4, 4, 0x00002012, 0x0006, (xtensa_mask_t *) mask10, | |
502 | 0, 0 }, | |
503 | { /* 0141 */ "asid2", 564, xtRegisterTypeMapped, 0x1010, 0, | |
504 | 8, 4, 4, 0x00002013, 0x0006, (xtensa_mask_t *) mask11, | |
505 | 0, 0 }, | |
506 | { /* 0142 */ "asid1", 568, xtRegisterTypeMapped, 0x1010, 0, | |
507 | 8, 4, 4, 0x00002014, 0x0006, (xtensa_mask_t *) mask12, | |
508 | 0, 0 }, | |
509 | { /* 0143 */ "instpgszid4", 572, xtRegisterTypeMapped, 0x1010, 0, | |
510 | 2, 4, 4, 0x00002015, 0x0006, (xtensa_mask_t *) mask13, | |
511 | 0, 0 }, | |
512 | { /* 0144 */ "datapgszid4", 576, xtRegisterTypeMapped, 0x1010, 0, | |
513 | 2, 4, 4, 0x00002016, 0x0006, (xtensa_mask_t *) mask14, | |
514 | 0, 0 }, | |
515 | { /* 0145 */ "ptbase", 580, xtRegisterTypeMapped, 0x1010, 0, | |
516 | 10, 4, 4, 0x00002017, 0x0006, (xtensa_mask_t *) mask15, | |
517 | 0, 0 }, | |
518 | }; | |
519 | ||
520 | ||
521 | struct gdbarch_tdep xtensa_tdep = | |
522 | { | |
523 | /* target_flags */ 0, | |
524 | /* spill_location */ -1, | |
525 | /* spill_size */ 0, | |
526 | /* unused */ 0, | |
527 | /* call_abi */ 0, | |
528 | /* debug_interrupt_level */ XCHAL_DEBUGLEVEL, | |
529 | /* icache_line_bytes */ XCHAL_ICACHE_LINESIZE, | |
530 | /* dcache_line_bytes */ XCHAL_DCACHE_LINESIZE, | |
531 | /* dcache_writeback */ XCHAL_DCACHE_IS_WRITEBACK, | |
532 | /* isa_use_windowed_registers */ XCHAL_HAVE_WINDOWED, | |
533 | /* isa_use_density_instructions */ XCHAL_HAVE_DENSITY, | |
534 | /* isa_use_exceptions */ 1, | |
535 | /* isa_use_ext_l32r */ 0 /* XCHAL_USE_ABSOLUTE_LITERALS */, | |
536 | /* isa_max_insn_size */ 3, | |
537 | /* debug_num_ibreaks */ XCHAL_NUM_IBREAK, | |
538 | /* debug_num_dbreaks */ XCHAL_NUM_DBREAK, | |
539 | /* rmap */ rmap, | |
540 | /* num_regs */ 114, | |
541 | /* num_pseudo_regs */ 32, | |
542 | /* num_aregs */ 64, | |
543 | /* num_contexts */ 0, | |
544 | /* ar_base */ 0, | |
545 | /* a0_base */ 114, | |
546 | /* wb_regnum */ 92, | |
547 | /* ws_regnum */ 93, | |
548 | /* pc_regnum */ 113, | |
549 | /* ps_regnum */ 96, | |
550 | /* lbeg_regnum */ 64, | |
551 | /* lend_regnum */ 65, | |
552 | /* lcount_regnum */ 66, | |
553 | /* sar_regnum */ 94, | |
554 | /* litbase_regnum */ 0, | |
555 | /* debugcause_regnum */ 108, | |
556 | /* exccause_regnum */ 89, | |
557 | /* excvaddr_regnum */ 91, | |
558 | /* max_register_raw_size */ 4, | |
559 | /* max_register_virtual_size */ 4, | |
560 | /* fp_layout */ 0, | |
561 | /* fp_layout_bytes */ 0, | |
562 | /* gregmap */ 0 | |
563 | }; |