[deliverable/binutils-gdb.git] / gdb / xtensa-tdep.h

/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.

   Copyright (C) 2003-2014 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */


/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
   whenever the "tdep" structure changes in an incompatible way.  */

#define XTENSA_TDEP_VERSION 0x60

/*  Xtensa register type.  */

typedef enum 
{
  xtRegisterTypeArRegfile = 1,	/* Register File ar0..arXX.  */
  xtRegisterTypeSpecialReg,	/* CPU states, such as PS, Booleans, (rsr).  */
  xtRegisterTypeUserReg,	/* User defined registers (rur).  */
  xtRegisterTypeTieRegfile,	/* User define register files.  */
  xtRegisterTypeTieState,	/* TIE States (mapped on user regs).  */
  xtRegisterTypeMapped,		/* Mapped on Special Registers.  */
  xtRegisterTypeUnmapped,	/* Special case of masked registers.  */
  xtRegisterTypeWindow,		/* Live window registers (a0..a15).  */
  xtRegisterTypeVirtual,	/* PC, FP.  */
  xtRegisterTypeUnknown
} xtensa_register_type_t;


/*  Xtensa register group.  */

#define XTENSA_MAX_COPROCESSOR	0x10  /* Number of Xtensa coprocessors.  */

typedef enum 
{
  xtRegisterGroupUnknown = 0,
  xtRegisterGroupRegFile	= 0x0001,    /* Register files without ARx.  */
  xtRegisterGroupAddrReg	= 0x0002,    /* ARx.  */
  xtRegisterGroupSpecialReg	= 0x0004,    /* SRxx.  */
  xtRegisterGroupUserReg	= 0x0008,    /* URxx.  */
  xtRegisterGroupState 		= 0x0010,    /* States.  */

  xtRegisterGroupGeneral	= 0x0100,    /* General registers, Ax, SR.  */
  xtRegisterGroupUser		= 0x0200,    /* User registers.  */
  xtRegisterGroupFloat		= 0x0400,    /* Floating Point.  */
  xtRegisterGroupVectra		= 0x0800,    /* Vectra.  */
  xtRegisterGroupSystem		= 0x1000,    /* System.  */

  xtRegisterGroupNCP	    = 0x00800000,    /* Non-CP non-base opt/custom.  */
  xtRegisterGroupCP0	    = 0x01000000,    /* CP0.  */
  xtRegisterGroupCP1	    = 0x02000000,    /* CP1.  */
  xtRegisterGroupCP2	    = 0x04000000,    /* CP2.  */
  xtRegisterGroupCP3	    = 0x08000000,    /* CP3.  */
  xtRegisterGroupCP4	    = 0x10000000,    /* CP4.  */
  xtRegisterGroupCP5	    = 0x20000000,    /* CP5.  */
  xtRegisterGroupCP6	    = 0x40000000,    /* CP6.  */
  xtRegisterGroupCP7	    = 0x80000000,    /* CP7.  */

} xtensa_register_group_t;


/*  Xtensa target flags.  */

typedef enum 
{
  xtTargetFlagsNonVisibleRegs	= 0x0001,
  xtTargetFlagsUseFetchStore	= 0x0002,
} xtensa_target_flags_t;


/* Xtensa ELF core file register set representation ('.reg' section).
   Copied from target-side ELF header <xtensa/elf.h>.  */

typedef uint32_t xtensa_elf_greg_t;

typedef struct
{
  xtensa_elf_greg_t pc;
  xtensa_elf_greg_t ps;
  xtensa_elf_greg_t lbeg;
  xtensa_elf_greg_t lend;
  xtensa_elf_greg_t lcount;
  xtensa_elf_greg_t sar;
  xtensa_elf_greg_t windowstart;
  xtensa_elf_greg_t windowbase;
  xtensa_elf_greg_t reserved[8+48];
  xtensa_elf_greg_t ar[64];
} xtensa_elf_gregset_t;

#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
			  / sizeof (xtensa_elf_greg_t))

/*  Mask.  */

typedef struct 
{
  int reg_num;
  int bit_start;
  int bit_size;
} xtensa_reg_mask_t;

typedef struct 
{
  int count;
  xtensa_reg_mask_t *mask;
} xtensa_mask_t;


/*  Xtensa register representation.  */

typedef struct 
{
  char* name;             	/* Register name.  */
  int offset;             	/* Offset.  */
  xtensa_register_type_t type;  /* Register type.  */
  xtensa_register_group_t group;/* Register group.  */
  struct type* ctype;		/* C-type.  */
  int bit_size;  		/* The actual bit size in the target.  */
  int byte_size;          	/* Actual space allocated in registers[].  */
  int align;			/* Alignment for this register.  */

  unsigned int target_number;	/* Register target number.  */

  int flags;			/* Flags.  */
  int coprocessor;		/* Coprocessor num, -1 for non-CP, else -2.  */

  const xtensa_mask_t *mask;	/* Register is a compilation of other regs.  */
  const char *fetch;		/* Instruction sequence to fetch register.  */
  const char *store;		/* Instruction sequence to store register.  */
} xtensa_register_t;

/*  For xtensa-config.c to expand to the structure above.  */
#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
	{#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \
	 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},

#define XTENSA_REGISTER_FLAGS_PRIVILEGED	0x0001
#define XTENSA_REGISTER_FLAGS_READABLE		0x0002
#define XTENSA_REGISTER_FLAGS_WRITABLE		0x0004
#define XTENSA_REGISTER_FLAGS_VOLATILE		0x0008

/*  Call-ABI for stack frame.  */

typedef enum 
{
  CallAbiDefault = 0,		/* Any 'callX' instructions; default stack.  */
  CallAbiCall0Only,		/* Only 'call0' instructions; flat stack.  */
} call_abi_t;


/*  Xtensa-specific target dependencies.  */

struct gdbarch_tdep
{
  unsigned int target_flags;

  /* Spill location for TIE register files under ocd.  */

  unsigned int spill_location;
  unsigned int spill_size;

  char *unused;				/* Placeholder for compatibility.  */
  call_abi_t call_abi;			/* Calling convention.  */

  /* CPU configuration.  */

  unsigned int debug_interrupt_level;

  unsigned int icache_line_bytes;
  unsigned int dcache_line_bytes;
  unsigned int dcache_writeback;

  unsigned int isa_use_windowed_registers;
  unsigned int isa_use_density_instructions;
  unsigned int isa_use_exceptions;
  unsigned int isa_use_ext_l32r;
  unsigned int isa_max_insn_size;	/* Maximum instruction length.  */
  unsigned int debug_num_ibreaks;	/* Number of IBREAKs.  */
  unsigned int debug_num_dbreaks;

  /* Register map.  */

  xtensa_register_t* regmap;

  unsigned int num_regs;	/* Number of registers in register map.  */
  unsigned int num_nopriv_regs;	/* Number of non-privileged registers.  */
  unsigned int num_pseudo_regs;	/* Number of pseudo registers.  */
  unsigned int num_aregs;	/* Size of register file.  */
  unsigned int num_contexts;

  int ar_base;			/* Register number for AR0.  */
  int a0_base;			/* Register number for A0 (pseudo).  */
  int wb_regnum;		/* Register number for WB.  */
  int ws_regnum;		/* Register number for WS.  */
  int pc_regnum;		/* Register number for PC.  */
  int ps_regnum;		/* Register number for PS.  */
  int lbeg_regnum;		/* Register numbers for count regs.  */
  int lend_regnum;
  int lcount_regnum;
  int sar_regnum;		/* Register number of SAR.  */
  int litbase_regnum;		/* Register number of LITBASE.  */

  int interrupt_regnum;		/* Register number for interrupt.  */
  int interrupt2_regnum;	/* Register number for interrupt2.  */
  int cpenable_regnum;		/* Register number for cpenable.  */
  int debugcause_regnum;	/* Register number for debugcause.  */
  int exccause_regnum;		/* Register number for exccause.  */
  int excvaddr_regnum;		/* Register number for excvaddr.  */

  int max_register_raw_size;
  int max_register_virtual_size;
  unsigned long *fp_layout;	/* Layout of custom/TIE regs in 'FP' area.  */
  unsigned int fp_layout_bytes;	/* Size of layout information (in bytes).  */
  unsigned long *gregmap;

  /* Cached register types.  */
  struct ctype_cache
    {
      struct ctype_cache *next;
      int size;
      struct type *virtual_type;
    } *type_entries;
};

/* Macro to instantiate a gdbarch_tdep structure.  */

#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz)		\
	{							\
	  .target_flags = 0,					\
	  .spill_location = -1,					\
	  .spill_size = (spillsz),				\
	  .unused = 0,						\
	  .call_abi = 0,					\
	  .debug_interrupt_level = XCHAL_DEBUGLEVEL,		\
	  .icache_line_bytes = XCHAL_ICACHE_LINESIZE,		\
	  .dcache_line_bytes = XCHAL_DCACHE_LINESIZE,		\
	  .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK,	\
	  .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0),	\
	  .isa_use_density_instructions = XCHAL_HAVE_DENSITY,	\
	  .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS,		\
	  .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS,	\
	  .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE,	\
	  .debug_num_ibreaks = XCHAL_NUM_IBREAK,		\
	  .debug_num_dbreaks = XCHAL_NUM_DBREAK,		\
	  .regmap = rmap,			\
	  .num_regs = 0,			\
	  .num_nopriv_regs = 0,			\
	  .num_pseudo_regs = 0,			\
	  .num_aregs = XCHAL_NUM_AREGS,		\
	  .num_contexts = XCHAL_NUM_CONTEXTS,	\
	  .ar_base = -1,			\
	  .a0_base = -1,			\
	  .wb_regnum = -1,			\
	  .ws_regnum = -1,			\
	  .pc_regnum = -1,			\
	  .ps_regnum = -1,			\
	  .lbeg_regnum = -1,			\
	  .lend_regnum = -1,			\
	  .lcount_regnum = -1,			\
	  .sar_regnum = -1,			\
	  .litbase_regnum = -1,			\
	  .interrupt_regnum = -1,		\
	  .interrupt2_regnum = -1,		\
	  .cpenable_regnum = -1,		\
	  .debugcause_regnum = -1,		\
	  .exccause_regnum = -1,		\
	  .excvaddr_regnum = -1,		\
	  .max_register_raw_size = 0,		\
	  .max_register_virtual_size = 0,	\
	  .fp_layout = 0,			\
	  .fp_layout_bytes = 0,			\
	  .gregmap = 0,				\
	}
#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size)	\
	struct gdbarch_tdep xtensa_tdep = \
	  XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);

#ifndef XCHAL_NUM_CONTEXTS
#define XCHAL_NUM_CONTEXTS	0
#endif
#ifndef XCHAL_HAVE_EXCEPTIONS
#define XCHAL_HAVE_EXCEPTIONS	1
#endif
#define WB_SHIFT	  2

/* We assign fixed numbers to the registers of the "current" window 
   (i.e., relative to WB).  The registers get remapped via the reg_map 
   data structure to their corresponding register in the AR register 
   file (see xtensa-tdep.c).  */
Commit	Line	Data
ca3bf3bd DJ	1	/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
ca3bf3bd DJ	2
ecd75fc8	3	Copyright (C) 2003-2014 Free Software Foundation, Inc.
ca3bf3bd DJ	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
ca3bf3bd DJ	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
ca3bf3bd DJ	19
	20
	21	/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
	22	whenever the "tdep" structure changes in an incompatible way. */
	23
	24	#define XTENSA_TDEP_VERSION 0x60
	25
	26	/* Xtensa register type. */
	27
	28	typedef enum
	29	{
	30	xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
	31	xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
	32	xtRegisterTypeUserReg, /* User defined registers (rur). */
	33	xtRegisterTypeTieRegfile, /* User define register files. */
	34	xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
	35	xtRegisterTypeMapped, /* Mapped on Special Registers. */
	36	xtRegisterTypeUnmapped, /* Special case of masked registers. */
	37	xtRegisterTypeWindow, /* Live window registers (a0..a15). */
	38	xtRegisterTypeVirtual, /* PC, FP. */
	39	xtRegisterTypeUnknown
	40	} xtensa_register_type_t;
	41
	42
	43	/* Xtensa register group. */
	44
4d1acb11	45	#define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */
7b871568	46
ca3bf3bd DJ	47	typedef enum
	48	{
	49	xtRegisterGroupUnknown = 0,
	50	xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */
	51	xtRegisterGroupAddrReg = 0x0002, /* ARx. */
	52	xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */
	53	xtRegisterGroupUserReg = 0x0008, /* URxx. */
	54	xtRegisterGroupState = 0x0010, /* States. */
	55
	56	xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */
	57	xtRegisterGroupUser = 0x0200, /* User registers. */
	58	xtRegisterGroupFloat = 0x0400, /* Floating Point. */
	59	xtRegisterGroupVectra = 0x0800, /* Vectra. */
	60	xtRegisterGroupSystem = 0x1000, /* System. */
7b871568	61
94a0e877	62	xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */
7b871568 MG	63	xtRegisterGroupCP0 = 0x01000000, /* CP0. */
	64	xtRegisterGroupCP1 = 0x02000000, /* CP1. */
	65	xtRegisterGroupCP2 = 0x04000000, /* CP2. */
	66	xtRegisterGroupCP3 = 0x08000000, /* CP3. */
	67	xtRegisterGroupCP4 = 0x10000000, /* CP4. */
	68	xtRegisterGroupCP5 = 0x20000000, /* CP5. */
	69	xtRegisterGroupCP6 = 0x40000000, /* CP6. */
	70	xtRegisterGroupCP7 = 0x80000000, /* CP7. */
	71
ca3bf3bd DJ	72	} xtensa_register_group_t;
	73
	74
	75	/* Xtensa target flags. */
	76
	77	typedef enum
	78	{
	79	xtTargetFlagsNonVisibleRegs = 0x0001,
	80	xtTargetFlagsUseFetchStore = 0x0002,
	81	} xtensa_target_flags_t;
	82
	83
581e13c1	84	/* Xtensa ELF core file register set representation ('.reg' section).
ca3bf3bd DJ	85	Copied from target-side ELF header <xtensa/elf.h>. */
ca3bf3bd DJ	86
54bff650	87	typedef uint32_t xtensa_elf_greg_t;
ca3bf3bd DJ	88
	89	typedef struct
	90	{
ca3bf3bd DJ	91	xtensa_elf_greg_t pc;
ca3bf3bd DJ	92	xtensa_elf_greg_t ps;
ca3bf3bd DJ	93	xtensa_elf_greg_t lbeg;
	94	xtensa_elf_greg_t lend;
	95	xtensa_elf_greg_t lcount;
	96	xtensa_elf_greg_t sar;
94a0e877 MG	97	xtensa_elf_greg_t windowstart;
	98	xtensa_elf_greg_t windowbase;
	99	xtensa_elf_greg_t reserved[8+48];
	100	xtensa_elf_greg_t ar[64];
ca3bf3bd DJ	101	} xtensa_elf_gregset_t;
ca3bf3bd DJ	102
94a0e877 MG	103	#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
94a0e877 MG	104	/ sizeof (xtensa_elf_greg_t))
ca3bf3bd DJ	105
	106	/* Mask. */
	107
ff7a4c00 MG	108	typedef struct
	109	{
	110	int reg_num;
	111	int bit_start;
	112	int bit_size;
	113	} xtensa_reg_mask_t;
	114
ca3bf3bd DJ	115	typedef struct
	116	{
	117	int count;
ff7a4c00	118	xtensa_reg_mask_t *mask;
ca3bf3bd DJ	119	} xtensa_mask_t;
	120
	121
	122	/* Xtensa register representation. */
	123
	124	typedef struct
	125	{
	126	char* name; /* Register name. */
	127	int offset; /* Offset. */
	128	xtensa_register_type_t type; /* Register type. */
	129	xtensa_register_group_t group;/* Register group. */
	130	struct type* ctype; /* C-type. */
	131	int bit_size; /* The actual bit size in the target. */
	132	int byte_size; /* Actual space allocated in registers[]. */
	133	int align; /* Alignment for this register. */
	134
	135	unsigned int target_number; /* Register target number. */
	136
	137	int flags; /* Flags. */
94a0e877	138	int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */
ca3bf3bd DJ	139
	140	const xtensa_mask_t mask; / Register is a compilation of other regs. */
	141	const char fetch; / Instruction sequence to fetch register. */
	142	const char store; / Instruction sequence to store register. */
	143	} xtensa_register_t;
	144
94a0e877 MG	145	/* For xtensa-config.c to expand to the structure above. */
94a0e877 MG	146	#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
581e13c1	147	{#name, ofs, ty, ((gr) \| ((xtRegisterGroupNCP >> 2) << (cp + 2))), \
94a0e877 MG	148	ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
94a0e877 MG	149	#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
ca3bf3bd	150
94a0e877	151	#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
ca3bf3bd DJ	152	#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
	153	#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
	154	#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
	155
ca3bf3bd DJ	156	/* Call-ABI for stack frame. */
	157
	158	typedef enum
	159	{
	160	CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */
	161	CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */
	162	} call_abi_t;
	163
	164
	165	/* Xtensa-specific target dependencies. */
	166
	167	struct gdbarch_tdep
	168	{
	169	unsigned int target_flags;
	170
	171	/* Spill location for TIE register files under ocd. */
	172
	173	unsigned int spill_location;
	174	unsigned int spill_size;
	175
	176	char unused; / Placeholder for compatibility. */
	177	call_abi_t call_abi; /* Calling convention. */
	178
	179	/* CPU configuration. */
	180
	181	unsigned int debug_interrupt_level;
	182
	183	unsigned int icache_line_bytes;
	184	unsigned int dcache_line_bytes;
	185	unsigned int dcache_writeback;
	186
	187	unsigned int isa_use_windowed_registers;
	188	unsigned int isa_use_density_instructions;
	189	unsigned int isa_use_exceptions;
	190	unsigned int isa_use_ext_l32r;
	191	unsigned int isa_max_insn_size; /* Maximum instruction length. */
	192	unsigned int debug_num_ibreaks; /* Number of IBREAKs. */
	193	unsigned int debug_num_dbreaks;
	194
	195	/* Register map. */
	196
	197	xtensa_register_t* regmap;
	198
94a0e877 MG	199	unsigned int num_regs; /* Number of registers in register map. */
94a0e877 MG	200	unsigned int num_nopriv_regs; /* Number of non-privileged registers. */
ca3bf3bd DJ	201	unsigned int num_pseudo_regs; /* Number of pseudo registers. */
	202	unsigned int num_aregs; /* Size of register file. */
	203	unsigned int num_contexts;
	204
	205	int ar_base; /* Register number for AR0. */
	206	int a0_base; /* Register number for A0 (pseudo). */
	207	int wb_regnum; /* Register number for WB. */
	208	int ws_regnum; /* Register number for WS. */
	209	int pc_regnum; /* Register number for PC. */
	210	int ps_regnum; /* Register number for PS. */
	211	int lbeg_regnum; /* Register numbers for count regs. */
	212	int lend_regnum;
	213	int lcount_regnum;
	214	int sar_regnum; /* Register number of SAR. */
	215	int litbase_regnum; /* Register number of LITBASE. */
	216
	217	int interrupt_regnum; /* Register number for interrupt. */
	218	int interrupt2_regnum; /* Register number for interrupt2. */
	219	int cpenable_regnum; /* Register number for cpenable. */
	220	int debugcause_regnum; /* Register number for debugcause. */
	221	int exccause_regnum; /* Register number for exccause. */
	222	int excvaddr_regnum; /* Register number for excvaddr. */
	223
	224	int max_register_raw_size;
	225	int max_register_virtual_size;
	226	unsigned long fp_layout; / Layout of custom/TIE regs in 'FP' area. */
	227	unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */
	228	unsigned long *gregmap;
df4df182 UW	229
	230	/* Cached register types. */
	231	struct ctype_cache
	232	{
	233	struct ctype_cache *next;
	234	int size;
	235	struct type *virtual_type;
	236	} *type_entries;
ca3bf3bd DJ	237	};
ca3bf3bd DJ	238
94a0e877 MG	239	/* Macro to instantiate a gdbarch_tdep structure. */
	240
	241	#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \
	242	{ \
	243	.target_flags = 0, \
	244	.spill_location = -1, \
	245	.spill_size = (spillsz), \
	246	.unused = 0, \
	247	.call_abi = 0, \
	248	.debug_interrupt_level = XCHAL_DEBUGLEVEL, \
	249	.icache_line_bytes = XCHAL_ICACHE_LINESIZE, \
	250	.dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
	251	.dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \
	252	.isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
	253	.isa_use_density_instructions = XCHAL_HAVE_DENSITY, \
	254	.isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \
	255	.isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \
	256	.isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
	257	.debug_num_ibreaks = XCHAL_NUM_IBREAK, \
	258	.debug_num_dbreaks = XCHAL_NUM_DBREAK, \
	259	.regmap = rmap, \
	260	.num_regs = 0, \
	261	.num_nopriv_regs = 0, \
	262	.num_pseudo_regs = 0, \
	263	.num_aregs = XCHAL_NUM_AREGS, \
	264	.num_contexts = XCHAL_NUM_CONTEXTS, \
	265	.ar_base = -1, \
	266	.a0_base = -1, \
	267	.wb_regnum = -1, \
	268	.ws_regnum = -1, \
	269	.pc_regnum = -1, \
	270	.ps_regnum = -1, \
	271	.lbeg_regnum = -1, \
	272	.lend_regnum = -1, \
	273	.lcount_regnum = -1, \
	274	.sar_regnum = -1, \
	275	.litbase_regnum = -1, \
	276	.interrupt_regnum = -1, \
	277	.interrupt2_regnum = -1, \
	278	.cpenable_regnum = -1, \
	279	.debugcause_regnum = -1, \
	280	.exccause_regnum = -1, \
	281	.excvaddr_regnum = -1, \
	282	.max_register_raw_size = 0, \
	283	.max_register_virtual_size = 0, \
	284	.fp_layout = 0, \
	285	.fp_layout_bytes = 0, \
	286	.gregmap = 0, \
	287	}
	288	#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \
	289	struct gdbarch_tdep xtensa_tdep = \
	290	XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
	291
	292	#ifndef XCHAL_NUM_CONTEXTS
	293	#define XCHAL_NUM_CONTEXTS 0
	294	#endif
	295	#ifndef XCHAL_HAVE_EXCEPTIONS
	296	#define XCHAL_HAVE_EXCEPTIONS 1
	297	#endif
ca3bf3bd DJ	298	#define WB_SHIFT 2
	299
	300	/* We assign fixed numbers to the registers of the "current" window
	301	(i.e., relative to WB). The registers get remapped via the reg_map
	302	data structure to their corresponding register in the AR register
	303	file (see xtensa-tdep.c). */
	304