[deliverable/binutils-gdb.git] / gdb / xtensa-tdep.h

/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.

   Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */


/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
   whenever the "tdep" structure changes in an incompatible way.  */

#define XTENSA_TDEP_VERSION 0x60

/*  Xtensa register type.  */

typedef enum 
{
  xtRegisterTypeArRegfile = 1,	/* Register File ar0..arXX.  */
  xtRegisterTypeSpecialReg,	/* CPU states, such as PS, Booleans, (rsr).  */
  xtRegisterTypeUserReg,	/* User defined registers (rur).  */
  xtRegisterTypeTieRegfile,	/* User define register files.  */
  xtRegisterTypeTieState,	/* TIE States (mapped on user regs).  */
  xtRegisterTypeMapped,		/* Mapped on Special Registers.  */
  xtRegisterTypeUnmapped,	/* Special case of masked registers.  */
  xtRegisterTypeWindow,		/* Live window registers (a0..a15).  */
  xtRegisterTypeVirtual,	/* PC, FP.  */
  xtRegisterTypeUnknown
} xtensa_register_type_t;


/*  Xtensa register group.  */

#define XTENSA_MAX_COPROCESSOR	0x08  /* Number of Xtensa coprocessors.  */

typedef enum 
{
  xtRegisterGroupUnknown = 0,
  xtRegisterGroupRegFile	= 0x0001,    /* Register files without ARx.  */
  xtRegisterGroupAddrReg	= 0x0002,    /* ARx.  */
  xtRegisterGroupSpecialReg	= 0x0004,    /* SRxx.  */
  xtRegisterGroupUserReg	= 0x0008,    /* URxx.  */
  xtRegisterGroupState 		= 0x0010,    /* States.  */

  xtRegisterGroupGeneral	= 0x0100,    /* General registers, Ax, SR.  */
  xtRegisterGroupUser		= 0x0200,    /* User registers.  */
  xtRegisterGroupFloat		= 0x0400,    /* Floating Point.  */
  xtRegisterGroupVectra		= 0x0800,    /* Vectra.  */
  xtRegisterGroupSystem		= 0x1000,    /* System.  */

  xtRegisterGroupNCP	    = 0x00800000,    /* Non-CP non-base opt/custom.  */
  xtRegisterGroupCP0	    = 0x01000000,    /* CP0.  */
  xtRegisterGroupCP1	    = 0x02000000,    /* CP1.  */
  xtRegisterGroupCP2	    = 0x04000000,    /* CP2.  */
  xtRegisterGroupCP3	    = 0x08000000,    /* CP3.  */
  xtRegisterGroupCP4	    = 0x10000000,    /* CP4.  */
  xtRegisterGroupCP5	    = 0x20000000,    /* CP5.  */
  xtRegisterGroupCP6	    = 0x40000000,    /* CP6.  */
  xtRegisterGroupCP7	    = 0x80000000,    /* CP7.  */

} xtensa_register_group_t;


/*  Xtensa target flags.  */

typedef enum 
{
  xtTargetFlagsNonVisibleRegs	= 0x0001,
  xtTargetFlagsUseFetchStore	= 0x0002,
} xtensa_target_flags_t;


/* Xtensa ELF core file register set representation ('.reg' section). 
   Copied from target-side ELF header <xtensa/elf.h>.  */

typedef unsigned long xtensa_elf_greg_t;

typedef struct
{
  xtensa_elf_greg_t pc;
  xtensa_elf_greg_t ps;
  xtensa_elf_greg_t lbeg;
  xtensa_elf_greg_t lend;
  xtensa_elf_greg_t lcount;
  xtensa_elf_greg_t sar;
  xtensa_elf_greg_t windowstart;
  xtensa_elf_greg_t windowbase;
  xtensa_elf_greg_t reserved[8+48];
  xtensa_elf_greg_t ar[64];
} xtensa_elf_gregset_t;

#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
			  / sizeof (xtensa_elf_greg_t))

/*  Mask.  */

typedef struct 
{
  int reg_num;
  int bit_start;
  int bit_size;
} xtensa_reg_mask_t;

typedef struct 
{
  int count;
  xtensa_reg_mask_t *mask;
} xtensa_mask_t;


/*  Xtensa register representation.  */

typedef struct 
{
  char* name;             	/* Register name.  */
  int offset;             	/* Offset.  */
  xtensa_register_type_t type;  /* Register type.  */
  xtensa_register_group_t group;/* Register group.  */
  struct type* ctype;		/* C-type.  */
  int bit_size;  		/* The actual bit size in the target.  */
  int byte_size;          	/* Actual space allocated in registers[].  */
  int align;			/* Alignment for this register.  */

  unsigned int target_number;	/* Register target number.  */

  int flags;			/* Flags.  */
  int coprocessor;		/* Coprocessor num, -1 for non-CP, else -2.  */

  const xtensa_mask_t *mask;	/* Register is a compilation of other regs.  */
  const char *fetch;		/* Instruction sequence to fetch register.  */
  const char *store;		/* Instruction sequence to store register.  */
} xtensa_register_t;

/*  For xtensa-config.c to expand to the structure above.  */
#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
	{#name, ofs, ty, ((gr)|((xtRegisterGroupNCP>>2)<<(cp+2))), \
	 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},

#define XTENSA_REGISTER_FLAGS_PRIVILEGED	0x0001
#define XTENSA_REGISTER_FLAGS_READABLE		0x0002
#define XTENSA_REGISTER_FLAGS_WRITABLE		0x0004
#define XTENSA_REGISTER_FLAGS_VOLATILE		0x0008

/*  Call-ABI for stack frame.  */

typedef enum 
{
  CallAbiDefault = 0,		/* Any 'callX' instructions; default stack.  */
  CallAbiCall0Only,		/* Only 'call0' instructions; flat stack.  */
} call_abi_t;


/*  Xtensa-specific target dependencies.  */

struct gdbarch_tdep
{
  unsigned int target_flags;

  /* Spill location for TIE register files under ocd.  */

  unsigned int spill_location;
  unsigned int spill_size;

  char *unused;				/* Placeholder for compatibility.  */
  call_abi_t call_abi;			/* Calling convention.  */

  /* CPU configuration.  */

  unsigned int debug_interrupt_level;

  unsigned int icache_line_bytes;
  unsigned int dcache_line_bytes;
  unsigned int dcache_writeback;

  unsigned int isa_use_windowed_registers;
  unsigned int isa_use_density_instructions;
  unsigned int isa_use_exceptions;
  unsigned int isa_use_ext_l32r;
  unsigned int isa_max_insn_size;	/* Maximum instruction length.  */
  unsigned int debug_num_ibreaks;	/* Number of IBREAKs.  */
  unsigned int debug_num_dbreaks;

  /* Register map.  */

  xtensa_register_t* regmap;

  unsigned int num_regs;	/* Number of registers in register map.  */
  unsigned int num_nopriv_regs;	/* Number of non-privileged registers.  */
  unsigned int num_pseudo_regs;	/* Number of pseudo registers.  */
  unsigned int num_aregs;	/* Size of register file.  */
  unsigned int num_contexts;

  int ar_base;			/* Register number for AR0.  */
  int a0_base;			/* Register number for A0 (pseudo).  */
  int wb_regnum;		/* Register number for WB.  */
  int ws_regnum;		/* Register number for WS.  */
  int pc_regnum;		/* Register number for PC.  */
  int ps_regnum;		/* Register number for PS.  */
  int lbeg_regnum;		/* Register numbers for count regs.  */
  int lend_regnum;
  int lcount_regnum;
  int sar_regnum;		/* Register number of SAR.  */
  int litbase_regnum;		/* Register number of LITBASE.  */

  int interrupt_regnum;		/* Register number for interrupt.  */
  int interrupt2_regnum;	/* Register number for interrupt2.  */
  int cpenable_regnum;		/* Register number for cpenable.  */
  int debugcause_regnum;	/* Register number for debugcause.  */
  int exccause_regnum;		/* Register number for exccause.  */
  int excvaddr_regnum;		/* Register number for excvaddr.  */

  int max_register_raw_size;
  int max_register_virtual_size;
  unsigned long *fp_layout;	/* Layout of custom/TIE regs in 'FP' area.  */
  unsigned int fp_layout_bytes;	/* Size of layout information (in bytes).  */
  unsigned long *gregmap;

  /* Cached register types.  */
  struct ctype_cache
    {
      struct ctype_cache *next;
      int size;
      struct type *virtual_type;
    } *type_entries;
};

/* Macro to instantiate a gdbarch_tdep structure.  */

#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz)		\
	{							\
	  .target_flags = 0,					\
	  .spill_location = -1,					\
	  .spill_size = (spillsz),				\
	  .unused = 0,						\
	  .call_abi = 0,					\
	  .debug_interrupt_level = XCHAL_DEBUGLEVEL,		\
	  .icache_line_bytes = XCHAL_ICACHE_LINESIZE,		\
	  .dcache_line_bytes = XCHAL_DCACHE_LINESIZE,		\
	  .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK,	\
	  .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0),	\
	  .isa_use_density_instructions = XCHAL_HAVE_DENSITY,	\
	  .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS,		\
	  .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS,	\
	  .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE,	\
	  .debug_num_ibreaks = XCHAL_NUM_IBREAK,		\
	  .debug_num_dbreaks = XCHAL_NUM_DBREAK,		\
	  .regmap = rmap,			\
	  .num_regs = 0,			\
	  .num_nopriv_regs = 0,			\
	  .num_pseudo_regs = 0,			\
	  .num_aregs = XCHAL_NUM_AREGS,		\
	  .num_contexts = XCHAL_NUM_CONTEXTS,	\
	  .ar_base = -1,			\
	  .a0_base = -1,			\
	  .wb_regnum = -1,			\
	  .ws_regnum = -1,			\
	  .pc_regnum = -1,			\
	  .ps_regnum = -1,			\
	  .lbeg_regnum = -1,			\
	  .lend_regnum = -1,			\
	  .lcount_regnum = -1,			\
	  .sar_regnum = -1,			\
	  .litbase_regnum = -1,			\
	  .interrupt_regnum = -1,		\
	  .interrupt2_regnum = -1,		\
	  .cpenable_regnum = -1,		\
	  .debugcause_regnum = -1,		\
	  .exccause_regnum = -1,		\
	  .excvaddr_regnum = -1,		\
	  .max_register_raw_size = 0,		\
	  .max_register_virtual_size = 0,	\
	  .fp_layout = 0,			\
	  .fp_layout_bytes = 0,			\
	  .gregmap = 0,				\
	}
#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size)	\
	struct gdbarch_tdep xtensa_tdep = \
	  XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);

#ifndef XCHAL_NUM_CONTEXTS
#define XCHAL_NUM_CONTEXTS	0
#endif
#ifndef XCHAL_HAVE_EXCEPTIONS
#define XCHAL_HAVE_EXCEPTIONS	1
#endif
#define WB_SHIFT	  2

/* We assign fixed numbers to the registers of the "current" window 
   (i.e., relative to WB).  The registers get remapped via the reg_map 
   data structure to their corresponding register in the AR register 
   file (see xtensa-tdep.c).  */
Commit	Line	Data
ca3bf3bd DJ	1	/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
ca3bf3bd DJ	2
4c38e0a4	3	Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010
0fb0cc75	4	Free Software Foundation, Inc.
ca3bf3bd DJ	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
a9762ec7	10	the Free Software Foundation; either version 3 of the License, or
ca3bf3bd DJ	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
a9762ec7	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
ca3bf3bd DJ	20
	21
	22	/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
	23	whenever the "tdep" structure changes in an incompatible way. */
	24
	25	#define XTENSA_TDEP_VERSION 0x60
	26
	27	/* Xtensa register type. */
	28
	29	typedef enum
	30	{
	31	xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
	32	xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
	33	xtRegisterTypeUserReg, /* User defined registers (rur). */
	34	xtRegisterTypeTieRegfile, /* User define register files. */
	35	xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
	36	xtRegisterTypeMapped, /* Mapped on Special Registers. */
	37	xtRegisterTypeUnmapped, /* Special case of masked registers. */
	38	xtRegisterTypeWindow, /* Live window registers (a0..a15). */
	39	xtRegisterTypeVirtual, /* PC, FP. */
	40	xtRegisterTypeUnknown
	41	} xtensa_register_type_t;
	42
	43
	44	/* Xtensa register group. */
	45
7b871568 MG	46	#define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */
7b871568 MG	47
ca3bf3bd DJ	48	typedef enum
	49	{
	50	xtRegisterGroupUnknown = 0,
	51	xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */
	52	xtRegisterGroupAddrReg = 0x0002, /* ARx. */
	53	xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */
	54	xtRegisterGroupUserReg = 0x0008, /* URxx. */
	55	xtRegisterGroupState = 0x0010, /* States. */
	56
	57	xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */
	58	xtRegisterGroupUser = 0x0200, /* User registers. */
	59	xtRegisterGroupFloat = 0x0400, /* Floating Point. */
	60	xtRegisterGroupVectra = 0x0800, /* Vectra. */
	61	xtRegisterGroupSystem = 0x1000, /* System. */
7b871568	62
94a0e877	63	xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */
7b871568 MG	64	xtRegisterGroupCP0 = 0x01000000, /* CP0. */
	65	xtRegisterGroupCP1 = 0x02000000, /* CP1. */
	66	xtRegisterGroupCP2 = 0x04000000, /* CP2. */
	67	xtRegisterGroupCP3 = 0x08000000, /* CP3. */
	68	xtRegisterGroupCP4 = 0x10000000, /* CP4. */
	69	xtRegisterGroupCP5 = 0x20000000, /* CP5. */
	70	xtRegisterGroupCP6 = 0x40000000, /* CP6. */
	71	xtRegisterGroupCP7 = 0x80000000, /* CP7. */
	72
ca3bf3bd DJ	73	} xtensa_register_group_t;
	74
	75
	76	/* Xtensa target flags. */
	77
	78	typedef enum
	79	{
	80	xtTargetFlagsNonVisibleRegs = 0x0001,
	81	xtTargetFlagsUseFetchStore = 0x0002,
	82	} xtensa_target_flags_t;
	83
	84
	85	/* Xtensa ELF core file register set representation ('.reg' section).
	86	Copied from target-side ELF header <xtensa/elf.h>. */
	87
	88	typedef unsigned long xtensa_elf_greg_t;
	89
	90	typedef struct
	91	{
ca3bf3bd DJ	92	xtensa_elf_greg_t pc;
ca3bf3bd DJ	93	xtensa_elf_greg_t ps;
ca3bf3bd DJ	94	xtensa_elf_greg_t lbeg;
	95	xtensa_elf_greg_t lend;
	96	xtensa_elf_greg_t lcount;
	97	xtensa_elf_greg_t sar;
94a0e877 MG	98	xtensa_elf_greg_t windowstart;
	99	xtensa_elf_greg_t windowbase;
	100	xtensa_elf_greg_t reserved[8+48];
	101	xtensa_elf_greg_t ar[64];
ca3bf3bd DJ	102	} xtensa_elf_gregset_t;
ca3bf3bd DJ	103
94a0e877 MG	104	#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
94a0e877 MG	105	/ sizeof (xtensa_elf_greg_t))
ca3bf3bd DJ	106
	107	/* Mask. */
	108
ff7a4c00 MG	109	typedef struct
	110	{
	111	int reg_num;
	112	int bit_start;
	113	int bit_size;
	114	} xtensa_reg_mask_t;
	115
ca3bf3bd DJ	116	typedef struct
	117	{
	118	int count;
ff7a4c00	119	xtensa_reg_mask_t *mask;
ca3bf3bd DJ	120	} xtensa_mask_t;
	121
	122
	123	/* Xtensa register representation. */
	124
	125	typedef struct
	126	{
	127	char* name; /* Register name. */
	128	int offset; /* Offset. */
	129	xtensa_register_type_t type; /* Register type. */
	130	xtensa_register_group_t group;/* Register group. */
	131	struct type* ctype; /* C-type. */
	132	int bit_size; /* The actual bit size in the target. */
	133	int byte_size; /* Actual space allocated in registers[]. */
	134	int align; /* Alignment for this register. */
	135
	136	unsigned int target_number; /* Register target number. */
	137
	138	int flags; /* Flags. */
94a0e877	139	int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */
ca3bf3bd DJ	140
	141	const xtensa_mask_t mask; / Register is a compilation of other regs. */
	142	const char fetch; / Instruction sequence to fetch register. */
	143	const char store; / Instruction sequence to store register. */
	144	} xtensa_register_t;
	145
94a0e877 MG	146	/* For xtensa-config.c to expand to the structure above. */
	147	#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
	148	{#name, ofs, ty, ((gr)\|((xtRegisterGroupNCP>>2)<<(cp+2))), \
	149	ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
	150	#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
ca3bf3bd	151
94a0e877	152	#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
ca3bf3bd DJ	153	#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
	154	#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
	155	#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
	156
ca3bf3bd DJ	157	/* Call-ABI for stack frame. */
	158
	159	typedef enum
	160	{
	161	CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */
	162	CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */
	163	} call_abi_t;
	164
	165
	166	/* Xtensa-specific target dependencies. */
	167
	168	struct gdbarch_tdep
	169	{
	170	unsigned int target_flags;
	171
	172	/* Spill location for TIE register files under ocd. */
	173
	174	unsigned int spill_location;
	175	unsigned int spill_size;
	176
	177	char unused; / Placeholder for compatibility. */
	178	call_abi_t call_abi; /* Calling convention. */
	179
	180	/* CPU configuration. */
	181
	182	unsigned int debug_interrupt_level;
	183
	184	unsigned int icache_line_bytes;
	185	unsigned int dcache_line_bytes;
	186	unsigned int dcache_writeback;
	187
	188	unsigned int isa_use_windowed_registers;
	189	unsigned int isa_use_density_instructions;
	190	unsigned int isa_use_exceptions;
	191	unsigned int isa_use_ext_l32r;
	192	unsigned int isa_max_insn_size; /* Maximum instruction length. */
	193	unsigned int debug_num_ibreaks; /* Number of IBREAKs. */
	194	unsigned int debug_num_dbreaks;
	195
	196	/* Register map. */
	197
	198	xtensa_register_t* regmap;
	199
94a0e877 MG	200	unsigned int num_regs; /* Number of registers in register map. */
94a0e877 MG	201	unsigned int num_nopriv_regs; /* Number of non-privileged registers. */
ca3bf3bd DJ	202	unsigned int num_pseudo_regs; /* Number of pseudo registers. */
	203	unsigned int num_aregs; /* Size of register file. */
	204	unsigned int num_contexts;
	205
	206	int ar_base; /* Register number for AR0. */
	207	int a0_base; /* Register number for A0 (pseudo). */
	208	int wb_regnum; /* Register number for WB. */
	209	int ws_regnum; /* Register number for WS. */
	210	int pc_regnum; /* Register number for PC. */
	211	int ps_regnum; /* Register number for PS. */
	212	int lbeg_regnum; /* Register numbers for count regs. */
	213	int lend_regnum;
	214	int lcount_regnum;
	215	int sar_regnum; /* Register number of SAR. */
	216	int litbase_regnum; /* Register number of LITBASE. */
	217
	218	int interrupt_regnum; /* Register number for interrupt. */
	219	int interrupt2_regnum; /* Register number for interrupt2. */
	220	int cpenable_regnum; /* Register number for cpenable. */
	221	int debugcause_regnum; /* Register number for debugcause. */
	222	int exccause_regnum; /* Register number for exccause. */
	223	int excvaddr_regnum; /* Register number for excvaddr. */
	224
	225	int max_register_raw_size;
	226	int max_register_virtual_size;
	227	unsigned long fp_layout; / Layout of custom/TIE regs in 'FP' area. */
	228	unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */
	229	unsigned long *gregmap;
df4df182 UW	230
	231	/* Cached register types. */
	232	struct ctype_cache
	233	{
	234	struct ctype_cache *next;
	235	int size;
	236	struct type *virtual_type;
	237	} *type_entries;
ca3bf3bd DJ	238	};
ca3bf3bd DJ	239
94a0e877 MG	240	/* Macro to instantiate a gdbarch_tdep structure. */
	241
	242	#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \
	243	{ \
	244	.target_flags = 0, \
	245	.spill_location = -1, \
	246	.spill_size = (spillsz), \
	247	.unused = 0, \
	248	.call_abi = 0, \
	249	.debug_interrupt_level = XCHAL_DEBUGLEVEL, \
	250	.icache_line_bytes = XCHAL_ICACHE_LINESIZE, \
	251	.dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
	252	.dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \
	253	.isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
	254	.isa_use_density_instructions = XCHAL_HAVE_DENSITY, \
	255	.isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \
	256	.isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \
	257	.isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
	258	.debug_num_ibreaks = XCHAL_NUM_IBREAK, \
	259	.debug_num_dbreaks = XCHAL_NUM_DBREAK, \
	260	.regmap = rmap, \
	261	.num_regs = 0, \
	262	.num_nopriv_regs = 0, \
	263	.num_pseudo_regs = 0, \
	264	.num_aregs = XCHAL_NUM_AREGS, \
	265	.num_contexts = XCHAL_NUM_CONTEXTS, \
	266	.ar_base = -1, \
	267	.a0_base = -1, \
	268	.wb_regnum = -1, \
	269	.ws_regnum = -1, \
	270	.pc_regnum = -1, \
	271	.ps_regnum = -1, \
	272	.lbeg_regnum = -1, \
	273	.lend_regnum = -1, \
	274	.lcount_regnum = -1, \
	275	.sar_regnum = -1, \
	276	.litbase_regnum = -1, \
	277	.interrupt_regnum = -1, \
	278	.interrupt2_regnum = -1, \
	279	.cpenable_regnum = -1, \
	280	.debugcause_regnum = -1, \
	281	.exccause_regnum = -1, \
	282	.excvaddr_regnum = -1, \
	283	.max_register_raw_size = 0, \
	284	.max_register_virtual_size = 0, \
	285	.fp_layout = 0, \
	286	.fp_layout_bytes = 0, \
	287	.gregmap = 0, \
	288	}
	289	#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \
	290	struct gdbarch_tdep xtensa_tdep = \
	291	XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
	292
	293	#ifndef XCHAL_NUM_CONTEXTS
	294	#define XCHAL_NUM_CONTEXTS 0
	295	#endif
	296	#ifndef XCHAL_HAVE_EXCEPTIONS
	297	#define XCHAL_HAVE_EXCEPTIONS 1
	298	#endif
ca3bf3bd DJ	299	#define WB_SHIFT 2
	300
	301	/* We assign fixed numbers to the registers of the "current" window
	302	(i.e., relative to WB). The registers get remapped via the reg_map
	303	data structure to their corresponding register in the AR register
	304	file (see xtensa-tdep.c). */
	305