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28b48aa1 SB |
1 | /* Target-dependent code for the Z80. |
2 | ||
3 | Copyright (C) 1986-2021 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "arch-utils.h" | |
22 | #include "dis-asm.h" | |
23 | #include "frame.h" | |
24 | #include "frame-unwind.h" | |
25 | #include "frame-base.h" | |
26 | #include "trad-frame.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "inferior.h" | |
31 | #include "objfiles.h" | |
32 | #include "symfile.h" | |
33 | ||
34 | #include "z80-tdep.h" | |
35 | #include "features/z80.c" | |
36 | ||
37 | /* You need to define __gdb_break_handler symbol pointing to the breakpoint | |
38 | handler. The value of the symbol will be used to determine the instruction | |
39 | for software breakpoint. If __gdb_break_handler points to one of standard | |
40 | RST addresses (0x00, 0x08, 0x10,... 0x38) then RST __gdb_break_handler | |
41 | instruction will be used, else CALL __gdb_break_handler | |
42 | ||
43 | ;breakpoint handler | |
44 | .globl __gdb_break_handler | |
45 | .org 8 | |
46 | __gdb_break_handler: | |
47 | jp _debug_swbreak | |
48 | ||
49 | */ | |
50 | ||
51 | /* Meaning of terms "previous" and "next": | |
52 | previous frame - frame of callee, which is called by current function | |
53 | current frame - frame of current function which has called callee | |
54 | next frame - frame of caller, which has called current function | |
55 | */ | |
56 | ||
57 | struct gdbarch_tdep | |
58 | { | |
59 | /* Number of bytes used for address: | |
60 | 2 bytes for all Z80 family | |
61 | 3 bytes for eZ80 CPUs operating in ADL mode */ | |
62 | int addr_length; | |
63 | ||
64 | /* Type for void. */ | |
65 | struct type *void_type; | |
66 | /* Type for a function returning void. */ | |
67 | struct type *func_void_type; | |
68 | /* Type for a pointer to a function. Used for the type of PC. */ | |
69 | struct type *pc_type; | |
70 | }; | |
71 | ||
72 | /* At any time stack frame contains following parts: | |
73 | [<current PC>] | |
74 | [<temporaries, y bytes>] | |
75 | [<local variables, x bytes> | |
76 | <next frame FP>] | |
77 | [<saved state (critical or interrupt functions), 2 or 10 bytes>] | |
78 | In simplest case <next PC> is pointer to the call instruction | |
79 | (or call __call_hl). There are more difficult cases: interrupt handler or | |
80 | push/ret and jp; but they are untrackable. | |
81 | */ | |
82 | ||
83 | struct z80_unwind_cache | |
84 | { | |
85 | /* The previous frame's inner most stack address (SP after call executed), | |
86 | it is current frame's frame_id. */ | |
87 | CORE_ADDR prev_sp; | |
88 | ||
89 | /* Size of the frame, prev_sp + size = next_frame.prev_sp */ | |
90 | ULONGEST size; | |
91 | ||
92 | /* size of saved state (including frame pointer and return address), | |
93 | assume: prev_sp + size = IX + state_size */ | |
94 | ULONGEST state_size; | |
95 | ||
96 | struct | |
97 | { | |
98 | int called:1; /* there is return address on stack */ | |
99 | int load_args:1; /* prologues loads args using POPs */ | |
100 | int fp_sdcc:1; /* prologue saves and adjusts frame pointer IX */ | |
101 | int interrupt:1; /* __interrupt handler */ | |
102 | int critical:1; /* __critical function */ | |
103 | } prologue_type; | |
104 | ||
105 | /* Table indicating the location of each and every register. */ | |
106 | struct trad_frame_saved_reg *saved_regs; | |
107 | }; | |
108 | ||
109 | enum instruction_type | |
110 | { | |
111 | insn_default, | |
112 | insn_z80, | |
113 | insn_adl, | |
114 | insn_z80_ed, | |
115 | insn_adl_ed, | |
116 | insn_z80_ddfd, | |
117 | insn_adl_ddfd, | |
118 | insn_djnz_d, | |
119 | insn_jr_d, | |
120 | insn_jr_cc_d, | |
121 | insn_jp_nn, | |
122 | insn_jp_rr, | |
123 | insn_jp_cc_nn, | |
124 | insn_call_nn, | |
125 | insn_call_cc_nn, | |
126 | insn_rst_n, | |
127 | insn_ret, | |
128 | insn_ret_cc, | |
129 | insn_push_rr, | |
130 | insn_pop_rr, | |
131 | insn_dec_sp, | |
132 | insn_inc_sp, | |
133 | insn_ld_sp_nn, | |
134 | insn_ld_sp_6nn9, /* ld sp, (nn) */ | |
135 | insn_ld_sp_rr, | |
136 | insn_force_nop /* invalid opcode prefix */ | |
137 | }; | |
138 | ||
139 | struct insn_info | |
140 | { | |
141 | gdb_byte code; | |
142 | gdb_byte mask; | |
143 | gdb_byte size; /* without prefix(es) */ | |
144 | enum instruction_type type; | |
145 | }; | |
146 | ||
147 | /* Constants */ | |
148 | ||
149 | static const struct insn_info * | |
150 | z80_get_insn_info (struct gdbarch *gdbarch, const gdb_byte *buf, int *size); | |
151 | ||
152 | static const char *z80_reg_names[] = | |
153 | { | |
154 | /* 24 bit on eZ80, else 16 bit */ | |
155 | "af", "bc", "de", "hl", | |
156 | "sp", "pc", "ix", "iy", | |
157 | "af'", "bc'", "de'", "hl'", | |
158 | "ir", | |
159 | /* eZ80 only */ | |
160 | "sps" | |
161 | }; | |
162 | ||
163 | /* Return the name of register REGNUM. */ | |
164 | static const char * | |
165 | z80_register_name (struct gdbarch *gdbarch, int regnum) | |
166 | { | |
167 | if (regnum >= 0 && regnum < ARRAY_SIZE (z80_reg_names)) | |
168 | return z80_reg_names[regnum]; | |
169 | ||
170 | return NULL; | |
171 | } | |
172 | ||
173 | /* Return the type of a register specified by the architecture. Only | |
174 | the register cache should call this function directly; others should | |
175 | use "register_type". */ | |
176 | static struct type * | |
177 | z80_register_type (struct gdbarch *gdbarch, int reg_nr) | |
178 | { | |
179 | return builtin_type (gdbarch)->builtin_data_ptr; | |
180 | } | |
181 | ||
182 | /* The next 2 functions check BUF for instruction. If it is pop/push rr, then | |
183 | it returns register number OR'ed with 0x100 */ | |
184 | static int | |
185 | z80_is_pop_rr (const gdb_byte buf[], int *size) | |
186 | { | |
187 | switch (buf[0]) | |
188 | { | |
189 | case 0xc1: | |
190 | *size = 1; | |
191 | return Z80_BC_REGNUM | 0x100; | |
192 | case 0xd1: | |
193 | *size = 1; | |
194 | return Z80_DE_REGNUM | 0x100; | |
195 | case 0xe1: | |
196 | *size = 1; | |
197 | return Z80_HL_REGNUM | 0x100; | |
198 | case 0xf1: | |
199 | *size = 1; | |
200 | return Z80_AF_REGNUM | 0x100; | |
201 | case 0xdd: | |
202 | *size = 2; | |
203 | return (buf[1] == 0xe1) ? (Z80_IX_REGNUM | 0x100) : 0; | |
204 | case 0xfd: | |
205 | *size = 2; | |
206 | return (buf[1] == 0xe1) ? (Z80_IY_REGNUM | 0x100) : 0; | |
207 | } | |
208 | *size = 0; | |
209 | return 0; | |
210 | } | |
211 | ||
212 | static int | |
213 | z80_is_push_rr (const gdb_byte buf[], int *size) | |
214 | { | |
215 | switch (buf[0]) | |
216 | { | |
217 | case 0xc5: | |
218 | *size = 1; | |
219 | return Z80_BC_REGNUM | 0x100; | |
220 | case 0xd5: | |
221 | *size = 1; | |
222 | return Z80_DE_REGNUM | 0x100; | |
223 | case 0xe5: | |
224 | *size = 1; | |
225 | return Z80_HL_REGNUM | 0x100; | |
226 | case 0xf5: | |
227 | *size = 1; | |
228 | return Z80_AF_REGNUM | 0x100; | |
229 | case 0xdd: | |
230 | *size = 2; | |
231 | return (buf[1] == 0xe5) ? (Z80_IX_REGNUM | 0x100) : 0; | |
232 | case 0xfd: | |
233 | *size = 2; | |
234 | return (buf[1] == 0xe5) ? (Z80_IY_REGNUM | 0x100) : 0; | |
235 | } | |
236 | *size = 0; | |
237 | return 0; | |
238 | } | |
239 | ||
240 | /* Function: z80_scan_prologue | |
241 | ||
242 | This function decodes a function prologue to determine: | |
243 | 1) the size of the stack frame | |
244 | 2) which registers are saved on it | |
245 | 3) the offsets of saved regs | |
246 | This information is stored in the z80_unwind_cache structure. | |
247 | Small SDCC functions may just load args using POP instructions in prologue: | |
248 | pop af | |
249 | pop de | |
250 | pop hl | |
251 | pop bc | |
252 | push bc | |
253 | push hl | |
254 | push de | |
255 | push af | |
256 | SDCC function prologue may have up to 3 sections (all are optional): | |
257 | 1) save state | |
258 | a) __critical functions: | |
259 | ld a,i | |
260 | di | |
261 | push af | |
262 | b) __interrupt (both int and nmi) functions: | |
263 | push af | |
264 | push bc | |
265 | push de | |
266 | push hl | |
267 | push iy | |
268 | 2) save and adjust frame pointer | |
269 | a) call to special function (size optimization) | |
270 | call ___sdcc_enter_ix | |
271 | b) inline (speed optimization) | |
272 | push ix | |
273 | ld ix, #0 | |
274 | add ix, sp | |
275 | c) without FP, but saving it (IX is optimized out) | |
276 | push ix | |
277 | 3) allocate local variables | |
278 | a) via series of PUSH AF and optional DEC SP (size optimization) | |
279 | push af | |
280 | ... | |
281 | push af | |
282 | dec sp ;optional, if allocated odd numbers of bytes | |
283 | b) via SP decrements | |
284 | dec sp | |
285 | ... | |
286 | dec sp | |
287 | c) via addition (for large frames: 5+ for speed and 9+ for size opt.) | |
288 | ld hl, #xxxx ;size of stack frame | |
289 | add hl, sp | |
290 | ld sp, hl | |
291 | d) same, but using register IY (arrays or for __z88dk_fastcall functions) | |
292 | ld iy, #xxxx ;size of stack frame | |
293 | add iy, sp | |
294 | ld sp, iy | |
295 | e) same as c, but for eZ80 | |
296 | lea hl, ix - #nn | |
297 | ld sp, hl | |
298 | f) same as d, but for eZ80 | |
299 | lea iy, ix - #nn | |
300 | ld sp, iy | |
301 | */ | |
302 | ||
303 | static int | |
304 | z80_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end, | |
305 | struct z80_unwind_cache *info) | |
306 | { | |
307 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
308 | int addr_len = gdbarch_tdep (gdbarch)->addr_length; | |
309 | gdb_byte prologue[32]; /* max prologue is 24 bytes: __interrupt with local array */ | |
310 | int pos = 0; | |
311 | int len; | |
312 | int reg; | |
313 | CORE_ADDR value; | |
314 | ||
315 | len = pc_end - pc_beg; | |
316 | if (len > (int)sizeof (prologue)) | |
317 | len = sizeof (prologue); | |
318 | ||
319 | read_memory (pc_beg, prologue, len); | |
320 | ||
321 | /* stage0: check for series of POPs and then PUSHs */ | |
322 | if ((reg = z80_is_pop_rr(prologue, &pos))) | |
323 | { | |
324 | int i; | |
325 | int size = pos; | |
326 | gdb_byte regs[8]; /* Z80 have only 6 register pairs */ | |
327 | regs[0] = reg & 0xff; | |
328 | for (i = 1; i < 8 && (regs[i] = z80_is_pop_rr (&prologue[pos], &size)); | |
329 | ++i, pos += size); | |
330 | /* now we expect series of PUSHs in reverse order */ | |
331 | for (--i; i >= 0 && regs[i] == z80_is_push_rr (&prologue[pos], &size); | |
332 | --i, pos += size); | |
333 | if (i == -1 && pos > 0) | |
334 | info->prologue_type.load_args = 1; | |
335 | else | |
336 | pos = 0; | |
337 | } | |
338 | /* stage1: check for __interrupt handlers and __critical functions */ | |
339 | else if (!memcmp (&prologue[pos], "\355\127\363\365", 4)) | |
340 | { /* ld a, i; di; push af */ | |
341 | info->prologue_type.critical = 1; | |
342 | pos += 4; | |
343 | info->state_size += addr_len; | |
344 | } | |
345 | else if (!memcmp (&prologue[pos], "\365\305\325\345\375\345", 6)) | |
346 | { /* push af; push bc; push de; push hl; push iy */ | |
347 | info->prologue_type.interrupt = 1; | |
348 | pos += 6; | |
349 | info->state_size += addr_len * 5; | |
350 | } | |
351 | ||
352 | /* stage2: check for FP saving scheme */ | |
353 | if (prologue[pos] == 0xcd) /* call nn */ | |
354 | { | |
355 | struct bound_minimal_symbol msymbol; | |
356 | msymbol = lookup_minimal_symbol ("__sdcc_enter_ix", NULL, NULL); | |
357 | if (msymbol.minsym) | |
358 | { | |
359 | value = BMSYMBOL_VALUE_ADDRESS (msymbol); | |
360 | if (value == extract_unsigned_integer (&prologue[pos+1], addr_len, byte_order)) | |
361 | { | |
362 | pos += 1 + addr_len; | |
363 | info->prologue_type.fp_sdcc = 1; | |
364 | } | |
365 | } | |
366 | } | |
367 | else if (!memcmp (&prologue[pos], "\335\345\335\041\000\000", 4+addr_len) && | |
368 | !memcmp (&prologue[pos+4+addr_len], "\335\071\335\371", 4)) | |
369 | { /* push ix; ld ix, #0; add ix, sp; ld sp, ix */ | |
370 | pos += 4 + addr_len + 4; | |
371 | info->prologue_type.fp_sdcc = 1; | |
372 | } | |
373 | else if (!memcmp (&prologue[pos], "\335\345", 2)) | |
374 | { /* push ix */ | |
375 | pos += 2; | |
376 | info->prologue_type.fp_sdcc = 1; | |
377 | } | |
378 | ||
379 | /* stage3: check for local variables allocation */ | |
380 | switch (prologue[pos]) | |
381 | { | |
382 | case 0xf5: /* push af */ | |
383 | info->size = 0; | |
384 | while (prologue[pos] == 0xf5) | |
385 | { | |
386 | info->size += addr_len; | |
387 | pos++; | |
388 | } | |
389 | if (prologue[pos] == 0x3b) /* dec sp */ | |
390 | { | |
391 | info->size++; | |
392 | pos++; | |
393 | } | |
394 | break; | |
395 | case 0x3b: /* dec sp */ | |
396 | info->size = 0; | |
397 | while (prologue[pos] == 0x3b) | |
398 | { | |
399 | info->size++; | |
400 | pos++; | |
401 | } | |
402 | break; | |
403 | case 0x21: /*ld hl, -nn */ | |
404 | if (prologue[pos+addr_len] == 0x39 && prologue[pos+addr_len] >= 0x80 && | |
405 | prologue[pos+addr_len+1] == 0xf9) | |
406 | { /* add hl, sp; ld sp, hl */ | |
407 | info->size = -extract_signed_integer(&prologue[pos+1], addr_len, byte_order); | |
408 | pos += 1 + addr_len + 2; | |
409 | } | |
410 | break; | |
411 | case 0xfd: /* ld iy, -nn */ | |
412 | if (prologue[pos+1] == 0x21 && prologue[pos+1+addr_len] >= 0x80 && | |
413 | !memcmp (&prologue[pos+2+addr_len], "\375\071\375\371", 4)) | |
414 | { | |
415 | info->size = -extract_signed_integer(&prologue[pos+2], addr_len, byte_order); | |
416 | pos += 2 + addr_len + 4; | |
417 | } | |
418 | break; | |
419 | case 0xed: /* check for lea xx, ix - n */ | |
420 | switch (prologue[pos+1]) | |
421 | { | |
422 | case 0x22: /* lea hl, ix - n */ | |
423 | if (prologue[pos+2] >= 0x80 && prologue[pos+3] == 0xf9) | |
424 | { /* ld sp, hl */ | |
425 | info->size = -extract_signed_integer(&prologue[pos+2], 1, byte_order); | |
426 | pos += 4; | |
427 | } | |
428 | break; | |
429 | case 0x55: /* lea iy, ix - n */ | |
430 | if (prologue[pos+2] >= 0x80 && prologue[pos+3] == 0xfd && | |
431 | prologue[pos+4] == 0xf9) | |
432 | { /* ld sp, iy */ | |
433 | info->size = -extract_signed_integer(&prologue[pos+2], 1, byte_order); | |
434 | pos += 5; | |
435 | } | |
436 | break; | |
437 | } | |
438 | break; | |
439 | } | |
440 | len = 0; | |
441 | ||
442 | if (info->prologue_type.interrupt) | |
443 | { | |
444 | info->saved_regs[Z80_AF_REGNUM].set_addr (len++); | |
445 | info->saved_regs[Z80_BC_REGNUM].set_addr (len++); | |
446 | info->saved_regs[Z80_DE_REGNUM].set_addr (len++); | |
447 | info->saved_regs[Z80_HL_REGNUM].set_addr (len++); | |
448 | info->saved_regs[Z80_IY_REGNUM].set_addr (len++); | |
449 | } | |
450 | ||
451 | if (info->prologue_type.critical) | |
452 | len++; /* just skip IFF2 saved state */ | |
453 | ||
454 | if (info->prologue_type.fp_sdcc) | |
455 | info->saved_regs[Z80_IX_REGNUM].set_addr (len++); | |
456 | ||
457 | info->state_size += len * addr_len; | |
458 | ||
459 | return pc_beg + pos; | |
460 | } | |
461 | ||
462 | static CORE_ADDR | |
463 | z80_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
464 | { | |
465 | CORE_ADDR func_addr, func_end; | |
466 | CORE_ADDR prologue_end; | |
467 | ||
468 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
469 | return pc; | |
470 | ||
471 | prologue_end = skip_prologue_using_sal (gdbarch, func_addr); | |
472 | if (prologue_end != 0) | |
473 | return std::max (pc, prologue_end); | |
474 | ||
475 | { | |
476 | struct z80_unwind_cache info = {0}; | |
477 | struct trad_frame_saved_reg saved_regs[Z80_NUM_REGS]; | |
478 | ||
479 | info.saved_regs = saved_regs; | |
480 | ||
481 | /* Need to run the prologue scanner to figure out if the function has a | |
482 | prologue. */ | |
483 | ||
484 | prologue_end = z80_scan_prologue (gdbarch, func_addr, func_end, &info); | |
485 | ||
486 | if (info.prologue_type.fp_sdcc || info.prologue_type.interrupt || | |
487 | info.prologue_type.critical) | |
488 | return std::max (pc, prologue_end); | |
489 | } | |
490 | ||
491 | if (prologue_end != 0) | |
492 | { | |
493 | struct symtab_and_line prologue_sal = find_pc_line (func_addr, 0); | |
494 | struct compunit_symtab *compunit = SYMTAB_COMPUNIT (prologue_sal.symtab); | |
495 | const char *debug_format = COMPUNIT_DEBUGFORMAT (compunit); | |
496 | ||
497 | if (debug_format != NULL && | |
498 | !strncasecmp ("dwarf", debug_format, strlen("dwarf"))) | |
499 | return std::max (pc, prologue_end); | |
500 | } | |
501 | ||
502 | return pc; | |
503 | } | |
504 | ||
505 | /* Return the return-value convention that will be used by FUNCTION | |
506 | to return a value of type VALTYPE. FUNCTION may be NULL in which | |
507 | case the return convention is computed based only on VALTYPE. | |
508 | ||
509 | If READBUF is not NULL, extract the return value and save it in this buffer. | |
510 | ||
511 | If WRITEBUF is not NULL, it contains a return value which will be | |
512 | stored into the appropriate register. This can be used when we want | |
513 | to force the value returned by a function (see the "return" command | |
514 | for instance). */ | |
515 | static enum return_value_convention | |
516 | z80_return_value (struct gdbarch *gdbarch, struct value *function, | |
517 | struct type *valtype, struct regcache *regcache, | |
518 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
519 | { | |
520 | /* Byte are returned in L, word in HL, dword in DEHL. */ | |
521 | int len = TYPE_LENGTH (valtype); | |
522 | ||
523 | if ((valtype->code () == TYPE_CODE_STRUCT | |
524 | || valtype->code () == TYPE_CODE_UNION | |
525 | || valtype->code () == TYPE_CODE_ARRAY) | |
526 | && len > 4) | |
527 | return RETURN_VALUE_STRUCT_CONVENTION; | |
528 | ||
529 | if (writebuf != NULL) | |
530 | { | |
531 | if (len > 2) | |
532 | { | |
533 | regcache->cooked_write_part (Z80_DE_REGNUM, 0, len - 2, writebuf+2); | |
534 | len = 2; | |
535 | } | |
536 | regcache->cooked_write_part (Z80_HL_REGNUM, 0, len, writebuf); | |
537 | } | |
538 | ||
539 | if (readbuf != NULL) | |
540 | { | |
541 | if (len > 2) | |
542 | { | |
543 | regcache->cooked_read_part (Z80_DE_REGNUM, 0, len - 2, readbuf+2); | |
544 | len = 2; | |
545 | } | |
546 | regcache->cooked_read_part (Z80_HL_REGNUM, 0, len, readbuf); | |
547 | } | |
548 | ||
549 | return RETURN_VALUE_REGISTER_CONVENTION; | |
550 | } | |
551 | ||
552 | /* function unwinds current stack frame and returns next one */ | |
553 | static struct z80_unwind_cache * | |
554 | z80_frame_unwind_cache (struct frame_info *this_frame, | |
555 | void **this_prologue_cache) | |
556 | { | |
557 | CORE_ADDR start_pc, current_pc; | |
558 | ULONGEST this_base; | |
559 | int i; | |
560 | gdb_byte buf[sizeof(void*)]; | |
561 | struct z80_unwind_cache *info; | |
562 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
563 | int addr_len = gdbarch_tdep (gdbarch)->addr_length; | |
564 | ||
565 | if (*this_prologue_cache) | |
566 | return (struct z80_unwind_cache *) *this_prologue_cache; | |
567 | ||
568 | info = FRAME_OBSTACK_ZALLOC (struct z80_unwind_cache); | |
569 | memset (info, 0, sizeof (*info)); | |
570 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
571 | *this_prologue_cache = info; | |
572 | ||
573 | start_pc = get_frame_func (this_frame); | |
574 | current_pc = get_frame_pc (this_frame); | |
575 | if ((start_pc > 0) && (start_pc <= current_pc)) | |
576 | z80_scan_prologue (get_frame_arch (this_frame), | |
577 | start_pc, current_pc, info); | |
578 | ||
579 | if (info->prologue_type.fp_sdcc) | |
580 | { | |
581 | /* With SDCC standard prologue, IX points to the end of current frame | |
582 | (where previous frame pointer and state are saved). */ | |
583 | this_base = get_frame_register_unsigned (this_frame, Z80_IX_REGNUM); | |
584 | info->prev_sp = this_base + info->size; | |
585 | } | |
586 | else | |
587 | { | |
588 | CORE_ADDR addr; | |
589 | CORE_ADDR sp; | |
590 | CORE_ADDR sp_mask = (1 << gdbarch_ptr_bit(gdbarch)) - 1; | |
591 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
592 | /* Assume that the FP is this frame's SP but with that pushed | |
593 | stack space added back. */ | |
594 | this_base = get_frame_register_unsigned (this_frame, Z80_SP_REGNUM); | |
595 | sp = this_base + info->size; | |
596 | for (;; ++sp) | |
597 | { | |
598 | sp &= sp_mask; | |
599 | if (sp < this_base) | |
600 | { /* overflow, looks like end of stack */ | |
601 | sp = this_base + info->size; | |
602 | break; | |
603 | } | |
604 | /* find return address */ | |
605 | read_memory (sp, buf, addr_len); | |
606 | addr = extract_unsigned_integer(buf, addr_len, byte_order); | |
607 | read_memory (addr-addr_len-1, buf, addr_len+1); | |
608 | if (buf[0] == 0xcd || (buf[0] & 0307) == 0304) /* Is it CALL */ | |
609 | { /* CALL nn or CALL cc,nn */ | |
610 | static const char *names[] = | |
611 | { | |
612 | "__sdcc_call_ix", "__sdcc_call_iy", "__sdcc_call_hl" | |
613 | }; | |
614 | addr = extract_unsigned_integer(buf+1, addr_len, byte_order); | |
615 | if (addr == start_pc) | |
616 | break; /* found */ | |
617 | for (i = sizeof(names)/sizeof(*names)-1; i >= 0; --i) | |
618 | { | |
619 | struct bound_minimal_symbol msymbol; | |
620 | msymbol = lookup_minimal_symbol (names[i], NULL, NULL); | |
621 | if (!msymbol.minsym) | |
622 | continue; | |
623 | if (addr == BMSYMBOL_VALUE_ADDRESS (msymbol)) | |
624 | break; | |
625 | } | |
626 | if (i >= 0) | |
627 | break; | |
628 | continue; | |
629 | } | |
630 | else | |
631 | continue; /* it is not call_nn, call_cc_nn */ | |
632 | } | |
633 | info->prev_sp = sp; | |
634 | } | |
635 | ||
636 | /* Adjust all the saved registers so that they contain addresses and not | |
637 | offsets. */ | |
638 | for (i = 0; i < gdbarch_num_regs (gdbarch) - 1; i++) | |
639 | if (info->saved_regs[i].addr () > 0) | |
640 | info->saved_regs[i].set_addr | |
641 | (info->prev_sp - info->saved_regs[i].addr () * addr_len); | |
642 | ||
643 | /* Except for the startup code, the return PC is always saved on | |
644 | the stack and is at the base of the frame. */ | |
645 | info->saved_regs[Z80_PC_REGNUM].set_addr (info->prev_sp); | |
646 | ||
647 | /* The previous frame's SP needed to be computed. Save the computed | |
648 | value. */ | |
649 | info->saved_regs[Z80_SP_REGNUM].set_value (info->prev_sp + addr_len); | |
650 | return info; | |
651 | } | |
652 | ||
653 | /* Given a GDB frame, determine the address of the calling function's | |
654 | frame. This will be used to create a new GDB frame struct. */ | |
655 | static void | |
656 | z80_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
657 | struct frame_id *this_id) | |
658 | { | |
659 | struct frame_id id; | |
660 | struct z80_unwind_cache *info; | |
661 | CORE_ADDR base; | |
662 | CORE_ADDR func; | |
663 | ||
664 | /* The FUNC is easy. */ | |
665 | func = get_frame_func (this_frame); | |
666 | ||
667 | info = z80_frame_unwind_cache (this_frame, this_cache); | |
668 | /* Hopefully the prologue analysis either correctly determined the | |
669 | frame's base (which is the SP from the previous frame), or set | |
670 | that base to "NULL". */ | |
671 | base = info->prev_sp; | |
672 | if (base == 0) | |
673 | return; | |
674 | ||
675 | id = frame_id_build (base, func); | |
676 | *this_id = id; | |
677 | } | |
678 | ||
679 | static struct value * | |
680 | z80_frame_prev_register (struct frame_info *this_frame, | |
681 | void **this_prologue_cache, int regnum) | |
682 | { | |
683 | struct z80_unwind_cache *info | |
684 | = z80_frame_unwind_cache (this_frame, this_prologue_cache); | |
685 | ||
686 | if (regnum == Z80_PC_REGNUM) | |
687 | { | |
688 | if (info->saved_regs[Z80_PC_REGNUM].is_addr ()) | |
689 | { | |
690 | /* Reading the return PC from the PC register is slightly | |
691 | abnormal. */ | |
692 | ULONGEST pc; | |
693 | gdb_byte buf[3]; | |
694 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
695 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
696 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
697 | ||
698 | read_memory (info->saved_regs[Z80_PC_REGNUM].addr (), | |
699 | buf, tdep->addr_length); | |
700 | pc = extract_unsigned_integer (buf, tdep->addr_length, byte_order); | |
701 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
702 | } | |
703 | ||
704 | return frame_unwind_got_optimized (this_frame, regnum); | |
705 | } | |
706 | ||
707 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
708 | } | |
709 | ||
710 | /* Return the breakpoint kind for this target based on *PCPTR. */ | |
711 | static int | |
712 | z80_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
713 | { | |
714 | static int addr = -1; | |
715 | if (addr == -1) | |
716 | { | |
717 | struct bound_minimal_symbol bh; | |
718 | bh = lookup_minimal_symbol ("_break_handler", NULL, NULL); | |
719 | if (bh.minsym) | |
720 | addr = BMSYMBOL_VALUE_ADDRESS (bh); | |
721 | else | |
722 | { | |
723 | warning(_("Unable to determine inferior's software breakpoint type: " | |
724 | "couldn't find `_break_handler' function in inferior. Will " | |
725 | "be used default software breakpoint instruction RST 0x08.")); | |
726 | addr = 0x0008; | |
727 | } | |
728 | } | |
729 | return addr; | |
730 | } | |
731 | ||
732 | /* Return the software breakpoint from KIND. KIND is just address of breakpoint | |
733 | handler. If address is on of standard RSTs, then RST n instruction is used | |
734 | as breakpoint. | |
735 | SIZE is set to the software breakpoint's length in memory. */ | |
736 | static const gdb_byte * | |
737 | z80_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
738 | { | |
739 | static gdb_byte break_insn[8]; | |
740 | ||
741 | if ((kind & 070) == kind) | |
742 | { | |
743 | break_insn[0] = kind | 0307; | |
744 | *size = 1; | |
745 | } | |
746 | else /* kind is non-RST address, use CALL instead, but it is dungerous */ | |
747 | { | |
748 | gdb_byte *p = break_insn; | |
749 | *p++ = 0xcd; | |
750 | *p++ = (kind >> 0) & 0xff; | |
751 | *p++ = (kind >> 8) & 0xff; | |
752 | if (gdbarch_tdep (gdbarch)->addr_length > 2) | |
753 | *p++ = (kind >> 16) & 0xff; | |
754 | *size = p - break_insn; | |
755 | } | |
756 | return break_insn; | |
757 | } | |
758 | ||
759 | /* Return a vector of addresses on which the software single step | |
760 | breakpoints should be inserted. NULL means software single step is | |
761 | not used. | |
762 | Only one breakpoint address will be returned: conditional branches | |
763 | will be always evaluated. */ | |
764 | static std::vector<CORE_ADDR> | |
765 | z80_software_single_step (struct regcache *regcache) | |
766 | { | |
767 | static const int flag_mask[] = {1 << 6, 1 << 0, 1 << 2, 1 << 7}; | |
768 | gdb_byte buf[8]; | |
769 | ULONGEST t; | |
770 | ULONGEST addr; | |
771 | int opcode; | |
772 | int size; | |
773 | const struct insn_info *info; | |
774 | std::vector<CORE_ADDR> ret (1); | |
775 | struct gdbarch *gdbarch = target_gdbarch (); | |
776 | ||
777 | regcache->cooked_read (Z80_PC_REGNUM, &addr); | |
778 | read_memory (addr, buf, sizeof(buf)); | |
779 | info = z80_get_insn_info (gdbarch, buf, &size); | |
780 | ret[0] = addr + size; | |
781 | if (info == NULL) /* possible in case of double prefix */ | |
782 | { /* forced NOP, TODO: replace by NOP */ | |
783 | return ret; | |
784 | } | |
785 | opcode = buf[size - info->size]; /* take opcode instead of prefix */ | |
786 | /* stage 1: check for conditions */ | |
787 | switch (info->type) | |
788 | { | |
789 | case insn_djnz_d: | |
790 | regcache->cooked_read (Z80_BC_REGNUM, &t); | |
791 | if ((t & 0xff00) != 0x100) | |
792 | return ret; | |
793 | break; | |
794 | case insn_jr_cc_d: | |
795 | opcode &= 030; /* JR NZ,d has cc equal to 040, but others 000 */ | |
796 | /* fall through */ | |
797 | case insn_jp_cc_nn: | |
798 | case insn_call_cc_nn: | |
799 | case insn_ret_cc: | |
800 | regcache->cooked_read (Z80_AF_REGNUM, &t); | |
801 | /* lower bit of condition inverts match, so invert flags if set */ | |
802 | if ((opcode & 010) != 0) | |
803 | t = ~t; | |
804 | /* two higher bits of condition field defines flag, so use them only | |
805 | to check condition of "not execute" */ | |
806 | if (t & flag_mask[(opcode >> 4) & 3]) | |
807 | return ret; | |
808 | break; | |
809 | } | |
810 | /* stage 2: compute address */ | |
811 | /* TODO: implement eZ80 MADL support */ | |
812 | switch (info->type) | |
813 | { | |
814 | default: | |
815 | return ret; | |
816 | case insn_djnz_d: | |
817 | case insn_jr_d: | |
818 | case insn_jr_cc_d: | |
819 | addr += size; | |
820 | addr += (signed char)buf[size-1]; | |
821 | break; | |
822 | case insn_jp_rr: | |
823 | if (size == 1) | |
824 | opcode = Z80_HL_REGNUM; | |
825 | else | |
826 | opcode = (buf[size-2] & 0x20) ? Z80_IY_REGNUM : Z80_IX_REGNUM; | |
827 | regcache->cooked_read (opcode, &addr); | |
828 | break; | |
829 | case insn_jp_nn: | |
830 | case insn_jp_cc_nn: | |
831 | case insn_call_nn: | |
832 | case insn_call_cc_nn: | |
833 | addr = buf[size-1] * 0x100 + buf[size-2]; | |
834 | if (info->size > 3) /* long instruction mode */ | |
835 | addr = addr * 0x100 + buf[size-3]; | |
836 | break; | |
837 | case insn_rst_n: | |
838 | addr = opcode & 070; | |
839 | break; | |
840 | case insn_ret: | |
841 | case insn_ret_cc: | |
842 | regcache->cooked_read (Z80_SP_REGNUM, &addr); | |
843 | read_memory (addr, buf, 3); | |
844 | addr = buf[1] * 0x100 + buf[0]; | |
845 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ez80_adl) | |
846 | addr = addr * 0x100 + buf[2]; | |
847 | break; | |
848 | } | |
849 | ret[0] = addr; | |
850 | return ret; | |
851 | } | |
852 | ||
853 | /* Cached, dynamically allocated copies of the target data structures: */ | |
854 | static unsigned (*cache_ovly_region_table)[3] = 0; | |
855 | static unsigned cache_novly_regions; | |
856 | static CORE_ADDR cache_ovly_region_table_base = 0; | |
857 | enum ovly_index | |
858 | { | |
859 | VMA, OSIZE, MAPPED_TO_LMA | |
860 | }; | |
861 | ||
862 | static void | |
863 | z80_free_overlay_region_table (void) | |
864 | { | |
865 | if (cache_ovly_region_table) | |
866 | xfree (cache_ovly_region_table); | |
867 | cache_novly_regions = 0; | |
868 | cache_ovly_region_table = NULL; | |
869 | cache_ovly_region_table_base = 0; | |
870 | } | |
871 | ||
872 | /* Read an array of ints of size SIZE from the target into a local buffer. | |
873 | Convert to host order. LEN is number of ints. */ | |
874 | ||
875 | static void | |
876 | read_target_long_array (CORE_ADDR memaddr, unsigned int *myaddr, | |
877 | int len, int size, enum bfd_endian byte_order) | |
878 | { | |
879 | /* alloca is safe here, because regions array is very small. */ | |
880 | gdb_byte *buf = (gdb_byte *) alloca (len * size); | |
881 | int i; | |
882 | ||
883 | read_memory (memaddr, buf, len * size); | |
884 | for (i = 0; i < len; i++) | |
885 | myaddr[i] = extract_unsigned_integer (size * i + buf, size, byte_order); | |
886 | } | |
887 | ||
888 | static int | |
889 | z80_read_overlay_region_table () | |
890 | { | |
891 | struct bound_minimal_symbol novly_regions_msym; | |
892 | struct bound_minimal_symbol ovly_region_table_msym; | |
893 | struct gdbarch *gdbarch; | |
894 | int word_size; | |
895 | enum bfd_endian byte_order; | |
896 | ||
897 | z80_free_overlay_region_table (); | |
898 | novly_regions_msym = lookup_minimal_symbol ("_novly_regions", NULL, NULL); | |
899 | if (! novly_regions_msym.minsym) | |
900 | { | |
901 | error (_("Error reading inferior's overlay table: " | |
902 | "couldn't find `_novly_regions'\n" | |
903 | "variable in inferior. Use `overlay manual' mode.")); | |
904 | return 0; | |
905 | } | |
906 | ||
907 | ovly_region_table_msym = lookup_bound_minimal_symbol ("_ovly_region_table"); | |
908 | if (! ovly_region_table_msym.minsym) | |
909 | { | |
910 | error (_("Error reading inferior's overlay table: couldn't find " | |
911 | "`_ovly_region_table'\n" | |
912 | "array in inferior. Use `overlay manual' mode.")); | |
913 | return 0; | |
914 | } | |
915 | ||
916 | const enum overlay_debugging_state save_ovly_dbg = overlay_debugging; | |
917 | /* prevent infinite recurse */ | |
918 | overlay_debugging = ovly_off; | |
919 | ||
920 | gdbarch = ovly_region_table_msym.objfile->arch (); | |
921 | word_size = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT; | |
922 | byte_order = gdbarch_byte_order (gdbarch); | |
923 | ||
924 | cache_novly_regions = read_memory_integer ( | |
925 | BMSYMBOL_VALUE_ADDRESS (novly_regions_msym), | |
926 | 4, byte_order); | |
927 | cache_ovly_region_table | |
928 | = (unsigned int (*)[3]) xmalloc (cache_novly_regions * | |
929 | sizeof (*cache_ovly_region_table)); | |
930 | cache_ovly_region_table_base | |
931 | = BMSYMBOL_VALUE_ADDRESS (ovly_region_table_msym); | |
932 | read_target_long_array (cache_ovly_region_table_base, | |
933 | (unsigned int *) cache_ovly_region_table, | |
934 | cache_novly_regions * 3, word_size, byte_order); | |
935 | ||
936 | overlay_debugging = save_ovly_dbg; | |
937 | return 1; /* SUCCESS */ | |
938 | } | |
939 | ||
940 | static int | |
941 | z80_overlay_update_1 (struct obj_section *osect) | |
942 | { | |
943 | int i; | |
944 | asection *bsect = osect->the_bfd_section; | |
945 | unsigned lma; | |
946 | unsigned vma = bfd_section_vma (bsect); | |
947 | ||
948 | /* find region corresponding to the section VMA */ | |
949 | for (i = 0; i < cache_novly_regions; i++) | |
950 | if (cache_ovly_region_table[i][VMA] == vma) | |
951 | break; | |
952 | if (i == cache_novly_regions) | |
953 | return 0; /* no such region */ | |
954 | ||
955 | lma = cache_ovly_region_table[i][MAPPED_TO_LMA]; | |
956 | i = 0; | |
957 | ||
958 | /* we have interest for sections with same VMA */ | |
959 | for (objfile *objfile : current_program_space->objfiles ()) | |
960 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
961 | if (section_is_overlay (osect)) | |
962 | { | |
963 | osect->ovly_mapped = (lma == bfd_section_lma (osect->the_bfd_section)); | |
964 | i |= osect->ovly_mapped; /* true, if at least one section is mapped */ | |
965 | } | |
966 | return i; | |
967 | } | |
968 | ||
969 | /* Refresh overlay mapped state for section OSECT. */ | |
970 | static void | |
971 | z80_overlay_update (struct obj_section *osect) | |
972 | { | |
973 | /* Always need to read the entire table anew. */ | |
974 | if (!z80_read_overlay_region_table ()) | |
975 | return; | |
976 | ||
977 | /* Were we given an osect to look up? NULL means do all of them. */ | |
978 | if (osect != nullptr && z80_overlay_update_1 (osect)) | |
979 | return; | |
980 | ||
981 | /* Update all sections, even if only one was requested. */ | |
982 | for (objfile *objfile : current_program_space->objfiles ()) | |
983 | ALL_OBJFILE_OSECTIONS (objfile, osect) | |
984 | { | |
985 | if (!section_is_overlay (osect)) | |
986 | continue; | |
987 | ||
988 | asection *bsect = osect->the_bfd_section; | |
989 | bfd_vma lma = bfd_section_lma (bsect); | |
990 | bfd_vma vma = bfd_section_vma (bsect); | |
991 | ||
992 | for (int i = 0; i < cache_novly_regions; ++i) | |
993 | if (cache_ovly_region_table[i][VMA] == vma) | |
994 | osect->ovly_mapped = | |
995 | (cache_ovly_region_table[i][MAPPED_TO_LMA] == lma); | |
996 | } | |
997 | } | |
998 | ||
999 | /* Return non-zero if the instruction at ADDR is a call; zero otherwise. */ | |
1000 | static int | |
1001 | z80_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1002 | { | |
1003 | gdb_byte buf[8]; | |
1004 | int size; | |
1005 | const struct insn_info *info; | |
1006 | read_memory (addr, buf, sizeof(buf)); | |
1007 | info = z80_get_insn_info (gdbarch, buf, &size); | |
1008 | if (info) | |
1009 | switch (info->type) | |
1010 | { | |
1011 | case insn_call_nn: | |
1012 | case insn_call_cc_nn: | |
1013 | case insn_rst_n: | |
1014 | return 1; | |
1015 | } | |
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | /* Return non-zero if the instruction at ADDR is a return; zero otherwise. */ | |
1020 | static int | |
1021 | z80_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1022 | { | |
1023 | gdb_byte buf[8]; | |
1024 | int size; | |
1025 | const struct insn_info *info; | |
1026 | read_memory (addr, buf, sizeof(buf)); | |
1027 | info = z80_get_insn_info (gdbarch, buf, &size); | |
1028 | if (info) | |
1029 | switch (info->type) | |
1030 | { | |
1031 | case insn_ret: | |
1032 | case insn_ret_cc: | |
1033 | return 1; | |
1034 | } | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /* Return non-zero if the instruction at ADDR is a jump; zero otherwise. */ | |
1039 | static int | |
1040 | z80_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1041 | { | |
1042 | gdb_byte buf[8]; | |
1043 | int size; | |
1044 | const struct insn_info *info; | |
1045 | read_memory (addr, buf, sizeof(buf)); | |
1046 | info = z80_get_insn_info (gdbarch, buf, &size); | |
1047 | if (info) | |
1048 | switch (info->type) | |
1049 | { | |
1050 | case insn_jp_nn: | |
1051 | case insn_jp_cc_nn: | |
1052 | case insn_jp_rr: | |
1053 | case insn_jr_d: | |
1054 | case insn_jr_cc_d: | |
1055 | case insn_djnz_d: | |
1056 | return 1; | |
1057 | } | |
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | static const struct frame_unwind | |
1062 | z80_frame_unwind = | |
1063 | { | |
1064 | "z80", | |
1065 | NORMAL_FRAME, | |
1066 | default_frame_unwind_stop_reason, | |
1067 | z80_frame_this_id, | |
1068 | z80_frame_prev_register, | |
1069 | NULL, /*unwind_data*/ | |
1070 | default_frame_sniffer | |
1071 | /*dealloc_cache*/ | |
1072 | /*prev_arch*/ | |
1073 | }; | |
1074 | ||
1075 | /* Initialize the gdbarch struct for the Z80 arch */ | |
1076 | static struct gdbarch * | |
1077 | z80_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1078 | { | |
1079 | struct gdbarch *gdbarch; | |
1080 | struct gdbarch_tdep *tdep; | |
1081 | struct gdbarch_list *best_arch; | |
1082 | tdesc_arch_data_up tdesc_data; | |
1083 | unsigned long mach = info.bfd_arch_info->mach; | |
1084 | const struct target_desc *tdesc = info.target_desc; | |
1085 | ||
1086 | if (!tdesc_has_registers (tdesc)) | |
1087 | /* Pick a default target description. */ | |
1088 | tdesc = tdesc_z80; | |
1089 | ||
1090 | /* Check any target description for validity. */ | |
1091 | if (tdesc_has_registers (tdesc)) | |
1092 | { | |
1093 | const struct tdesc_feature *feature; | |
1094 | int valid_p; | |
1095 | ||
1096 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.z80.cpu"); | |
1097 | if (feature == NULL) | |
1098 | return NULL; | |
1099 | ||
1100 | tdesc_data = tdesc_data_alloc (); | |
1101 | ||
1102 | valid_p = 1; | |
1103 | ||
1104 | for (unsigned i = 0; i < Z80_NUM_REGS; i++) | |
1105 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, | |
1106 | z80_reg_names[i]); | |
1107 | ||
1108 | if (!valid_p) | |
1109 | return NULL; | |
1110 | } | |
1111 | ||
1112 | /* If there is already a candidate, use it. */ | |
1113 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
1114 | best_arch != NULL; | |
1115 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
1116 | { | |
1117 | if (mach == gdbarch_bfd_arch_info (best_arch->gdbarch)->mach) | |
1118 | return best_arch->gdbarch; | |
1119 | } | |
1120 | ||
1121 | /* None found, create a new architecture from the information provided. */ | |
1122 | tdep = XCNEW (struct gdbarch_tdep); | |
1123 | gdbarch = gdbarch_alloc (&info, tdep); | |
1124 | ||
1125 | if (mach == bfd_mach_ez80_adl) | |
1126 | { | |
1127 | tdep->addr_length = 3; | |
1128 | set_gdbarch_max_insn_length (gdbarch, 6); | |
1129 | } | |
1130 | else | |
1131 | { | |
1132 | tdep->addr_length = 2; | |
1133 | set_gdbarch_max_insn_length (gdbarch, 4); | |
1134 | } | |
1135 | ||
1136 | /* Create a type for PC. We can't use builtin types here, as they may not | |
1137 | be defined. */ | |
1138 | tdep->void_type = arch_type (gdbarch, TYPE_CODE_VOID, TARGET_CHAR_BIT, | |
1139 | "void"); | |
1140 | tdep->func_void_type = make_function_type (tdep->void_type, NULL); | |
1141 | tdep->pc_type = arch_pointer_type (gdbarch, | |
1142 | tdep->addr_length * TARGET_CHAR_BIT, | |
1143 | NULL, tdep->func_void_type); | |
1144 | ||
1145 | set_gdbarch_short_bit (gdbarch, TARGET_CHAR_BIT); | |
1146 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1147 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1148 | set_gdbarch_ptr_bit (gdbarch, tdep->addr_length * TARGET_CHAR_BIT); | |
1149 | set_gdbarch_addr_bit (gdbarch, tdep->addr_length * TARGET_CHAR_BIT); | |
1150 | ||
1151 | set_gdbarch_num_regs (gdbarch, (mach == bfd_mach_ez80_adl) ? EZ80_NUM_REGS | |
1152 | : Z80_NUM_REGS); | |
1153 | set_gdbarch_sp_regnum (gdbarch, Z80_SP_REGNUM); | |
1154 | set_gdbarch_pc_regnum (gdbarch, Z80_PC_REGNUM); | |
1155 | ||
1156 | set_gdbarch_register_name (gdbarch, z80_register_name); | |
1157 | set_gdbarch_register_type (gdbarch, z80_register_type); | |
1158 | ||
1159 | /* TODO: get FP type from binary (extra flags required) */ | |
1160 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1161 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1162 | set_gdbarch_long_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1163 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1164 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); | |
1165 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_single); | |
1166 | ||
1167 | set_gdbarch_return_value (gdbarch, z80_return_value); | |
1168 | ||
1169 | set_gdbarch_skip_prologue (gdbarch, z80_skip_prologue); | |
1170 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); // falling stack | |
1171 | ||
1172 | set_gdbarch_software_single_step (gdbarch, z80_software_single_step); | |
1173 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, z80_breakpoint_kind_from_pc); | |
1174 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, z80_sw_breakpoint_from_kind); | |
1175 | set_gdbarch_insn_is_call (gdbarch, z80_insn_is_call); | |
1176 | set_gdbarch_insn_is_jump (gdbarch, z80_insn_is_jump); | |
1177 | set_gdbarch_insn_is_ret (gdbarch, z80_insn_is_ret); | |
1178 | ||
1179 | set_gdbarch_overlay_update (gdbarch, z80_overlay_update); | |
1180 | ||
1181 | frame_unwind_append_unwinder (gdbarch, &z80_frame_unwind); | |
1182 | if (tdesc_data) | |
1183 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
1184 | ||
1185 | return gdbarch; | |
1186 | } | |
1187 | ||
1188 | /* Table to disassemble machine codes without prefix. */ | |
1189 | static const struct insn_info | |
1190 | ez80_main_insn_table[] = | |
1191 | { /* table with double prefix check */ | |
1192 | { 0100, 0377, 0, insn_force_nop}, //double prefix | |
1193 | { 0111, 0377, 0, insn_force_nop}, //double prefix | |
1194 | { 0122, 0377, 0, insn_force_nop}, //double prefix | |
1195 | { 0133, 0377, 0, insn_force_nop}, //double prefix | |
1196 | /* initial table for eZ80_z80 */ | |
1197 | { 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix | |
1198 | { 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix | |
1199 | { 0122, 0377, 1, insn_adl }, //eZ80 mode prefix | |
1200 | { 0133, 0377, 1, insn_adl }, //eZ80 mode prefix | |
1201 | /* here common Z80/Z180/eZ80 opcodes */ | |
1202 | { 0000, 0367, 1, insn_default }, //"nop", "ex af,af'" | |
1203 | { 0061, 0377, 3, insn_ld_sp_nn }, //"ld sp,nn" | |
1204 | { 0001, 0317, 3, insn_default }, //"ld rr,nn" | |
1205 | { 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)" | |
1206 | { 0042, 0347, 3, insn_default }, //"ld (nn),hl/a", "ld hl/a,(nn)" | |
1207 | { 0063, 0377, 1, insn_inc_sp }, //"inc sp" | |
1208 | { 0073, 0377, 1, insn_dec_sp }, //"dec sp" | |
1209 | { 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ... | |
1210 | { 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)" | |
1211 | { 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n" | |
1212 | { 0020, 0377, 2, insn_djnz_d }, //"djnz dis" | |
1213 | { 0030, 0377, 2, insn_jr_d }, //"jr dis" | |
1214 | { 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis" | |
1215 | { 0100, 0300, 1, insn_default }, //"ld r,r", "halt" | |
1216 | { 0200, 0300, 1, insn_default }, //"alu_op a,r" | |
1217 | { 0300, 0307, 1, insn_ret_cc }, //"ret cc" | |
1218 | { 0301, 0317, 1, insn_pop_rr }, //"pop rr" | |
1219 | { 0302, 0307, 3, insn_jp_cc_nn }, //"jp cc,nn" | |
1220 | { 0303, 0377, 3, insn_jp_nn }, //"jp nn" | |
1221 | { 0304, 0307, 3, insn_call_cc_nn}, //"call cc,nn" | |
1222 | { 0305, 0317, 1, insn_push_rr }, //"push rr" | |
1223 | { 0306, 0307, 2, insn_default }, //"alu_op a,n" | |
1224 | { 0307, 0307, 1, insn_rst_n }, //"rst n" | |
1225 | { 0311, 0377, 1, insn_ret }, //"ret" | |
1226 | { 0313, 0377, 2, insn_default }, //CB prefix | |
1227 | { 0315, 0377, 3, insn_call_nn }, //"call nn" | |
1228 | { 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)" | |
1229 | { 0335, 0337, 1, insn_z80_ddfd }, //DD/FD prefix | |
1230 | { 0351, 0377, 1, insn_jp_rr }, //"jp (hl)" | |
1231 | { 0355, 0377, 1, insn_z80_ed }, //ED prefix | |
1232 | { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl" | |
1233 | { 0000, 0000, 1, insn_default } //others | |
1234 | } ; | |
1235 | ||
1236 | static const struct insn_info | |
1237 | ez80_adl_main_insn_table[] = | |
1238 | { /* table with double prefix check */ | |
1239 | { 0100, 0377, 0, insn_force_nop}, //double prefix | |
1240 | { 0111, 0377, 0, insn_force_nop}, //double prefix | |
1241 | { 0122, 0377, 0, insn_force_nop}, //double prefix | |
1242 | { 0133, 0377, 0, insn_force_nop}, //double prefix | |
1243 | /* initial table for eZ80_adl */ | |
1244 | { 0000, 0367, 1, insn_default }, //"nop", "ex af,af'" | |
1245 | { 0061, 0377, 4, insn_ld_sp_nn }, //"ld sp,Mmn" | |
1246 | { 0001, 0317, 4, insn_default }, //"ld rr,Mmn" | |
1247 | { 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)" | |
1248 | { 0042, 0347, 4, insn_default }, //"ld (Mmn),hl/a", "ld hl/a,(Mmn)" | |
1249 | { 0063, 0377, 1, insn_inc_sp }, //"inc sp" | |
1250 | { 0073, 0377, 1, insn_dec_sp }, //"dec sp" | |
1251 | { 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ... | |
1252 | { 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)" | |
1253 | { 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n" | |
1254 | { 0020, 0377, 2, insn_djnz_d }, //"djnz dis" | |
1255 | { 0030, 0377, 2, insn_jr_d }, //"jr dis" | |
1256 | { 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis" | |
1257 | { 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction) | |
1258 | { 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction) | |
1259 | { 0122, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction) | |
1260 | { 0133, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction) | |
1261 | { 0100, 0300, 1, insn_default }, //"ld r,r", "halt" | |
1262 | { 0200, 0300, 1, insn_default }, //"alu_op a,r" | |
1263 | { 0300, 0307, 1, insn_ret_cc }, //"ret cc" | |
1264 | { 0301, 0317, 1, insn_pop_rr }, //"pop rr" | |
1265 | { 0302, 0307, 4, insn_jp_cc_nn }, //"jp cc,nn" | |
1266 | { 0303, 0377, 4, insn_jp_nn }, //"jp nn" | |
1267 | { 0304, 0307, 4, insn_call_cc_nn}, //"call cc,Mmn" | |
1268 | { 0305, 0317, 1, insn_push_rr }, //"push rr" | |
1269 | { 0306, 0307, 2, insn_default }, //"alu_op a,n" | |
1270 | { 0307, 0307, 1, insn_rst_n }, //"rst n" | |
1271 | { 0311, 0377, 1, insn_ret }, //"ret" | |
1272 | { 0313, 0377, 2, insn_default }, //CB prefix | |
1273 | { 0315, 0377, 4, insn_call_nn }, //"call Mmn" | |
1274 | { 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)" | |
1275 | { 0335, 0337, 1, insn_adl_ddfd }, //DD/FD prefix | |
1276 | { 0351, 0377, 1, insn_jp_rr }, //"jp (hl)" | |
1277 | { 0355, 0377, 1, insn_adl_ed }, //ED prefix | |
1278 | { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl" | |
1279 | { 0000, 0000, 1, insn_default } //others | |
1280 | }; | |
1281 | ||
1282 | /* ED prefix opcodes table. | |
1283 | Note the instruction length does include the ED prefix (+ 1 byte) | |
1284 | */ | |
1285 | static const struct insn_info | |
1286 | ez80_ed_insn_table[] = | |
1287 | { | |
1288 | /* eZ80 only instructions */ | |
1289 | { 0002, 0366, 2, insn_default }, //"lea rr,ii+d" | |
1290 | { 0124, 0376, 2, insn_default }, //"lea ix,iy+d", "lea iy,ix+d" | |
1291 | { 0145, 0377, 2, insn_default }, //"pea ix+d" | |
1292 | { 0146, 0377, 2, insn_default }, //"pea iy+d" | |
1293 | { 0164, 0377, 2, insn_default }, //"tstio n" | |
1294 | /* Z180/eZ80 only instructions */ | |
1295 | { 0060, 0376, 1, insn_default }, //not an instruction | |
1296 | { 0000, 0306, 2, insn_default }, //"in0 r,(n)", "out0 (n),r" | |
1297 | { 0144, 0377, 2, insn_default }, //"tst a, n" | |
1298 | /* common instructions */ | |
1299 | { 0173, 0377, 3, insn_ld_sp_6nn9 }, //"ld sp,(nn)" | |
1300 | { 0103, 0307, 3, insn_default }, //"ld (nn),rr", "ld rr,(nn)" | |
1301 | { 0105, 0317, 1, insn_ret }, //"retn", "reti" | |
1302 | { 0000, 0000, 1, insn_default } | |
1303 | }; | |
1304 | ||
1305 | static const struct insn_info | |
1306 | ez80_adl_ed_insn_table[] = | |
1307 | { | |
1308 | { 0002, 0366, 2, insn_default }, //"lea rr,ii+d" | |
1309 | { 0124, 0376, 2, insn_default }, //"lea ix,iy+d", "lea iy,ix+d" | |
1310 | { 0145, 0377, 2, insn_default }, //"pea ix+d" | |
1311 | { 0146, 0377, 2, insn_default }, //"pea iy+d" | |
1312 | { 0164, 0377, 2, insn_default }, //"tstio n" | |
1313 | { 0060, 0376, 1, insn_default }, //not an instruction | |
1314 | { 0000, 0306, 2, insn_default }, //"in0 r,(n)", "out0 (n),r" | |
1315 | { 0144, 0377, 2, insn_default }, //"tst a, n" | |
1316 | { 0173, 0377, 4, insn_ld_sp_6nn9 }, //"ld sp,(nn)" | |
1317 | { 0103, 0307, 4, insn_default }, //"ld (nn),rr", "ld rr,(nn)" | |
1318 | { 0105, 0317, 1, insn_ret }, //"retn", "reti" | |
1319 | { 0000, 0000, 1, insn_default } | |
1320 | }; | |
1321 | ||
1322 | /* table for FD and DD prefixed instructions */ | |
1323 | static const struct insn_info | |
1324 | ez80_ddfd_insn_table[] = | |
1325 | { | |
1326 | /* ez80 only instructions */ | |
1327 | { 0007, 0307, 2, insn_default }, //"ld rr,(ii+d)" | |
1328 | { 0061, 0377, 2, insn_default }, //"ld ii,(ii+d)" | |
1329 | /* common instructions */ | |
1330 | { 0011, 0367, 2, insn_default }, //"add ii,rr" | |
1331 | { 0041, 0377, 3, insn_default }, //"ld ii,nn" | |
1332 | { 0042, 0367, 3, insn_default }, //"ld (nn),ii", "ld ii,(nn)" | |
1333 | { 0043, 0367, 1, insn_default }, //"inc ii", "dec ii" | |
1334 | { 0044, 0366, 1, insn_default }, //"inc/dec iih/iil" | |
1335 | { 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n" | |
1336 | { 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)" | |
1337 | { 0066, 0377, 2, insn_default }, //"ld (ii+d),n" | |
1338 | { 0166, 0377, 0, insn_default }, //not an instruction | |
1339 | { 0160, 0370, 2, insn_default }, //"ld (ii+d),r" | |
1340 | { 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil" | |
1341 | { 0106, 0307, 2, insn_default }, //"ld r,(ii+d)" | |
1342 | { 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r" | |
1343 | { 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil" | |
1344 | { 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)" | |
1345 | { 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions | |
1346 | { 0335, 0337, 0, insn_force_nop}, //double DD/FD prefix, exec DD/FD as NOP | |
1347 | { 0341, 0373, 1, insn_default }, //"pop ii", "push ii" | |
1348 | { 0343, 0377, 1, insn_default }, //"ex (sp),ii" | |
1349 | { 0351, 0377, 1, insn_jp_rr }, //"jp (ii)" | |
1350 | { 0371, 0377, 1, insn_ld_sp_rr}, //"ld sp,ii" | |
1351 | { 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP | |
1352 | }; | |
1353 | ||
1354 | static const struct insn_info | |
1355 | ez80_adl_ddfd_insn_table[] = | |
1356 | { | |
1357 | { 0007, 0307, 2, insn_default }, //"ld rr,(ii+d)" | |
1358 | { 0061, 0377, 2, insn_default }, //"ld ii,(ii+d)" | |
1359 | { 0011, 0367, 1, insn_default }, //"add ii,rr" | |
1360 | { 0041, 0377, 4, insn_default }, //"ld ii,nn" | |
1361 | { 0042, 0367, 4, insn_default }, //"ld (nn),ii", "ld ii,(nn)" | |
1362 | { 0043, 0367, 1, insn_default }, //"inc ii", "dec ii" | |
1363 | { 0044, 0366, 1, insn_default }, //"inc/dec iih/iil" | |
1364 | { 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n" | |
1365 | { 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)" | |
1366 | { 0066, 0377, 3, insn_default }, //"ld (ii+d),n" | |
1367 | { 0166, 0377, 0, insn_default }, //not an instruction | |
1368 | { 0160, 0370, 2, insn_default }, //"ld (ii+d),r" | |
1369 | { 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil" | |
1370 | { 0106, 0307, 2, insn_default }, //"ld r,(ii+d)" | |
1371 | { 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r" | |
1372 | { 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil" | |
1373 | { 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)" | |
1374 | { 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions | |
1375 | { 0335, 0337, 0, insn_force_nop}, //double DD/FD prefix, exec DD/FD as NOP | |
1376 | { 0341, 0373, 1, insn_default }, //"pop ii", "push ii" | |
1377 | { 0343, 0377, 1, insn_default }, //"ex (sp),ii" | |
1378 | { 0351, 0377, 1, insn_jp_rr }, //"jp (ii)" | |
1379 | { 0371, 0377, 1, insn_ld_sp_rr}, //"ld sp,ii" | |
1380 | { 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP | |
1381 | }; | |
1382 | ||
1383 | /* Return pointer to instruction information structure corresponded to opcode | |
1384 | in buf. */ | |
1385 | static const struct insn_info * | |
1386 | z80_get_insn_info (struct gdbarch *gdbarch, const gdb_byte *buf, int *size) | |
1387 | { | |
1388 | int code; | |
1389 | const struct insn_info *info; | |
1390 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; | |
1391 | *size = 0; | |
1392 | switch (mach) | |
1393 | { | |
1394 | case bfd_mach_ez80_z80: | |
1395 | info = &ez80_main_insn_table[4]; /* skip force_nops */ | |
1396 | break; | |
1397 | case bfd_mach_ez80_adl: | |
1398 | info = &ez80_adl_main_insn_table[4]; /* skip force_nops */ | |
1399 | break; | |
1400 | default: | |
1401 | info = &ez80_main_insn_table[8]; /* skip eZ80 prefices and force_nops */ | |
1402 | break; | |
1403 | } | |
1404 | do | |
1405 | { | |
1406 | for (; ((code = buf[*size]) & info->mask) != info->code; ++info) | |
1407 | ; | |
1408 | *size += info->size; | |
1409 | /* process instruction type */ | |
1410 | switch (info->type) | |
1411 | { | |
1412 | case insn_z80: | |
1413 | if (mach == bfd_mach_ez80_z80 || mach == bfd_mach_ez80_adl) | |
1414 | info = &ez80_main_insn_table[0]; | |
1415 | else | |
1416 | info = &ez80_main_insn_table[8]; | |
1417 | break; | |
1418 | case insn_adl: | |
1419 | info = &ez80_adl_main_insn_table[0]; | |
1420 | break; | |
1421 | /* These two (for GameBoy Z80 & Z80 Next CPUs) haven't been tested. | |
1422 | ||
1423 | case bfd_mach_gbz80: | |
1424 | info = &gbz80_main_insn_table[0]; | |
1425 | break; | |
1426 | case bfd_mach_z80n: | |
1427 | info = &z80n_main_insn_table[0]; | |
1428 | break; | |
1429 | */ | |
1430 | case insn_z80_ddfd: | |
1431 | if (mach == bfd_mach_ez80_z80 || mach == bfd_mach_ez80_adl) | |
1432 | info = &ez80_ddfd_insn_table[0]; | |
1433 | else | |
1434 | info = &ez80_ddfd_insn_table[2]; | |
1435 | break; | |
1436 | case insn_adl_ddfd: | |
1437 | info = &ez80_adl_ddfd_insn_table[0]; | |
1438 | break; | |
1439 | case insn_z80_ed: | |
1440 | info = &ez80_ed_insn_table[0]; | |
1441 | break; | |
1442 | case insn_adl_ed: | |
1443 | info = &ez80_adl_ed_insn_table[0]; | |
1444 | break; | |
1445 | case insn_force_nop: | |
1446 | return NULL; | |
1447 | default: | |
1448 | return info; | |
1449 | } | |
1450 | } | |
1451 | while (1); | |
1452 | } | |
1453 | ||
1454 | extern initialize_file_ftype _initialize_z80_tdep; | |
1455 | ||
1456 | void | |
1457 | _initialize_z80_tdep () | |
1458 | { | |
1459 | register_gdbarch_init (bfd_arch_z80, z80_gdbarch_init); | |
1460 | initialize_tdesc_z80 (); | |
1461 | } |