Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
7cc17433 AH |
25 | #include "linux-aarch32-tdesc.h" |
26 | #include "linux-arm-tdesc.h" | |
0a30fbc4 | 27 | |
bd9e6534 | 28 | #include <sys/uio.h> |
3743bb4f DE |
29 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
30 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
31 | #ifndef ELFMAG0 | |
58d6951d | 32 | #include <elf.h> |
3743bb4f | 33 | #endif |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 35 | #include <signal.h> |
d9311bfa | 36 | #include <sys/syscall.h> |
9308fc88 | 37 | |
9308fc88 DJ |
38 | #ifndef PTRACE_GET_THREAD_AREA |
39 | #define PTRACE_GET_THREAD_AREA 22 | |
40 | #endif | |
41 | ||
fb1e4ffc DJ |
42 | #ifndef PTRACE_GETWMMXREGS |
43 | # define PTRACE_GETWMMXREGS 18 | |
44 | # define PTRACE_SETWMMXREGS 19 | |
45 | #endif | |
46 | ||
58d6951d DJ |
47 | #ifndef PTRACE_GETVFPREGS |
48 | # define PTRACE_GETVFPREGS 27 | |
49 | # define PTRACE_SETVFPREGS 28 | |
50 | #endif | |
51 | ||
09b4ad9f UW |
52 | #ifndef PTRACE_GETHBPREGS |
53 | #define PTRACE_GETHBPREGS 29 | |
54 | #define PTRACE_SETHBPREGS 30 | |
55 | #endif | |
56 | ||
ef0478f6 TBA |
57 | /* Linux target op definitions for the ARM architecture. */ |
58 | ||
59 | class arm_target : public linux_process_target | |
60 | { | |
61 | public: | |
62 | ||
aa8d21c9 TBA |
63 | const regs_info *get_regs_info () override; |
64 | ||
06250e4e TBA |
65 | int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; |
66 | ||
67 | int breakpoint_kind_from_current_state (CORE_ADDR *pcptr) override; | |
68 | ||
3ca4edb6 TBA |
69 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
70 | ||
7582c77c TBA |
71 | bool supports_software_single_step () override; |
72 | ||
007c9b97 TBA |
73 | bool supports_z_point_type (char z_type) override; |
74 | ||
797bcff5 TBA |
75 | protected: |
76 | ||
77 | void low_arch_setup () override; | |
daca57a7 TBA |
78 | |
79 | bool low_cannot_fetch_register (int regno) override; | |
80 | ||
81 | bool low_cannot_store_register (int regno) override; | |
bf9ae9d8 TBA |
82 | |
83 | bool low_supports_breakpoints () override; | |
84 | ||
85 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
86 | ||
87 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
7582c77c TBA |
88 | |
89 | std::vector<CORE_ADDR> low_get_next_pcs (regcache *regcache) override; | |
d7146cda TBA |
90 | |
91 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
92 | |
93 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
94 | int size, raw_breakpoint *bp) override; | |
95 | ||
96 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
97 | int size, raw_breakpoint *bp) override; | |
ef0478f6 TBA |
98 | }; |
99 | ||
100 | /* The singleton target ops object. */ | |
101 | ||
102 | static arm_target the_arm_target; | |
103 | ||
bf9ae9d8 TBA |
104 | bool |
105 | arm_target::low_supports_breakpoints () | |
106 | { | |
107 | return true; | |
108 | } | |
109 | ||
110 | CORE_ADDR | |
111 | arm_target::low_get_pc (regcache *regcache) | |
112 | { | |
113 | return linux_get_pc_32bit (regcache); | |
114 | } | |
115 | ||
116 | void | |
117 | arm_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
118 | { | |
119 | linux_set_pc_32bit (regcache, pc); | |
120 | } | |
121 | ||
06250e4e TBA |
122 | int |
123 | arm_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
124 | { | |
125 | return arm_breakpoint_kind_from_pc (pcptr); | |
126 | } | |
127 | ||
128 | int | |
129 | arm_target::breakpoint_kind_from_current_state (CORE_ADDR *pcptr) | |
130 | { | |
131 | return arm_breakpoint_kind_from_current_state (pcptr); | |
132 | } | |
133 | ||
3ca4edb6 TBA |
134 | const gdb_byte * |
135 | arm_target::sw_breakpoint_from_kind (int kind, int *size) | |
136 | { | |
137 | return arm_sw_breakpoint_from_kind (kind, size); | |
138 | } | |
139 | ||
d7146cda TBA |
140 | bool |
141 | arm_target::low_breakpoint_at (CORE_ADDR pc) | |
142 | { | |
143 | return arm_breakpoint_at (pc); | |
144 | } | |
145 | ||
09b4ad9f | 146 | /* Information describing the hardware breakpoint capabilities. */ |
71487fd7 | 147 | static struct |
09b4ad9f UW |
148 | { |
149 | unsigned char arch; | |
150 | unsigned char max_wp_length; | |
151 | unsigned char wp_count; | |
152 | unsigned char bp_count; | |
71487fd7 | 153 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
154 | |
155 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
156 | typedef enum | |
157 | { | |
158 | arm_hwbp_break = 0, | |
159 | arm_hwbp_load = 1, | |
160 | arm_hwbp_store = 2, | |
161 | arm_hwbp_access = 3 | |
162 | } arm_hwbp_type; | |
163 | ||
164 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
165 | typedef unsigned int arm_hwbp_control_t; | |
166 | ||
167 | /* Structure used to keep track of hardware break-/watch-points. */ | |
168 | struct arm_linux_hw_breakpoint | |
169 | { | |
170 | /* Address to break on, or being watched. */ | |
171 | unsigned int address; | |
172 | /* Control register for break-/watch- point. */ | |
173 | arm_hwbp_control_t control; | |
174 | }; | |
175 | ||
176 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
177 | assume a maximum number of supported break-/watchpoints. */ | |
178 | #define MAX_BPTS 32 | |
179 | #define MAX_WPTS 32 | |
180 | ||
181 | /* Per-process arch-specific data we want to keep. */ | |
182 | struct arch_process_info | |
183 | { | |
184 | /* Hardware breakpoints for this process. */ | |
185 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
186 | /* Hardware watchpoints for this process. */ | |
187 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
188 | }; | |
189 | ||
190 | /* Per-thread arch-specific data we want to keep. */ | |
191 | struct arch_lwp_info | |
192 | { | |
193 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
194 | char bpts_changed[MAX_BPTS]; | |
195 | char wpts_changed[MAX_WPTS]; | |
196 | /* Cached stopped data address. */ | |
197 | CORE_ADDR stopped_data_address; | |
198 | }; | |
199 | ||
58d6951d DJ |
200 | /* These are in <asm/elf.h> in current kernels. */ |
201 | #define HWCAP_VFP 64 | |
202 | #define HWCAP_IWMMXT 512 | |
203 | #define HWCAP_NEON 4096 | |
204 | #define HWCAP_VFPv3 8192 | |
205 | #define HWCAP_VFPv3D16 16384 | |
206 | ||
0a30fbc4 DJ |
207 | #ifdef HAVE_SYS_REG_H |
208 | #include <sys/reg.h> | |
209 | #endif | |
210 | ||
23ce3b1c | 211 | #define arm_num_regs 26 |
0a30fbc4 | 212 | |
2ec06d2e | 213 | static int arm_regmap[] = { |
0a30fbc4 DJ |
214 | 0, 4, 8, 12, 16, 20, 24, 28, |
215 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
216 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
217 | 64 | |
0a30fbc4 DJ |
218 | }; |
219 | ||
d9311bfa AT |
220 | /* Forward declarations needed for get_next_pcs ops. */ |
221 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
222 | int len, | |
223 | int byte_order); | |
224 | ||
225 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
226 | CORE_ADDR val); | |
227 | ||
553cb527 | 228 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
229 | |
230 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
231 | ||
232 | /* get_next_pcs operations. */ | |
233 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
234 | get_next_pcs_read_memory_unsigned_integer, | |
235 | get_next_pcs_syscall_next_pc, | |
236 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
237 | get_next_pcs_is_thumb, |
238 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
239 | }; |
240 | ||
daca57a7 TBA |
241 | bool |
242 | arm_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 243 | { |
2ec06d2e | 244 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
245 | } |
246 | ||
daca57a7 TBA |
247 | bool |
248 | arm_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 249 | { |
2ec06d2e | 250 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
251 | } |
252 | ||
fb1e4ffc | 253 | static void |
442ea881 | 254 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 255 | { |
7cc17433 | 256 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
257 | return; |
258 | ||
166a82be | 259 | for (int i = 0; i < 16; i++) |
442ea881 | 260 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
261 | |
262 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 263 | for (int i = 0; i < 6; i++) |
442ea881 PA |
264 | collect_register (regcache, arm_num_regs + i + 16, |
265 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
266 | } |
267 | ||
268 | static void | |
442ea881 | 269 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 270 | { |
7cc17433 | 271 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
272 | return; |
273 | ||
166a82be | 274 | for (int i = 0; i < 16; i++) |
442ea881 | 275 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
276 | |
277 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 278 | for (int i = 0; i < 6; i++) |
442ea881 PA |
279 | supply_register (regcache, arm_num_regs + i + 16, |
280 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
281 | } |
282 | ||
58d6951d | 283 | static void |
442ea881 | 284 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 285 | { |
bd9e6534 | 286 | int num; |
58d6951d | 287 | |
7cc17433 | 288 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 289 | num = 32; |
89abb039 | 290 | else |
7cc17433 AH |
291 | { |
292 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
293 | ||
294 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
295 | num = 32; | |
296 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
297 | num = 16; | |
298 | else | |
299 | return; | |
300 | } | |
58d6951d | 301 | |
bd9e6534 | 302 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
303 | } |
304 | ||
d9311bfa AT |
305 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
306 | static CORE_ADDR | |
307 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
308 | { | |
309 | return UNMAKE_THUMB_ADDR (val); | |
310 | } | |
311 | ||
58d6951d | 312 | static void |
442ea881 | 313 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 314 | { |
bd9e6534 | 315 | int num; |
58d6951d | 316 | |
7cc17433 | 317 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 318 | num = 32; |
89abb039 | 319 | else |
7cc17433 AH |
320 | { |
321 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
322 | ||
323 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
324 | num = 32; | |
325 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
326 | num = 16; | |
327 | else | |
328 | return; | |
329 | } | |
58d6951d | 330 | |
bd9e6534 | 331 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 332 | } |
fb1e4ffc | 333 | |
d9311bfa AT |
334 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
335 | static int | |
336 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
337 | { | |
338 | return arm_is_thumb_mode (); | |
339 | } | |
340 | ||
30baf67b | 341 | /* Read memory from the inferior. |
d9311bfa AT |
342 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's |
343 | read_memory_unsigned_integer. */ | |
344 | static ULONGEST | |
345 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
346 | int len, | |
347 | int byte_order) | |
348 | { | |
349 | ULONGEST res; | |
350 | ||
9e784964 | 351 | res = 0; |
694b382c AT |
352 | target_read_memory (memaddr, (unsigned char *) &res, len); |
353 | ||
d9311bfa AT |
354 | return res; |
355 | } | |
356 | ||
9308fc88 DJ |
357 | /* Fetch the thread-local storage pointer for libthread_db. */ |
358 | ||
359 | ps_err_e | |
754653a7 | 360 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 361 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
362 | { |
363 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
364 | return PS_ERR; | |
365 | ||
366 | /* IDX is the bias from the thread pointer to the beginning of the | |
367 | thread descriptor. It has to be subtracted due to implementation | |
368 | quirks in libthread_db. */ | |
369 | *base = (void *) ((char *)*base - idx); | |
370 | ||
371 | return PS_OK; | |
372 | } | |
373 | ||
09b4ad9f | 374 | |
71487fd7 UW |
375 | /* Query Hardware Breakpoint information for the target we are attached to |
376 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
377 | static void | |
378 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 379 | { |
71487fd7 | 380 | unsigned int val; |
09b4ad9f | 381 | |
71487fd7 UW |
382 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
383 | return; | |
09b4ad9f | 384 | |
71487fd7 UW |
385 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
386 | if (arm_linux_hwbp_cap.arch == 0) | |
387 | return; | |
09b4ad9f | 388 | |
71487fd7 UW |
389 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
390 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
391 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 392 | |
71487fd7 UW |
393 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
394 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
395 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
396 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
397 | } |
398 | ||
399 | /* How many hardware breakpoints are available? */ | |
400 | static int | |
401 | arm_linux_get_hw_breakpoint_count (void) | |
402 | { | |
71487fd7 | 403 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
404 | } |
405 | ||
406 | /* How many hardware watchpoints are available? */ | |
407 | static int | |
408 | arm_linux_get_hw_watchpoint_count (void) | |
409 | { | |
71487fd7 | 410 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
411 | } |
412 | ||
413 | /* Maximum length of area watched by hardware watchpoint. */ | |
414 | static int | |
415 | arm_linux_get_hw_watchpoint_max_length (void) | |
416 | { | |
71487fd7 | 417 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
418 | } |
419 | ||
420 | /* Initialize an ARM hardware break-/watch-point control register value. | |
421 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
422 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
423 | */ | |
424 | static arm_hwbp_control_t | |
425 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
426 | arm_hwbp_type hwbp_type, | |
427 | int enable) | |
428 | { | |
429 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
430 | gdb_assert (hwbp_type != arm_hwbp_break | |
431 | || ((byte_address_select & 0xfU) != 0)); | |
432 | ||
433 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
434 | } | |
435 | ||
436 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
437 | static int | |
438 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
439 | { | |
440 | return control & 0x1; | |
441 | } | |
442 | ||
443 | /* Is the breakpoint control value CONTROL initialized? */ | |
444 | static int | |
445 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
446 | { | |
447 | return control != 0; | |
448 | } | |
449 | ||
450 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
451 | static arm_hwbp_control_t | |
452 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
453 | { | |
454 | return control & ~0x1; | |
455 | } | |
456 | ||
457 | /* Are two break-/watch-points equal? */ | |
458 | static int | |
459 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
460 | const struct arm_linux_hw_breakpoint *p2) | |
461 | { | |
462 | return p1->address == p2->address && p1->control == p2->control; | |
463 | } | |
464 | ||
802e8e6d PA |
465 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
466 | ||
171de4b8 | 467 | static arm_hwbp_type |
802e8e6d PA |
468 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
469 | { | |
470 | switch (raw_type) | |
471 | { | |
472 | case raw_bkpt_type_hw: | |
473 | return arm_hwbp_break; | |
474 | case raw_bkpt_type_write_wp: | |
475 | return arm_hwbp_store; | |
476 | case raw_bkpt_type_read_wp: | |
477 | return arm_hwbp_load; | |
478 | case raw_bkpt_type_access_wp: | |
479 | return arm_hwbp_access; | |
480 | default: | |
481 | gdb_assert_not_reached ("unhandled raw type"); | |
482 | } | |
483 | } | |
484 | ||
09b4ad9f UW |
485 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
486 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
487 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
488 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
489 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 490 | static int |
802e8e6d PA |
491 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
492 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
493 | { |
494 | arm_hwbp_type hwbp_type; | |
495 | unsigned mask; | |
496 | ||
802e8e6d | 497 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
498 | |
499 | if (hwbp_type == arm_hwbp_break) | |
500 | { | |
501 | /* For breakpoints, the length field encodes the mode. */ | |
502 | switch (len) | |
503 | { | |
504 | case 2: /* 16-bit Thumb mode breakpoint */ | |
505 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
506 | mask = 0x3; |
507 | addr &= ~1; | |
09b4ad9f UW |
508 | break; |
509 | case 4: /* 32-bit ARM mode breakpoint */ | |
510 | mask = 0xf; | |
fcf303ab | 511 | addr &= ~3; |
09b4ad9f UW |
512 | break; |
513 | default: | |
514 | /* Unsupported. */ | |
b62e2b27 | 515 | return -2; |
09b4ad9f | 516 | } |
09b4ad9f UW |
517 | } |
518 | else | |
519 | { | |
520 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
521 | CORE_ADDR aligned_addr; | |
522 | ||
523 | /* Can not set watchpoints for zero or negative lengths. */ | |
524 | if (len <= 0) | |
b62e2b27 | 525 | return -2; |
09b4ad9f UW |
526 | /* The current ptrace interface can only handle watchpoints that are a |
527 | power of 2. */ | |
528 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 529 | return -2; |
09b4ad9f UW |
530 | |
531 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
532 | range covered by a watchpoint. */ | |
533 | aligned_addr = addr & ~(max_wp_length - 1); | |
534 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 535 | return -2; |
09b4ad9f UW |
536 | |
537 | mask = (1 << len) - 1; | |
538 | } | |
539 | ||
540 | p->address = (unsigned int) addr; | |
541 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
542 | ||
543 | return hwbp_type != arm_hwbp_break; | |
544 | } | |
545 | ||
546 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
547 | the current process. */ | |
548 | ||
00192f77 SM |
549 | static void |
550 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 551 | { |
d86d4aaf | 552 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 553 | |
00192f77 SM |
554 | /* The actual update is done later just before resuming the lwp, |
555 | we just mark that the registers need updating. */ | |
556 | if (watch) | |
557 | lwp->arch_private->wpts_changed[i] = 1; | |
558 | else | |
559 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 560 | |
00192f77 SM |
561 | /* If the lwp isn't stopped, force it to momentarily pause, so |
562 | we can update its breakpoint registers. */ | |
563 | if (!lwp->stopped) | |
564 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
565 | } |
566 | ||
007c9b97 TBA |
567 | bool |
568 | arm_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
569 | { |
570 | switch (z_type) | |
571 | { | |
abeead09 | 572 | case Z_PACKET_SW_BP: |
802e8e6d PA |
573 | case Z_PACKET_HW_BP: |
574 | case Z_PACKET_WRITE_WP: | |
575 | case Z_PACKET_READ_WP: | |
576 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 577 | return true; |
802e8e6d PA |
578 | default: |
579 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
007c9b97 | 580 | return false; |
802e8e6d PA |
581 | } |
582 | } | |
583 | ||
09b4ad9f | 584 | /* Insert hardware break-/watchpoint. */ |
9db9aa23 TBA |
585 | int |
586 | arm_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
587 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
588 | { |
589 | struct process_info *proc = current_process (); | |
590 | struct arm_linux_hw_breakpoint p, *pts; | |
591 | int watch, i, count; | |
592 | ||
593 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
594 | if (watch < 0) | |
595 | { | |
596 | /* Unsupported. */ | |
b62e2b27 | 597 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
598 | } |
599 | ||
600 | if (watch) | |
601 | { | |
602 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 603 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
604 | } |
605 | else | |
606 | { | |
607 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 608 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
609 | } |
610 | ||
611 | for (i = 0; i < count; i++) | |
612 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
613 | { | |
09b4ad9f | 614 | pts[i] = p; |
00192f77 SM |
615 | |
616 | /* Only update the threads of the current process. */ | |
617 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
618 | { | |
619 | update_registers_callback (thread, watch, i); | |
620 | }); | |
621 | ||
09b4ad9f UW |
622 | return 0; |
623 | } | |
624 | ||
625 | /* We're out of watchpoints. */ | |
626 | return -1; | |
627 | } | |
628 | ||
629 | /* Remove hardware break-/watchpoint. */ | |
9db9aa23 TBA |
630 | int |
631 | arm_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
632 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
633 | { |
634 | struct process_info *proc = current_process (); | |
635 | struct arm_linux_hw_breakpoint p, *pts; | |
636 | int watch, i, count; | |
637 | ||
638 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
639 | if (watch < 0) | |
640 | { | |
641 | /* Unsupported. */ | |
642 | return -1; | |
643 | } | |
644 | ||
645 | if (watch) | |
646 | { | |
647 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 648 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
649 | } |
650 | else | |
651 | { | |
652 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 653 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
654 | } |
655 | ||
656 | for (i = 0; i < count; i++) | |
657 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
658 | { | |
09b4ad9f | 659 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
660 | |
661 | /* Only update the threads of the current process. */ | |
662 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
663 | { | |
664 | update_registers_callback (thread, watch, i); | |
665 | }); | |
666 | ||
09b4ad9f UW |
667 | return 0; |
668 | } | |
669 | ||
670 | /* No watchpoint matched. */ | |
671 | return -1; | |
672 | } | |
673 | ||
674 | /* Return whether current thread is stopped due to a watchpoint. */ | |
675 | static int | |
676 | arm_stopped_by_watchpoint (void) | |
677 | { | |
0bfdf32f | 678 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 679 | siginfo_t siginfo; |
09b4ad9f UW |
680 | |
681 | /* We must be able to set hardware watchpoints. */ | |
682 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
683 | return 0; | |
684 | ||
685 | /* Retrieve siginfo. */ | |
686 | errno = 0; | |
0bfdf32f | 687 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
688 | if (errno != 0) |
689 | return 0; | |
690 | ||
691 | /* This must be a hardware breakpoint. */ | |
692 | if (siginfo.si_signo != SIGTRAP | |
693 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
694 | return 0; | |
695 | ||
696 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
697 | a watchpoint. */ | |
698 | if (siginfo.si_errno >= 0) | |
699 | return 0; | |
700 | ||
701 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
702 | lwp->arch_private->stopped_data_address | |
703 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
704 | ||
705 | return 1; | |
706 | } | |
707 | ||
708 | /* Return data address that triggered watchpoint. Called only if | |
709 | arm_stopped_by_watchpoint returned true. */ | |
710 | static CORE_ADDR | |
711 | arm_stopped_data_address (void) | |
712 | { | |
0bfdf32f | 713 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
714 | return lwp->arch_private->stopped_data_address; |
715 | } | |
716 | ||
717 | /* Called when a new process is created. */ | |
718 | static struct arch_process_info * | |
719 | arm_new_process (void) | |
720 | { | |
8d749320 | 721 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
722 | return info; |
723 | } | |
724 | ||
04ec7890 SM |
725 | /* Called when a process is being deleted. */ |
726 | ||
727 | static void | |
728 | arm_delete_process (struct arch_process_info *info) | |
729 | { | |
730 | xfree (info); | |
731 | } | |
732 | ||
09b4ad9f | 733 | /* Called when a new thread is detected. */ |
34c703da GB |
734 | static void |
735 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f | 736 | { |
8d749320 | 737 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
738 | int i; |
739 | ||
740 | for (i = 0; i < MAX_BPTS; i++) | |
741 | info->bpts_changed[i] = 1; | |
742 | for (i = 0; i < MAX_WPTS; i++) | |
743 | info->wpts_changed[i] = 1; | |
744 | ||
34c703da | 745 | lwp->arch_private = info; |
09b4ad9f UW |
746 | } |
747 | ||
466eecee SM |
748 | /* Function to call when a thread is being deleted. */ |
749 | ||
750 | static void | |
751 | arm_delete_thread (struct arch_lwp_info *arch_lwp) | |
752 | { | |
753 | xfree (arch_lwp); | |
754 | } | |
755 | ||
3a8a0396 DB |
756 | static void |
757 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
758 | { | |
69291610 HW |
759 | struct arch_process_info *parent_proc_info; |
760 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
761 | struct lwp_info *child_lwp; |
762 | struct arch_lwp_info *child_lwp_info; | |
763 | int i; | |
764 | ||
765 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
766 | gdb_assert (parent->priv != NULL |
767 | && parent->priv->arch_private != NULL); | |
768 | gdb_assert (child->priv != NULL | |
769 | && child->priv->arch_private != NULL); | |
3a8a0396 | 770 | |
69291610 HW |
771 | parent_proc_info = parent->priv->arch_private; |
772 | child_proc_info = child->priv->arch_private; | |
773 | ||
3a8a0396 DB |
774 | /* Linux kernel before 2.6.33 commit |
775 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
776 | will inherit hardware debug registers from parent | |
777 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
778 | zeroed debug registers. | |
779 | ||
780 | GDB core assumes the child inherits the watchpoints/hw | |
781 | breakpoints of the parent, and will remove them all from the | |
782 | forked off process. Copy the debug registers mirrors into the | |
783 | new process so that all breakpoints and watchpoints can be | |
784 | removed together. The debug registers mirror will become zeroed | |
785 | in the end before detaching the forked off process, thus making | |
786 | this compatible with older Linux kernels too. */ | |
787 | ||
788 | *child_proc_info = *parent_proc_info; | |
789 | ||
790 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
791 | make sure that the registers will be updated. */ | |
9179355e | 792 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
793 | child_lwp_info = child_lwp->arch_private; |
794 | for (i = 0; i < MAX_BPTS; i++) | |
795 | child_lwp_info->bpts_changed[i] = 1; | |
796 | for (i = 0; i < MAX_WPTS; i++) | |
797 | child_lwp_info->wpts_changed[i] = 1; | |
798 | } | |
799 | ||
09b4ad9f UW |
800 | /* Called when resuming a thread. |
801 | If the debug regs have changed, update the thread's copies. */ | |
802 | static void | |
803 | arm_prepare_to_resume (struct lwp_info *lwp) | |
804 | { | |
d86d4aaf DE |
805 | struct thread_info *thread = get_lwp_thread (lwp); |
806 | int pid = lwpid_of (thread); | |
807 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 808 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
809 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
810 | int i; | |
811 | ||
812 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
813 | if (lwp_info->bpts_changed[i]) | |
814 | { | |
815 | errno = 0; | |
816 | ||
817 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 818 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 819 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 820 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 821 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
822 | |
823 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 824 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 825 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 826 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 827 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
828 | |
829 | lwp_info->bpts_changed[i] = 0; | |
830 | } | |
831 | ||
832 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
833 | if (lwp_info->wpts_changed[i]) | |
834 | { | |
835 | errno = 0; | |
836 | ||
837 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 838 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 839 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 840 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 841 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
842 | |
843 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 844 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 845 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 846 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 847 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
848 | |
849 | lwp_info->wpts_changed[i] = 0; | |
850 | } | |
851 | } | |
852 | ||
f7a6a40d YQ |
853 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
854 | addition, set IS_THUMB depending on whether we will return to ARM | |
855 | or Thumb code. | |
d9311bfa AT |
856 | See arm-linux.h for stack layout details. */ |
857 | static CORE_ADDR | |
f7a6a40d YQ |
858 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
859 | int *is_thumb) | |
d9311bfa AT |
860 | { |
861 | unsigned long sp; | |
862 | unsigned long sp_data; | |
863 | /* Offset of PC register. */ | |
864 | int pc_offset = 0; | |
865 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 866 | uint32_t cpsr; |
d9311bfa AT |
867 | |
868 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
869 | ||
870 | collect_register_by_name (regcache, "sp", &sp); | |
52405d85 | 871 | the_target->read_memory (sp, (unsigned char *) &sp_data, 4); |
d9311bfa AT |
872 | |
873 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
874 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
875 | ||
52405d85 | 876 | the_target->read_memory (sp + pc_offset, (unsigned char *) &next_pc, 4); |
d9311bfa | 877 | |
f7a6a40d | 878 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
52405d85 | 879 | the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); |
f7a6a40d YQ |
880 | *is_thumb = ((cpsr & CPSR_T) != 0); |
881 | ||
d9311bfa AT |
882 | return next_pc; |
883 | } | |
884 | ||
885 | /* When PC is at a syscall instruction, return the PC of the next | |
886 | instruction to be executed. */ | |
887 | static CORE_ADDR | |
553cb527 | 888 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
889 | { |
890 | CORE_ADDR next_pc = 0; | |
553cb527 | 891 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
892 | int is_thumb = arm_is_thumb_mode (); |
893 | ULONGEST svc_number = 0; | |
894 | struct regcache *regcache = self->regcache; | |
895 | ||
896 | if (is_thumb) | |
897 | { | |
898 | collect_register (regcache, 7, &svc_number); | |
899 | next_pc = pc + 2; | |
900 | } | |
901 | else | |
902 | { | |
903 | unsigned long this_instr; | |
904 | unsigned long svc_operand; | |
905 | ||
694b382c | 906 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
907 | svc_operand = (0x00ffffff & this_instr); |
908 | ||
909 | if (svc_operand) /* OABI. */ | |
910 | { | |
911 | svc_number = svc_operand - 0x900000; | |
912 | } | |
913 | else /* EABI. */ | |
914 | { | |
915 | collect_register (regcache, 7, &svc_number); | |
916 | } | |
917 | ||
918 | next_pc = pc + 4; | |
919 | } | |
920 | ||
921 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
922 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
923 | { | |
f7a6a40d YQ |
924 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
925 | update IS_THUMB. */ | |
926 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
927 | } |
928 | ||
929 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
930 | if (is_thumb) | |
931 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
932 | ||
933 | return next_pc; | |
934 | } | |
09b4ad9f | 935 | |
3aee8918 PA |
936 | static const struct target_desc * |
937 | arm_read_description (void) | |
58d6951d | 938 | { |
974c89e0 | 939 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 940 | |
58d6951d | 941 | if (arm_hwcap & HWCAP_IWMMXT) |
7cc17433 | 942 | return arm_linux_read_description (ARM_FP_TYPE_IWMMXT); |
58d6951d DJ |
943 | |
944 | if (arm_hwcap & HWCAP_VFP) | |
945 | { | |
166a82be AH |
946 | /* Make sure that the kernel supports reading VFP registers. Support was |
947 | added in 2.6.30. */ | |
948 | int pid = lwpid_of (current_thread); | |
949 | errno = 0; | |
950 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
951 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
7cc17433 | 952 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
953 | |
954 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
955 | it with VFP. */ | |
956 | if (arm_hwcap & HWCAP_NEON) | |
7cc17433 | 957 | return aarch32_linux_read_description (); |
58d6951d | 958 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
7cc17433 | 959 | return arm_linux_read_description (ARM_FP_TYPE_VFPV3); |
58d6951d | 960 | else |
7cc17433 | 961 | return arm_linux_read_description (ARM_FP_TYPE_VFPV2); |
58d6951d DJ |
962 | } |
963 | ||
964 | /* The default configuration uses legacy FPA registers, probably | |
965 | simulated. */ | |
7cc17433 | 966 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
967 | } |
968 | ||
797bcff5 TBA |
969 | void |
970 | arm_target::low_arch_setup () | |
3aee8918 | 971 | { |
bd9e6534 YQ |
972 | int tid = lwpid_of (current_thread); |
973 | int gpregs[18]; | |
974 | struct iovec iov; | |
975 | ||
166a82be AH |
976 | /* Query hardware watchpoint/breakpoint capabilities. */ |
977 | arm_linux_init_hwbp_cap (tid); | |
978 | ||
3aee8918 | 979 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
980 | |
981 | iov.iov_base = gpregs; | |
982 | iov.iov_len = sizeof (gpregs); | |
983 | ||
984 | /* Check if PTRACE_GETREGSET works. */ | |
985 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
986 | have_ptrace_getregset = 1; | |
987 | else | |
988 | have_ptrace_getregset = 0; | |
3aee8918 PA |
989 | } |
990 | ||
7582c77c TBA |
991 | bool |
992 | arm_target::supports_software_single_step () | |
993 | { | |
994 | return true; | |
995 | } | |
996 | ||
d9311bfa AT |
997 | /* Fetch the next possible PCs after the current instruction executes. */ |
998 | ||
7582c77c TBA |
999 | std::vector<CORE_ADDR> |
1000 | arm_target::low_get_next_pcs (regcache *regcache) | |
d9311bfa AT |
1001 | { |
1002 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
1003 | |
1004 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
1005 | &get_next_pcs_ops, | |
1006 | /* Byte order is ignored assumed as host. */ | |
1007 | 0, | |
1008 | 0, | |
1b451dda | 1009 | 1, |
d9311bfa AT |
1010 | regcache); |
1011 | ||
a0ff9e1a | 1012 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
1013 | } |
1014 | ||
7d00775e AT |
1015 | /* Support for hardware single step. */ |
1016 | ||
1017 | static int | |
1018 | arm_supports_hardware_single_step (void) | |
1019 | { | |
1020 | return 0; | |
1021 | } | |
1022 | ||
79e7fd4f YQ |
1023 | /* Implementation of linux_target_ops method "get_syscall_trapinfo". */ |
1024 | ||
1025 | static void | |
1026 | arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) | |
1027 | { | |
1028 | if (arm_is_thumb_mode ()) | |
1029 | collect_register_by_name (regcache, "r7", sysno); | |
1030 | else | |
1031 | { | |
1032 | unsigned long pc; | |
1033 | unsigned long insn; | |
1034 | ||
1035 | collect_register_by_name (regcache, "pc", &pc); | |
1036 | ||
52405d85 | 1037 | if (the_target->read_memory (pc - 4, (unsigned char *) &insn, 4)) |
79e7fd4f YQ |
1038 | *sysno = UNKNOWN_SYSCALL; |
1039 | else | |
1040 | { | |
1041 | unsigned long svc_operand = (0x00ffffff & insn); | |
1042 | ||
1043 | if (svc_operand) | |
1044 | { | |
1045 | /* OABI */ | |
1046 | *sysno = svc_operand - 0x900000; | |
1047 | } | |
1048 | else | |
1049 | { | |
1050 | /* EABI */ | |
1051 | collect_register_by_name (regcache, "r7", sysno); | |
1052 | } | |
1053 | } | |
1054 | } | |
1055 | } | |
1056 | ||
bd9e6534 YQ |
1057 | /* Register sets without using PTRACE_GETREGSET. */ |
1058 | ||
3aee8918 | 1059 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
1060 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
1061 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 1062 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 1063 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 1064 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 1065 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 1066 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 1067 | NULL_REGSET |
fb1e4ffc DJ |
1068 | }; |
1069 | ||
3aee8918 PA |
1070 | static struct regsets_info arm_regsets_info = |
1071 | { | |
1072 | arm_regsets, /* regsets */ | |
1073 | 0, /* num_regsets */ | |
1074 | NULL, /* disabled_regsets */ | |
1075 | }; | |
1076 | ||
1077 | static struct usrregs_info arm_usrregs_info = | |
1078 | { | |
1079 | arm_num_regs, | |
1080 | arm_regmap, | |
1081 | }; | |
1082 | ||
bd9e6534 | 1083 | static struct regs_info regs_info_arm = |
3aee8918 PA |
1084 | { |
1085 | NULL, /* regset_bitmap */ | |
1086 | &arm_usrregs_info, | |
1087 | &arm_regsets_info | |
1088 | }; | |
1089 | ||
aa8d21c9 TBA |
1090 | const regs_info * |
1091 | arm_target::get_regs_info () | |
3aee8918 | 1092 | { |
bd9e6534 YQ |
1093 | const struct target_desc *tdesc = current_process ()->tdesc; |
1094 | ||
1095 | if (have_ptrace_getregset == 1 | |
7cc17433 AH |
1096 | && (is_aarch32_linux_description (tdesc) |
1097 | || arm_linux_get_tdesc_fp_type (tdesc) == ARM_FP_TYPE_VFPV3)) | |
bd9e6534 | 1098 | return ®s_info_aarch32; |
7cc17433 AH |
1099 | |
1100 | return ®s_info_arm; | |
3aee8918 PA |
1101 | } |
1102 | ||
dd373349 | 1103 | struct linux_target_ops the_low_target = { |
09b4ad9f UW |
1104 | arm_stopped_by_watchpoint, |
1105 | arm_stopped_data_address, | |
1106 | NULL, /* collect_ptrace_register */ | |
1107 | NULL, /* supply_ptrace_register */ | |
1108 | NULL, /* siginfo_fixup */ | |
1109 | arm_new_process, | |
04ec7890 | 1110 | arm_delete_process, |
09b4ad9f | 1111 | arm_new_thread, |
466eecee | 1112 | arm_delete_thread, |
3a8a0396 | 1113 | arm_new_fork, |
09b4ad9f | 1114 | arm_prepare_to_resume, |
769ef81f AT |
1115 | NULL, /* process_qsupported */ |
1116 | NULL, /* supports_tracepoints */ | |
1117 | NULL, /* get_thread_area */ | |
1118 | NULL, /* install_fast_tracepoint_jump_pad */ | |
1119 | NULL, /* emit_ops */ | |
1120 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
1121 | NULL, /* supports_range_stepping */ | |
79e7fd4f YQ |
1122 | arm_supports_hardware_single_step, |
1123 | arm_get_syscall_trapinfo, | |
2ec06d2e | 1124 | }; |
3aee8918 | 1125 | |
ef0478f6 TBA |
1126 | /* The linux target ops object. */ |
1127 | ||
1128 | linux_process_target *the_linux_target = &the_arm_target; | |
1129 | ||
3aee8918 PA |
1130 | void |
1131 | initialize_low_arch (void) | |
1132 | { | |
bd9e6534 | 1133 | initialize_low_arch_aarch32 (); |
3aee8918 PA |
1134 | initialize_regsets_info (&arm_regsets_info); |
1135 | } |