Commit | Line | Data |
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45b134e5 | 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
45b134e5 OF |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
45b134e5 OF |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
45b134e5 OF |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
5826e159 | 21 | #include "nat/gdb_ptrace.h" |
45b134e5 | 22 | |
ef0478f6 TBA |
23 | /* Linux target op definitions for the CRIS architecture. */ |
24 | ||
25 | class crisv32_target : public linux_process_target | |
26 | { | |
27 | public: | |
28 | ||
797bcff5 TBA |
29 | protected: |
30 | ||
31 | void low_arch_setup () override; | |
ef0478f6 TBA |
32 | }; |
33 | ||
34 | /* The singleton target ops object. */ | |
35 | ||
36 | static crisv32_target the_crisv32_target; | |
37 | ||
d05b4ac3 UW |
38 | /* Defined in auto-generated file reg-crisv32.c. */ |
39 | void init_registers_crisv32 (void); | |
3aee8918 | 40 | extern const struct target_desc *tdesc_crisv32; |
d05b4ac3 | 41 | |
45b134e5 OF |
42 | /* CRISv32 */ |
43 | #define cris_num_regs 49 | |
44 | ||
8eb3d7b6 RW |
45 | #ifndef PTRACE_GET_THREAD_AREA |
46 | #define PTRACE_GET_THREAD_AREA 25 | |
47 | #endif | |
48 | ||
45b134e5 OF |
49 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble |
50 | without any significant gain). */ | |
51 | ||
52 | /* Locations need to match <include/asm/arch/ptrace.h>. */ | |
53 | static int cris_regmap[] = { | |
54 | 1*4, 2*4, 3*4, 4*4, | |
55 | 5*4, 6*4, 7*4, 8*4, | |
56 | 9*4, 10*4, 11*4, 12*4, | |
57 | 13*4, 14*4, 24*4, 15*4, | |
58 | ||
59 | -1, -1, -1, 16*4, | |
60 | -1, 22*4, 23*4, 17*4, | |
61 | -1, -1, 21*4, 20*4, | |
62 | -1, 19*4, -1, 18*4, | |
63 | ||
64 | 25*4, | |
65 | ||
1b3f6016 | 66 | 26*4, -1, -1, 29*4, |
45b134e5 OF |
67 | 30*4, 31*4, 32*4, 33*4, |
68 | 34*4, 35*4, 36*4, 37*4, | |
69 | 38*4, 39*4, 40*4, -1 | |
1b3f6016 | 70 | |
45b134e5 OF |
71 | }; |
72 | ||
45b134e5 OF |
73 | static const unsigned short cris_breakpoint = 0xe938; |
74 | #define cris_breakpoint_len 2 | |
75 | ||
dd373349 AT |
76 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
77 | ||
78 | static const gdb_byte * | |
79 | cris_sw_breakpoint_from_kind (int kind, int *size) | |
80 | { | |
81 | *size = cris_breakpoint_len; | |
82 | return (const gdb_byte *) &cris_breakpoint; | |
83 | } | |
84 | ||
45b134e5 OF |
85 | static int |
86 | cris_breakpoint_at (CORE_ADDR where) | |
87 | { | |
88 | unsigned short insn; | |
89 | ||
52405d85 TBA |
90 | the_target->read_memory (where, (unsigned char *) &insn, |
91 | cris_breakpoint_len); | |
45b134e5 OF |
92 | if (insn == cris_breakpoint) |
93 | return 1; | |
94 | ||
95 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
96 | one. */ | |
97 | return 0; | |
98 | } | |
99 | ||
45b134e5 | 100 | static void |
442ea881 PA |
101 | cris_write_data_breakpoint (struct regcache *regcache, |
102 | int bp, unsigned long start, unsigned long end) | |
45b134e5 OF |
103 | { |
104 | switch (bp) | |
105 | { | |
106 | case 0: | |
442ea881 PA |
107 | supply_register_by_name (regcache, "s3", &start); |
108 | supply_register_by_name (regcache, "s4", &end); | |
45b134e5 OF |
109 | break; |
110 | case 1: | |
442ea881 PA |
111 | supply_register_by_name (regcache, "s5", &start); |
112 | supply_register_by_name (regcache, "s6", &end); | |
45b134e5 OF |
113 | break; |
114 | case 2: | |
442ea881 PA |
115 | supply_register_by_name (regcache, "s7", &start); |
116 | supply_register_by_name (regcache, "s8", &end); | |
45b134e5 OF |
117 | break; |
118 | case 3: | |
442ea881 PA |
119 | supply_register_by_name (regcache, "s9", &start); |
120 | supply_register_by_name (regcache, "s10", &end); | |
45b134e5 OF |
121 | break; |
122 | case 4: | |
442ea881 PA |
123 | supply_register_by_name (regcache, "s11", &start); |
124 | supply_register_by_name (regcache, "s12", &end); | |
45b134e5 OF |
125 | break; |
126 | case 5: | |
442ea881 PA |
127 | supply_register_by_name (regcache, "s13", &start); |
128 | supply_register_by_name (regcache, "s14", &end); | |
45b134e5 OF |
129 | break; |
130 | } | |
131 | } | |
132 | ||
133 | static int | |
802e8e6d PA |
134 | cris_supports_z_point_type (char z_type) |
135 | { | |
136 | switch (z_type) | |
137 | { | |
138 | case Z_PACKET_WRITE_WP: | |
139 | case Z_PACKET_READ_WP: | |
140 | case Z_PACKET_ACCESS_WP: | |
141 | return 1; | |
142 | default: | |
143 | return 0; | |
144 | } | |
145 | } | |
146 | ||
147 | static int | |
148 | cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
149 | int len, struct raw_breakpoint *bp) | |
45b134e5 OF |
150 | { |
151 | int bp; | |
152 | unsigned long bp_ctrl; | |
153 | unsigned long start, end; | |
154 | unsigned long ccs; | |
442ea881 | 155 | struct regcache *regcache; |
1b3f6016 | 156 | |
0bfdf32f | 157 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 158 | |
45b134e5 OF |
159 | /* Read watchpoints are set as access watchpoints, because of GDB's |
160 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
161 | if (type == raw_bkpt_type_read_wp) |
162 | type = raw_bkpt_type_access_wp; | |
45b134e5 OF |
163 | |
164 | /* Get the configuration register. */ | |
442ea881 | 165 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
166 | |
167 | /* The watchpoint allocation scheme is the simplest possible. | |
168 | For example, if a region is watched for read and | |
169 | a write watch is requested, a new watchpoint will | |
170 | be used. Also, if a watch for a region that is already | |
171 | covered by one or more existing watchpoints, a new | |
172 | watchpoint will be used. */ | |
1b3f6016 | 173 | |
45b134e5 OF |
174 | /* First, find a free data watchpoint. */ |
175 | for (bp = 0; bp < 6; bp++) | |
176 | { | |
177 | /* Each data watchpoint's control registers occupy 2 bits | |
178 | (hence the 3), starting at bit 2 for D0 (hence the 2) | |
179 | with 4 bits between for each watchpoint (yes, the 4). */ | |
1b3f6016 | 180 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
45b134e5 OF |
181 | break; |
182 | } | |
1b3f6016 | 183 | |
45b134e5 OF |
184 | if (bp > 5) |
185 | { | |
186 | /* We're out of watchpoints. */ | |
187 | return -1; | |
188 | } | |
189 | ||
190 | /* Configure the control register first. */ | |
802e8e6d | 191 | if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
192 | { |
193 | /* Trigger on read. */ | |
194 | bp_ctrl |= (1 << (2 + bp * 4)); | |
195 | } | |
802e8e6d | 196 | if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
197 | { |
198 | /* Trigger on write. */ | |
199 | bp_ctrl |= (2 << (2 + bp * 4)); | |
200 | } | |
1b3f6016 | 201 | |
45b134e5 | 202 | /* Setup the configuration register. */ |
442ea881 | 203 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
1b3f6016 | 204 | |
45b134e5 OF |
205 | /* Setup the range. */ |
206 | start = addr; | |
207 | end = addr + len - 1; | |
208 | ||
209 | /* Configure the watchpoint register. */ | |
442ea881 | 210 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 | 211 | |
442ea881 | 212 | collect_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
213 | /* Set the S1 flag to enable watchpoints. */ |
214 | ccs |= (1 << 19); | |
442ea881 | 215 | supply_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
216 | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static int | |
802e8e6d PA |
221 | cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len, |
222 | struct raw_breakpoint *bp) | |
45b134e5 OF |
223 | { |
224 | int bp; | |
225 | unsigned long bp_ctrl; | |
226 | unsigned long start, end; | |
442ea881 | 227 | struct regcache *regcache; |
07c04788 | 228 | unsigned long bp_d_regs[12]; |
1b3f6016 | 229 | |
0bfdf32f | 230 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 231 | |
45b134e5 OF |
232 | /* Read watchpoints are set as access watchpoints, because of GDB's |
233 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
234 | if (type == raw_bkpt_type_read_wp) |
235 | type = raw_bkpt_type_access_wp; | |
1b3f6016 | 236 | |
45b134e5 | 237 | /* Get the configuration register. */ |
442ea881 | 238 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
239 | |
240 | /* Try to find a watchpoint that is configured for the | |
241 | specified range, then check that read/write also matches. */ | |
1b3f6016 | 242 | |
45b134e5 OF |
243 | /* Ugly pointer arithmetic, since I cannot rely on a |
244 | single switch (addr) as there may be several watchpoints with | |
245 | the same start address for example. */ | |
246 | ||
45b134e5 | 247 | /* Get all range registers to simplify search. */ |
442ea881 PA |
248 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
249 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); | |
250 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); | |
251 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); | |
252 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); | |
253 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); | |
254 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); | |
255 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); | |
256 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); | |
257 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); | |
258 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); | |
259 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); | |
45b134e5 | 260 | |
1b3f6016 | 261 | for (bp = 0; bp < 6; bp++) |
45b134e5 | 262 | { |
1b3f6016 | 263 | if (bp_d_regs[bp * 2] == addr |
45b134e5 OF |
264 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
265 | /* Matching range. */ | |
266 | int bitpos = 2 + bp * 4; | |
267 | int rw_bits; | |
1b3f6016 | 268 | |
45b134e5 OF |
269 | /* Read/write bits for this BP. */ |
270 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; | |
1b3f6016 | 271 | |
802e8e6d PA |
272 | if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1) |
273 | || (type == raw_bkpt_type_write_wp && rw_bits == 0x2) | |
274 | || (type == raw_bkpt_type_access_wp && rw_bits == 0x3)) | |
45b134e5 OF |
275 | { |
276 | /* Read/write matched. */ | |
277 | break; | |
278 | } | |
279 | } | |
280 | } | |
1b3f6016 | 281 | |
45b134e5 OF |
282 | if (bp > 5) |
283 | { | |
284 | /* No watchpoint matched. */ | |
285 | return -1; | |
286 | } | |
1b3f6016 | 287 | |
45b134e5 OF |
288 | /* Found a matching watchpoint. Now, deconfigure it by |
289 | both disabling read/write in bp_ctrl and zeroing its | |
290 | start/end addresses. */ | |
291 | bp_ctrl &= ~(3 << (2 + (bp * 4))); | |
292 | /* Setup the configuration register. */ | |
442ea881 | 293 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
294 | |
295 | start = end = 0; | |
296 | /* Configure the watchpoint register. */ | |
442ea881 | 297 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 OF |
298 | |
299 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ | |
300 | return 0; | |
301 | } | |
302 | ||
303 | static int | |
304 | cris_stopped_by_watchpoint (void) | |
305 | { | |
306 | unsigned long exs; | |
0bfdf32f | 307 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 308 | |
07c04788 | 309 | collect_register_by_name (regcache, "exs", &exs); |
45b134e5 OF |
310 | |
311 | return (((exs & 0xff00) >> 8) == 0xc); | |
312 | } | |
313 | ||
314 | static CORE_ADDR | |
315 | cris_stopped_data_address (void) | |
316 | { | |
317 | unsigned long eda; | |
0bfdf32f | 318 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 319 | |
07c04788 | 320 | collect_register_by_name (regcache, "eda", &eda); |
45b134e5 OF |
321 | |
322 | /* FIXME: Possibly adjust to match watched range. */ | |
323 | return eda; | |
324 | } | |
325 | ||
8eb3d7b6 | 326 | ps_err_e |
754653a7 | 327 | ps_get_thread_area (struct ps_prochandle *ph, |
8eb3d7b6 RW |
328 | lwpid_t lwpid, int idx, void **base) |
329 | { | |
330 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
331 | return PS_ERR; | |
332 | ||
333 | /* IDX is the bias from the thread pointer to the beginning of the | |
334 | thread descriptor. It has to be subtracted due to implementation | |
335 | quirks in libthread_db. */ | |
336 | *base = (void *) ((char *) *base - idx); | |
337 | return PS_OK; | |
338 | } | |
339 | ||
45b134e5 | 340 | static void |
07c04788 | 341 | cris_fill_gregset (struct regcache *regcache, void *buf) |
45b134e5 OF |
342 | { |
343 | int i; | |
344 | ||
345 | for (i = 0; i < cris_num_regs; i++) | |
346 | { | |
347 | if (cris_regmap[i] != -1) | |
07c04788 | 348 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
349 | } |
350 | } | |
351 | ||
352 | static void | |
07c04788 | 353 | cris_store_gregset (struct regcache *regcache, const void *buf) |
45b134e5 OF |
354 | { |
355 | int i; | |
356 | ||
357 | for (i = 0; i < cris_num_regs; i++) | |
358 | { | |
359 | if (cris_regmap[i] != -1) | |
07c04788 | 360 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
361 | } |
362 | } | |
363 | ||
797bcff5 TBA |
364 | void |
365 | crisv32_target::low_arch_setup () | |
3aee8918 PA |
366 | { |
367 | current_process ()->tdesc = tdesc_crisv32; | |
368 | } | |
369 | ||
7d00775e AT |
370 | /* Support for hardware single step. */ |
371 | ||
372 | static int | |
373 | cris_supports_hardware_single_step (void) | |
374 | { | |
375 | return 1; | |
376 | } | |
377 | ||
3aee8918 | 378 | static struct regset_info cris_regsets[] = { |
07c04788 | 379 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
45b134e5 | 380 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
50bc912a | 381 | NULL_REGSET |
45b134e5 OF |
382 | }; |
383 | ||
3aee8918 PA |
384 | |
385 | static struct regsets_info cris_regsets_info = | |
386 | { | |
387 | cris_regsets, /* regsets */ | |
388 | 0, /* num_regsets */ | |
389 | NULL, /* disabled_regsets */ | |
390 | }; | |
391 | ||
392 | static struct usrregs_info cris_usrregs_info = | |
393 | { | |
394 | cris_num_regs, | |
395 | cris_regmap, | |
396 | }; | |
397 | ||
398 | static struct regs_info regs_info = | |
399 | { | |
400 | NULL, /* regset_bitmap */ | |
401 | &cris_usrregs_info, | |
402 | &cris_regsets_info | |
403 | }; | |
404 | ||
405 | static const struct regs_info * | |
406 | cris_regs_info (void) | |
407 | { | |
408 | return ®s_info; | |
409 | } | |
410 | ||
45b134e5 | 411 | struct linux_target_ops the_low_target = { |
3aee8918 | 412 | cris_regs_info, |
45b134e5 | 413 | NULL, |
1faeff08 | 414 | NULL, |
c14dfd32 | 415 | NULL, /* fetch_register */ |
276d4552 YQ |
416 | linux_get_pc_32bit, |
417 | linux_set_pc_32bit, | |
dd373349 AT |
418 | NULL, /* breakpoint_kind_from_pc */ |
419 | cris_sw_breakpoint_from_kind, | |
fa5308bd | 420 | NULL, /* get_next_pcs */ |
45b134e5 OF |
421 | 0, |
422 | cris_breakpoint_at, | |
802e8e6d | 423 | cris_supports_z_point_type, |
d993e290 PA |
424 | cris_insert_point, |
425 | cris_remove_point, | |
45b134e5 OF |
426 | cris_stopped_by_watchpoint, |
427 | cris_stopped_data_address, | |
7d00775e AT |
428 | NULL, /* collect_ptrace_register */ |
429 | NULL, /* supply_ptrace_register */ | |
430 | NULL, /* siginfo_fixup */ | |
431 | NULL, /* new_process */ | |
04ec7890 | 432 | NULL, /* delete_process */ |
7d00775e | 433 | NULL, /* new_thread */ |
466eecee | 434 | NULL, /* delete_thread */ |
7d00775e AT |
435 | NULL, /* new_fork */ |
436 | NULL, /* prepare_to_resume */ | |
437 | NULL, /* process_qsupported */ | |
438 | NULL, /* supports_tracepoints */ | |
439 | NULL, /* get_thread_area */ | |
440 | NULL, /* install_fast_tracepoint_jump_pad */ | |
441 | NULL, /* emit_ops */ | |
442 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
443 | NULL, /* supports_range_stepping */ | |
444 | NULL, /* breakpoint_kind_from_current_state */ | |
445 | cris_supports_hardware_single_step, | |
45b134e5 | 446 | }; |
3aee8918 | 447 | |
ef0478f6 TBA |
448 | /* The linux target ops object. */ |
449 | ||
450 | linux_process_target *the_linux_target = &the_crisv32_target; | |
451 | ||
3aee8918 PA |
452 | void |
453 | initialize_low_arch (void) | |
454 | { | |
eddddb9d | 455 | init_registers_crisv32 (); |
3aee8918 PA |
456 | |
457 | initialize_regsets_info (&cris_regsets_info); | |
458 | } |