Commit | Line | Data |
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45b134e5 | 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
45b134e5 OF |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
45b134e5 OF |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
45b134e5 OF |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
5826e159 | 21 | #include "nat/gdb_ptrace.h" |
45b134e5 | 22 | |
ef0478f6 TBA |
23 | /* Linux target op definitions for the CRIS architecture. */ |
24 | ||
25 | class crisv32_target : public linux_process_target | |
26 | { | |
27 | public: | |
28 | ||
aa8d21c9 TBA |
29 | const regs_info *get_regs_info () override; |
30 | ||
797bcff5 TBA |
31 | protected: |
32 | ||
33 | void low_arch_setup () override; | |
daca57a7 TBA |
34 | |
35 | bool low_cannot_fetch_register (int regno) override; | |
36 | ||
37 | bool low_cannot_store_register (int regno) override; | |
bf9ae9d8 TBA |
38 | |
39 | bool low_supports_breakpoints () override; | |
40 | ||
41 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
42 | ||
43 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
ef0478f6 TBA |
44 | }; |
45 | ||
46 | /* The singleton target ops object. */ | |
47 | ||
48 | static crisv32_target the_crisv32_target; | |
49 | ||
daca57a7 TBA |
50 | bool |
51 | crisv32_target::low_cannot_fetch_register (int regno) | |
52 | { | |
53 | gdb_assert_not_reached ("linux target op low_cannot_fetch_register " | |
54 | "is not implemented by the target"); | |
55 | } | |
56 | ||
57 | bool | |
58 | crisv32_target::low_cannot_store_register (int regno) | |
59 | { | |
60 | gdb_assert_not_reached ("linux target op low_cannot_store_register " | |
61 | "is not implemented by the target"); | |
62 | } | |
63 | ||
bf9ae9d8 TBA |
64 | bool |
65 | crisv32_target::low_supports_breakpoints () | |
66 | { | |
67 | return true; | |
68 | } | |
69 | ||
70 | CORE_ADDR | |
71 | crisv32_target::low_get_pc (regcache *regcache) | |
72 | { | |
73 | return linux_get_pc_32bit (regcache); | |
74 | } | |
75 | ||
76 | void | |
77 | crisv32_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
78 | { | |
79 | linux_set_pc_32bit (regcache, pc); | |
80 | } | |
81 | ||
d05b4ac3 UW |
82 | /* Defined in auto-generated file reg-crisv32.c. */ |
83 | void init_registers_crisv32 (void); | |
3aee8918 | 84 | extern const struct target_desc *tdesc_crisv32; |
d05b4ac3 | 85 | |
45b134e5 OF |
86 | /* CRISv32 */ |
87 | #define cris_num_regs 49 | |
88 | ||
8eb3d7b6 RW |
89 | #ifndef PTRACE_GET_THREAD_AREA |
90 | #define PTRACE_GET_THREAD_AREA 25 | |
91 | #endif | |
92 | ||
45b134e5 OF |
93 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble |
94 | without any significant gain). */ | |
95 | ||
96 | /* Locations need to match <include/asm/arch/ptrace.h>. */ | |
97 | static int cris_regmap[] = { | |
98 | 1*4, 2*4, 3*4, 4*4, | |
99 | 5*4, 6*4, 7*4, 8*4, | |
100 | 9*4, 10*4, 11*4, 12*4, | |
101 | 13*4, 14*4, 24*4, 15*4, | |
102 | ||
103 | -1, -1, -1, 16*4, | |
104 | -1, 22*4, 23*4, 17*4, | |
105 | -1, -1, 21*4, 20*4, | |
106 | -1, 19*4, -1, 18*4, | |
107 | ||
108 | 25*4, | |
109 | ||
1b3f6016 | 110 | 26*4, -1, -1, 29*4, |
45b134e5 OF |
111 | 30*4, 31*4, 32*4, 33*4, |
112 | 34*4, 35*4, 36*4, 37*4, | |
113 | 38*4, 39*4, 40*4, -1 | |
1b3f6016 | 114 | |
45b134e5 OF |
115 | }; |
116 | ||
45b134e5 OF |
117 | static const unsigned short cris_breakpoint = 0xe938; |
118 | #define cris_breakpoint_len 2 | |
119 | ||
dd373349 AT |
120 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
121 | ||
122 | static const gdb_byte * | |
123 | cris_sw_breakpoint_from_kind (int kind, int *size) | |
124 | { | |
125 | *size = cris_breakpoint_len; | |
126 | return (const gdb_byte *) &cris_breakpoint; | |
127 | } | |
128 | ||
45b134e5 OF |
129 | static int |
130 | cris_breakpoint_at (CORE_ADDR where) | |
131 | { | |
132 | unsigned short insn; | |
133 | ||
52405d85 TBA |
134 | the_target->read_memory (where, (unsigned char *) &insn, |
135 | cris_breakpoint_len); | |
45b134e5 OF |
136 | if (insn == cris_breakpoint) |
137 | return 1; | |
138 | ||
139 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
140 | one. */ | |
141 | return 0; | |
142 | } | |
143 | ||
45b134e5 | 144 | static void |
442ea881 PA |
145 | cris_write_data_breakpoint (struct regcache *regcache, |
146 | int bp, unsigned long start, unsigned long end) | |
45b134e5 OF |
147 | { |
148 | switch (bp) | |
149 | { | |
150 | case 0: | |
442ea881 PA |
151 | supply_register_by_name (regcache, "s3", &start); |
152 | supply_register_by_name (regcache, "s4", &end); | |
45b134e5 OF |
153 | break; |
154 | case 1: | |
442ea881 PA |
155 | supply_register_by_name (regcache, "s5", &start); |
156 | supply_register_by_name (regcache, "s6", &end); | |
45b134e5 OF |
157 | break; |
158 | case 2: | |
442ea881 PA |
159 | supply_register_by_name (regcache, "s7", &start); |
160 | supply_register_by_name (regcache, "s8", &end); | |
45b134e5 OF |
161 | break; |
162 | case 3: | |
442ea881 PA |
163 | supply_register_by_name (regcache, "s9", &start); |
164 | supply_register_by_name (regcache, "s10", &end); | |
45b134e5 OF |
165 | break; |
166 | case 4: | |
442ea881 PA |
167 | supply_register_by_name (regcache, "s11", &start); |
168 | supply_register_by_name (regcache, "s12", &end); | |
45b134e5 OF |
169 | break; |
170 | case 5: | |
442ea881 PA |
171 | supply_register_by_name (regcache, "s13", &start); |
172 | supply_register_by_name (regcache, "s14", &end); | |
45b134e5 OF |
173 | break; |
174 | } | |
175 | } | |
176 | ||
177 | static int | |
802e8e6d PA |
178 | cris_supports_z_point_type (char z_type) |
179 | { | |
180 | switch (z_type) | |
181 | { | |
182 | case Z_PACKET_WRITE_WP: | |
183 | case Z_PACKET_READ_WP: | |
184 | case Z_PACKET_ACCESS_WP: | |
185 | return 1; | |
186 | default: | |
187 | return 0; | |
188 | } | |
189 | } | |
190 | ||
191 | static int | |
192 | cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
193 | int len, struct raw_breakpoint *bp) | |
45b134e5 OF |
194 | { |
195 | int bp; | |
196 | unsigned long bp_ctrl; | |
197 | unsigned long start, end; | |
198 | unsigned long ccs; | |
442ea881 | 199 | struct regcache *regcache; |
1b3f6016 | 200 | |
0bfdf32f | 201 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 202 | |
45b134e5 OF |
203 | /* Read watchpoints are set as access watchpoints, because of GDB's |
204 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
205 | if (type == raw_bkpt_type_read_wp) |
206 | type = raw_bkpt_type_access_wp; | |
45b134e5 OF |
207 | |
208 | /* Get the configuration register. */ | |
442ea881 | 209 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
210 | |
211 | /* The watchpoint allocation scheme is the simplest possible. | |
212 | For example, if a region is watched for read and | |
213 | a write watch is requested, a new watchpoint will | |
214 | be used. Also, if a watch for a region that is already | |
215 | covered by one or more existing watchpoints, a new | |
216 | watchpoint will be used. */ | |
1b3f6016 | 217 | |
45b134e5 OF |
218 | /* First, find a free data watchpoint. */ |
219 | for (bp = 0; bp < 6; bp++) | |
220 | { | |
221 | /* Each data watchpoint's control registers occupy 2 bits | |
222 | (hence the 3), starting at bit 2 for D0 (hence the 2) | |
223 | with 4 bits between for each watchpoint (yes, the 4). */ | |
1b3f6016 | 224 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
45b134e5 OF |
225 | break; |
226 | } | |
1b3f6016 | 227 | |
45b134e5 OF |
228 | if (bp > 5) |
229 | { | |
230 | /* We're out of watchpoints. */ | |
231 | return -1; | |
232 | } | |
233 | ||
234 | /* Configure the control register first. */ | |
802e8e6d | 235 | if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
236 | { |
237 | /* Trigger on read. */ | |
238 | bp_ctrl |= (1 << (2 + bp * 4)); | |
239 | } | |
802e8e6d | 240 | if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
241 | { |
242 | /* Trigger on write. */ | |
243 | bp_ctrl |= (2 << (2 + bp * 4)); | |
244 | } | |
1b3f6016 | 245 | |
45b134e5 | 246 | /* Setup the configuration register. */ |
442ea881 | 247 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
1b3f6016 | 248 | |
45b134e5 OF |
249 | /* Setup the range. */ |
250 | start = addr; | |
251 | end = addr + len - 1; | |
252 | ||
253 | /* Configure the watchpoint register. */ | |
442ea881 | 254 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 | 255 | |
442ea881 | 256 | collect_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
257 | /* Set the S1 flag to enable watchpoints. */ |
258 | ccs |= (1 << 19); | |
442ea881 | 259 | supply_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
260 | |
261 | return 0; | |
262 | } | |
263 | ||
264 | static int | |
802e8e6d PA |
265 | cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len, |
266 | struct raw_breakpoint *bp) | |
45b134e5 OF |
267 | { |
268 | int bp; | |
269 | unsigned long bp_ctrl; | |
270 | unsigned long start, end; | |
442ea881 | 271 | struct regcache *regcache; |
07c04788 | 272 | unsigned long bp_d_regs[12]; |
1b3f6016 | 273 | |
0bfdf32f | 274 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 275 | |
45b134e5 OF |
276 | /* Read watchpoints are set as access watchpoints, because of GDB's |
277 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
278 | if (type == raw_bkpt_type_read_wp) |
279 | type = raw_bkpt_type_access_wp; | |
1b3f6016 | 280 | |
45b134e5 | 281 | /* Get the configuration register. */ |
442ea881 | 282 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
283 | |
284 | /* Try to find a watchpoint that is configured for the | |
285 | specified range, then check that read/write also matches. */ | |
1b3f6016 | 286 | |
45b134e5 OF |
287 | /* Ugly pointer arithmetic, since I cannot rely on a |
288 | single switch (addr) as there may be several watchpoints with | |
289 | the same start address for example. */ | |
290 | ||
45b134e5 | 291 | /* Get all range registers to simplify search. */ |
442ea881 PA |
292 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
293 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); | |
294 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); | |
295 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); | |
296 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); | |
297 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); | |
298 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); | |
299 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); | |
300 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); | |
301 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); | |
302 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); | |
303 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); | |
45b134e5 | 304 | |
1b3f6016 | 305 | for (bp = 0; bp < 6; bp++) |
45b134e5 | 306 | { |
1b3f6016 | 307 | if (bp_d_regs[bp * 2] == addr |
45b134e5 OF |
308 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
309 | /* Matching range. */ | |
310 | int bitpos = 2 + bp * 4; | |
311 | int rw_bits; | |
1b3f6016 | 312 | |
45b134e5 OF |
313 | /* Read/write bits for this BP. */ |
314 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; | |
1b3f6016 | 315 | |
802e8e6d PA |
316 | if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1) |
317 | || (type == raw_bkpt_type_write_wp && rw_bits == 0x2) | |
318 | || (type == raw_bkpt_type_access_wp && rw_bits == 0x3)) | |
45b134e5 OF |
319 | { |
320 | /* Read/write matched. */ | |
321 | break; | |
322 | } | |
323 | } | |
324 | } | |
1b3f6016 | 325 | |
45b134e5 OF |
326 | if (bp > 5) |
327 | { | |
328 | /* No watchpoint matched. */ | |
329 | return -1; | |
330 | } | |
1b3f6016 | 331 | |
45b134e5 OF |
332 | /* Found a matching watchpoint. Now, deconfigure it by |
333 | both disabling read/write in bp_ctrl and zeroing its | |
334 | start/end addresses. */ | |
335 | bp_ctrl &= ~(3 << (2 + (bp * 4))); | |
336 | /* Setup the configuration register. */ | |
442ea881 | 337 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
338 | |
339 | start = end = 0; | |
340 | /* Configure the watchpoint register. */ | |
442ea881 | 341 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 OF |
342 | |
343 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static int | |
348 | cris_stopped_by_watchpoint (void) | |
349 | { | |
350 | unsigned long exs; | |
0bfdf32f | 351 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 352 | |
07c04788 | 353 | collect_register_by_name (regcache, "exs", &exs); |
45b134e5 OF |
354 | |
355 | return (((exs & 0xff00) >> 8) == 0xc); | |
356 | } | |
357 | ||
358 | static CORE_ADDR | |
359 | cris_stopped_data_address (void) | |
360 | { | |
361 | unsigned long eda; | |
0bfdf32f | 362 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 363 | |
07c04788 | 364 | collect_register_by_name (regcache, "eda", &eda); |
45b134e5 OF |
365 | |
366 | /* FIXME: Possibly adjust to match watched range. */ | |
367 | return eda; | |
368 | } | |
369 | ||
8eb3d7b6 | 370 | ps_err_e |
754653a7 | 371 | ps_get_thread_area (struct ps_prochandle *ph, |
8eb3d7b6 RW |
372 | lwpid_t lwpid, int idx, void **base) |
373 | { | |
374 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
375 | return PS_ERR; | |
376 | ||
377 | /* IDX is the bias from the thread pointer to the beginning of the | |
378 | thread descriptor. It has to be subtracted due to implementation | |
379 | quirks in libthread_db. */ | |
380 | *base = (void *) ((char *) *base - idx); | |
381 | return PS_OK; | |
382 | } | |
383 | ||
45b134e5 | 384 | static void |
07c04788 | 385 | cris_fill_gregset (struct regcache *regcache, void *buf) |
45b134e5 OF |
386 | { |
387 | int i; | |
388 | ||
389 | for (i = 0; i < cris_num_regs; i++) | |
390 | { | |
391 | if (cris_regmap[i] != -1) | |
07c04788 | 392 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
393 | } |
394 | } | |
395 | ||
396 | static void | |
07c04788 | 397 | cris_store_gregset (struct regcache *regcache, const void *buf) |
45b134e5 OF |
398 | { |
399 | int i; | |
400 | ||
401 | for (i = 0; i < cris_num_regs; i++) | |
402 | { | |
403 | if (cris_regmap[i] != -1) | |
07c04788 | 404 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
405 | } |
406 | } | |
407 | ||
797bcff5 TBA |
408 | void |
409 | crisv32_target::low_arch_setup () | |
3aee8918 PA |
410 | { |
411 | current_process ()->tdesc = tdesc_crisv32; | |
412 | } | |
413 | ||
7d00775e AT |
414 | /* Support for hardware single step. */ |
415 | ||
416 | static int | |
417 | cris_supports_hardware_single_step (void) | |
418 | { | |
419 | return 1; | |
420 | } | |
421 | ||
3aee8918 | 422 | static struct regset_info cris_regsets[] = { |
07c04788 | 423 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
45b134e5 | 424 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
50bc912a | 425 | NULL_REGSET |
45b134e5 OF |
426 | }; |
427 | ||
3aee8918 PA |
428 | |
429 | static struct regsets_info cris_regsets_info = | |
430 | { | |
431 | cris_regsets, /* regsets */ | |
432 | 0, /* num_regsets */ | |
433 | NULL, /* disabled_regsets */ | |
434 | }; | |
435 | ||
436 | static struct usrregs_info cris_usrregs_info = | |
437 | { | |
438 | cris_num_regs, | |
439 | cris_regmap, | |
440 | }; | |
441 | ||
aa8d21c9 | 442 | static struct regs_info myregs_info = |
3aee8918 PA |
443 | { |
444 | NULL, /* regset_bitmap */ | |
445 | &cris_usrregs_info, | |
446 | &cris_regsets_info | |
447 | }; | |
448 | ||
aa8d21c9 TBA |
449 | const regs_info * |
450 | crisv32_target::get_regs_info () | |
3aee8918 | 451 | { |
aa8d21c9 | 452 | return &myregs_info; |
3aee8918 PA |
453 | } |
454 | ||
45b134e5 | 455 | struct linux_target_ops the_low_target = { |
dd373349 AT |
456 | NULL, /* breakpoint_kind_from_pc */ |
457 | cris_sw_breakpoint_from_kind, | |
fa5308bd | 458 | NULL, /* get_next_pcs */ |
45b134e5 OF |
459 | 0, |
460 | cris_breakpoint_at, | |
802e8e6d | 461 | cris_supports_z_point_type, |
d993e290 PA |
462 | cris_insert_point, |
463 | cris_remove_point, | |
45b134e5 OF |
464 | cris_stopped_by_watchpoint, |
465 | cris_stopped_data_address, | |
7d00775e AT |
466 | NULL, /* collect_ptrace_register */ |
467 | NULL, /* supply_ptrace_register */ | |
468 | NULL, /* siginfo_fixup */ | |
469 | NULL, /* new_process */ | |
04ec7890 | 470 | NULL, /* delete_process */ |
7d00775e | 471 | NULL, /* new_thread */ |
466eecee | 472 | NULL, /* delete_thread */ |
7d00775e AT |
473 | NULL, /* new_fork */ |
474 | NULL, /* prepare_to_resume */ | |
475 | NULL, /* process_qsupported */ | |
476 | NULL, /* supports_tracepoints */ | |
477 | NULL, /* get_thread_area */ | |
478 | NULL, /* install_fast_tracepoint_jump_pad */ | |
479 | NULL, /* emit_ops */ | |
480 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
481 | NULL, /* supports_range_stepping */ | |
482 | NULL, /* breakpoint_kind_from_current_state */ | |
483 | cris_supports_hardware_single_step, | |
45b134e5 | 484 | }; |
3aee8918 | 485 | |
ef0478f6 TBA |
486 | /* The linux target ops object. */ |
487 | ||
488 | linux_process_target *the_linux_target = &the_crisv32_target; | |
489 | ||
3aee8918 PA |
490 | void |
491 | initialize_low_arch (void) | |
492 | { | |
eddddb9d | 493 | init_registers_crisv32 (); |
3aee8918 PA |
494 | |
495 | initialize_regsets_info (&cris_regsets_info); | |
496 | } |