Commit | Line | Data |
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45b134e5 | 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
45b134e5 OF |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
45b134e5 OF |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
45b134e5 OF |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
5826e159 | 21 | #include "nat/gdb_ptrace.h" |
45b134e5 | 22 | |
ef0478f6 TBA |
23 | /* Linux target op definitions for the CRIS architecture. */ |
24 | ||
25 | class crisv32_target : public linux_process_target | |
26 | { | |
27 | public: | |
28 | ||
aa8d21c9 TBA |
29 | const regs_info *get_regs_info () override; |
30 | ||
3ca4edb6 TBA |
31 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
32 | ||
007c9b97 TBA |
33 | bool supports_z_point_type (char z_type) override; |
34 | ||
797bcff5 TBA |
35 | protected: |
36 | ||
37 | void low_arch_setup () override; | |
daca57a7 TBA |
38 | |
39 | bool low_cannot_fetch_register (int regno) override; | |
40 | ||
41 | bool low_cannot_store_register (int regno) override; | |
bf9ae9d8 TBA |
42 | |
43 | bool low_supports_breakpoints () override; | |
44 | ||
45 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
46 | ||
47 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
d7146cda TBA |
48 | |
49 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
50 | |
51 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
52 | int size, raw_breakpoint *bp) override; | |
53 | ||
54 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
55 | int size, raw_breakpoint *bp) override; | |
ac1bbaca TBA |
56 | |
57 | bool low_stopped_by_watchpoint () override; | |
58 | ||
59 | CORE_ADDR low_stopped_data_address () override; | |
ef0478f6 TBA |
60 | }; |
61 | ||
62 | /* The singleton target ops object. */ | |
63 | ||
64 | static crisv32_target the_crisv32_target; | |
65 | ||
daca57a7 TBA |
66 | bool |
67 | crisv32_target::low_cannot_fetch_register (int regno) | |
68 | { | |
69 | gdb_assert_not_reached ("linux target op low_cannot_fetch_register " | |
70 | "is not implemented by the target"); | |
71 | } | |
72 | ||
73 | bool | |
74 | crisv32_target::low_cannot_store_register (int regno) | |
75 | { | |
76 | gdb_assert_not_reached ("linux target op low_cannot_store_register " | |
77 | "is not implemented by the target"); | |
78 | } | |
79 | ||
bf9ae9d8 TBA |
80 | bool |
81 | crisv32_target::low_supports_breakpoints () | |
82 | { | |
83 | return true; | |
84 | } | |
85 | ||
86 | CORE_ADDR | |
87 | crisv32_target::low_get_pc (regcache *regcache) | |
88 | { | |
89 | return linux_get_pc_32bit (regcache); | |
90 | } | |
91 | ||
92 | void | |
93 | crisv32_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
94 | { | |
95 | linux_set_pc_32bit (regcache, pc); | |
96 | } | |
97 | ||
d05b4ac3 UW |
98 | /* Defined in auto-generated file reg-crisv32.c. */ |
99 | void init_registers_crisv32 (void); | |
3aee8918 | 100 | extern const struct target_desc *tdesc_crisv32; |
d05b4ac3 | 101 | |
45b134e5 OF |
102 | /* CRISv32 */ |
103 | #define cris_num_regs 49 | |
104 | ||
8eb3d7b6 RW |
105 | #ifndef PTRACE_GET_THREAD_AREA |
106 | #define PTRACE_GET_THREAD_AREA 25 | |
107 | #endif | |
108 | ||
45b134e5 OF |
109 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble |
110 | without any significant gain). */ | |
111 | ||
112 | /* Locations need to match <include/asm/arch/ptrace.h>. */ | |
113 | static int cris_regmap[] = { | |
114 | 1*4, 2*4, 3*4, 4*4, | |
115 | 5*4, 6*4, 7*4, 8*4, | |
116 | 9*4, 10*4, 11*4, 12*4, | |
117 | 13*4, 14*4, 24*4, 15*4, | |
118 | ||
119 | -1, -1, -1, 16*4, | |
120 | -1, 22*4, 23*4, 17*4, | |
121 | -1, -1, 21*4, 20*4, | |
122 | -1, 19*4, -1, 18*4, | |
123 | ||
124 | 25*4, | |
125 | ||
1b3f6016 | 126 | 26*4, -1, -1, 29*4, |
45b134e5 OF |
127 | 30*4, 31*4, 32*4, 33*4, |
128 | 34*4, 35*4, 36*4, 37*4, | |
129 | 38*4, 39*4, 40*4, -1 | |
1b3f6016 | 130 | |
45b134e5 OF |
131 | }; |
132 | ||
45b134e5 OF |
133 | static const unsigned short cris_breakpoint = 0xe938; |
134 | #define cris_breakpoint_len 2 | |
135 | ||
3ca4edb6 | 136 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 137 | |
3ca4edb6 TBA |
138 | const gdb_byte * |
139 | crisv32_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
140 | { |
141 | *size = cris_breakpoint_len; | |
142 | return (const gdb_byte *) &cris_breakpoint; | |
143 | } | |
144 | ||
d7146cda TBA |
145 | bool |
146 | crisv32_target::low_breakpoint_at (CORE_ADDR where) | |
45b134e5 OF |
147 | { |
148 | unsigned short insn; | |
149 | ||
d7146cda | 150 | read_memory (where, (unsigned char *) &insn, cris_breakpoint_len); |
45b134e5 | 151 | if (insn == cris_breakpoint) |
d7146cda | 152 | return true; |
45b134e5 OF |
153 | |
154 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
155 | one. */ | |
d7146cda | 156 | return false; |
45b134e5 OF |
157 | } |
158 | ||
45b134e5 | 159 | static void |
442ea881 PA |
160 | cris_write_data_breakpoint (struct regcache *regcache, |
161 | int bp, unsigned long start, unsigned long end) | |
45b134e5 OF |
162 | { |
163 | switch (bp) | |
164 | { | |
165 | case 0: | |
442ea881 PA |
166 | supply_register_by_name (regcache, "s3", &start); |
167 | supply_register_by_name (regcache, "s4", &end); | |
45b134e5 OF |
168 | break; |
169 | case 1: | |
442ea881 PA |
170 | supply_register_by_name (regcache, "s5", &start); |
171 | supply_register_by_name (regcache, "s6", &end); | |
45b134e5 OF |
172 | break; |
173 | case 2: | |
442ea881 PA |
174 | supply_register_by_name (regcache, "s7", &start); |
175 | supply_register_by_name (regcache, "s8", &end); | |
45b134e5 OF |
176 | break; |
177 | case 3: | |
442ea881 PA |
178 | supply_register_by_name (regcache, "s9", &start); |
179 | supply_register_by_name (regcache, "s10", &end); | |
45b134e5 OF |
180 | break; |
181 | case 4: | |
442ea881 PA |
182 | supply_register_by_name (regcache, "s11", &start); |
183 | supply_register_by_name (regcache, "s12", &end); | |
45b134e5 OF |
184 | break; |
185 | case 5: | |
442ea881 PA |
186 | supply_register_by_name (regcache, "s13", &start); |
187 | supply_register_by_name (regcache, "s14", &end); | |
45b134e5 OF |
188 | break; |
189 | } | |
190 | } | |
191 | ||
007c9b97 TBA |
192 | bool |
193 | crisv32_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
194 | { |
195 | switch (z_type) | |
196 | { | |
197 | case Z_PACKET_WRITE_WP: | |
198 | case Z_PACKET_READ_WP: | |
199 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 200 | return true; |
802e8e6d | 201 | default: |
007c9b97 | 202 | return false; |
802e8e6d PA |
203 | } |
204 | } | |
205 | ||
9db9aa23 TBA |
206 | int |
207 | crisv32_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
208 | int len, raw_breakpoint *bp) | |
45b134e5 OF |
209 | { |
210 | int bp; | |
211 | unsigned long bp_ctrl; | |
212 | unsigned long start, end; | |
213 | unsigned long ccs; | |
442ea881 | 214 | struct regcache *regcache; |
1b3f6016 | 215 | |
0bfdf32f | 216 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 217 | |
45b134e5 OF |
218 | /* Read watchpoints are set as access watchpoints, because of GDB's |
219 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
220 | if (type == raw_bkpt_type_read_wp) |
221 | type = raw_bkpt_type_access_wp; | |
45b134e5 OF |
222 | |
223 | /* Get the configuration register. */ | |
442ea881 | 224 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
225 | |
226 | /* The watchpoint allocation scheme is the simplest possible. | |
227 | For example, if a region is watched for read and | |
228 | a write watch is requested, a new watchpoint will | |
229 | be used. Also, if a watch for a region that is already | |
230 | covered by one or more existing watchpoints, a new | |
231 | watchpoint will be used. */ | |
1b3f6016 | 232 | |
45b134e5 OF |
233 | /* First, find a free data watchpoint. */ |
234 | for (bp = 0; bp < 6; bp++) | |
235 | { | |
236 | /* Each data watchpoint's control registers occupy 2 bits | |
237 | (hence the 3), starting at bit 2 for D0 (hence the 2) | |
238 | with 4 bits between for each watchpoint (yes, the 4). */ | |
1b3f6016 | 239 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
45b134e5 OF |
240 | break; |
241 | } | |
1b3f6016 | 242 | |
45b134e5 OF |
243 | if (bp > 5) |
244 | { | |
245 | /* We're out of watchpoints. */ | |
246 | return -1; | |
247 | } | |
248 | ||
249 | /* Configure the control register first. */ | |
802e8e6d | 250 | if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
251 | { |
252 | /* Trigger on read. */ | |
253 | bp_ctrl |= (1 << (2 + bp * 4)); | |
254 | } | |
802e8e6d | 255 | if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
256 | { |
257 | /* Trigger on write. */ | |
258 | bp_ctrl |= (2 << (2 + bp * 4)); | |
259 | } | |
1b3f6016 | 260 | |
45b134e5 | 261 | /* Setup the configuration register. */ |
442ea881 | 262 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
1b3f6016 | 263 | |
45b134e5 OF |
264 | /* Setup the range. */ |
265 | start = addr; | |
266 | end = addr + len - 1; | |
267 | ||
268 | /* Configure the watchpoint register. */ | |
442ea881 | 269 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 | 270 | |
442ea881 | 271 | collect_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
272 | /* Set the S1 flag to enable watchpoints. */ |
273 | ccs |= (1 << 19); | |
442ea881 | 274 | supply_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
275 | |
276 | return 0; | |
277 | } | |
278 | ||
9db9aa23 TBA |
279 | int |
280 | crisv32_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
281 | int len, raw_breakpoint *bp) | |
45b134e5 OF |
282 | { |
283 | int bp; | |
284 | unsigned long bp_ctrl; | |
285 | unsigned long start, end; | |
442ea881 | 286 | struct regcache *regcache; |
07c04788 | 287 | unsigned long bp_d_regs[12]; |
1b3f6016 | 288 | |
0bfdf32f | 289 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 290 | |
45b134e5 OF |
291 | /* Read watchpoints are set as access watchpoints, because of GDB's |
292 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
293 | if (type == raw_bkpt_type_read_wp) |
294 | type = raw_bkpt_type_access_wp; | |
1b3f6016 | 295 | |
45b134e5 | 296 | /* Get the configuration register. */ |
442ea881 | 297 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
298 | |
299 | /* Try to find a watchpoint that is configured for the | |
300 | specified range, then check that read/write also matches. */ | |
1b3f6016 | 301 | |
45b134e5 OF |
302 | /* Ugly pointer arithmetic, since I cannot rely on a |
303 | single switch (addr) as there may be several watchpoints with | |
304 | the same start address for example. */ | |
305 | ||
45b134e5 | 306 | /* Get all range registers to simplify search. */ |
442ea881 PA |
307 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
308 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); | |
309 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); | |
310 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); | |
311 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); | |
312 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); | |
313 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); | |
314 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); | |
315 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); | |
316 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); | |
317 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); | |
318 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); | |
45b134e5 | 319 | |
1b3f6016 | 320 | for (bp = 0; bp < 6; bp++) |
45b134e5 | 321 | { |
1b3f6016 | 322 | if (bp_d_regs[bp * 2] == addr |
45b134e5 OF |
323 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
324 | /* Matching range. */ | |
325 | int bitpos = 2 + bp * 4; | |
326 | int rw_bits; | |
1b3f6016 | 327 | |
45b134e5 OF |
328 | /* Read/write bits for this BP. */ |
329 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; | |
1b3f6016 | 330 | |
802e8e6d PA |
331 | if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1) |
332 | || (type == raw_bkpt_type_write_wp && rw_bits == 0x2) | |
333 | || (type == raw_bkpt_type_access_wp && rw_bits == 0x3)) | |
45b134e5 OF |
334 | { |
335 | /* Read/write matched. */ | |
336 | break; | |
337 | } | |
338 | } | |
339 | } | |
1b3f6016 | 340 | |
45b134e5 OF |
341 | if (bp > 5) |
342 | { | |
343 | /* No watchpoint matched. */ | |
344 | return -1; | |
345 | } | |
1b3f6016 | 346 | |
45b134e5 OF |
347 | /* Found a matching watchpoint. Now, deconfigure it by |
348 | both disabling read/write in bp_ctrl and zeroing its | |
349 | start/end addresses. */ | |
350 | bp_ctrl &= ~(3 << (2 + (bp * 4))); | |
351 | /* Setup the configuration register. */ | |
442ea881 | 352 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
353 | |
354 | start = end = 0; | |
355 | /* Configure the watchpoint register. */ | |
442ea881 | 356 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 OF |
357 | |
358 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ | |
359 | return 0; | |
360 | } | |
361 | ||
ac1bbaca TBA |
362 | bool |
363 | crisv32_target::low_stopped_by_watchpoint () | |
45b134e5 OF |
364 | { |
365 | unsigned long exs; | |
0bfdf32f | 366 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 367 | |
07c04788 | 368 | collect_register_by_name (regcache, "exs", &exs); |
45b134e5 OF |
369 | |
370 | return (((exs & 0xff00) >> 8) == 0xc); | |
371 | } | |
372 | ||
ac1bbaca TBA |
373 | CORE_ADDR |
374 | crisv32_target::low_stopped_data_address () | |
45b134e5 OF |
375 | { |
376 | unsigned long eda; | |
0bfdf32f | 377 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 378 | |
07c04788 | 379 | collect_register_by_name (regcache, "eda", &eda); |
45b134e5 OF |
380 | |
381 | /* FIXME: Possibly adjust to match watched range. */ | |
382 | return eda; | |
383 | } | |
384 | ||
8eb3d7b6 | 385 | ps_err_e |
754653a7 | 386 | ps_get_thread_area (struct ps_prochandle *ph, |
8eb3d7b6 RW |
387 | lwpid_t lwpid, int idx, void **base) |
388 | { | |
389 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
390 | return PS_ERR; | |
391 | ||
392 | /* IDX is the bias from the thread pointer to the beginning of the | |
393 | thread descriptor. It has to be subtracted due to implementation | |
394 | quirks in libthread_db. */ | |
395 | *base = (void *) ((char *) *base - idx); | |
396 | return PS_OK; | |
397 | } | |
398 | ||
45b134e5 | 399 | static void |
07c04788 | 400 | cris_fill_gregset (struct regcache *regcache, void *buf) |
45b134e5 OF |
401 | { |
402 | int i; | |
403 | ||
404 | for (i = 0; i < cris_num_regs; i++) | |
405 | { | |
406 | if (cris_regmap[i] != -1) | |
07c04788 | 407 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
408 | } |
409 | } | |
410 | ||
411 | static void | |
07c04788 | 412 | cris_store_gregset (struct regcache *regcache, const void *buf) |
45b134e5 OF |
413 | { |
414 | int i; | |
415 | ||
416 | for (i = 0; i < cris_num_regs; i++) | |
417 | { | |
418 | if (cris_regmap[i] != -1) | |
07c04788 | 419 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
420 | } |
421 | } | |
422 | ||
797bcff5 TBA |
423 | void |
424 | crisv32_target::low_arch_setup () | |
3aee8918 PA |
425 | { |
426 | current_process ()->tdesc = tdesc_crisv32; | |
427 | } | |
428 | ||
7d00775e AT |
429 | /* Support for hardware single step. */ |
430 | ||
431 | static int | |
432 | cris_supports_hardware_single_step (void) | |
433 | { | |
434 | return 1; | |
435 | } | |
436 | ||
3aee8918 | 437 | static struct regset_info cris_regsets[] = { |
07c04788 | 438 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
45b134e5 | 439 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
50bc912a | 440 | NULL_REGSET |
45b134e5 OF |
441 | }; |
442 | ||
3aee8918 PA |
443 | |
444 | static struct regsets_info cris_regsets_info = | |
445 | { | |
446 | cris_regsets, /* regsets */ | |
447 | 0, /* num_regsets */ | |
448 | NULL, /* disabled_regsets */ | |
449 | }; | |
450 | ||
451 | static struct usrregs_info cris_usrregs_info = | |
452 | { | |
453 | cris_num_regs, | |
454 | cris_regmap, | |
455 | }; | |
456 | ||
aa8d21c9 | 457 | static struct regs_info myregs_info = |
3aee8918 PA |
458 | { |
459 | NULL, /* regset_bitmap */ | |
460 | &cris_usrregs_info, | |
461 | &cris_regsets_info | |
462 | }; | |
463 | ||
aa8d21c9 TBA |
464 | const regs_info * |
465 | crisv32_target::get_regs_info () | |
3aee8918 | 466 | { |
aa8d21c9 | 467 | return &myregs_info; |
3aee8918 PA |
468 | } |
469 | ||
45b134e5 | 470 | struct linux_target_ops the_low_target = { |
7d00775e | 471 | NULL, /* new_process */ |
04ec7890 | 472 | NULL, /* delete_process */ |
7d00775e | 473 | NULL, /* new_thread */ |
466eecee | 474 | NULL, /* delete_thread */ |
7d00775e AT |
475 | NULL, /* new_fork */ |
476 | NULL, /* prepare_to_resume */ | |
477 | NULL, /* process_qsupported */ | |
478 | NULL, /* supports_tracepoints */ | |
479 | NULL, /* get_thread_area */ | |
480 | NULL, /* install_fast_tracepoint_jump_pad */ | |
481 | NULL, /* emit_ops */ | |
482 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
483 | NULL, /* supports_range_stepping */ | |
7d00775e | 484 | cris_supports_hardware_single_step, |
45b134e5 | 485 | }; |
3aee8918 | 486 | |
ef0478f6 TBA |
487 | /* The linux target ops object. */ |
488 | ||
489 | linux_process_target *the_linux_target = &the_crisv32_target; | |
490 | ||
3aee8918 PA |
491 | void |
492 | initialize_low_arch (void) | |
493 | { | |
eddddb9d | 494 | init_registers_crisv32 (); |
3aee8918 PA |
495 | |
496 | initialize_regsets_info (&cris_regsets_info); | |
497 | } |