Commit | Line | Data |
---|---|---|
0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
ef0478f6 TBA |
28 | /* Linux target op definitions for the MIPS architecture. */ |
29 | ||
30 | class mips_target : public linux_process_target | |
31 | { | |
32 | public: | |
33 | ||
aa8d21c9 TBA |
34 | const regs_info *get_regs_info () override; |
35 | ||
3ca4edb6 TBA |
36 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
37 | ||
797bcff5 TBA |
38 | protected: |
39 | ||
40 | void low_arch_setup () override; | |
daca57a7 TBA |
41 | |
42 | bool low_cannot_fetch_register (int regno) override; | |
43 | ||
44 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
45 | |
46 | bool low_fetch_register (regcache *regcache, int regno) override; | |
bf9ae9d8 TBA |
47 | |
48 | bool low_supports_breakpoints () override; | |
49 | ||
50 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
51 | ||
52 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
ef0478f6 TBA |
53 | }; |
54 | ||
55 | /* The singleton target ops object. */ | |
56 | ||
57 | static mips_target the_mips_target; | |
58 | ||
d05b4ac3 UW |
59 | /* Defined in auto-generated file mips-linux.c. */ |
60 | void init_registers_mips_linux (void); | |
3aee8918 PA |
61 | extern const struct target_desc *tdesc_mips_linux; |
62 | ||
1faeff08 MR |
63 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
64 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
65 | extern const struct target_desc *tdesc_mips_dsp_linux; |
66 | ||
d05b4ac3 UW |
67 | /* Defined in auto-generated file mips64-linux.c. */ |
68 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
69 | extern const struct target_desc *tdesc_mips64_linux; |
70 | ||
1faeff08 MR |
71 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
72 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 73 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
74 | |
75 | #ifdef __mips64 | |
3aee8918 PA |
76 | #define tdesc_mips_linux tdesc_mips64_linux |
77 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 78 | #endif |
d05b4ac3 | 79 | |
21b0f40c DJ |
80 | #ifndef PTRACE_GET_THREAD_AREA |
81 | #define PTRACE_GET_THREAD_AREA 25 | |
82 | #endif | |
83 | ||
0a30fbc4 DJ |
84 | #ifdef HAVE_SYS_REG_H |
85 | #include <sys/reg.h> | |
86 | #endif | |
87 | ||
117ce543 | 88 | #define mips_num_regs 73 |
1faeff08 | 89 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
90 | |
91 | #include <asm/ptrace.h> | |
92 | ||
1faeff08 MR |
93 | #ifndef DSP_BASE |
94 | #define DSP_BASE 71 | |
95 | #define DSP_CONTROL 77 | |
96 | #endif | |
97 | ||
186947f7 DJ |
98 | union mips_register |
99 | { | |
100 | unsigned char buf[8]; | |
101 | ||
102 | /* Deliberately signed, for proper sign extension. */ | |
103 | int reg32; | |
104 | long long reg64; | |
105 | }; | |
106 | ||
0a30fbc4 DJ |
107 | /* Return the ptrace ``address'' of register REGNO. */ |
108 | ||
1faeff08 MR |
109 | #define mips_base_regs \ |
110 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
111 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
112 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
113 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
114 | \ | |
115 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
116 | \ | |
117 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
118 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
119 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
120 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
121 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
122 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
123 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
124 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
125 | FPC_CSR, FPC_EIR | |
126 | ||
127 | #define mips_dsp_regs \ | |
128 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
129 | DSP_BASE + 4, DSP_BASE + 5, \ | |
130 | DSP_CONTROL | |
131 | ||
132 | static int mips_regmap[mips_num_regs] = { | |
133 | mips_base_regs, | |
134 | 0 | |
135 | }; | |
0a30fbc4 | 136 | |
1faeff08 MR |
137 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
138 | mips_base_regs, | |
139 | mips_dsp_regs, | |
140 | 0 | |
141 | }; | |
0a30fbc4 | 142 | |
1faeff08 MR |
143 | /* DSP registers are not in any regset and can only be accessed |
144 | individually. */ | |
0a30fbc4 | 145 | |
1faeff08 MR |
146 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
147 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
148 | }; |
149 | ||
3aee8918 PA |
150 | static int have_dsp = -1; |
151 | ||
1faeff08 MR |
152 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
153 | user register set accordingly. */ | |
154 | ||
3aee8918 PA |
155 | static const struct target_desc * |
156 | mips_read_description (void) | |
1faeff08 | 157 | { |
3aee8918 | 158 | if (have_dsp < 0) |
1faeff08 | 159 | { |
0bfdf32f | 160 | int pid = lwpid_of (current_thread); |
1faeff08 | 161 | |
ac740bc7 | 162 | errno = 0; |
1faeff08 MR |
163 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
164 | switch (errno) | |
165 | { | |
166 | case 0: | |
3aee8918 | 167 | have_dsp = 1; |
1faeff08 MR |
168 | break; |
169 | case EIO: | |
3aee8918 | 170 | have_dsp = 0; |
1faeff08 MR |
171 | break; |
172 | default: | |
173 | perror_with_name ("ptrace"); | |
174 | break; | |
175 | } | |
176 | } | |
3aee8918 PA |
177 | |
178 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
179 | } | |
180 | ||
797bcff5 TBA |
181 | void |
182 | mips_target::low_arch_setup () | |
3aee8918 PA |
183 | { |
184 | current_process ()->tdesc = mips_read_description (); | |
185 | } | |
186 | ||
7a60ad40 YQ |
187 | /* Per-process arch-specific data we want to keep. */ |
188 | ||
189 | struct arch_process_info | |
190 | { | |
191 | /* -1 if the kernel and/or CPU do not support watch registers. | |
192 | 1 if watch_readback is valid and we can read style, num_valid | |
193 | and the masks. | |
194 | 0 if we need to read the watch_readback. */ | |
195 | ||
196 | int watch_readback_valid; | |
197 | ||
198 | /* Cached watch register read values. */ | |
199 | ||
200 | struct pt_watch_regs watch_readback; | |
201 | ||
202 | /* Current watchpoint requests for this process. */ | |
203 | ||
204 | struct mips_watchpoint *current_watches; | |
205 | ||
206 | /* The current set of watch register values for writing the | |
207 | registers. */ | |
208 | ||
209 | struct pt_watch_regs watch_mirror; | |
210 | }; | |
211 | ||
212 | /* Per-thread arch-specific data we want to keep. */ | |
213 | ||
214 | struct arch_lwp_info | |
215 | { | |
216 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
217 | int watch_registers_changed; | |
218 | }; | |
219 | ||
0a30fbc4 DJ |
220 | /* From mips-linux-nat.c. */ |
221 | ||
222 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
223 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
e4439e43 MR |
224 | ZERO_REGNUM, it's always 0. We also can not set BADVADDR, CAUSE, |
225 | or FCRIR via ptrace(). */ | |
0a30fbc4 | 226 | |
daca57a7 TBA |
227 | bool |
228 | mips_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 229 | { |
3aee8918 PA |
230 | const struct target_desc *tdesc; |
231 | ||
daca57a7 TBA |
232 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
233 | return true; | |
0a30fbc4 | 234 | |
3aee8918 PA |
235 | tdesc = current_process ()->tdesc; |
236 | ||
75d74cca MR |
237 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ |
238 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 239 | return true; |
75d74cca | 240 | |
3aee8918 | 241 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 242 | return true; |
0a30fbc4 | 243 | |
daca57a7 | 244 | return false; |
0a30fbc4 DJ |
245 | } |
246 | ||
daca57a7 TBA |
247 | bool |
248 | mips_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 249 | { |
3aee8918 PA |
250 | const struct target_desc *tdesc; |
251 | ||
daca57a7 TBA |
252 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
253 | return true; | |
0a30fbc4 | 254 | |
3aee8918 PA |
255 | tdesc = current_process ()->tdesc; |
256 | ||
75d74cca MR |
257 | /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ |
258 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 259 | return true; |
75d74cca | 260 | |
3aee8918 | 261 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 262 | return true; |
0a30fbc4 | 263 | |
3aee8918 | 264 | if (find_regno (tdesc, "cause") == regno) |
daca57a7 | 265 | return true; |
0a30fbc4 | 266 | |
3aee8918 | 267 | if (find_regno (tdesc, "badvaddr") == regno) |
daca57a7 | 268 | return true; |
0a30fbc4 | 269 | |
3aee8918 | 270 | if (find_regno (tdesc, "fir") == regno) |
daca57a7 | 271 | return true; |
0a30fbc4 | 272 | |
daca57a7 | 273 | return false; |
0a30fbc4 | 274 | } |
2ec06d2e | 275 | |
bd70b1f2 TBA |
276 | bool |
277 | mips_target::low_fetch_register (regcache *regcache, int regno) | |
e4439e43 MR |
278 | { |
279 | const struct target_desc *tdesc = current_process ()->tdesc; | |
280 | ||
281 | if (find_regno (tdesc, "r0") == regno) | |
282 | { | |
283 | supply_register_zeroed (regcache, regno); | |
bd70b1f2 | 284 | return true; |
e4439e43 MR |
285 | } |
286 | ||
bd70b1f2 | 287 | return false; |
e4439e43 MR |
288 | } |
289 | ||
bf9ae9d8 TBA |
290 | bool |
291 | mips_target::low_supports_breakpoints () | |
292 | { | |
293 | return true; | |
294 | } | |
295 | ||
296 | CORE_ADDR | |
297 | mips_target::low_get_pc (regcache *regcache) | |
0d62e5e8 | 298 | { |
186947f7 | 299 | union mips_register pc; |
442ea881 | 300 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 301 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
302 | } |
303 | ||
bf9ae9d8 TBA |
304 | void |
305 | mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
0d62e5e8 | 306 | { |
186947f7 | 307 | union mips_register newpc; |
3aee8918 | 308 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
309 | newpc.reg32 = pc; |
310 | else | |
311 | newpc.reg64 = pc; | |
312 | ||
442ea881 | 313 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
314 | } |
315 | ||
316 | /* Correct in either endianness. */ | |
186947f7 | 317 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
318 | #define mips_breakpoint_len 4 |
319 | ||
3ca4edb6 | 320 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 321 | |
3ca4edb6 TBA |
322 | const gdb_byte * |
323 | mips_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
324 | { |
325 | *size = mips_breakpoint_len; | |
326 | return (const gdb_byte *) &mips_breakpoint; | |
327 | } | |
328 | ||
0d62e5e8 DJ |
329 | static int |
330 | mips_breakpoint_at (CORE_ADDR where) | |
331 | { | |
186947f7 | 332 | unsigned int insn; |
0d62e5e8 | 333 | |
52405d85 | 334 | the_target->read_memory (where, (unsigned char *) &insn, 4); |
0d62e5e8 DJ |
335 | if (insn == mips_breakpoint) |
336 | return 1; | |
337 | ||
338 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
339 | one. */ | |
340 | return 0; | |
341 | } | |
342 | ||
da25033c | 343 | /* Mark the watch registers of lwp, represented by ENTRY, as changed. */ |
7a60ad40 | 344 | |
da25033c SM |
345 | static void |
346 | update_watch_registers_callback (thread_info *thread) | |
7a60ad40 | 347 | { |
d86d4aaf | 348 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 | 349 | |
da25033c SM |
350 | /* The actual update is done later just before resuming the lwp, |
351 | we just mark that the registers need updating. */ | |
352 | lwp->arch_private->watch_registers_changed = 1; | |
7a60ad40 | 353 | |
da25033c SM |
354 | /* If the lwp isn't stopped, force it to momentarily pause, so |
355 | we can update its watch registers. */ | |
356 | if (!lwp->stopped) | |
357 | linux_stop_lwp (lwp); | |
7a60ad40 YQ |
358 | } |
359 | ||
360 | /* This is the implementation of linux_target_ops method | |
361 | new_process. */ | |
362 | ||
363 | static struct arch_process_info * | |
364 | mips_linux_new_process (void) | |
365 | { | |
8d749320 | 366 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
367 | |
368 | return info; | |
369 | } | |
370 | ||
04ec7890 SM |
371 | /* This is the implementation of linux_target_ops method |
372 | delete_process. */ | |
373 | ||
374 | static void | |
375 | mips_linux_delete_process (struct arch_process_info *info) | |
376 | { | |
377 | xfree (info); | |
378 | } | |
379 | ||
7a60ad40 YQ |
380 | /* This is the implementation of linux_target_ops method new_thread. |
381 | Mark the watch registers as changed, so the threads' copies will | |
382 | be updated. */ | |
383 | ||
34c703da GB |
384 | static void |
385 | mips_linux_new_thread (struct lwp_info *lwp) | |
7a60ad40 | 386 | { |
8d749320 | 387 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
388 | |
389 | info->watch_registers_changed = 1; | |
390 | ||
34c703da | 391 | lwp->arch_private = info; |
7a60ad40 YQ |
392 | } |
393 | ||
466eecee SM |
394 | /* Function to call when a thread is being deleted. */ |
395 | ||
396 | static void | |
397 | mips_linux_delete_thread (struct arch_lwp_info *arch_lwp) | |
398 | { | |
399 | xfree (arch_lwp); | |
400 | } | |
401 | ||
3a8a0396 DB |
402 | /* Create a new mips_watchpoint and add it to the list. */ |
403 | ||
404 | static void | |
cbec665b | 405 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 406 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
407 | { |
408 | struct mips_watchpoint *new_watch; | |
409 | struct mips_watchpoint **pw; | |
410 | ||
8d749320 | 411 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
412 | new_watch->addr = addr; |
413 | new_watch->len = len; | |
414 | new_watch->type = watch_type; | |
415 | new_watch->next = NULL; | |
416 | ||
cbec665b | 417 | pw = &priv->current_watches; |
3a8a0396 DB |
418 | while (*pw != NULL) |
419 | pw = &(*pw)->next; | |
420 | *pw = new_watch; | |
421 | } | |
422 | ||
423 | /* Hook to call when a new fork is attached. */ | |
424 | ||
425 | static void | |
426 | mips_linux_new_fork (struct process_info *parent, | |
427 | struct process_info *child) | |
428 | { | |
429 | struct arch_process_info *parent_private; | |
430 | struct arch_process_info *child_private; | |
431 | struct mips_watchpoint *wp; | |
432 | ||
433 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
434 | gdb_assert (parent->priv != NULL |
435 | && parent->priv->arch_private != NULL); | |
436 | gdb_assert (child->priv != NULL | |
437 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
438 | |
439 | /* Linux kernel before 2.6.33 commit | |
440 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
441 | will inherit hardware debug registers from parent | |
442 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
443 | zeroed debug registers. | |
444 | ||
445 | GDB core assumes the child inherits the watchpoints/hw | |
446 | breakpoints of the parent, and will remove them all from the | |
447 | forked off process. Copy the debug registers mirrors into the | |
448 | new process so that all breakpoints and watchpoints can be | |
449 | removed together. The debug registers mirror will become zeroed | |
450 | in the end before detaching the forked off process, thus making | |
451 | this compatible with older Linux kernels too. */ | |
452 | ||
61a7418c DB |
453 | parent_private = parent->priv->arch_private; |
454 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
455 | |
456 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
457 | child_private->watch_readback = parent_private->watch_readback; | |
458 | ||
459 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
460 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
461 | ||
462 | child_private->watch_mirror = parent_private->watch_mirror; | |
463 | } | |
7a60ad40 YQ |
464 | /* This is the implementation of linux_target_ops method |
465 | prepare_to_resume. If the watch regs have changed, update the | |
466 | thread's copies. */ | |
467 | ||
468 | static void | |
469 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
470 | { | |
d86d4aaf | 471 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
e99b03dc | 472 | struct process_info *proc = find_process_pid (ptid.pid ()); |
fe978cb0 | 473 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
474 | |
475 | if (lwp->arch_private->watch_registers_changed) | |
476 | { | |
477 | /* Only update the watch registers if we have set or unset a | |
478 | watchpoint already. */ | |
fe978cb0 | 479 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
480 | { |
481 | /* Write the mirrored watch register values. */ | |
e38504b3 | 482 | int tid = ptid.lwp (); |
7a60ad40 YQ |
483 | |
484 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 485 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
486 | perror_with_name ("Couldn't write watch register"); |
487 | } | |
488 | ||
489 | lwp->arch_private->watch_registers_changed = 0; | |
490 | } | |
491 | } | |
492 | ||
802e8e6d PA |
493 | static int |
494 | mips_supports_z_point_type (char z_type) | |
495 | { | |
496 | switch (z_type) | |
497 | { | |
498 | case Z_PACKET_WRITE_WP: | |
499 | case Z_PACKET_READ_WP: | |
500 | case Z_PACKET_ACCESS_WP: | |
501 | return 1; | |
502 | default: | |
503 | return 0; | |
504 | } | |
505 | } | |
506 | ||
7a60ad40 YQ |
507 | /* This is the implementation of linux_target_ops method |
508 | insert_point. */ | |
509 | ||
510 | static int | |
802e8e6d PA |
511 | mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
512 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
513 | { |
514 | struct process_info *proc = current_process (); | |
fe978cb0 | 515 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 516 | struct pt_watch_regs regs; |
7a60ad40 YQ |
517 | long lwpid; |
518 | enum target_hw_bp_type watch_type; | |
519 | uint32_t irw; | |
520 | ||
0bfdf32f | 521 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 522 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
523 | &priv->watch_readback, |
524 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
525 | 0)) |
526 | return -1; | |
527 | ||
528 | if (len <= 0) | |
529 | return -1; | |
530 | ||
fe978cb0 | 531 | regs = priv->watch_readback; |
7a60ad40 | 532 | /* Add the current watches. */ |
fe978cb0 | 533 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
534 | |
535 | /* Now try to add the new watch. */ | |
802e8e6d | 536 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
537 | irw = mips_linux_watch_type_to_irw (watch_type); |
538 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
539 | return -1; | |
540 | ||
541 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 542 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 543 | |
fe978cb0 | 544 | priv->watch_mirror = regs; |
7a60ad40 YQ |
545 | |
546 | /* Only update the threads of this process. */ | |
da25033c | 547 | for_each_thread (proc->pid, update_watch_registers_callback); |
7a60ad40 YQ |
548 | |
549 | return 0; | |
550 | } | |
551 | ||
552 | /* This is the implementation of linux_target_ops method | |
553 | remove_point. */ | |
554 | ||
555 | static int | |
802e8e6d PA |
556 | mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
557 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
558 | { |
559 | struct process_info *proc = current_process (); | |
fe978cb0 | 560 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
561 | |
562 | int deleted_one; | |
7a60ad40 YQ |
563 | enum target_hw_bp_type watch_type; |
564 | ||
565 | struct mips_watchpoint **pw; | |
566 | struct mips_watchpoint *w; | |
567 | ||
7a60ad40 | 568 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 569 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 570 | deleted_one = 0; |
fe978cb0 | 571 | pw = &priv->current_watches; |
7a60ad40 YQ |
572 | while ((w = *pw)) |
573 | { | |
574 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
575 | { | |
576 | *pw = w->next; | |
577 | free (w); | |
578 | deleted_one = 1; | |
579 | break; | |
580 | } | |
581 | pw = &(w->next); | |
582 | } | |
583 | ||
584 | if (!deleted_one) | |
585 | return -1; /* We don't know about it, fail doing nothing. */ | |
586 | ||
587 | /* At this point watch_readback is known to be valid because we | |
588 | could not have added the watch without reading it. */ | |
fe978cb0 | 589 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 590 | |
fe978cb0 PA |
591 | priv->watch_mirror = priv->watch_readback; |
592 | mips_linux_watch_populate_regs (priv->current_watches, | |
593 | &priv->watch_mirror); | |
7a60ad40 YQ |
594 | |
595 | /* Only update the threads of this process. */ | |
da25033c SM |
596 | for_each_thread (proc->pid, update_watch_registers_callback); |
597 | ||
7a60ad40 YQ |
598 | return 0; |
599 | } | |
600 | ||
601 | /* This is the implementation of linux_target_ops method | |
602 | stopped_by_watchpoint. The watchhi R and W bits indicate | |
603 | the watch register triggered. */ | |
604 | ||
605 | static int | |
606 | mips_stopped_by_watchpoint (void) | |
607 | { | |
608 | struct process_info *proc = current_process (); | |
fe978cb0 | 609 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
610 | int n; |
611 | int num_valid; | |
0bfdf32f | 612 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
613 | |
614 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
615 | &priv->watch_readback, |
616 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
617 | 1)) |
618 | return 0; | |
619 | ||
fe978cb0 | 620 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
621 | |
622 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 623 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
624 | & (R_MASK | W_MASK)) |
625 | return 1; | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | /* This is the implementation of linux_target_ops method | |
631 | stopped_data_address. */ | |
632 | ||
633 | static CORE_ADDR | |
634 | mips_stopped_data_address (void) | |
635 | { | |
636 | struct process_info *proc = current_process (); | |
fe978cb0 | 637 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
638 | int n; |
639 | int num_valid; | |
0bfdf32f | 640 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
641 | |
642 | /* On MIPS we don't know the low order 3 bits of the data address. | |
643 | GDB does not support remote targets that can't report the | |
644 | watchpoint address. So, make our best guess; return the starting | |
645 | address of a watchpoint request which overlaps the one that | |
646 | triggered. */ | |
647 | ||
648 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
649 | &priv->watch_readback, |
650 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
651 | 0)) |
652 | return 0; | |
653 | ||
fe978cb0 | 654 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
655 | |
656 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 657 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
658 | & (R_MASK | W_MASK)) |
659 | { | |
660 | CORE_ADDR t_low, t_hi; | |
661 | int t_irw; | |
662 | struct mips_watchpoint *watch; | |
663 | ||
fe978cb0 | 664 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 665 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 666 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
667 | | IRW_MASK); |
668 | t_low &= ~(CORE_ADDR)t_hi; | |
669 | ||
fe978cb0 | 670 | for (watch = priv->current_watches; |
7a60ad40 YQ |
671 | watch != NULL; |
672 | watch = watch->next) | |
673 | { | |
674 | CORE_ADDR addr = watch->addr; | |
675 | CORE_ADDR last_byte = addr + watch->len - 1; | |
676 | ||
677 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
678 | { | |
679 | /* Different type. */ | |
680 | continue; | |
681 | } | |
682 | /* Check for overlap of even a single byte. */ | |
683 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
684 | return addr; | |
685 | } | |
686 | } | |
687 | ||
688 | /* Shouldn't happen. */ | |
689 | return 0; | |
690 | } | |
691 | ||
21b0f40c DJ |
692 | /* Fetch the thread-local storage pointer for libthread_db. */ |
693 | ||
694 | ps_err_e | |
754653a7 | 695 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 696 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
697 | { |
698 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
699 | return PS_ERR; | |
700 | ||
701 | /* IDX is the bias from the thread pointer to the beginning of the | |
702 | thread descriptor. It has to be subtracted due to implementation | |
703 | quirks in libthread_db. */ | |
704 | *base = (void *) ((char *)*base - idx); | |
705 | ||
706 | return PS_OK; | |
707 | } | |
708 | ||
186947f7 | 709 | static void |
442ea881 PA |
710 | mips_collect_register (struct regcache *regcache, |
711 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
712 | { |
713 | union mips_register tmp_reg; | |
714 | ||
715 | if (use_64bit) | |
716 | { | |
442ea881 | 717 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
718 | *reg = tmp_reg; |
719 | } | |
720 | else | |
721 | { | |
442ea881 | 722 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
723 | reg->reg64 = tmp_reg.reg32; |
724 | } | |
725 | } | |
726 | ||
727 | static void | |
442ea881 PA |
728 | mips_supply_register (struct regcache *regcache, |
729 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
730 | { |
731 | int offset = 0; | |
732 | ||
733 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
734 | eight-byte slot. */ | |
735 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
736 | offset = 4; | |
737 | ||
442ea881 | 738 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
739 | } |
740 | ||
7e947ad3 MR |
741 | #ifdef HAVE_PTRACE_GETREGS |
742 | ||
186947f7 | 743 | static void |
442ea881 PA |
744 | mips_collect_register_32bit (struct regcache *regcache, |
745 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
746 | { |
747 | union mips_register tmp_reg; | |
748 | int reg32; | |
749 | ||
442ea881 | 750 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
751 | reg32 = tmp_reg.reg64; |
752 | memcpy (buf, ®32, 4); | |
753 | } | |
754 | ||
755 | static void | |
442ea881 PA |
756 | mips_supply_register_32bit (struct regcache *regcache, |
757 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
758 | { |
759 | union mips_register tmp_reg; | |
760 | int reg32; | |
761 | ||
762 | memcpy (®32, buf, 4); | |
763 | tmp_reg.reg64 = reg32; | |
442ea881 | 764 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
765 | } |
766 | ||
767 | static void | |
442ea881 | 768 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 769 | { |
1996e237 | 770 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 771 | int i, use_64bit; |
3aee8918 | 772 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 773 | |
3aee8918 | 774 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 775 | |
117ce543 | 776 | for (i = 1; i < 32; i++) |
442ea881 PA |
777 | mips_collect_register (regcache, use_64bit, i, regset + i); |
778 | ||
779 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 780 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 781 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 782 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 783 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 784 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 785 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 786 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 787 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 788 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 789 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 790 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
791 | |
792 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 793 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
794 | } |
795 | ||
796 | static void | |
442ea881 | 797 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 798 | { |
1996e237 | 799 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
800 | int i, use_64bit; |
801 | ||
3aee8918 | 802 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 | 803 | |
e4439e43 MR |
804 | supply_register_by_name_zeroed (regcache, "r0"); |
805 | ||
806 | for (i = 1; i < 32; i++) | |
442ea881 PA |
807 | mips_supply_register (regcache, use_64bit, i, regset + i); |
808 | ||
442ea881 | 809 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
810 | find_regno (regcache->tdesc, "lo"), regset + 32); |
811 | mips_supply_register (regcache, use_64bit, | |
812 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 813 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 814 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 815 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
816 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
817 | mips_supply_register (regcache, use_64bit, | |
818 | find_regno (regcache->tdesc, "status"), regset + 36); | |
819 | mips_supply_register (regcache, use_64bit, | |
820 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
821 | |
822 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 823 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
824 | } |
825 | ||
826 | static void | |
442ea881 | 827 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 828 | { |
1996e237 | 829 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
830 | int i, use_64bit, first_fp, big_endian; |
831 | ||
3aee8918 PA |
832 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
833 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
834 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
835 | ||
836 | /* See GDB for a discussion of this peculiar layout. */ | |
837 | for (i = 0; i < 32; i++) | |
838 | if (use_64bit) | |
442ea881 | 839 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 840 | else |
442ea881 | 841 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
842 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
843 | ||
442ea881 | 844 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
845 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
846 | mips_collect_register_32bit (regcache, use_64bit, | |
847 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
848 | regset[32].buf + 4); |
849 | } | |
850 | ||
851 | static void | |
442ea881 | 852 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 853 | { |
1996e237 | 854 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
855 | int i, use_64bit, first_fp, big_endian; |
856 | ||
3aee8918 PA |
857 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
858 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
859 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
860 | ||
861 | /* See GDB for a discussion of this peculiar layout. */ | |
862 | for (i = 0; i < 32; i++) | |
863 | if (use_64bit) | |
442ea881 | 864 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 865 | else |
442ea881 | 866 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
867 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
868 | ||
442ea881 | 869 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
870 | find_regno (regcache->tdesc, "fcsr"), |
871 | regset[32].buf); | |
872 | mips_supply_register_32bit (regcache, use_64bit, | |
873 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
874 | regset[32].buf + 4); |
875 | } | |
876 | #endif /* HAVE_PTRACE_GETREGS */ | |
877 | ||
7e947ad3 MR |
878 | /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side. */ |
879 | ||
880 | static void | |
881 | mips_collect_ptrace_register (struct regcache *regcache, | |
882 | int regno, char *buf) | |
883 | { | |
7e947ad3 MR |
884 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
885 | ||
886 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
887 | { | |
888 | union mips_register reg; | |
889 | ||
890 | mips_collect_register (regcache, 0, regno, ®); | |
891 | memcpy (buf, ®, sizeof (reg)); | |
892 | } | |
893 | else | |
894 | collect_register (regcache, regno, buf); | |
895 | } | |
896 | ||
897 | /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side. */ | |
898 | ||
899 | static void | |
900 | mips_supply_ptrace_register (struct regcache *regcache, | |
901 | int regno, const char *buf) | |
902 | { | |
7e947ad3 MR |
903 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
904 | ||
905 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
906 | { | |
907 | union mips_register reg; | |
908 | ||
909 | memcpy (®, buf, sizeof (reg)); | |
910 | mips_supply_register (regcache, 0, regno, ®); | |
911 | } | |
912 | else | |
913 | supply_register (regcache, regno, buf); | |
914 | } | |
915 | ||
3aee8918 | 916 | static struct regset_info mips_regsets[] = { |
186947f7 | 917 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 918 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 919 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 920 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
921 | mips_fill_fpregset, mips_store_fpregset }, |
922 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 923 | NULL_REGSET |
186947f7 DJ |
924 | }; |
925 | ||
3aee8918 PA |
926 | static struct regsets_info mips_regsets_info = |
927 | { | |
928 | mips_regsets, /* regsets */ | |
929 | 0, /* num_regsets */ | |
930 | NULL, /* disabled_regsets */ | |
931 | }; | |
932 | ||
933 | static struct usrregs_info mips_dsp_usrregs_info = | |
934 | { | |
935 | mips_dsp_num_regs, | |
936 | mips_dsp_regmap, | |
937 | }; | |
938 | ||
939 | static struct usrregs_info mips_usrregs_info = | |
940 | { | |
941 | mips_num_regs, | |
942 | mips_regmap, | |
943 | }; | |
944 | ||
945 | static struct regs_info dsp_regs_info = | |
946 | { | |
947 | mips_dsp_regset_bitmap, | |
948 | &mips_dsp_usrregs_info, | |
949 | &mips_regsets_info | |
950 | }; | |
951 | ||
aa8d21c9 | 952 | static struct regs_info myregs_info = |
3aee8918 PA |
953 | { |
954 | NULL, /* regset_bitmap */ | |
955 | &mips_usrregs_info, | |
956 | &mips_regsets_info | |
957 | }; | |
958 | ||
aa8d21c9 TBA |
959 | const regs_info * |
960 | mips_target::get_regs_info () | |
3aee8918 PA |
961 | { |
962 | if (have_dsp) | |
963 | return &dsp_regs_info; | |
964 | else | |
aa8d21c9 | 965 | return &myregs_info; |
3aee8918 PA |
966 | } |
967 | ||
2ec06d2e | 968 | struct linux_target_ops the_low_target = { |
fa5308bd | 969 | NULL, /* get_next_pcs */ |
0d62e5e8 DJ |
970 | 0, |
971 | mips_breakpoint_at, | |
802e8e6d | 972 | mips_supports_z_point_type, |
7a60ad40 YQ |
973 | mips_insert_point, |
974 | mips_remove_point, | |
975 | mips_stopped_by_watchpoint, | |
976 | mips_stopped_data_address, | |
7e947ad3 MR |
977 | mips_collect_ptrace_register, |
978 | mips_supply_ptrace_register, | |
7a60ad40 YQ |
979 | NULL, /* siginfo_fixup */ |
980 | mips_linux_new_process, | |
04ec7890 | 981 | mips_linux_delete_process, |
7a60ad40 | 982 | mips_linux_new_thread, |
466eecee | 983 | mips_linux_delete_thread, |
3a8a0396 | 984 | mips_linux_new_fork, |
7a60ad40 | 985 | mips_linux_prepare_to_resume |
2ec06d2e | 986 | }; |
3aee8918 | 987 | |
ef0478f6 TBA |
988 | /* The linux target ops object. */ |
989 | ||
990 | linux_process_target *the_linux_target = &the_mips_target; | |
991 | ||
3aee8918 PA |
992 | void |
993 | initialize_low_arch (void) | |
994 | { | |
995 | /* Initialize the Linux target descriptions. */ | |
996 | init_registers_mips_linux (); | |
997 | init_registers_mips_dsp_linux (); | |
998 | init_registers_mips64_linux (); | |
999 | init_registers_mips64_dsp_linux (); | |
1000 | ||
1001 | initialize_regsets_info (&mips_regsets_info); | |
1002 | } |