Commit | Line | Data |
---|---|---|
0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
ef0478f6 TBA |
28 | /* Linux target op definitions for the MIPS architecture. */ |
29 | ||
30 | class mips_target : public linux_process_target | |
31 | { | |
32 | public: | |
33 | ||
aa8d21c9 TBA |
34 | const regs_info *get_regs_info () override; |
35 | ||
3ca4edb6 TBA |
36 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
37 | ||
797bcff5 TBA |
38 | protected: |
39 | ||
40 | void low_arch_setup () override; | |
daca57a7 TBA |
41 | |
42 | bool low_cannot_fetch_register (int regno) override; | |
43 | ||
44 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
45 | |
46 | bool low_fetch_register (regcache *regcache, int regno) override; | |
bf9ae9d8 TBA |
47 | |
48 | bool low_supports_breakpoints () override; | |
49 | ||
50 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
51 | ||
52 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
d7146cda TBA |
53 | |
54 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
ef0478f6 TBA |
55 | }; |
56 | ||
57 | /* The singleton target ops object. */ | |
58 | ||
59 | static mips_target the_mips_target; | |
60 | ||
d05b4ac3 UW |
61 | /* Defined in auto-generated file mips-linux.c. */ |
62 | void init_registers_mips_linux (void); | |
3aee8918 PA |
63 | extern const struct target_desc *tdesc_mips_linux; |
64 | ||
1faeff08 MR |
65 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
66 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
67 | extern const struct target_desc *tdesc_mips_dsp_linux; |
68 | ||
d05b4ac3 UW |
69 | /* Defined in auto-generated file mips64-linux.c. */ |
70 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
71 | extern const struct target_desc *tdesc_mips64_linux; |
72 | ||
1faeff08 MR |
73 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
74 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 75 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
76 | |
77 | #ifdef __mips64 | |
3aee8918 PA |
78 | #define tdesc_mips_linux tdesc_mips64_linux |
79 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 80 | #endif |
d05b4ac3 | 81 | |
21b0f40c DJ |
82 | #ifndef PTRACE_GET_THREAD_AREA |
83 | #define PTRACE_GET_THREAD_AREA 25 | |
84 | #endif | |
85 | ||
0a30fbc4 DJ |
86 | #ifdef HAVE_SYS_REG_H |
87 | #include <sys/reg.h> | |
88 | #endif | |
89 | ||
117ce543 | 90 | #define mips_num_regs 73 |
1faeff08 | 91 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
92 | |
93 | #include <asm/ptrace.h> | |
94 | ||
1faeff08 MR |
95 | #ifndef DSP_BASE |
96 | #define DSP_BASE 71 | |
97 | #define DSP_CONTROL 77 | |
98 | #endif | |
99 | ||
186947f7 DJ |
100 | union mips_register |
101 | { | |
102 | unsigned char buf[8]; | |
103 | ||
104 | /* Deliberately signed, for proper sign extension. */ | |
105 | int reg32; | |
106 | long long reg64; | |
107 | }; | |
108 | ||
0a30fbc4 DJ |
109 | /* Return the ptrace ``address'' of register REGNO. */ |
110 | ||
1faeff08 MR |
111 | #define mips_base_regs \ |
112 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
113 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
114 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
115 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
116 | \ | |
117 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
118 | \ | |
119 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
120 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
121 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
122 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
123 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
124 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
125 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
126 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
127 | FPC_CSR, FPC_EIR | |
128 | ||
129 | #define mips_dsp_regs \ | |
130 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
131 | DSP_BASE + 4, DSP_BASE + 5, \ | |
132 | DSP_CONTROL | |
133 | ||
134 | static int mips_regmap[mips_num_regs] = { | |
135 | mips_base_regs, | |
136 | 0 | |
137 | }; | |
0a30fbc4 | 138 | |
1faeff08 MR |
139 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
140 | mips_base_regs, | |
141 | mips_dsp_regs, | |
142 | 0 | |
143 | }; | |
0a30fbc4 | 144 | |
1faeff08 MR |
145 | /* DSP registers are not in any regset and can only be accessed |
146 | individually. */ | |
0a30fbc4 | 147 | |
1faeff08 MR |
148 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
149 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
150 | }; |
151 | ||
3aee8918 PA |
152 | static int have_dsp = -1; |
153 | ||
1faeff08 MR |
154 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
155 | user register set accordingly. */ | |
156 | ||
3aee8918 PA |
157 | static const struct target_desc * |
158 | mips_read_description (void) | |
1faeff08 | 159 | { |
3aee8918 | 160 | if (have_dsp < 0) |
1faeff08 | 161 | { |
0bfdf32f | 162 | int pid = lwpid_of (current_thread); |
1faeff08 | 163 | |
ac740bc7 | 164 | errno = 0; |
1faeff08 MR |
165 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
166 | switch (errno) | |
167 | { | |
168 | case 0: | |
3aee8918 | 169 | have_dsp = 1; |
1faeff08 MR |
170 | break; |
171 | case EIO: | |
3aee8918 | 172 | have_dsp = 0; |
1faeff08 MR |
173 | break; |
174 | default: | |
175 | perror_with_name ("ptrace"); | |
176 | break; | |
177 | } | |
178 | } | |
3aee8918 PA |
179 | |
180 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
181 | } | |
182 | ||
797bcff5 TBA |
183 | void |
184 | mips_target::low_arch_setup () | |
3aee8918 PA |
185 | { |
186 | current_process ()->tdesc = mips_read_description (); | |
187 | } | |
188 | ||
7a60ad40 YQ |
189 | /* Per-process arch-specific data we want to keep. */ |
190 | ||
191 | struct arch_process_info | |
192 | { | |
193 | /* -1 if the kernel and/or CPU do not support watch registers. | |
194 | 1 if watch_readback is valid and we can read style, num_valid | |
195 | and the masks. | |
196 | 0 if we need to read the watch_readback. */ | |
197 | ||
198 | int watch_readback_valid; | |
199 | ||
200 | /* Cached watch register read values. */ | |
201 | ||
202 | struct pt_watch_regs watch_readback; | |
203 | ||
204 | /* Current watchpoint requests for this process. */ | |
205 | ||
206 | struct mips_watchpoint *current_watches; | |
207 | ||
208 | /* The current set of watch register values for writing the | |
209 | registers. */ | |
210 | ||
211 | struct pt_watch_regs watch_mirror; | |
212 | }; | |
213 | ||
214 | /* Per-thread arch-specific data we want to keep. */ | |
215 | ||
216 | struct arch_lwp_info | |
217 | { | |
218 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
219 | int watch_registers_changed; | |
220 | }; | |
221 | ||
0a30fbc4 DJ |
222 | /* From mips-linux-nat.c. */ |
223 | ||
224 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
225 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
e4439e43 MR |
226 | ZERO_REGNUM, it's always 0. We also can not set BADVADDR, CAUSE, |
227 | or FCRIR via ptrace(). */ | |
0a30fbc4 | 228 | |
daca57a7 TBA |
229 | bool |
230 | mips_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 231 | { |
3aee8918 PA |
232 | const struct target_desc *tdesc; |
233 | ||
daca57a7 TBA |
234 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
235 | return true; | |
0a30fbc4 | 236 | |
3aee8918 PA |
237 | tdesc = current_process ()->tdesc; |
238 | ||
75d74cca MR |
239 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ |
240 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 241 | return true; |
75d74cca | 242 | |
3aee8918 | 243 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 244 | return true; |
0a30fbc4 | 245 | |
daca57a7 | 246 | return false; |
0a30fbc4 DJ |
247 | } |
248 | ||
daca57a7 TBA |
249 | bool |
250 | mips_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 251 | { |
3aee8918 PA |
252 | const struct target_desc *tdesc; |
253 | ||
daca57a7 TBA |
254 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
255 | return true; | |
0a30fbc4 | 256 | |
3aee8918 PA |
257 | tdesc = current_process ()->tdesc; |
258 | ||
75d74cca MR |
259 | /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ |
260 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 261 | return true; |
75d74cca | 262 | |
3aee8918 | 263 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 264 | return true; |
0a30fbc4 | 265 | |
3aee8918 | 266 | if (find_regno (tdesc, "cause") == regno) |
daca57a7 | 267 | return true; |
0a30fbc4 | 268 | |
3aee8918 | 269 | if (find_regno (tdesc, "badvaddr") == regno) |
daca57a7 | 270 | return true; |
0a30fbc4 | 271 | |
3aee8918 | 272 | if (find_regno (tdesc, "fir") == regno) |
daca57a7 | 273 | return true; |
0a30fbc4 | 274 | |
daca57a7 | 275 | return false; |
0a30fbc4 | 276 | } |
2ec06d2e | 277 | |
bd70b1f2 TBA |
278 | bool |
279 | mips_target::low_fetch_register (regcache *regcache, int regno) | |
e4439e43 MR |
280 | { |
281 | const struct target_desc *tdesc = current_process ()->tdesc; | |
282 | ||
283 | if (find_regno (tdesc, "r0") == regno) | |
284 | { | |
285 | supply_register_zeroed (regcache, regno); | |
bd70b1f2 | 286 | return true; |
e4439e43 MR |
287 | } |
288 | ||
bd70b1f2 | 289 | return false; |
e4439e43 MR |
290 | } |
291 | ||
bf9ae9d8 TBA |
292 | bool |
293 | mips_target::low_supports_breakpoints () | |
294 | { | |
295 | return true; | |
296 | } | |
297 | ||
298 | CORE_ADDR | |
299 | mips_target::low_get_pc (regcache *regcache) | |
0d62e5e8 | 300 | { |
186947f7 | 301 | union mips_register pc; |
442ea881 | 302 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 303 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
304 | } |
305 | ||
bf9ae9d8 TBA |
306 | void |
307 | mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
0d62e5e8 | 308 | { |
186947f7 | 309 | union mips_register newpc; |
3aee8918 | 310 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
311 | newpc.reg32 = pc; |
312 | else | |
313 | newpc.reg64 = pc; | |
314 | ||
442ea881 | 315 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
316 | } |
317 | ||
318 | /* Correct in either endianness. */ | |
186947f7 | 319 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
320 | #define mips_breakpoint_len 4 |
321 | ||
3ca4edb6 | 322 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 323 | |
3ca4edb6 TBA |
324 | const gdb_byte * |
325 | mips_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
326 | { |
327 | *size = mips_breakpoint_len; | |
328 | return (const gdb_byte *) &mips_breakpoint; | |
329 | } | |
330 | ||
d7146cda TBA |
331 | bool |
332 | mips_target::low_breakpoint_at (CORE_ADDR where) | |
0d62e5e8 | 333 | { |
186947f7 | 334 | unsigned int insn; |
0d62e5e8 | 335 | |
d7146cda | 336 | read_memory (where, (unsigned char *) &insn, 4); |
0d62e5e8 | 337 | if (insn == mips_breakpoint) |
d7146cda | 338 | return true; |
0d62e5e8 DJ |
339 | |
340 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
341 | one. */ | |
d7146cda | 342 | return false; |
0d62e5e8 DJ |
343 | } |
344 | ||
da25033c | 345 | /* Mark the watch registers of lwp, represented by ENTRY, as changed. */ |
7a60ad40 | 346 | |
da25033c SM |
347 | static void |
348 | update_watch_registers_callback (thread_info *thread) | |
7a60ad40 | 349 | { |
d86d4aaf | 350 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 | 351 | |
da25033c SM |
352 | /* The actual update is done later just before resuming the lwp, |
353 | we just mark that the registers need updating. */ | |
354 | lwp->arch_private->watch_registers_changed = 1; | |
7a60ad40 | 355 | |
da25033c SM |
356 | /* If the lwp isn't stopped, force it to momentarily pause, so |
357 | we can update its watch registers. */ | |
358 | if (!lwp->stopped) | |
359 | linux_stop_lwp (lwp); | |
7a60ad40 YQ |
360 | } |
361 | ||
362 | /* This is the implementation of linux_target_ops method | |
363 | new_process. */ | |
364 | ||
365 | static struct arch_process_info * | |
366 | mips_linux_new_process (void) | |
367 | { | |
8d749320 | 368 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
369 | |
370 | return info; | |
371 | } | |
372 | ||
04ec7890 SM |
373 | /* This is the implementation of linux_target_ops method |
374 | delete_process. */ | |
375 | ||
376 | static void | |
377 | mips_linux_delete_process (struct arch_process_info *info) | |
378 | { | |
379 | xfree (info); | |
380 | } | |
381 | ||
7a60ad40 YQ |
382 | /* This is the implementation of linux_target_ops method new_thread. |
383 | Mark the watch registers as changed, so the threads' copies will | |
384 | be updated. */ | |
385 | ||
34c703da GB |
386 | static void |
387 | mips_linux_new_thread (struct lwp_info *lwp) | |
7a60ad40 | 388 | { |
8d749320 | 389 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
390 | |
391 | info->watch_registers_changed = 1; | |
392 | ||
34c703da | 393 | lwp->arch_private = info; |
7a60ad40 YQ |
394 | } |
395 | ||
466eecee SM |
396 | /* Function to call when a thread is being deleted. */ |
397 | ||
398 | static void | |
399 | mips_linux_delete_thread (struct arch_lwp_info *arch_lwp) | |
400 | { | |
401 | xfree (arch_lwp); | |
402 | } | |
403 | ||
3a8a0396 DB |
404 | /* Create a new mips_watchpoint and add it to the list. */ |
405 | ||
406 | static void | |
cbec665b | 407 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 408 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
409 | { |
410 | struct mips_watchpoint *new_watch; | |
411 | struct mips_watchpoint **pw; | |
412 | ||
8d749320 | 413 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
414 | new_watch->addr = addr; |
415 | new_watch->len = len; | |
416 | new_watch->type = watch_type; | |
417 | new_watch->next = NULL; | |
418 | ||
cbec665b | 419 | pw = &priv->current_watches; |
3a8a0396 DB |
420 | while (*pw != NULL) |
421 | pw = &(*pw)->next; | |
422 | *pw = new_watch; | |
423 | } | |
424 | ||
425 | /* Hook to call when a new fork is attached. */ | |
426 | ||
427 | static void | |
428 | mips_linux_new_fork (struct process_info *parent, | |
429 | struct process_info *child) | |
430 | { | |
431 | struct arch_process_info *parent_private; | |
432 | struct arch_process_info *child_private; | |
433 | struct mips_watchpoint *wp; | |
434 | ||
435 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
436 | gdb_assert (parent->priv != NULL |
437 | && parent->priv->arch_private != NULL); | |
438 | gdb_assert (child->priv != NULL | |
439 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
440 | |
441 | /* Linux kernel before 2.6.33 commit | |
442 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
443 | will inherit hardware debug registers from parent | |
444 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
445 | zeroed debug registers. | |
446 | ||
447 | GDB core assumes the child inherits the watchpoints/hw | |
448 | breakpoints of the parent, and will remove them all from the | |
449 | forked off process. Copy the debug registers mirrors into the | |
450 | new process so that all breakpoints and watchpoints can be | |
451 | removed together. The debug registers mirror will become zeroed | |
452 | in the end before detaching the forked off process, thus making | |
453 | this compatible with older Linux kernels too. */ | |
454 | ||
61a7418c DB |
455 | parent_private = parent->priv->arch_private; |
456 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
457 | |
458 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
459 | child_private->watch_readback = parent_private->watch_readback; | |
460 | ||
461 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
462 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
463 | ||
464 | child_private->watch_mirror = parent_private->watch_mirror; | |
465 | } | |
7a60ad40 YQ |
466 | /* This is the implementation of linux_target_ops method |
467 | prepare_to_resume. If the watch regs have changed, update the | |
468 | thread's copies. */ | |
469 | ||
470 | static void | |
471 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
472 | { | |
d86d4aaf | 473 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
e99b03dc | 474 | struct process_info *proc = find_process_pid (ptid.pid ()); |
fe978cb0 | 475 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
476 | |
477 | if (lwp->arch_private->watch_registers_changed) | |
478 | { | |
479 | /* Only update the watch registers if we have set or unset a | |
480 | watchpoint already. */ | |
fe978cb0 | 481 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
482 | { |
483 | /* Write the mirrored watch register values. */ | |
e38504b3 | 484 | int tid = ptid.lwp (); |
7a60ad40 YQ |
485 | |
486 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 487 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
488 | perror_with_name ("Couldn't write watch register"); |
489 | } | |
490 | ||
491 | lwp->arch_private->watch_registers_changed = 0; | |
492 | } | |
493 | } | |
494 | ||
802e8e6d PA |
495 | static int |
496 | mips_supports_z_point_type (char z_type) | |
497 | { | |
498 | switch (z_type) | |
499 | { | |
500 | case Z_PACKET_WRITE_WP: | |
501 | case Z_PACKET_READ_WP: | |
502 | case Z_PACKET_ACCESS_WP: | |
503 | return 1; | |
504 | default: | |
505 | return 0; | |
506 | } | |
507 | } | |
508 | ||
7a60ad40 YQ |
509 | /* This is the implementation of linux_target_ops method |
510 | insert_point. */ | |
511 | ||
512 | static int | |
802e8e6d PA |
513 | mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
514 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
515 | { |
516 | struct process_info *proc = current_process (); | |
fe978cb0 | 517 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 518 | struct pt_watch_regs regs; |
7a60ad40 YQ |
519 | long lwpid; |
520 | enum target_hw_bp_type watch_type; | |
521 | uint32_t irw; | |
522 | ||
0bfdf32f | 523 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 524 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
525 | &priv->watch_readback, |
526 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
527 | 0)) |
528 | return -1; | |
529 | ||
530 | if (len <= 0) | |
531 | return -1; | |
532 | ||
fe978cb0 | 533 | regs = priv->watch_readback; |
7a60ad40 | 534 | /* Add the current watches. */ |
fe978cb0 | 535 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
536 | |
537 | /* Now try to add the new watch. */ | |
802e8e6d | 538 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
539 | irw = mips_linux_watch_type_to_irw (watch_type); |
540 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
541 | return -1; | |
542 | ||
543 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 544 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 545 | |
fe978cb0 | 546 | priv->watch_mirror = regs; |
7a60ad40 YQ |
547 | |
548 | /* Only update the threads of this process. */ | |
da25033c | 549 | for_each_thread (proc->pid, update_watch_registers_callback); |
7a60ad40 YQ |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
554 | /* This is the implementation of linux_target_ops method | |
555 | remove_point. */ | |
556 | ||
557 | static int | |
802e8e6d PA |
558 | mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
559 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
560 | { |
561 | struct process_info *proc = current_process (); | |
fe978cb0 | 562 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
563 | |
564 | int deleted_one; | |
7a60ad40 YQ |
565 | enum target_hw_bp_type watch_type; |
566 | ||
567 | struct mips_watchpoint **pw; | |
568 | struct mips_watchpoint *w; | |
569 | ||
7a60ad40 | 570 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 571 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 572 | deleted_one = 0; |
fe978cb0 | 573 | pw = &priv->current_watches; |
7a60ad40 YQ |
574 | while ((w = *pw)) |
575 | { | |
576 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
577 | { | |
578 | *pw = w->next; | |
579 | free (w); | |
580 | deleted_one = 1; | |
581 | break; | |
582 | } | |
583 | pw = &(w->next); | |
584 | } | |
585 | ||
586 | if (!deleted_one) | |
587 | return -1; /* We don't know about it, fail doing nothing. */ | |
588 | ||
589 | /* At this point watch_readback is known to be valid because we | |
590 | could not have added the watch without reading it. */ | |
fe978cb0 | 591 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 592 | |
fe978cb0 PA |
593 | priv->watch_mirror = priv->watch_readback; |
594 | mips_linux_watch_populate_regs (priv->current_watches, | |
595 | &priv->watch_mirror); | |
7a60ad40 YQ |
596 | |
597 | /* Only update the threads of this process. */ | |
da25033c SM |
598 | for_each_thread (proc->pid, update_watch_registers_callback); |
599 | ||
7a60ad40 YQ |
600 | return 0; |
601 | } | |
602 | ||
603 | /* This is the implementation of linux_target_ops method | |
604 | stopped_by_watchpoint. The watchhi R and W bits indicate | |
605 | the watch register triggered. */ | |
606 | ||
607 | static int | |
608 | mips_stopped_by_watchpoint (void) | |
609 | { | |
610 | struct process_info *proc = current_process (); | |
fe978cb0 | 611 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
612 | int n; |
613 | int num_valid; | |
0bfdf32f | 614 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
615 | |
616 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
617 | &priv->watch_readback, |
618 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
619 | 1)) |
620 | return 0; | |
621 | ||
fe978cb0 | 622 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
623 | |
624 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 625 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
626 | & (R_MASK | W_MASK)) |
627 | return 1; | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
632 | /* This is the implementation of linux_target_ops method | |
633 | stopped_data_address. */ | |
634 | ||
635 | static CORE_ADDR | |
636 | mips_stopped_data_address (void) | |
637 | { | |
638 | struct process_info *proc = current_process (); | |
fe978cb0 | 639 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
640 | int n; |
641 | int num_valid; | |
0bfdf32f | 642 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
643 | |
644 | /* On MIPS we don't know the low order 3 bits of the data address. | |
645 | GDB does not support remote targets that can't report the | |
646 | watchpoint address. So, make our best guess; return the starting | |
647 | address of a watchpoint request which overlaps the one that | |
648 | triggered. */ | |
649 | ||
650 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
651 | &priv->watch_readback, |
652 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
653 | 0)) |
654 | return 0; | |
655 | ||
fe978cb0 | 656 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
657 | |
658 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 659 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
660 | & (R_MASK | W_MASK)) |
661 | { | |
662 | CORE_ADDR t_low, t_hi; | |
663 | int t_irw; | |
664 | struct mips_watchpoint *watch; | |
665 | ||
fe978cb0 | 666 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 667 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 668 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
669 | | IRW_MASK); |
670 | t_low &= ~(CORE_ADDR)t_hi; | |
671 | ||
fe978cb0 | 672 | for (watch = priv->current_watches; |
7a60ad40 YQ |
673 | watch != NULL; |
674 | watch = watch->next) | |
675 | { | |
676 | CORE_ADDR addr = watch->addr; | |
677 | CORE_ADDR last_byte = addr + watch->len - 1; | |
678 | ||
679 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
680 | { | |
681 | /* Different type. */ | |
682 | continue; | |
683 | } | |
684 | /* Check for overlap of even a single byte. */ | |
685 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
686 | return addr; | |
687 | } | |
688 | } | |
689 | ||
690 | /* Shouldn't happen. */ | |
691 | return 0; | |
692 | } | |
693 | ||
21b0f40c DJ |
694 | /* Fetch the thread-local storage pointer for libthread_db. */ |
695 | ||
696 | ps_err_e | |
754653a7 | 697 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 698 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
699 | { |
700 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
701 | return PS_ERR; | |
702 | ||
703 | /* IDX is the bias from the thread pointer to the beginning of the | |
704 | thread descriptor. It has to be subtracted due to implementation | |
705 | quirks in libthread_db. */ | |
706 | *base = (void *) ((char *)*base - idx); | |
707 | ||
708 | return PS_OK; | |
709 | } | |
710 | ||
186947f7 | 711 | static void |
442ea881 PA |
712 | mips_collect_register (struct regcache *regcache, |
713 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
714 | { |
715 | union mips_register tmp_reg; | |
716 | ||
717 | if (use_64bit) | |
718 | { | |
442ea881 | 719 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
720 | *reg = tmp_reg; |
721 | } | |
722 | else | |
723 | { | |
442ea881 | 724 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
725 | reg->reg64 = tmp_reg.reg32; |
726 | } | |
727 | } | |
728 | ||
729 | static void | |
442ea881 PA |
730 | mips_supply_register (struct regcache *regcache, |
731 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
732 | { |
733 | int offset = 0; | |
734 | ||
735 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
736 | eight-byte slot. */ | |
737 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
738 | offset = 4; | |
739 | ||
442ea881 | 740 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
741 | } |
742 | ||
7e947ad3 MR |
743 | #ifdef HAVE_PTRACE_GETREGS |
744 | ||
186947f7 | 745 | static void |
442ea881 PA |
746 | mips_collect_register_32bit (struct regcache *regcache, |
747 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
748 | { |
749 | union mips_register tmp_reg; | |
750 | int reg32; | |
751 | ||
442ea881 | 752 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
753 | reg32 = tmp_reg.reg64; |
754 | memcpy (buf, ®32, 4); | |
755 | } | |
756 | ||
757 | static void | |
442ea881 PA |
758 | mips_supply_register_32bit (struct regcache *regcache, |
759 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
760 | { |
761 | union mips_register tmp_reg; | |
762 | int reg32; | |
763 | ||
764 | memcpy (®32, buf, 4); | |
765 | tmp_reg.reg64 = reg32; | |
442ea881 | 766 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
767 | } |
768 | ||
769 | static void | |
442ea881 | 770 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 771 | { |
1996e237 | 772 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 773 | int i, use_64bit; |
3aee8918 | 774 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 775 | |
3aee8918 | 776 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 777 | |
117ce543 | 778 | for (i = 1; i < 32; i++) |
442ea881 PA |
779 | mips_collect_register (regcache, use_64bit, i, regset + i); |
780 | ||
781 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 782 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 783 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 784 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 785 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 786 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 787 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 788 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 789 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 790 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 791 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 792 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
793 | |
794 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 795 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
796 | } |
797 | ||
798 | static void | |
442ea881 | 799 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 800 | { |
1996e237 | 801 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
802 | int i, use_64bit; |
803 | ||
3aee8918 | 804 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 | 805 | |
e4439e43 MR |
806 | supply_register_by_name_zeroed (regcache, "r0"); |
807 | ||
808 | for (i = 1; i < 32; i++) | |
442ea881 PA |
809 | mips_supply_register (regcache, use_64bit, i, regset + i); |
810 | ||
442ea881 | 811 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
812 | find_regno (regcache->tdesc, "lo"), regset + 32); |
813 | mips_supply_register (regcache, use_64bit, | |
814 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 815 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 816 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 817 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
818 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
819 | mips_supply_register (regcache, use_64bit, | |
820 | find_regno (regcache->tdesc, "status"), regset + 36); | |
821 | mips_supply_register (regcache, use_64bit, | |
822 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
823 | |
824 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 825 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
826 | } |
827 | ||
828 | static void | |
442ea881 | 829 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 830 | { |
1996e237 | 831 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
832 | int i, use_64bit, first_fp, big_endian; |
833 | ||
3aee8918 PA |
834 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
835 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
836 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
837 | ||
838 | /* See GDB for a discussion of this peculiar layout. */ | |
839 | for (i = 0; i < 32; i++) | |
840 | if (use_64bit) | |
442ea881 | 841 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 842 | else |
442ea881 | 843 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
844 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
845 | ||
442ea881 | 846 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
847 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
848 | mips_collect_register_32bit (regcache, use_64bit, | |
849 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
850 | regset[32].buf + 4); |
851 | } | |
852 | ||
853 | static void | |
442ea881 | 854 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 855 | { |
1996e237 | 856 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
857 | int i, use_64bit, first_fp, big_endian; |
858 | ||
3aee8918 PA |
859 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
860 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
861 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
862 | ||
863 | /* See GDB for a discussion of this peculiar layout. */ | |
864 | for (i = 0; i < 32; i++) | |
865 | if (use_64bit) | |
442ea881 | 866 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 867 | else |
442ea881 | 868 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
869 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
870 | ||
442ea881 | 871 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
872 | find_regno (regcache->tdesc, "fcsr"), |
873 | regset[32].buf); | |
874 | mips_supply_register_32bit (regcache, use_64bit, | |
875 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
876 | regset[32].buf + 4); |
877 | } | |
878 | #endif /* HAVE_PTRACE_GETREGS */ | |
879 | ||
7e947ad3 MR |
880 | /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side. */ |
881 | ||
882 | static void | |
883 | mips_collect_ptrace_register (struct regcache *regcache, | |
884 | int regno, char *buf) | |
885 | { | |
7e947ad3 MR |
886 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
887 | ||
888 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
889 | { | |
890 | union mips_register reg; | |
891 | ||
892 | mips_collect_register (regcache, 0, regno, ®); | |
893 | memcpy (buf, ®, sizeof (reg)); | |
894 | } | |
895 | else | |
896 | collect_register (regcache, regno, buf); | |
897 | } | |
898 | ||
899 | /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side. */ | |
900 | ||
901 | static void | |
902 | mips_supply_ptrace_register (struct regcache *regcache, | |
903 | int regno, const char *buf) | |
904 | { | |
7e947ad3 MR |
905 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
906 | ||
907 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
908 | { | |
909 | union mips_register reg; | |
910 | ||
911 | memcpy (®, buf, sizeof (reg)); | |
912 | mips_supply_register (regcache, 0, regno, ®); | |
913 | } | |
914 | else | |
915 | supply_register (regcache, regno, buf); | |
916 | } | |
917 | ||
3aee8918 | 918 | static struct regset_info mips_regsets[] = { |
186947f7 | 919 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 920 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 921 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 922 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
923 | mips_fill_fpregset, mips_store_fpregset }, |
924 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 925 | NULL_REGSET |
186947f7 DJ |
926 | }; |
927 | ||
3aee8918 PA |
928 | static struct regsets_info mips_regsets_info = |
929 | { | |
930 | mips_regsets, /* regsets */ | |
931 | 0, /* num_regsets */ | |
932 | NULL, /* disabled_regsets */ | |
933 | }; | |
934 | ||
935 | static struct usrregs_info mips_dsp_usrregs_info = | |
936 | { | |
937 | mips_dsp_num_regs, | |
938 | mips_dsp_regmap, | |
939 | }; | |
940 | ||
941 | static struct usrregs_info mips_usrregs_info = | |
942 | { | |
943 | mips_num_regs, | |
944 | mips_regmap, | |
945 | }; | |
946 | ||
947 | static struct regs_info dsp_regs_info = | |
948 | { | |
949 | mips_dsp_regset_bitmap, | |
950 | &mips_dsp_usrregs_info, | |
951 | &mips_regsets_info | |
952 | }; | |
953 | ||
aa8d21c9 | 954 | static struct regs_info myregs_info = |
3aee8918 PA |
955 | { |
956 | NULL, /* regset_bitmap */ | |
957 | &mips_usrregs_info, | |
958 | &mips_regsets_info | |
959 | }; | |
960 | ||
aa8d21c9 TBA |
961 | const regs_info * |
962 | mips_target::get_regs_info () | |
3aee8918 PA |
963 | { |
964 | if (have_dsp) | |
965 | return &dsp_regs_info; | |
966 | else | |
aa8d21c9 | 967 | return &myregs_info; |
3aee8918 PA |
968 | } |
969 | ||
2ec06d2e | 970 | struct linux_target_ops the_low_target = { |
802e8e6d | 971 | mips_supports_z_point_type, |
7a60ad40 YQ |
972 | mips_insert_point, |
973 | mips_remove_point, | |
974 | mips_stopped_by_watchpoint, | |
975 | mips_stopped_data_address, | |
7e947ad3 MR |
976 | mips_collect_ptrace_register, |
977 | mips_supply_ptrace_register, | |
7a60ad40 YQ |
978 | NULL, /* siginfo_fixup */ |
979 | mips_linux_new_process, | |
04ec7890 | 980 | mips_linux_delete_process, |
7a60ad40 | 981 | mips_linux_new_thread, |
466eecee | 982 | mips_linux_delete_thread, |
3a8a0396 | 983 | mips_linux_new_fork, |
7a60ad40 | 984 | mips_linux_prepare_to_resume |
2ec06d2e | 985 | }; |
3aee8918 | 986 | |
ef0478f6 TBA |
987 | /* The linux target ops object. */ |
988 | ||
989 | linux_process_target *the_linux_target = &the_mips_target; | |
990 | ||
3aee8918 PA |
991 | void |
992 | initialize_low_arch (void) | |
993 | { | |
994 | /* Initialize the Linux target descriptions. */ | |
995 | init_registers_mips_linux (); | |
996 | init_registers_mips_dsp_linux (); | |
997 | init_registers_mips64_linux (); | |
998 | init_registers_mips64_dsp_linux (); | |
999 | ||
1000 | initialize_regsets_info (&mips_regsets_info); | |
1001 | } |