Commit | Line | Data |
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0a30fbc4 DJ |
1 | /* GNU/Linux/PowerPC specific low level interface, for the remote server for |
2 | GDB. | |
b811d2c2 | 3 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
19 | |
20 | #include "server.h" | |
58caa3dc | 21 | #include "linux-low.h" |
0a30fbc4 | 22 | |
7ca18ed6 EBM |
23 | #include "elf/common.h" |
24 | #include <sys/uio.h> | |
b6430ec3 | 25 | #include <elf.h> |
0a30fbc4 DJ |
26 | #include <asm/ptrace.h> |
27 | ||
bd64614e PFC |
28 | #include "arch/ppc-linux-common.h" |
29 | #include "arch/ppc-linux-tdesc.h" | |
514c5338 | 30 | #include "nat/ppc-linux.h" |
64f57f3d | 31 | #include "nat/linux-ptrace.h" |
bd64614e | 32 | #include "linux-ppc-tdesc-init.h" |
a2174ba4 MK |
33 | #include "ax.h" |
34 | #include "tracepoint.h" | |
35 | ||
36 | #define PPC_FIELD(value, from, len) \ | |
37 | (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1)) | |
38 | #define PPC_SEXT(v, bs) \ | |
39 | ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \ | |
40 | ^ ((CORE_ADDR) 1 << ((bs) - 1))) \ | |
41 | - ((CORE_ADDR) 1 << ((bs) - 1))) | |
42 | #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6) | |
43 | #define PPC_BO(insn) PPC_FIELD (insn, 6, 5) | |
44 | #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2) | |
45 | #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2) | |
b6430ec3 | 46 | |
ef0478f6 TBA |
47 | /* Linux target op definitions for the PowerPC architecture. */ |
48 | ||
49 | class ppc_target : public linux_process_target | |
50 | { | |
51 | public: | |
52 | ||
aa8d21c9 TBA |
53 | const regs_info *get_regs_info () override; |
54 | ||
797bcff5 TBA |
55 | protected: |
56 | ||
57 | void low_arch_setup () override; | |
daca57a7 TBA |
58 | |
59 | bool low_cannot_fetch_register (int regno) override; | |
60 | ||
61 | bool low_cannot_store_register (int regno) override; | |
ef0478f6 TBA |
62 | }; |
63 | ||
64 | /* The singleton target ops object. */ | |
65 | ||
66 | static ppc_target the_ppc_target; | |
67 | ||
7ca18ed6 EBM |
68 | /* Holds the AT_HWCAP auxv entry. */ |
69 | ||
b6430ec3 UW |
70 | static unsigned long ppc_hwcap; |
71 | ||
7ca18ed6 EBM |
72 | /* Holds the AT_HWCAP2 auxv entry. */ |
73 | ||
74 | static unsigned long ppc_hwcap2; | |
75 | ||
b6430ec3 | 76 | |
7284e1be UW |
77 | #define ppc_num_regs 73 |
78 | ||
5b0a002e UW |
79 | #ifdef __powerpc64__ |
80 | /* We use a constant for FPSCR instead of PT_FPSCR, because | |
81 | many shipped PPC64 kernels had the wrong value in ptrace.h. */ | |
82 | static int ppc_regmap[] = | |
83 | {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8, | |
84 | PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8, | |
85 | PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8, | |
86 | PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8, | |
87 | PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8, | |
88 | PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8, | |
89 | PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8, | |
90 | PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8, | |
91 | PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24, | |
92 | PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56, | |
93 | PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88, | |
94 | PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120, | |
95 | PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152, | |
96 | PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184, | |
97 | PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216, | |
98 | PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248, | |
99 | PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8, | |
7284e1be UW |
100 | PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256, |
101 | PT_ORIG_R3 * 8, PT_TRAP * 8 }; | |
5b0a002e | 102 | #else |
0a30fbc4 | 103 | /* Currently, don't check/send MQ. */ |
2ec06d2e | 104 | static int ppc_regmap[] = |
0a30fbc4 DJ |
105 | {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, |
106 | PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, | |
107 | PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, | |
108 | PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, | |
109 | PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, | |
110 | PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, | |
111 | PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, | |
112 | PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, | |
113 | PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24, | |
114 | PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56, | |
115 | PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88, | |
116 | PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120, | |
117 | PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152, | |
118 | PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184, | |
119 | PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216, | |
120 | PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248, | |
121 | PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, | |
7284e1be UW |
122 | PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4, |
123 | PT_ORIG_R3 * 4, PT_TRAP * 4 | |
b6430ec3 UW |
124 | }; |
125 | ||
126 | static int ppc_regmap_e500[] = | |
127 | {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, | |
128 | PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, | |
129 | PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, | |
130 | PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, | |
131 | PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, | |
132 | PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, | |
133 | PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, | |
134 | PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, | |
135 | -1, -1, -1, -1, | |
136 | -1, -1, -1, -1, | |
137 | -1, -1, -1, -1, | |
138 | -1, -1, -1, -1, | |
139 | -1, -1, -1, -1, | |
140 | -1, -1, -1, -1, | |
141 | -1, -1, -1, -1, | |
142 | -1, -1, -1, -1, | |
143 | PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, | |
7284e1be UW |
144 | PT_CTR * 4, PT_XER * 4, -1, |
145 | PT_ORIG_R3 * 4, PT_TRAP * 4 | |
30ed0a8f | 146 | }; |
5b0a002e | 147 | #endif |
0a30fbc4 | 148 | |
7ca18ed6 EBM |
149 | /* Check whether the kernel provides a register set with number |
150 | REGSET_ID of size REGSETSIZE for process/thread TID. */ | |
151 | ||
152 | static int | |
153 | ppc_check_regset (int tid, int regset_id, int regsetsize) | |
154 | { | |
155 | void *buf = alloca (regsetsize); | |
156 | struct iovec iov; | |
157 | ||
158 | iov.iov_base = buf; | |
159 | iov.iov_len = regsetsize; | |
160 | ||
161 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0 | |
162 | || errno == ENODATA) | |
163 | return 1; | |
164 | return 0; | |
165 | } | |
166 | ||
daca57a7 TBA |
167 | bool |
168 | ppc_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 169 | { |
3aee8918 PA |
170 | const struct target_desc *tdesc = current_process ()->tdesc; |
171 | ||
b6430ec3 | 172 | #ifndef __powerpc64__ |
bc1e36ca | 173 | /* Some kernels do not allow us to store fpscr. */ |
3aee8918 PA |
174 | if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE) |
175 | && regno == find_regno (tdesc, "fpscr")) | |
daca57a7 | 176 | return true; |
30ed0a8f | 177 | #endif |
bc1e36ca | 178 | |
7284e1be | 179 | /* Some kernels do not allow us to store orig_r3 or trap. */ |
3aee8918 PA |
180 | if (regno == find_regno (tdesc, "orig_r3") |
181 | || regno == find_regno (tdesc, "trap")) | |
daca57a7 | 182 | return true; |
7284e1be | 183 | |
daca57a7 | 184 | return false; |
0a30fbc4 DJ |
185 | } |
186 | ||
daca57a7 TBA |
187 | bool |
188 | ppc_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 189 | { |
daca57a7 | 190 | return false; |
0a30fbc4 DJ |
191 | } |
192 | ||
5b0a002e | 193 | static void |
442ea881 | 194 | ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) |
5b0a002e | 195 | { |
76b233dd UW |
196 | memset (buf, 0, sizeof (long)); |
197 | ||
2e4bb98a EBM |
198 | if (__BYTE_ORDER == __LITTLE_ENDIAN) |
199 | { | |
200 | /* Little-endian values always sit at the left end of the buffer. */ | |
201 | collect_register (regcache, regno, buf); | |
202 | } | |
203 | else if (__BYTE_ORDER == __BIG_ENDIAN) | |
204 | { | |
205 | /* Big-endian values sit at the right end of the buffer. In case of | |
206 | registers whose sizes are smaller than sizeof (long), we must use a | |
207 | padding to access them correctly. */ | |
208 | int size = register_size (regcache->tdesc, regno); | |
209 | ||
210 | if (size < sizeof (long)) | |
211 | collect_register (regcache, regno, buf + sizeof (long) - size); | |
212 | else | |
213 | collect_register (regcache, regno, buf); | |
214 | } | |
5b0a002e | 215 | else |
2e4bb98a | 216 | perror_with_name ("Unexpected byte order"); |
5b0a002e UW |
217 | } |
218 | ||
219 | static void | |
442ea881 PA |
220 | ppc_supply_ptrace_register (struct regcache *regcache, |
221 | int regno, const char *buf) | |
5b0a002e | 222 | { |
2e4bb98a EBM |
223 | if (__BYTE_ORDER == __LITTLE_ENDIAN) |
224 | { | |
225 | /* Little-endian values always sit at the left end of the buffer. */ | |
226 | supply_register (regcache, regno, buf); | |
227 | } | |
228 | else if (__BYTE_ORDER == __BIG_ENDIAN) | |
229 | { | |
230 | /* Big-endian values sit at the right end of the buffer. In case of | |
231 | registers whose sizes are smaller than sizeof (long), we must use a | |
232 | padding to access them correctly. */ | |
233 | int size = register_size (regcache->tdesc, regno); | |
234 | ||
235 | if (size < sizeof (long)) | |
236 | supply_register (regcache, regno, buf + sizeof (long) - size); | |
237 | else | |
238 | supply_register (regcache, regno, buf); | |
239 | } | |
5b0a002e | 240 | else |
2e4bb98a | 241 | perror_with_name ("Unexpected byte order"); |
5b0a002e UW |
242 | } |
243 | ||
0d62e5e8 | 244 | static CORE_ADDR |
442ea881 | 245 | ppc_get_pc (struct regcache *regcache) |
0d62e5e8 | 246 | { |
abf516c6 | 247 | if (register_size (regcache->tdesc, 0) == 4) |
6fe305f7 UW |
248 | { |
249 | unsigned int pc; | |
442ea881 | 250 | collect_register_by_name (regcache, "pc", &pc); |
6fe305f7 UW |
251 | return (CORE_ADDR) pc; |
252 | } | |
253 | else | |
254 | { | |
255 | unsigned long pc; | |
442ea881 | 256 | collect_register_by_name (regcache, "pc", &pc); |
6fe305f7 UW |
257 | return (CORE_ADDR) pc; |
258 | } | |
0d62e5e8 DJ |
259 | } |
260 | ||
261 | static void | |
442ea881 | 262 | ppc_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 | 263 | { |
abf516c6 | 264 | if (register_size (regcache->tdesc, 0) == 4) |
6fe305f7 UW |
265 | { |
266 | unsigned int newpc = pc; | |
442ea881 | 267 | supply_register_by_name (regcache, "pc", &newpc); |
6fe305f7 UW |
268 | } |
269 | else | |
270 | { | |
271 | unsigned long newpc = pc; | |
442ea881 | 272 | supply_register_by_name (regcache, "pc", &newpc); |
6fe305f7 UW |
273 | } |
274 | } | |
275 | ||
3aee8918 PA |
276 | #ifndef __powerpc64__ |
277 | static int ppc_regmap_adjusted; | |
278 | #endif | |
279 | ||
0d62e5e8 | 280 | |
5b0a002e | 281 | /* Correct in either endianness. |
0d62e5e8 DJ |
282 | This instruction is "twge r2, r2", which GDB uses as a software |
283 | breakpoint. */ | |
5b0a002e | 284 | static const unsigned int ppc_breakpoint = 0x7d821008; |
0d62e5e8 DJ |
285 | #define ppc_breakpoint_len 4 |
286 | ||
dd373349 AT |
287 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
288 | ||
289 | static const gdb_byte * | |
290 | ppc_sw_breakpoint_from_kind (int kind, int *size) | |
291 | { | |
292 | *size = ppc_breakpoint_len; | |
293 | return (const gdb_byte *) &ppc_breakpoint; | |
294 | } | |
295 | ||
0d62e5e8 DJ |
296 | static int |
297 | ppc_breakpoint_at (CORE_ADDR where) | |
298 | { | |
5b0a002e | 299 | unsigned int insn; |
0d62e5e8 | 300 | |
52405d85 | 301 | the_target->read_memory (where, (unsigned char *) &insn, 4); |
abf516c6 UW |
302 | if (insn == ppc_breakpoint) |
303 | return 1; | |
304 | /* If necessary, recognize more trap instructions here. GDB only uses | |
305 | the one. */ | |
0b9ff2c0 | 306 | |
0d62e5e8 DJ |
307 | return 0; |
308 | } | |
309 | ||
657f9cde WW |
310 | /* Implement supports_z_point_type target-ops. |
311 | Returns true if type Z_TYPE breakpoint is supported. | |
312 | ||
313 | Handling software breakpoint at server side, so tracepoints | |
314 | and breakpoints can be inserted at the same location. */ | |
315 | ||
316 | static int | |
317 | ppc_supports_z_point_type (char z_type) | |
318 | { | |
319 | switch (z_type) | |
320 | { | |
321 | case Z_PACKET_SW_BP: | |
322 | return 1; | |
323 | case Z_PACKET_HW_BP: | |
324 | case Z_PACKET_WRITE_WP: | |
325 | case Z_PACKET_ACCESS_WP: | |
326 | default: | |
327 | return 0; | |
328 | } | |
329 | } | |
330 | ||
331 | /* Implement insert_point target-ops. | |
332 | Returns 0 on success, -1 on failure and 1 on unsupported. */ | |
333 | ||
334 | static int | |
335 | ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
336 | int size, struct raw_breakpoint *bp) | |
337 | { | |
338 | switch (type) | |
339 | { | |
340 | case raw_bkpt_type_sw: | |
341 | return insert_memory_breakpoint (bp); | |
342 | ||
343 | case raw_bkpt_type_hw: | |
344 | case raw_bkpt_type_write_wp: | |
345 | case raw_bkpt_type_access_wp: | |
346 | default: | |
347 | /* Unsupported. */ | |
348 | return 1; | |
349 | } | |
350 | } | |
351 | ||
352 | /* Implement remove_point target-ops. | |
353 | Returns 0 on success, -1 on failure and 1 on unsupported. */ | |
354 | ||
355 | static int | |
356 | ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
357 | int size, struct raw_breakpoint *bp) | |
358 | { | |
359 | switch (type) | |
360 | { | |
361 | case raw_bkpt_type_sw: | |
362 | return remove_memory_breakpoint (bp); | |
363 | ||
364 | case raw_bkpt_type_hw: | |
365 | case raw_bkpt_type_write_wp: | |
366 | case raw_bkpt_type_access_wp: | |
367 | default: | |
368 | /* Unsupported. */ | |
369 | return 1; | |
370 | } | |
371 | } | |
372 | ||
e9d25b98 DJ |
373 | /* Provide only a fill function for the general register set. ps_lgetregs |
374 | will use this for NPTL support. */ | |
375 | ||
442ea881 | 376 | static void ppc_fill_gregset (struct regcache *regcache, void *buf) |
e9d25b98 DJ |
377 | { |
378 | int i; | |
379 | ||
380 | for (i = 0; i < 32; i++) | |
442ea881 | 381 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
e9d25b98 DJ |
382 | |
383 | for (i = 64; i < 70; i++) | |
442ea881 | 384 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
7284e1be UW |
385 | |
386 | for (i = 71; i < 73; i++) | |
442ea881 | 387 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
e9d25b98 DJ |
388 | } |
389 | ||
7ca18ed6 EBM |
390 | /* Program Priority Register regset fill function. */ |
391 | ||
392 | static void | |
393 | ppc_fill_pprregset (struct regcache *regcache, void *buf) | |
394 | { | |
395 | char *ppr = (char *) buf; | |
396 | ||
397 | collect_register_by_name (regcache, "ppr", ppr); | |
398 | } | |
399 | ||
400 | /* Program Priority Register regset store function. */ | |
401 | ||
402 | static void | |
403 | ppc_store_pprregset (struct regcache *regcache, const void *buf) | |
404 | { | |
405 | const char *ppr = (const char *) buf; | |
406 | ||
407 | supply_register_by_name (regcache, "ppr", ppr); | |
408 | } | |
409 | ||
410 | /* Data Stream Control Register regset fill function. */ | |
411 | ||
412 | static void | |
413 | ppc_fill_dscrregset (struct regcache *regcache, void *buf) | |
414 | { | |
415 | char *dscr = (char *) buf; | |
416 | ||
417 | collect_register_by_name (regcache, "dscr", dscr); | |
418 | } | |
419 | ||
420 | /* Data Stream Control Register regset store function. */ | |
421 | ||
422 | static void | |
423 | ppc_store_dscrregset (struct regcache *regcache, const void *buf) | |
424 | { | |
425 | const char *dscr = (const char *) buf; | |
426 | ||
427 | supply_register_by_name (regcache, "dscr", dscr); | |
428 | } | |
429 | ||
f2cf6173 EBM |
430 | /* Target Address Register regset fill function. */ |
431 | ||
432 | static void | |
433 | ppc_fill_tarregset (struct regcache *regcache, void *buf) | |
434 | { | |
435 | char *tar = (char *) buf; | |
436 | ||
437 | collect_register_by_name (regcache, "tar", tar); | |
438 | } | |
439 | ||
440 | /* Target Address Register regset store function. */ | |
441 | ||
442 | static void | |
443 | ppc_store_tarregset (struct regcache *regcache, const void *buf) | |
444 | { | |
445 | const char *tar = (const char *) buf; | |
446 | ||
447 | supply_register_by_name (regcache, "tar", tar); | |
448 | } | |
449 | ||
232bfb86 EBM |
450 | /* Event-Based Branching regset store function. Unless the inferior |
451 | has a perf event open, ptrace can return in error when reading and | |
452 | writing to the regset, with ENODATA. For reading, the registers | |
453 | will correctly show as unavailable. For writing, gdbserver | |
454 | currently only caches any register writes from P and G packets and | |
455 | the stub always tries to write all the regsets when resuming the | |
456 | inferior, which would result in frequent warnings. For this | |
457 | reason, we don't define a fill function. This also means that the | |
458 | client-side regcache will be dirty if the user tries to write to | |
459 | the EBB registers. G packets that the client sends to write to | |
460 | unrelated registers will also include data for EBB registers, even | |
461 | if they are unavailable. */ | |
462 | ||
463 | static void | |
464 | ppc_store_ebbregset (struct regcache *regcache, const void *buf) | |
465 | { | |
466 | const char *regset = (const char *) buf; | |
467 | ||
468 | /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the | |
469 | .dat file is BESCR, EBBHR, EBBRR. */ | |
470 | supply_register_by_name (regcache, "ebbrr", ®set[0]); | |
471 | supply_register_by_name (regcache, "ebbhr", ®set[8]); | |
472 | supply_register_by_name (regcache, "bescr", ®set[16]); | |
473 | } | |
474 | ||
475 | /* Performance Monitoring Unit regset fill function. */ | |
476 | ||
477 | static void | |
478 | ppc_fill_pmuregset (struct regcache *regcache, void *buf) | |
479 | { | |
480 | char *regset = (char *) buf; | |
481 | ||
482 | /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0. | |
483 | In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */ | |
484 | collect_register_by_name (regcache, "siar", ®set[0]); | |
485 | collect_register_by_name (regcache, "sdar", ®set[8]); | |
486 | collect_register_by_name (regcache, "sier", ®set[16]); | |
487 | collect_register_by_name (regcache, "mmcr2", ®set[24]); | |
488 | collect_register_by_name (regcache, "mmcr0", ®set[32]); | |
489 | } | |
490 | ||
491 | /* Performance Monitoring Unit regset store function. */ | |
492 | ||
493 | static void | |
494 | ppc_store_pmuregset (struct regcache *regcache, const void *buf) | |
495 | { | |
496 | const char *regset = (const char *) buf; | |
497 | ||
498 | supply_register_by_name (regcache, "siar", ®set[0]); | |
499 | supply_register_by_name (regcache, "sdar", ®set[8]); | |
500 | supply_register_by_name (regcache, "sier", ®set[16]); | |
501 | supply_register_by_name (regcache, "mmcr2", ®set[24]); | |
502 | supply_register_by_name (regcache, "mmcr0", ®set[32]); | |
503 | } | |
504 | ||
8d619c01 EBM |
505 | /* Hardware Transactional Memory special-purpose register regset fill |
506 | function. */ | |
507 | ||
508 | static void | |
509 | ppc_fill_tm_sprregset (struct regcache *regcache, void *buf) | |
510 | { | |
511 | int i, base; | |
512 | char *regset = (char *) buf; | |
513 | ||
514 | base = find_regno (regcache->tdesc, "tfhar"); | |
515 | for (i = 0; i < 3; i++) | |
516 | collect_register (regcache, base + i, ®set[i * 8]); | |
517 | } | |
518 | ||
519 | /* Hardware Transactional Memory special-purpose register regset store | |
520 | function. */ | |
521 | ||
522 | static void | |
523 | ppc_store_tm_sprregset (struct regcache *regcache, const void *buf) | |
524 | { | |
525 | int i, base; | |
526 | const char *regset = (const char *) buf; | |
527 | ||
528 | base = find_regno (regcache->tdesc, "tfhar"); | |
529 | for (i = 0; i < 3; i++) | |
530 | supply_register (regcache, base + i, ®set[i * 8]); | |
531 | } | |
532 | ||
533 | /* For the same reasons as the EBB regset, none of the HTM | |
534 | checkpointed regsets have a fill function. These registers are | |
535 | only available if the inferior is in a transaction. */ | |
536 | ||
537 | /* Hardware Transactional Memory checkpointed general-purpose regset | |
538 | store function. */ | |
539 | ||
540 | static void | |
541 | ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf) | |
542 | { | |
543 | int i, base, size, endian_offset; | |
544 | const char *regset = (const char *) buf; | |
545 | ||
546 | base = find_regno (regcache->tdesc, "cr0"); | |
547 | size = register_size (regcache->tdesc, base); | |
548 | ||
549 | gdb_assert (size == 4 || size == 8); | |
550 | ||
551 | for (i = 0; i < 32; i++) | |
552 | supply_register (regcache, base + i, ®set[i * size]); | |
553 | ||
554 | endian_offset = 0; | |
555 | ||
556 | if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN)) | |
557 | endian_offset = 4; | |
558 | ||
559 | supply_register_by_name (regcache, "ccr", | |
560 | ®set[PT_CCR * size + endian_offset]); | |
561 | ||
562 | supply_register_by_name (regcache, "cxer", | |
563 | ®set[PT_XER * size + endian_offset]); | |
564 | ||
565 | supply_register_by_name (regcache, "clr", ®set[PT_LNK * size]); | |
566 | supply_register_by_name (regcache, "cctr", ®set[PT_CTR * size]); | |
567 | } | |
568 | ||
569 | /* Hardware Transactional Memory checkpointed floating-point regset | |
570 | store function. */ | |
571 | ||
572 | static void | |
573 | ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf) | |
574 | { | |
575 | int i, base; | |
576 | const char *regset = (const char *) buf; | |
577 | ||
578 | base = find_regno (regcache->tdesc, "cf0"); | |
579 | ||
580 | for (i = 0; i < 32; i++) | |
581 | supply_register (regcache, base + i, ®set[i * 8]); | |
582 | ||
583 | supply_register_by_name (regcache, "cfpscr", ®set[32 * 8]); | |
584 | } | |
585 | ||
586 | /* Hardware Transactional Memory checkpointed vector regset store | |
587 | function. */ | |
588 | ||
589 | static void | |
590 | ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf) | |
591 | { | |
592 | int i, base; | |
593 | const char *regset = (const char *) buf; | |
594 | int vscr_offset = 0; | |
595 | ||
596 | base = find_regno (regcache->tdesc, "cvr0"); | |
597 | ||
598 | for (i = 0; i < 32; i++) | |
599 | supply_register (regcache, base + i, ®set[i * 16]); | |
600 | ||
601 | if (__BYTE_ORDER == __BIG_ENDIAN) | |
602 | vscr_offset = 12; | |
603 | ||
604 | supply_register_by_name (regcache, "cvscr", | |
605 | ®set[32 * 16 + vscr_offset]); | |
606 | ||
607 | supply_register_by_name (regcache, "cvrsave", ®set[33 * 16]); | |
608 | } | |
609 | ||
610 | /* Hardware Transactional Memory checkpointed vector-scalar regset | |
611 | store function. */ | |
612 | ||
613 | static void | |
614 | ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf) | |
615 | { | |
616 | int i, base; | |
617 | const char *regset = (const char *) buf; | |
618 | ||
619 | base = find_regno (regcache->tdesc, "cvs0h"); | |
620 | for (i = 0; i < 32; i++) | |
621 | supply_register (regcache, base + i, ®set[i * 8]); | |
622 | } | |
623 | ||
624 | /* Hardware Transactional Memory checkpointed Program Priority | |
625 | Register regset store function. */ | |
626 | ||
627 | static void | |
628 | ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf) | |
629 | { | |
630 | const char *cppr = (const char *) buf; | |
631 | ||
632 | supply_register_by_name (regcache, "cppr", cppr); | |
633 | } | |
634 | ||
635 | /* Hardware Transactional Memory checkpointed Data Stream Control | |
636 | Register regset store function. */ | |
637 | ||
638 | static void | |
639 | ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf) | |
640 | { | |
641 | const char *cdscr = (const char *) buf; | |
642 | ||
643 | supply_register_by_name (regcache, "cdscr", cdscr); | |
644 | } | |
645 | ||
646 | /* Hardware Transactional Memory checkpointed Target Address Register | |
647 | regset store function. */ | |
648 | ||
649 | static void | |
650 | ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf) | |
651 | { | |
652 | const char *ctar = (const char *) buf; | |
653 | ||
654 | supply_register_by_name (regcache, "ctar", ctar); | |
655 | } | |
656 | ||
677c5bb1 | 657 | static void |
442ea881 | 658 | ppc_fill_vsxregset (struct regcache *regcache, void *buf) |
677c5bb1 LM |
659 | { |
660 | int i, base; | |
2bc84e8a | 661 | char *regset = (char *) buf; |
677c5bb1 | 662 | |
3aee8918 | 663 | base = find_regno (regcache->tdesc, "vs0h"); |
677c5bb1 | 664 | for (i = 0; i < 32; i++) |
442ea881 | 665 | collect_register (regcache, base + i, ®set[i * 8]); |
677c5bb1 LM |
666 | } |
667 | ||
668 | static void | |
442ea881 | 669 | ppc_store_vsxregset (struct regcache *regcache, const void *buf) |
677c5bb1 LM |
670 | { |
671 | int i, base; | |
2bc84e8a | 672 | const char *regset = (const char *) buf; |
677c5bb1 | 673 | |
3aee8918 | 674 | base = find_regno (regcache->tdesc, "vs0h"); |
677c5bb1 | 675 | for (i = 0; i < 32; i++) |
442ea881 | 676 | supply_register (regcache, base + i, ®set[i * 8]); |
677c5bb1 LM |
677 | } |
678 | ||
30ed0a8f | 679 | static void |
442ea881 | 680 | ppc_fill_vrregset (struct regcache *regcache, void *buf) |
30ed0a8f DJ |
681 | { |
682 | int i, base; | |
2bc84e8a | 683 | char *regset = (char *) buf; |
1d75a658 | 684 | int vscr_offset = 0; |
30ed0a8f | 685 | |
3aee8918 | 686 | base = find_regno (regcache->tdesc, "vr0"); |
30ed0a8f | 687 | for (i = 0; i < 32; i++) |
442ea881 | 688 | collect_register (regcache, base + i, ®set[i * 16]); |
30ed0a8f | 689 | |
1d75a658 PFC |
690 | if (__BYTE_ORDER == __BIG_ENDIAN) |
691 | vscr_offset = 12; | |
692 | ||
1d75a658 PFC |
693 | collect_register_by_name (regcache, "vscr", |
694 | ®set[32 * 16 + vscr_offset]); | |
695 | ||
442ea881 | 696 | collect_register_by_name (regcache, "vrsave", ®set[33 * 16]); |
30ed0a8f DJ |
697 | } |
698 | ||
699 | static void | |
442ea881 | 700 | ppc_store_vrregset (struct regcache *regcache, const void *buf) |
30ed0a8f DJ |
701 | { |
702 | int i, base; | |
2bc84e8a | 703 | const char *regset = (const char *) buf; |
1d75a658 | 704 | int vscr_offset = 0; |
30ed0a8f | 705 | |
3aee8918 | 706 | base = find_regno (regcache->tdesc, "vr0"); |
30ed0a8f | 707 | for (i = 0; i < 32; i++) |
442ea881 | 708 | supply_register (regcache, base + i, ®set[i * 16]); |
30ed0a8f | 709 | |
1d75a658 PFC |
710 | if (__BYTE_ORDER == __BIG_ENDIAN) |
711 | vscr_offset = 12; | |
712 | ||
713 | supply_register_by_name (regcache, "vscr", | |
714 | ®set[32 * 16 + vscr_offset]); | |
442ea881 | 715 | supply_register_by_name (regcache, "vrsave", ®set[33 * 16]); |
30ed0a8f DJ |
716 | } |
717 | ||
30ed0a8f DJ |
718 | struct gdb_evrregset_t |
719 | { | |
720 | unsigned long evr[32]; | |
721 | unsigned long long acc; | |
722 | unsigned long spefscr; | |
723 | }; | |
724 | ||
725 | static void | |
442ea881 | 726 | ppc_fill_evrregset (struct regcache *regcache, void *buf) |
30ed0a8f DJ |
727 | { |
728 | int i, ev0; | |
2bc84e8a | 729 | struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf; |
30ed0a8f | 730 | |
3aee8918 | 731 | ev0 = find_regno (regcache->tdesc, "ev0h"); |
30ed0a8f | 732 | for (i = 0; i < 32; i++) |
442ea881 | 733 | collect_register (regcache, ev0 + i, ®set->evr[i]); |
30ed0a8f | 734 | |
442ea881 PA |
735 | collect_register_by_name (regcache, "acc", ®set->acc); |
736 | collect_register_by_name (regcache, "spefscr", ®set->spefscr); | |
30ed0a8f DJ |
737 | } |
738 | ||
739 | static void | |
442ea881 | 740 | ppc_store_evrregset (struct regcache *regcache, const void *buf) |
30ed0a8f DJ |
741 | { |
742 | int i, ev0; | |
2bc84e8a | 743 | const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf; |
30ed0a8f | 744 | |
3aee8918 | 745 | ev0 = find_regno (regcache->tdesc, "ev0h"); |
30ed0a8f | 746 | for (i = 0; i < 32; i++) |
442ea881 | 747 | supply_register (regcache, ev0 + i, ®set->evr[i]); |
30ed0a8f | 748 | |
442ea881 PA |
749 | supply_register_by_name (regcache, "acc", ®set->acc); |
750 | supply_register_by_name (regcache, "spefscr", ®set->spefscr); | |
30ed0a8f | 751 | } |
30ed0a8f | 752 | |
7d00775e AT |
753 | /* Support for hardware single step. */ |
754 | ||
755 | static int | |
756 | ppc_supports_hardware_single_step (void) | |
757 | { | |
758 | return 1; | |
759 | } | |
760 | ||
3aee8918 | 761 | static struct regset_info ppc_regsets[] = { |
30ed0a8f DJ |
762 | /* List the extra register sets before GENERAL_REGS. That way we will |
763 | fetch them every time, but still fall back to PTRACE_PEEKUSER for the | |
764 | general registers. Some kernels support these, but not the newer | |
765 | PPC_PTRACE_GETREGS. */ | |
8d619c01 EBM |
766 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS, |
767 | NULL, ppc_store_tm_ctarregset }, | |
768 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS, | |
769 | NULL, ppc_store_tm_cdscrregset }, | |
770 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS, | |
771 | NULL, ppc_store_tm_cpprregset }, | |
772 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS, | |
773 | NULL, ppc_store_tm_cvsxregset }, | |
774 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS, | |
775 | NULL, ppc_store_tm_cvrregset }, | |
776 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS, | |
777 | NULL, ppc_store_tm_cfprregset }, | |
778 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS, | |
779 | NULL, ppc_store_tm_cgprregset }, | |
780 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS, | |
781 | ppc_fill_tm_sprregset, ppc_store_tm_sprregset }, | |
232bfb86 EBM |
782 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS, |
783 | NULL, ppc_store_ebbregset }, | |
784 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS, | |
785 | ppc_fill_pmuregset, ppc_store_pmuregset }, | |
f2cf6173 EBM |
786 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS, |
787 | ppc_fill_tarregset, ppc_store_tarregset }, | |
7ca18ed6 EBM |
788 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS, |
789 | ppc_fill_pprregset, ppc_store_pprregset }, | |
790 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS, | |
791 | ppc_fill_dscrregset, ppc_store_dscrregset }, | |
7273b5fc | 792 | { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS, |
677c5bb1 | 793 | ppc_fill_vsxregset, ppc_store_vsxregset }, |
7273b5fc | 794 | { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS, |
30ed0a8f | 795 | ppc_fill_vrregset, ppc_store_vrregset }, |
7273b5fc | 796 | { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS, |
30ed0a8f | 797 | ppc_fill_evrregset, ppc_store_evrregset }, |
1570b33e | 798 | { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL }, |
50bc912a | 799 | NULL_REGSET |
e9d25b98 DJ |
800 | }; |
801 | ||
3aee8918 PA |
802 | static struct usrregs_info ppc_usrregs_info = |
803 | { | |
804 | ppc_num_regs, | |
805 | ppc_regmap, | |
806 | }; | |
807 | ||
808 | static struct regsets_info ppc_regsets_info = | |
809 | { | |
810 | ppc_regsets, /* regsets */ | |
811 | 0, /* num_regsets */ | |
812 | NULL, /* disabled_regsets */ | |
813 | }; | |
814 | ||
aa8d21c9 | 815 | static struct regs_info myregs_info = |
3aee8918 PA |
816 | { |
817 | NULL, /* regset_bitmap */ | |
818 | &ppc_usrregs_info, | |
819 | &ppc_regsets_info | |
820 | }; | |
821 | ||
aa8d21c9 TBA |
822 | const regs_info * |
823 | ppc_target::get_regs_info () | |
3aee8918 | 824 | { |
aa8d21c9 | 825 | return &myregs_info; |
3aee8918 PA |
826 | } |
827 | ||
797bcff5 TBA |
828 | void |
829 | ppc_target::low_arch_setup () | |
e6c5bb05 SM |
830 | { |
831 | const struct target_desc *tdesc; | |
7273b5fc | 832 | struct regset_info *regset; |
bd64614e | 833 | struct ppc_linux_features features = ppc_linux_no_features; |
7273b5fc | 834 | |
2e077f5e | 835 | int tid = lwpid_of (current_thread); |
bd64614e | 836 | |
2e077f5e | 837 | features.wordsize = ppc_linux_target_wordsize (tid); |
e6c5bb05 | 838 | |
bd64614e | 839 | if (features.wordsize == 4) |
bd64614e | 840 | tdesc = tdesc_powerpc_32l; |
2e077f5e PFC |
841 | else |
842 | tdesc = tdesc_powerpc_64l; | |
843 | ||
844 | current_process ()->tdesc = tdesc; | |
e6c5bb05 | 845 | |
bd64614e PFC |
846 | /* The value of current_process ()->tdesc needs to be set for this |
847 | call. */ | |
974c89e0 AH |
848 | ppc_hwcap = linux_get_hwcap (features.wordsize); |
849 | ppc_hwcap2 = linux_get_hwcap2 (features.wordsize); | |
bd64614e PFC |
850 | |
851 | features.isa205 = ppc_linux_has_isa205 (ppc_hwcap); | |
852 | ||
853 | if (ppc_hwcap & PPC_FEATURE_HAS_VSX) | |
854 | features.vsx = true; | |
855 | ||
856 | if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC) | |
857 | features.altivec = true; | |
858 | ||
7ca18ed6 EBM |
859 | if ((ppc_hwcap2 & PPC_FEATURE2_DSCR) |
860 | && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET) | |
861 | && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET)) | |
f2cf6173 EBM |
862 | { |
863 | features.ppr_dscr = true; | |
864 | if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07) | |
865 | && (ppc_hwcap2 & PPC_FEATURE2_TAR) | |
232bfb86 | 866 | && (ppc_hwcap2 & PPC_FEATURE2_EBB) |
f2cf6173 | 867 | && ppc_check_regset (tid, NT_PPC_TAR, |
232bfb86 EBM |
868 | PPC_LINUX_SIZEOF_TARREGSET) |
869 | && ppc_check_regset (tid, NT_PPC_EBB, | |
870 | PPC_LINUX_SIZEOF_EBBREGSET) | |
871 | && ppc_check_regset (tid, NT_PPC_PMU, | |
872 | PPC_LINUX_SIZEOF_PMUREGSET)) | |
8d619c01 EBM |
873 | { |
874 | features.isa207 = true; | |
875 | if ((ppc_hwcap2 & PPC_FEATURE2_HTM) | |
876 | && ppc_check_regset (tid, NT_PPC_TM_SPR, | |
877 | PPC_LINUX_SIZEOF_TM_SPRREGSET)) | |
878 | features.htm = true; | |
879 | } | |
f2cf6173 | 880 | } |
7ca18ed6 | 881 | |
bd64614e | 882 | tdesc = ppc_linux_match_description (features); |
e6c5bb05 SM |
883 | |
884 | /* On 32-bit machines, check for SPE registers. | |
885 | Set the low target's regmap field as appropriately. */ | |
886 | #ifndef __powerpc64__ | |
887 | if (ppc_hwcap & PPC_FEATURE_HAS_SPE) | |
888 | tdesc = tdesc_powerpc_e500l; | |
889 | ||
890 | if (!ppc_regmap_adjusted) | |
891 | { | |
892 | if (ppc_hwcap & PPC_FEATURE_HAS_SPE) | |
893 | ppc_usrregs_info.regmap = ppc_regmap_e500; | |
894 | ||
895 | /* If the FPSCR is 64-bit wide, we need to fetch the whole | |
896 | 64-bit slot and not just its second word. The PT_FPSCR | |
897 | supplied in a 32-bit GDB compilation doesn't reflect | |
898 | this. */ | |
899 | if (register_size (tdesc, 70) == 8) | |
900 | ppc_regmap[70] = (48 + 2*32) * sizeof (long); | |
901 | ||
902 | ppc_regmap_adjusted = 1; | |
903 | } | |
904 | #endif | |
bd64614e | 905 | |
e6c5bb05 | 906 | current_process ()->tdesc = tdesc; |
7273b5fc PFC |
907 | |
908 | for (regset = ppc_regsets; regset->size >= 0; regset++) | |
909 | switch (regset->get_request) | |
910 | { | |
911 | case PTRACE_GETVRREGS: | |
d078308a | 912 | regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0; |
7273b5fc PFC |
913 | break; |
914 | case PTRACE_GETVSXREGS: | |
d078308a | 915 | regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0; |
7273b5fc PFC |
916 | break; |
917 | case PTRACE_GETEVRREGS: | |
918 | if (ppc_hwcap & PPC_FEATURE_HAS_SPE) | |
919 | regset->size = 32 * 4 + 8 + 4; | |
920 | else | |
921 | regset->size = 0; | |
922 | break; | |
7ca18ed6 EBM |
923 | case PTRACE_GETREGSET: |
924 | switch (regset->nt_type) | |
925 | { | |
926 | case NT_PPC_PPR: | |
927 | regset->size = (features.ppr_dscr ? | |
928 | PPC_LINUX_SIZEOF_PPRREGSET : 0); | |
929 | break; | |
930 | case NT_PPC_DSCR: | |
931 | regset->size = (features.ppr_dscr ? | |
932 | PPC_LINUX_SIZEOF_DSCRREGSET : 0); | |
933 | break; | |
f2cf6173 EBM |
934 | case NT_PPC_TAR: |
935 | regset->size = (features.isa207 ? | |
936 | PPC_LINUX_SIZEOF_TARREGSET : 0); | |
937 | break; | |
232bfb86 EBM |
938 | case NT_PPC_EBB: |
939 | regset->size = (features.isa207 ? | |
940 | PPC_LINUX_SIZEOF_EBBREGSET : 0); | |
941 | break; | |
942 | case NT_PPC_PMU: | |
943 | regset->size = (features.isa207 ? | |
944 | PPC_LINUX_SIZEOF_PMUREGSET : 0); | |
945 | break; | |
8d619c01 EBM |
946 | case NT_PPC_TM_SPR: |
947 | regset->size = (features.htm ? | |
948 | PPC_LINUX_SIZEOF_TM_SPRREGSET : 0); | |
949 | break; | |
950 | case NT_PPC_TM_CGPR: | |
951 | if (features.wordsize == 4) | |
952 | regset->size = (features.htm ? | |
953 | PPC32_LINUX_SIZEOF_CGPRREGSET : 0); | |
954 | else | |
955 | regset->size = (features.htm ? | |
956 | PPC64_LINUX_SIZEOF_CGPRREGSET : 0); | |
957 | break; | |
958 | case NT_PPC_TM_CFPR: | |
959 | regset->size = (features.htm ? | |
960 | PPC_LINUX_SIZEOF_CFPRREGSET : 0); | |
961 | break; | |
962 | case NT_PPC_TM_CVMX: | |
963 | regset->size = (features.htm ? | |
964 | PPC_LINUX_SIZEOF_CVMXREGSET : 0); | |
965 | break; | |
966 | case NT_PPC_TM_CVSX: | |
967 | regset->size = (features.htm ? | |
968 | PPC_LINUX_SIZEOF_CVSXREGSET : 0); | |
969 | break; | |
970 | case NT_PPC_TM_CPPR: | |
971 | regset->size = (features.htm ? | |
972 | PPC_LINUX_SIZEOF_CPPRREGSET : 0); | |
973 | break; | |
974 | case NT_PPC_TM_CDSCR: | |
975 | regset->size = (features.htm ? | |
976 | PPC_LINUX_SIZEOF_CDSCRREGSET : 0); | |
977 | break; | |
978 | case NT_PPC_TM_CTAR: | |
979 | regset->size = (features.htm ? | |
980 | PPC_LINUX_SIZEOF_CTARREGSET : 0); | |
981 | break; | |
7ca18ed6 EBM |
982 | default: |
983 | break; | |
984 | } | |
985 | break; | |
7273b5fc PFC |
986 | default: |
987 | break; | |
988 | } | |
e6c5bb05 SM |
989 | } |
990 | ||
a2174ba4 MK |
991 | /* Implementation of linux_target_ops method "supports_tracepoints". */ |
992 | ||
b04fd3be MK |
993 | static int |
994 | ppc_supports_tracepoints (void) | |
995 | { | |
996 | return 1; | |
997 | } | |
998 | ||
a2174ba4 MK |
999 | /* Get the thread area address. This is used to recognize which |
1000 | thread is which when tracing with the in-process agent library. We | |
1001 | don't read anything from the address, and treat it as opaque; it's | |
1002 | the address itself that we assume is unique per-thread. */ | |
1003 | ||
1004 | static int | |
1005 | ppc_get_thread_area (int lwpid, CORE_ADDR *addr) | |
1006 | { | |
f2907e49 | 1007 | struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid)); |
a2174ba4 MK |
1008 | struct thread_info *thr = get_lwp_thread (lwp); |
1009 | struct regcache *regcache = get_thread_regcache (thr, 1); | |
1010 | ULONGEST tp = 0; | |
1011 | ||
1012 | #ifdef __powerpc64__ | |
1013 | if (register_size (regcache->tdesc, 0) == 8) | |
1014 | collect_register_by_name (regcache, "r13", &tp); | |
1015 | else | |
1016 | #endif | |
1017 | collect_register_by_name (regcache, "r2", &tp); | |
1018 | ||
1019 | *addr = tp; | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | #ifdef __powerpc64__ | |
1025 | ||
1026 | /* Older glibc doesn't provide this. */ | |
1027 | ||
1028 | #ifndef EF_PPC64_ABI | |
1029 | #define EF_PPC64_ABI 3 | |
1030 | #endif | |
1031 | ||
1032 | /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit | |
1033 | inferiors. */ | |
1034 | ||
1035 | static int | |
1036 | is_elfv2_inferior (void) | |
1037 | { | |
1038 | /* To be used as fallback if we're unable to determine the right result - | |
1039 | assume inferior uses the same ABI as gdbserver. */ | |
1040 | #if _CALL_ELF == 2 | |
1041 | const int def_res = 1; | |
1042 | #else | |
1043 | const int def_res = 0; | |
1044 | #endif | |
0570503d | 1045 | CORE_ADDR phdr; |
a2174ba4 MK |
1046 | Elf64_Ehdr ehdr; |
1047 | ||
0570503d PFC |
1048 | const struct target_desc *tdesc = current_process ()->tdesc; |
1049 | int wordsize = register_size (tdesc, 0); | |
1050 | ||
1051 | if (!linux_get_auxv (wordsize, AT_PHDR, &phdr)) | |
a2174ba4 MK |
1052 | return def_res; |
1053 | ||
1054 | /* Assume ELF header is at the beginning of the page where program headers | |
1055 | are located. If it doesn't look like one, bail. */ | |
1056 | ||
1057 | read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr); | |
1058 | if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG)) | |
1059 | return def_res; | |
1060 | ||
1061 | return (ehdr.e_flags & EF_PPC64_ABI) == 2; | |
1062 | } | |
1063 | ||
1064 | #endif | |
1065 | ||
1066 | /* Generate a ds-form instruction in BUF and return the number of bytes written | |
1067 | ||
1068 | 0 6 11 16 30 32 | |
1069 | | OPCD | RST | RA | DS |XO| */ | |
1070 | ||
1071 | __attribute__((unused)) /* Maybe unused due to conditional compilation. */ | |
1072 | static int | |
1073 | gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo) | |
1074 | { | |
1075 | uint32_t insn; | |
1076 | ||
1077 | gdb_assert ((opcd & ~0x3f) == 0); | |
1078 | gdb_assert ((rst & ~0x1f) == 0); | |
1079 | gdb_assert ((ra & ~0x1f) == 0); | |
1080 | gdb_assert ((xo & ~0x3) == 0); | |
1081 | ||
1082 | insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3); | |
1083 | *buf = (opcd << 26) | insn; | |
1084 | return 1; | |
1085 | } | |
1086 | ||
1087 | /* Followings are frequently used ds-form instructions. */ | |
1088 | ||
1089 | #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0) | |
1090 | #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1) | |
1091 | #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0) | |
1092 | #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1) | |
1093 | ||
1094 | /* Generate a d-form instruction in BUF. | |
1095 | ||
1096 | 0 6 11 16 32 | |
1097 | | OPCD | RST | RA | D | */ | |
1098 | ||
1099 | static int | |
1100 | gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si) | |
1101 | { | |
1102 | uint32_t insn; | |
1103 | ||
1104 | gdb_assert ((opcd & ~0x3f) == 0); | |
1105 | gdb_assert ((rst & ~0x1f) == 0); | |
1106 | gdb_assert ((ra & ~0x1f) == 0); | |
1107 | ||
1108 | insn = (rst << 21) | (ra << 16) | (si & 0xffff); | |
1109 | *buf = (opcd << 26) | insn; | |
1110 | return 1; | |
1111 | } | |
1112 | ||
1113 | /* Followings are frequently used d-form instructions. */ | |
1114 | ||
1115 | #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si) | |
1116 | #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si) | |
1117 | #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si) | |
1118 | #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si) | |
1119 | #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si) | |
1120 | #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si) | |
1121 | #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si) | |
1122 | #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si) | |
1123 | #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si) | |
1124 | ||
1125 | /* Generate a xfx-form instruction in BUF and return the number of bytes | |
1126 | written. | |
1127 | ||
1128 | 0 6 11 21 31 32 | |
1129 | | OPCD | RST | RI | XO |/| */ | |
1130 | ||
1131 | static int | |
1132 | gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo) | |
1133 | { | |
1134 | uint32_t insn; | |
1135 | unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f); | |
1136 | ||
1137 | gdb_assert ((opcd & ~0x3f) == 0); | |
1138 | gdb_assert ((rst & ~0x1f) == 0); | |
1139 | gdb_assert ((xo & ~0x3ff) == 0); | |
1140 | ||
1141 | insn = (rst << 21) | (n << 11) | (xo << 1); | |
1142 | *buf = (opcd << 26) | insn; | |
1143 | return 1; | |
1144 | } | |
1145 | ||
1146 | /* Followings are frequently used xfx-form instructions. */ | |
1147 | ||
1148 | #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339) | |
1149 | #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467) | |
1150 | #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19) | |
1151 | #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144) | |
1152 | #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \ | |
1153 | E & 0xf, 598) | |
1154 | #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0) | |
1155 | ||
1156 | ||
1157 | /* Generate a x-form instruction in BUF and return the number of bytes written. | |
1158 | ||
1159 | 0 6 11 16 21 31 32 | |
1160 | | OPCD | RST | RA | RB | XO |RC| */ | |
1161 | ||
1162 | static int | |
1163 | gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc) | |
1164 | { | |
1165 | uint32_t insn; | |
1166 | ||
1167 | gdb_assert ((opcd & ~0x3f) == 0); | |
1168 | gdb_assert ((rst & ~0x1f) == 0); | |
1169 | gdb_assert ((ra & ~0x1f) == 0); | |
1170 | gdb_assert ((rb & ~0x1f) == 0); | |
1171 | gdb_assert ((xo & ~0x3ff) == 0); | |
1172 | gdb_assert ((rc & ~1) == 0); | |
1173 | ||
1174 | insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc; | |
1175 | *buf = (opcd << 26) | insn; | |
1176 | return 1; | |
1177 | } | |
1178 | ||
1179 | /* Followings are frequently used x-form instructions. */ | |
1180 | ||
1181 | #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0) | |
1182 | #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs) | |
1183 | #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0) | |
1184 | #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1) | |
1185 | /* Assume bf = cr7. */ | |
1186 | #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0) | |
1187 | ||
1188 | ||
1189 | /* Generate a md-form instruction in BUF and return the number of bytes written. | |
1190 | ||
1191 | 0 6 11 16 21 27 30 31 32 | |
1192 | | OPCD | RS | RA | sh | mb | XO |sh|Rc| */ | |
1193 | ||
1194 | static int | |
1195 | gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb, | |
1196 | int xo, int rc) | |
1197 | { | |
1198 | uint32_t insn; | |
1199 | unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1); | |
1200 | unsigned int sh0_4 = sh & 0x1f; | |
1201 | unsigned int sh5 = (sh >> 5) & 1; | |
1202 | ||
1203 | gdb_assert ((opcd & ~0x3f) == 0); | |
1204 | gdb_assert ((rs & ~0x1f) == 0); | |
1205 | gdb_assert ((ra & ~0x1f) == 0); | |
1206 | gdb_assert ((sh & ~0x3f) == 0); | |
1207 | gdb_assert ((mb & ~0x3f) == 0); | |
1208 | gdb_assert ((xo & ~0x7) == 0); | |
1209 | gdb_assert ((rc & ~0x1) == 0); | |
1210 | ||
1211 | insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5) | |
1212 | | (sh5 << 1) | (xo << 2) | (rc & 1); | |
1213 | *buf = (opcd << 26) | insn; | |
1214 | return 1; | |
1215 | } | |
1216 | ||
1217 | /* The following are frequently used md-form instructions. */ | |
1218 | ||
1219 | #define GEN_RLDICL(buf, ra, rs ,sh, mb) \ | |
1220 | gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0) | |
1221 | #define GEN_RLDICR(buf, ra, rs ,sh, mb) \ | |
1222 | gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0) | |
1223 | ||
1224 | /* Generate a i-form instruction in BUF and return the number of bytes written. | |
1225 | ||
1226 | 0 6 30 31 32 | |
1227 | | OPCD | LI |AA|LK| */ | |
1228 | ||
1229 | static int | |
1230 | gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk) | |
1231 | { | |
1232 | uint32_t insn; | |
1233 | ||
1234 | gdb_assert ((opcd & ~0x3f) == 0); | |
1235 | ||
1236 | insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1); | |
1237 | *buf = (opcd << 26) | insn; | |
1238 | return 1; | |
1239 | } | |
1240 | ||
1241 | /* The following are frequently used i-form instructions. */ | |
1242 | ||
1243 | #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0) | |
1244 | #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1) | |
1245 | ||
1246 | /* Generate a b-form instruction in BUF and return the number of bytes written. | |
1247 | ||
1248 | 0 6 11 16 30 31 32 | |
1249 | | OPCD | BO | BI | BD |AA|LK| */ | |
1250 | ||
1251 | static int | |
1252 | gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd, | |
1253 | int aa, int lk) | |
1254 | { | |
1255 | uint32_t insn; | |
1256 | ||
1257 | gdb_assert ((opcd & ~0x3f) == 0); | |
1258 | gdb_assert ((bo & ~0x1f) == 0); | |
1259 | gdb_assert ((bi & ~0x1f) == 0); | |
1260 | ||
1261 | insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1); | |
1262 | *buf = (opcd << 26) | insn; | |
1263 | return 1; | |
1264 | } | |
1265 | ||
1266 | /* The following are frequently used b-form instructions. */ | |
1267 | /* Assume bi = cr7. */ | |
1268 | #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0) | |
1269 | ||
1270 | /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32 | |
1271 | respectively. They are primary used for save/restore GPRs in jump-pad, | |
1272 | not used for bytecode compiling. */ | |
1273 | ||
1274 | #ifdef __powerpc64__ | |
1275 | #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \ | |
1276 | GEN_LD (buf, rt, ra, si) : \ | |
1277 | GEN_LWZ (buf, rt, ra, si)) | |
1278 | #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \ | |
1279 | GEN_STD (buf, rt, ra, si) : \ | |
1280 | GEN_STW (buf, rt, ra, si)) | |
1281 | #else | |
1282 | #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si) | |
1283 | #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si) | |
1284 | #endif | |
1285 | ||
1286 | /* Generate a sequence of instructions to load IMM in the register REG. | |
1287 | Write the instructions in BUF and return the number of bytes written. */ | |
1288 | ||
1289 | static int | |
1290 | gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64) | |
1291 | { | |
1292 | uint32_t *p = buf; | |
1293 | ||
1294 | if ((imm + 32768) < 65536) | |
1295 | { | |
1296 | /* li reg, imm[15:0] */ | |
1297 | p += GEN_LI (p, reg, imm); | |
1298 | } | |
1299 | else if ((imm >> 32) == 0) | |
1300 | { | |
1301 | /* lis reg, imm[31:16] | |
1302 | ori reg, reg, imm[15:0] | |
1303 | rldicl reg, reg, 0, 32 */ | |
1304 | p += GEN_LIS (p, reg, (imm >> 16) & 0xffff); | |
1305 | if ((imm & 0xffff) != 0) | |
1306 | p += GEN_ORI (p, reg, reg, imm & 0xffff); | |
1307 | /* Clear upper 32-bit if sign-bit is set. */ | |
1308 | if (imm & (1u << 31) && is_64) | |
1309 | p += GEN_RLDICL (p, reg, reg, 0, 32); | |
1310 | } | |
1311 | else | |
1312 | { | |
1313 | gdb_assert (is_64); | |
1314 | /* lis reg, <imm[63:48]> | |
1315 | ori reg, reg, <imm[48:32]> | |
1316 | rldicr reg, reg, 32, 31 | |
1317 | oris reg, reg, <imm[31:16]> | |
1318 | ori reg, reg, <imm[15:0]> */ | |
1319 | p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff)); | |
1320 | if (((imm >> 32) & 0xffff) != 0) | |
1321 | p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff)); | |
1322 | p += GEN_RLDICR (p, reg, reg, 32, 31); | |
1323 | if (((imm >> 16) & 0xffff) != 0) | |
1324 | p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff)); | |
1325 | if ((imm & 0xffff) != 0) | |
1326 | p += GEN_ORI (p, reg, reg, (imm & 0xffff)); | |
1327 | } | |
1328 | ||
1329 | return p - buf; | |
1330 | } | |
1331 | ||
1332 | /* Generate a sequence for atomically exchange at location LOCK. | |
1333 | This code sequence clobbers r6, r7, r8. LOCK is the location for | |
1334 | the atomic-xchg, OLD_VALUE is expected old value stored in the | |
1335 | location, and R_NEW is a register for the new value. */ | |
1336 | ||
1337 | static int | |
1338 | gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new, | |
1339 | int is_64) | |
1340 | { | |
1341 | const int r_lock = 6; | |
1342 | const int r_old = 7; | |
1343 | const int r_tmp = 8; | |
1344 | uint32_t *p = buf; | |
1345 | ||
1346 | /* | |
1347 | 1: lwarx TMP, 0, LOCK | |
1348 | cmpwi TMP, OLD | |
1349 | bne 1b | |
1350 | stwcx. NEW, 0, LOCK | |
1351 | bne 1b */ | |
1352 | ||
1353 | p += gen_limm (p, r_lock, lock, is_64); | |
1354 | p += gen_limm (p, r_old, old_value, is_64); | |
1355 | ||
1356 | p += GEN_LWARX (p, r_tmp, 0, r_lock); | |
1357 | p += GEN_CMPW (p, r_tmp, r_old); | |
1358 | p += GEN_BNE (p, -8); | |
1359 | p += GEN_STWCX (p, r_new, 0, r_lock); | |
1360 | p += GEN_BNE (p, -16); | |
1361 | ||
1362 | return p - buf; | |
1363 | } | |
1364 | ||
1365 | /* Generate a sequence of instructions for calling a function | |
1366 | at address of FN. Return the number of bytes are written in BUF. */ | |
1367 | ||
1368 | static int | |
1369 | gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd) | |
1370 | { | |
1371 | uint32_t *p = buf; | |
1372 | ||
1373 | /* Must be called by r12 for caller to calculate TOC address. */ | |
1374 | p += gen_limm (p, 12, fn, is_64); | |
1375 | if (is_opd) | |
1376 | { | |
1377 | p += GEN_LOAD (p, 11, 12, 16, is_64); | |
1378 | p += GEN_LOAD (p, 2, 12, 8, is_64); | |
1379 | p += GEN_LOAD (p, 12, 12, 0, is_64); | |
1380 | } | |
1381 | p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */ | |
1382 | *p++ = 0x4e800421; /* bctrl */ | |
1383 | ||
1384 | return p - buf; | |
1385 | } | |
1386 | ||
1387 | /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size | |
1388 | of instruction. This function is used to adjust pc-relative instructions | |
1389 | when copying. */ | |
1390 | ||
1391 | static void | |
1392 | ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc) | |
1393 | { | |
1394 | uint32_t insn, op6; | |
1395 | long rel, newrel; | |
1396 | ||
1397 | read_inferior_memory (oldloc, (unsigned char *) &insn, 4); | |
1398 | op6 = PPC_OP6 (insn); | |
1399 | ||
1400 | if (op6 == 18 && (insn & 2) == 0) | |
1401 | { | |
1402 | /* branch && AA = 0 */ | |
1403 | rel = PPC_LI (insn); | |
1404 | newrel = (oldloc - *to) + rel; | |
1405 | ||
1406 | /* Out of range. Cannot relocate instruction. */ | |
1407 | if (newrel >= (1 << 25) || newrel < -(1 << 25)) | |
1408 | return; | |
1409 | ||
1410 | insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc); | |
1411 | } | |
1412 | else if (op6 == 16 && (insn & 2) == 0) | |
1413 | { | |
1414 | /* conditional branch && AA = 0 */ | |
1415 | ||
1416 | /* If the new relocation is too big for even a 26-bit unconditional | |
1417 | branch, there is nothing we can do. Just abort. | |
1418 | ||
1419 | Otherwise, if it can be fit in 16-bit conditional branch, just | |
1420 | copy the instruction and relocate the address. | |
1421 | ||
1422 | If the it's big for conditional-branch (16-bit), try to invert the | |
1423 | condition and jump with 26-bit branch. For example, | |
1424 | ||
1425 | beq .Lgoto | |
1426 | INSN1 | |
1427 | ||
1428 | => | |
1429 | ||
1430 | bne 1f (+8) | |
1431 | b .Lgoto | |
1432 | 1:INSN1 | |
1433 | ||
1434 | After this transform, we are actually jump from *TO+4 instead of *TO, | |
1435 | so check the relocation again because it will be 1-insn farther then | |
1436 | before if *TO is after OLDLOC. | |
1437 | ||
1438 | ||
1439 | For BDNZT (or so) is transformed from | |
1440 | ||
1441 | bdnzt eq, .Lgoto | |
1442 | INSN1 | |
1443 | ||
1444 | => | |
1445 | ||
1446 | bdz 1f (+12) | |
1447 | bf eq, 1f (+8) | |
1448 | b .Lgoto | |
1449 | 1:INSN1 | |
1450 | ||
1451 | See also "BO field encodings". */ | |
1452 | ||
1453 | rel = PPC_BD (insn); | |
1454 | newrel = (oldloc - *to) + rel; | |
1455 | ||
1456 | if (newrel < (1 << 15) && newrel >= -(1 << 15)) | |
1457 | insn = (insn & ~0xfffc) | (newrel & 0xfffc); | |
1458 | else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10) | |
1459 | { | |
1460 | newrel -= 4; | |
1461 | ||
1462 | /* Out of range. Cannot relocate instruction. */ | |
1463 | if (newrel >= (1 << 25) || newrel < -(1 << 25)) | |
1464 | return; | |
1465 | ||
1466 | if ((PPC_BO (insn) & 0x14) == 0x4) | |
1467 | insn ^= (1 << 24); | |
1468 | else if ((PPC_BO (insn) & 0x14) == 0x10) | |
1469 | insn ^= (1 << 22); | |
1470 | ||
1471 | /* Jump over the unconditional branch. */ | |
1472 | insn = (insn & ~0xfffc) | 0x8; | |
4196ab2a | 1473 | target_write_memory (*to, (unsigned char *) &insn, 4); |
a2174ba4 MK |
1474 | *to += 4; |
1475 | ||
1476 | /* Build a unconditional branch and copy LK bit. */ | |
1477 | insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3); | |
4196ab2a | 1478 | target_write_memory (*to, (unsigned char *) &insn, 4); |
a2174ba4 MK |
1479 | *to += 4; |
1480 | ||
1481 | return; | |
1482 | } | |
1483 | else if ((PPC_BO (insn) & 0x14) == 0) | |
1484 | { | |
1485 | uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12; | |
1486 | uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8; | |
1487 | ||
1488 | newrel -= 8; | |
1489 | ||
1490 | /* Out of range. Cannot relocate instruction. */ | |
1491 | if (newrel >= (1 << 25) || newrel < -(1 << 25)) | |
1492 | return; | |
1493 | ||
1494 | /* Copy BI field. */ | |
1495 | bf_insn |= (insn & 0x1f0000); | |
1496 | ||
1497 | /* Invert condition. */ | |
1498 | bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22); | |
1499 | bf_insn |= (insn ^ (1 << 24)) & (1 << 24); | |
1500 | ||
4196ab2a | 1501 | target_write_memory (*to, (unsigned char *) &bdnz_insn, 4); |
a2174ba4 | 1502 | *to += 4; |
4196ab2a | 1503 | target_write_memory (*to, (unsigned char *) &bf_insn, 4); |
a2174ba4 MK |
1504 | *to += 4; |
1505 | ||
1506 | /* Build a unconditional branch and copy LK bit. */ | |
1507 | insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3); | |
4196ab2a | 1508 | target_write_memory (*to, (unsigned char *) &insn, 4); |
a2174ba4 MK |
1509 | *to += 4; |
1510 | ||
1511 | return; | |
1512 | } | |
1513 | else /* (BO & 0x14) == 0x14, branch always. */ | |
1514 | { | |
1515 | /* Out of range. Cannot relocate instruction. */ | |
1516 | if (newrel >= (1 << 25) || newrel < -(1 << 25)) | |
1517 | return; | |
1518 | ||
1519 | /* Build a unconditional branch and copy LK bit. */ | |
1520 | insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3); | |
4196ab2a | 1521 | target_write_memory (*to, (unsigned char *) &insn, 4); |
a2174ba4 MK |
1522 | *to += 4; |
1523 | ||
1524 | return; | |
1525 | } | |
1526 | } | |
1527 | ||
4196ab2a | 1528 | target_write_memory (*to, (unsigned char *) &insn, 4); |
a2174ba4 MK |
1529 | *to += 4; |
1530 | } | |
1531 | ||
1532 | /* Implement install_fast_tracepoint_jump_pad of target_ops. | |
1533 | See target.h for details. */ | |
1534 | ||
1535 | static int | |
1536 | ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, | |
1537 | CORE_ADDR collector, | |
1538 | CORE_ADDR lockaddr, | |
1539 | ULONGEST orig_size, | |
1540 | CORE_ADDR *jump_entry, | |
1541 | CORE_ADDR *trampoline, | |
1542 | ULONGEST *trampoline_size, | |
1543 | unsigned char *jjump_pad_insn, | |
1544 | ULONGEST *jjump_pad_insn_size, | |
1545 | CORE_ADDR *adjusted_insn_addr, | |
1546 | CORE_ADDR *adjusted_insn_addr_end, | |
1547 | char *err) | |
1548 | { | |
1549 | uint32_t buf[256]; | |
1550 | uint32_t *p = buf; | |
1551 | int j, offset; | |
1552 | CORE_ADDR buildaddr = *jump_entry; | |
1553 | const CORE_ADDR entryaddr = *jump_entry; | |
1554 | int rsz, min_frame, frame_size, tp_reg; | |
1555 | #ifdef __powerpc64__ | |
1556 | struct regcache *regcache = get_thread_regcache (current_thread, 0); | |
1557 | int is_64 = register_size (regcache->tdesc, 0) == 8; | |
1558 | int is_opd = is_64 && !is_elfv2_inferior (); | |
1559 | #else | |
1560 | int is_64 = 0, is_opd = 0; | |
1561 | #endif | |
1562 | ||
1563 | #ifdef __powerpc64__ | |
1564 | if (is_64) | |
1565 | { | |
1566 | /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */ | |
1567 | rsz = 8; | |
1568 | min_frame = 112; | |
1569 | frame_size = (40 * rsz) + min_frame; | |
1570 | tp_reg = 13; | |
1571 | } | |
1572 | else | |
1573 | { | |
1574 | #endif | |
1575 | rsz = 4; | |
1576 | min_frame = 16; | |
1577 | frame_size = (40 * rsz) + min_frame; | |
1578 | tp_reg = 2; | |
1579 | #ifdef __powerpc64__ | |
1580 | } | |
1581 | #endif | |
1582 | ||
1583 | /* Stack frame layout for this jump pad, | |
1584 | ||
1585 | High thread_area (r13/r2) | | |
1586 | tpoint - collecting_t obj | |
1587 | PC/<tpaddr> | +36 | |
1588 | CTR | +35 | |
1589 | LR | +34 | |
1590 | XER | +33 | |
1591 | CR | +32 | |
1592 | R31 | | |
1593 | R29 | | |
1594 | ... | | |
1595 | R1 | +1 | |
1596 | R0 - collected registers | |
1597 | ... | | |
1598 | ... | | |
1599 | Low Back-chain - | |
1600 | ||
1601 | ||
1602 | The code flow of this jump pad, | |
1603 | ||
1604 | 1. Adjust SP | |
1605 | 2. Save GPR and SPR | |
1606 | 3. Prepare argument | |
1607 | 4. Call gdb_collector | |
1608 | 5. Restore GPR and SPR | |
1609 | 6. Restore SP | |
1610 | 7. Build a jump for back to the program | |
1611 | 8. Copy/relocate original instruction | |
30baf67b | 1612 | 9. Build a jump for replacing original instruction. */ |
a2174ba4 MK |
1613 | |
1614 | /* Adjust stack pointer. */ | |
1615 | if (is_64) | |
1616 | p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */ | |
1617 | else | |
1618 | p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */ | |
1619 | ||
1620 | /* Store GPRs. Save R1 later, because it had just been modified, but | |
1621 | we want the original value. */ | |
1622 | for (j = 2; j < 32; j++) | |
1623 | p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64); | |
1624 | p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64); | |
1625 | /* Set r0 to the original value of r1 before adjusting stack frame, | |
1626 | and then save it. */ | |
1627 | p += GEN_ADDI (p, 0, 1, frame_size); | |
1628 | p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64); | |
1629 | ||
1630 | /* Save CR, XER, LR, and CTR. */ | |
1631 | p += GEN_MFCR (p, 3); /* mfcr r3 */ | |
1632 | p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */ | |
1633 | p += GEN_MFSPR (p, 5, 8); /* mflr r5 */ | |
1634 | p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */ | |
1635 | p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */ | |
1636 | p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */ | |
1637 | p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */ | |
1638 | p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */ | |
1639 | ||
1640 | /* Save PC<tpaddr> */ | |
1641 | p += gen_limm (p, 3, tpaddr, is_64); | |
1642 | p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64); | |
1643 | ||
1644 | ||
1645 | /* Setup arguments to collector. */ | |
1646 | /* Set r4 to collected registers. */ | |
1647 | p += GEN_ADDI (p, 4, 1, min_frame); | |
1648 | /* Set r3 to TPOINT. */ | |
1649 | p += gen_limm (p, 3, tpoint, is_64); | |
1650 | ||
1651 | /* Prepare collecting_t object for lock. */ | |
1652 | p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64); | |
1653 | p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64); | |
1654 | /* Set R5 to collecting object. */ | |
1655 | p += GEN_ADDI (p, 5, 1, 37 * rsz); | |
1656 | ||
1657 | p += GEN_LWSYNC (p); | |
1658 | p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64); | |
1659 | p += GEN_LWSYNC (p); | |
1660 | ||
1661 | /* Call to collector. */ | |
1662 | p += gen_call (p, collector, is_64, is_opd); | |
1663 | ||
1664 | /* Simply write 0 to release the lock. */ | |
1665 | p += gen_limm (p, 3, lockaddr, is_64); | |
1666 | p += gen_limm (p, 4, 0, is_64); | |
1667 | p += GEN_LWSYNC (p); | |
1668 | p += GEN_STORE (p, 4, 3, 0, is_64); | |
1669 | ||
1670 | /* Restore stack and registers. */ | |
1671 | p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */ | |
1672 | p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */ | |
1673 | p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */ | |
1674 | p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */ | |
1675 | p += GEN_MTCR (p, 3); /* mtcr r3 */ | |
1676 | p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */ | |
1677 | p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */ | |
1678 | p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */ | |
1679 | ||
1680 | /* Restore GPRs. */ | |
1681 | for (j = 2; j < 32; j++) | |
1682 | p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64); | |
1683 | p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64); | |
1684 | /* Restore SP. */ | |
1685 | p += GEN_ADDI (p, 1, 1, frame_size); | |
1686 | ||
1687 | /* Flush instructions to inferior memory. */ | |
4196ab2a | 1688 | target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4); |
a2174ba4 MK |
1689 | |
1690 | /* Now, insert the original instruction to execute in the jump pad. */ | |
1691 | *adjusted_insn_addr = buildaddr + (p - buf) * 4; | |
1692 | *adjusted_insn_addr_end = *adjusted_insn_addr; | |
1693 | ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr); | |
1694 | ||
1695 | /* Verify the relocation size. If should be 4 for normal copy, | |
1696 | 8 or 12 for some conditional branch. */ | |
1697 | if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0) | |
1698 | || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12)) | |
1699 | { | |
1700 | sprintf (err, "E.Unexpected instruction length = %d" | |
1701 | "when relocate instruction.", | |
1702 | (int) (*adjusted_insn_addr_end - *adjusted_insn_addr)); | |
1703 | return 1; | |
1704 | } | |
1705 | ||
1706 | buildaddr = *adjusted_insn_addr_end; | |
1707 | p = buf; | |
1708 | /* Finally, write a jump back to the program. */ | |
1709 | offset = (tpaddr + 4) - buildaddr; | |
1710 | if (offset >= (1 << 25) || offset < -(1 << 25)) | |
1711 | { | |
1712 | sprintf (err, "E.Jump back from jump pad too far from tracepoint " | |
1713 | "(offset 0x%x > 26-bit).", offset); | |
1714 | return 1; | |
1715 | } | |
1716 | /* b <tpaddr+4> */ | |
1717 | p += GEN_B (p, offset); | |
4196ab2a | 1718 | target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4); |
a2174ba4 MK |
1719 | *jump_entry = buildaddr + (p - buf) * 4; |
1720 | ||
1721 | /* The jump pad is now built. Wire in a jump to our jump pad. This | |
1722 | is always done last (by our caller actually), so that we can | |
1723 | install fast tracepoints with threads running. This relies on | |
1724 | the agent's atomic write support. */ | |
1725 | offset = entryaddr - tpaddr; | |
1726 | if (offset >= (1 << 25) || offset < -(1 << 25)) | |
1727 | { | |
1728 | sprintf (err, "E.Jump back from jump pad too far from tracepoint " | |
1729 | "(offset 0x%x > 26-bit).", offset); | |
1730 | return 1; | |
1731 | } | |
1732 | /* b <jentry> */ | |
1733 | GEN_B ((uint32_t *) jjump_pad_insn, offset); | |
1734 | *jjump_pad_insn_size = 4; | |
1735 | ||
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | /* Returns the minimum instruction length for installing a tracepoint. */ | |
1740 | ||
1741 | static int | |
1742 | ppc_get_min_fast_tracepoint_insn_len (void) | |
1743 | { | |
1744 | return 4; | |
1745 | } | |
1746 | ||
14e2b6d9 MK |
1747 | /* Emits a given buffer into the target at current_insn_ptr. Length |
1748 | is in units of 32-bit words. */ | |
1749 | ||
1750 | static void | |
1751 | emit_insns (uint32_t *buf, int n) | |
1752 | { | |
1753 | n = n * sizeof (uint32_t); | |
4196ab2a | 1754 | target_write_memory (current_insn_ptr, (unsigned char *) buf, n); |
14e2b6d9 MK |
1755 | current_insn_ptr += n; |
1756 | } | |
1757 | ||
1758 | #define __EMIT_ASM(NAME, INSNS) \ | |
1759 | do \ | |
1760 | { \ | |
1761 | extern uint32_t start_bcax_ ## NAME []; \ | |
1762 | extern uint32_t end_bcax_ ## NAME []; \ | |
1763 | emit_insns (start_bcax_ ## NAME, \ | |
1764 | end_bcax_ ## NAME - start_bcax_ ## NAME); \ | |
1765 | __asm__ (".section .text.__ppcbcax\n\t" \ | |
1766 | "start_bcax_" #NAME ":\n\t" \ | |
1767 | INSNS "\n\t" \ | |
1768 | "end_bcax_" #NAME ":\n\t" \ | |
1769 | ".previous\n\t"); \ | |
1770 | } while (0) | |
1771 | ||
1772 | #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS) | |
1773 | #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS) | |
1774 | ||
1775 | /* | |
1776 | ||
1777 | Bytecode execution stack frame - 32-bit | |
1778 | ||
1779 | | LR save area (SP + 4) | |
1780 | SP' -> +- Back chain (SP + 0) | |
1781 | | Save r31 for access saved arguments | |
1782 | | Save r30 for bytecode stack pointer | |
1783 | | Save r4 for incoming argument *value | |
1784 | | Save r3 for incoming argument regs | |
1785 | r30 -> +- Bytecode execution stack | |
1786 | | | |
1787 | | 64-byte (8 doublewords) at initial. | |
1788 | | Expand stack as needed. | |
1789 | | | |
1790 | +- | |
1791 | | Some padding for minimum stack frame and 16-byte alignment. | |
1792 | | 16 bytes. | |
1793 | SP +- Back-chain (SP') | |
1794 | ||
1795 | initial frame size | |
1796 | = 16 + (4 * 4) + 64 | |
1797 | = 96 | |
1798 | ||
1799 | r30 is the stack-pointer for bytecode machine. | |
1800 | It should point to next-empty, so we can use LDU for pop. | |
1801 | r3 is used for cache of the high part of TOP value. | |
1802 | It was the first argument, pointer to regs. | |
1803 | r4 is used for cache of the low part of TOP value. | |
1804 | It was the second argument, pointer to the result. | |
1805 | We should set *result = TOP after leaving this function. | |
1806 | ||
1807 | Note: | |
1808 | * To restore stack at epilogue | |
1809 | => sp = r31 | |
1810 | * To check stack is big enough for bytecode execution. | |
1811 | => r30 - 8 > SP + 8 | |
1812 | * To return execution result. | |
1813 | => 0(r4) = TOP | |
1814 | ||
1815 | */ | |
1816 | ||
1817 | /* Regardless of endian, register 3 is always high part, 4 is low part. | |
1818 | These defines are used when the register pair is stored/loaded. | |
1819 | Likewise, to simplify code, have a similiar define for 5:6. */ | |
1820 | ||
1821 | #if __BYTE_ORDER == __LITTLE_ENDIAN | |
1822 | #define TOP_FIRST "4" | |
1823 | #define TOP_SECOND "3" | |
1824 | #define TMP_FIRST "6" | |
1825 | #define TMP_SECOND "5" | |
1826 | #else | |
1827 | #define TOP_FIRST "3" | |
1828 | #define TOP_SECOND "4" | |
1829 | #define TMP_FIRST "5" | |
1830 | #define TMP_SECOND "6" | |
1831 | #endif | |
1832 | ||
1833 | /* Emit prologue in inferior memory. See above comments. */ | |
1834 | ||
1835 | static void | |
1836 | ppc_emit_prologue (void) | |
1837 | { | |
1838 | EMIT_ASM (/* Save return address. */ | |
1839 | "mflr 0 \n" | |
1840 | "stw 0, 4(1) \n" | |
1841 | /* Adjust SP. 96 is the initial frame size. */ | |
1842 | "stwu 1, -96(1) \n" | |
1843 | /* Save r30 and incoming arguments. */ | |
1844 | "stw 31, 96-4(1) \n" | |
1845 | "stw 30, 96-8(1) \n" | |
1846 | "stw 4, 96-12(1) \n" | |
1847 | "stw 3, 96-16(1) \n" | |
1848 | /* Point r31 to original r1 for access arguments. */ | |
1849 | "addi 31, 1, 96 \n" | |
1850 | /* Set r30 to pointing stack-top. */ | |
1851 | "addi 30, 1, 64 \n" | |
1852 | /* Initial r3/TOP to 0. */ | |
1853 | "li 3, 0 \n" | |
1854 | "li 4, 0 \n"); | |
1855 | } | |
1856 | ||
1857 | /* Emit epilogue in inferior memory. See above comments. */ | |
1858 | ||
1859 | static void | |
1860 | ppc_emit_epilogue (void) | |
1861 | { | |
1862 | EMIT_ASM (/* *result = TOP */ | |
1863 | "lwz 5, -12(31) \n" | |
1864 | "stw " TOP_FIRST ", 0(5) \n" | |
1865 | "stw " TOP_SECOND ", 4(5) \n" | |
1866 | /* Restore registers. */ | |
1867 | "lwz 31, -4(31) \n" | |
1868 | "lwz 30, -8(31) \n" | |
1869 | /* Restore SP. */ | |
1870 | "lwz 1, 0(1) \n" | |
1871 | /* Restore LR. */ | |
1872 | "lwz 0, 4(1) \n" | |
1873 | /* Return 0 for no-error. */ | |
1874 | "li 3, 0 \n" | |
1875 | "mtlr 0 \n" | |
1876 | "blr \n"); | |
1877 | } | |
1878 | ||
1879 | /* TOP = stack[--sp] + TOP */ | |
1880 | ||
1881 | static void | |
1882 | ppc_emit_add (void) | |
1883 | { | |
1884 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
1885 | "lwz " TMP_SECOND ", 4(30)\n" | |
1886 | "addc 4, 6, 4 \n" | |
1887 | "adde 3, 5, 3 \n"); | |
1888 | } | |
1889 | ||
1890 | /* TOP = stack[--sp] - TOP */ | |
1891 | ||
1892 | static void | |
1893 | ppc_emit_sub (void) | |
1894 | { | |
1895 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
1896 | "lwz " TMP_SECOND ", 4(30) \n" | |
1897 | "subfc 4, 4, 6 \n" | |
1898 | "subfe 3, 3, 5 \n"); | |
1899 | } | |
1900 | ||
1901 | /* TOP = stack[--sp] * TOP */ | |
1902 | ||
1903 | static void | |
1904 | ppc_emit_mul (void) | |
1905 | { | |
1906 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
1907 | "lwz " TMP_SECOND ", 4(30) \n" | |
1908 | "mulhwu 7, 6, 4 \n" | |
1909 | "mullw 3, 6, 3 \n" | |
1910 | "mullw 5, 4, 5 \n" | |
1911 | "mullw 4, 6, 4 \n" | |
1912 | "add 3, 5, 3 \n" | |
1913 | "add 3, 7, 3 \n"); | |
1914 | } | |
1915 | ||
1916 | /* TOP = stack[--sp] << TOP */ | |
1917 | ||
1918 | static void | |
1919 | ppc_emit_lsh (void) | |
1920 | { | |
1921 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
1922 | "lwz " TMP_SECOND ", 4(30) \n" | |
1923 | "subfic 3, 4, 32\n" /* r3 = 32 - TOP */ | |
1924 | "addi 7, 4, -32\n" /* r7 = TOP - 32 */ | |
1925 | "slw 5, 5, 4\n" /* Shift high part left */ | |
1926 | "slw 4, 6, 4\n" /* Shift low part left */ | |
1927 | "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */ | |
1928 | "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */ | |
1929 | "or 3, 5, 3\n" | |
1930 | "or 3, 7, 3\n"); /* Assemble high part */ | |
1931 | } | |
1932 | ||
1933 | /* Top = stack[--sp] >> TOP | |
1934 | (Arithmetic shift right) */ | |
1935 | ||
1936 | static void | |
1937 | ppc_emit_rsh_signed (void) | |
1938 | { | |
1939 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
1940 | "lwz " TMP_SECOND ", 4(30) \n" | |
1941 | "addi 7, 4, -32\n" /* r7 = TOP - 32 */ | |
1942 | "sraw 3, 5, 4\n" /* Shift high part right */ | |
1943 | "cmpwi 7, 1\n" | |
1944 | "blt 0, 1f\n" /* If shift <= 32, goto 1: */ | |
1945 | "sraw 4, 5, 7\n" /* Shift high to low */ | |
1946 | "b 2f\n" | |
1947 | "1:\n" | |
1948 | "subfic 7, 4, 32\n" /* r7 = 32 - TOP */ | |
1949 | "srw 4, 6, 4\n" /* Shift low part right */ | |
1950 | "slw 5, 5, 7\n" /* Shift high to low */ | |
1951 | "or 4, 4, 5\n" /* Assemble low part */ | |
1952 | "2:\n"); | |
1953 | } | |
1954 | ||
1955 | /* Top = stack[--sp] >> TOP | |
1956 | (Logical shift right) */ | |
1957 | ||
1958 | static void | |
1959 | ppc_emit_rsh_unsigned (void) | |
1960 | { | |
1961 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
1962 | "lwz " TMP_SECOND ", 4(30) \n" | |
1963 | "subfic 3, 4, 32\n" /* r3 = 32 - TOP */ | |
1964 | "addi 7, 4, -32\n" /* r7 = TOP - 32 */ | |
1965 | "srw 6, 6, 4\n" /* Shift low part right */ | |
1966 | "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */ | |
1967 | "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */ | |
1968 | "or 6, 6, 3\n" | |
1969 | "srw 3, 5, 4\n" /* Shift high part right */ | |
1970 | "or 4, 6, 7\n"); /* Assemble low part */ | |
1971 | } | |
1972 | ||
1973 | /* Emit code for signed-extension specified by ARG. */ | |
1974 | ||
1975 | static void | |
1976 | ppc_emit_ext (int arg) | |
1977 | { | |
1978 | switch (arg) | |
1979 | { | |
1980 | case 8: | |
1981 | EMIT_ASM ("extsb 4, 4\n" | |
1982 | "srawi 3, 4, 31"); | |
1983 | break; | |
1984 | case 16: | |
1985 | EMIT_ASM ("extsh 4, 4\n" | |
1986 | "srawi 3, 4, 31"); | |
1987 | break; | |
1988 | case 32: | |
1989 | EMIT_ASM ("srawi 3, 4, 31"); | |
1990 | break; | |
1991 | default: | |
1992 | emit_error = 1; | |
1993 | } | |
1994 | } | |
1995 | ||
1996 | /* Emit code for zero-extension specified by ARG. */ | |
1997 | ||
1998 | static void | |
1999 | ppc_emit_zero_ext (int arg) | |
2000 | { | |
2001 | switch (arg) | |
2002 | { | |
2003 | case 8: | |
2004 | EMIT_ASM ("clrlwi 4,4,24\n" | |
2005 | "li 3, 0\n"); | |
2006 | break; | |
2007 | case 16: | |
2008 | EMIT_ASM ("clrlwi 4,4,16\n" | |
2009 | "li 3, 0\n"); | |
2010 | break; | |
2011 | case 32: | |
2012 | EMIT_ASM ("li 3, 0"); | |
2013 | break; | |
2014 | default: | |
2015 | emit_error = 1; | |
2016 | } | |
2017 | } | |
2018 | ||
2019 | /* TOP = !TOP | |
2020 | i.e., TOP = (TOP == 0) ? 1 : 0; */ | |
2021 | ||
2022 | static void | |
2023 | ppc_emit_log_not (void) | |
2024 | { | |
2025 | EMIT_ASM ("or 4, 3, 4 \n" | |
2026 | "cntlzw 4, 4 \n" | |
2027 | "srwi 4, 4, 5 \n" | |
2028 | "li 3, 0 \n"); | |
2029 | } | |
2030 | ||
2031 | /* TOP = stack[--sp] & TOP */ | |
2032 | ||
2033 | static void | |
2034 | ppc_emit_bit_and (void) | |
2035 | { | |
2036 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2037 | "lwz " TMP_SECOND ", 4(30) \n" | |
2038 | "and 4, 6, 4 \n" | |
2039 | "and 3, 5, 3 \n"); | |
2040 | } | |
2041 | ||
2042 | /* TOP = stack[--sp] | TOP */ | |
2043 | ||
2044 | static void | |
2045 | ppc_emit_bit_or (void) | |
2046 | { | |
2047 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2048 | "lwz " TMP_SECOND ", 4(30) \n" | |
2049 | "or 4, 6, 4 \n" | |
2050 | "or 3, 5, 3 \n"); | |
2051 | } | |
2052 | ||
2053 | /* TOP = stack[--sp] ^ TOP */ | |
2054 | ||
2055 | static void | |
2056 | ppc_emit_bit_xor (void) | |
2057 | { | |
2058 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2059 | "lwz " TMP_SECOND ", 4(30) \n" | |
2060 | "xor 4, 6, 4 \n" | |
2061 | "xor 3, 5, 3 \n"); | |
2062 | } | |
2063 | ||
2064 | /* TOP = ~TOP | |
2065 | i.e., TOP = ~(TOP | TOP) */ | |
2066 | ||
2067 | static void | |
2068 | ppc_emit_bit_not (void) | |
2069 | { | |
2070 | EMIT_ASM ("nor 3, 3, 3 \n" | |
2071 | "nor 4, 4, 4 \n"); | |
2072 | } | |
2073 | ||
2074 | /* TOP = stack[--sp] == TOP */ | |
2075 | ||
2076 | static void | |
2077 | ppc_emit_equal (void) | |
2078 | { | |
2079 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2080 | "lwz " TMP_SECOND ", 4(30) \n" | |
2081 | "xor 4, 6, 4 \n" | |
2082 | "xor 3, 5, 3 \n" | |
2083 | "or 4, 3, 4 \n" | |
2084 | "cntlzw 4, 4 \n" | |
2085 | "srwi 4, 4, 5 \n" | |
2086 | "li 3, 0 \n"); | |
2087 | } | |
2088 | ||
2089 | /* TOP = stack[--sp] < TOP | |
2090 | (Signed comparison) */ | |
2091 | ||
2092 | static void | |
2093 | ppc_emit_less_signed (void) | |
2094 | { | |
2095 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2096 | "lwz " TMP_SECOND ", 4(30) \n" | |
2097 | "cmplw 6, 6, 4 \n" | |
2098 | "cmpw 7, 5, 3 \n" | |
2099 | /* CR6 bit 0 = low less and high equal */ | |
2100 | "crand 6*4+0, 6*4+0, 7*4+2\n" | |
2101 | /* CR7 bit 0 = (low less and high equal) or high less */ | |
2102 | "cror 7*4+0, 7*4+0, 6*4+0\n" | |
2103 | "mfcr 4 \n" | |
2104 | "rlwinm 4, 4, 29, 31, 31 \n" | |
2105 | "li 3, 0 \n"); | |
2106 | } | |
2107 | ||
2108 | /* TOP = stack[--sp] < TOP | |
2109 | (Unsigned comparison) */ | |
2110 | ||
2111 | static void | |
2112 | ppc_emit_less_unsigned (void) | |
2113 | { | |
2114 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2115 | "lwz " TMP_SECOND ", 4(30) \n" | |
2116 | "cmplw 6, 6, 4 \n" | |
2117 | "cmplw 7, 5, 3 \n" | |
2118 | /* CR6 bit 0 = low less and high equal */ | |
2119 | "crand 6*4+0, 6*4+0, 7*4+2\n" | |
2120 | /* CR7 bit 0 = (low less and high equal) or high less */ | |
2121 | "cror 7*4+0, 7*4+0, 6*4+0\n" | |
2122 | "mfcr 4 \n" | |
2123 | "rlwinm 4, 4, 29, 31, 31 \n" | |
2124 | "li 3, 0 \n"); | |
2125 | } | |
2126 | ||
2127 | /* Access the memory address in TOP in size of SIZE. | |
2128 | Zero-extend the read value. */ | |
2129 | ||
2130 | static void | |
2131 | ppc_emit_ref (int size) | |
2132 | { | |
2133 | switch (size) | |
2134 | { | |
2135 | case 1: | |
2136 | EMIT_ASM ("lbz 4, 0(4)\n" | |
2137 | "li 3, 0"); | |
2138 | break; | |
2139 | case 2: | |
2140 | EMIT_ASM ("lhz 4, 0(4)\n" | |
2141 | "li 3, 0"); | |
2142 | break; | |
2143 | case 4: | |
2144 | EMIT_ASM ("lwz 4, 0(4)\n" | |
2145 | "li 3, 0"); | |
2146 | break; | |
2147 | case 8: | |
2148 | if (__BYTE_ORDER == __LITTLE_ENDIAN) | |
2149 | EMIT_ASM ("lwz 3, 4(4)\n" | |
2150 | "lwz 4, 0(4)"); | |
2151 | else | |
2152 | EMIT_ASM ("lwz 3, 0(4)\n" | |
2153 | "lwz 4, 4(4)"); | |
2154 | break; | |
2155 | } | |
2156 | } | |
2157 | ||
2158 | /* TOP = NUM */ | |
2159 | ||
2160 | static void | |
2161 | ppc_emit_const (LONGEST num) | |
2162 | { | |
2163 | uint32_t buf[10]; | |
2164 | uint32_t *p = buf; | |
2165 | ||
2166 | p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0); | |
2167 | p += gen_limm (p, 4, num & 0xffffffff, 0); | |
2168 | ||
2169 | emit_insns (buf, p - buf); | |
2170 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2171 | } | |
2172 | ||
2173 | /* Set TOP to the value of register REG by calling get_raw_reg function | |
2174 | with two argument, collected buffer and register number. */ | |
2175 | ||
2176 | static void | |
2177 | ppc_emit_reg (int reg) | |
2178 | { | |
2179 | uint32_t buf[13]; | |
2180 | uint32_t *p = buf; | |
2181 | ||
2182 | /* fctx->regs is passed in r3 and then saved in -16(31). */ | |
2183 | p += GEN_LWZ (p, 3, 31, -16); | |
2184 | p += GEN_LI (p, 4, reg); /* li r4, reg */ | |
2185 | p += gen_call (p, get_raw_reg_func_addr (), 0, 0); | |
2186 | ||
2187 | emit_insns (buf, p - buf); | |
2188 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2189 | ||
2190 | if (__BYTE_ORDER == __LITTLE_ENDIAN) | |
2191 | { | |
2192 | EMIT_ASM ("mr 5, 4\n" | |
2193 | "mr 4, 3\n" | |
2194 | "mr 3, 5\n"); | |
2195 | } | |
2196 | } | |
2197 | ||
2198 | /* TOP = stack[--sp] */ | |
2199 | ||
2200 | static void | |
2201 | ppc_emit_pop (void) | |
2202 | { | |
2203 | EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n" | |
2204 | "lwz " TOP_SECOND ", 4(30) \n"); | |
2205 | } | |
2206 | ||
2207 | /* stack[sp++] = TOP | |
2208 | ||
2209 | Because we may use up bytecode stack, expand 8 doublewords more | |
2210 | if needed. */ | |
2211 | ||
2212 | static void | |
2213 | ppc_emit_stack_flush (void) | |
2214 | { | |
2215 | /* Make sure bytecode stack is big enough before push. | |
2216 | Otherwise, expand 64-byte more. */ | |
2217 | ||
2218 | EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n" | |
2219 | " stw " TOP_SECOND ", 4(30)\n" | |
2220 | " addi 5, 30, -(8 + 8) \n" | |
2221 | " cmpw 7, 5, 1 \n" | |
2222 | " bgt 7, 1f \n" | |
2223 | " stwu 31, -64(1) \n" | |
2224 | "1:addi 30, 30, -8 \n"); | |
2225 | } | |
2226 | ||
2227 | /* Swap TOP and stack[sp-1] */ | |
2228 | ||
2229 | static void | |
2230 | ppc_emit_swap (void) | |
2231 | { | |
2232 | EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n" | |
2233 | "lwz " TMP_SECOND ", 12(30) \n" | |
2234 | "stw " TOP_FIRST ", 8(30) \n" | |
2235 | "stw " TOP_SECOND ", 12(30) \n" | |
2236 | "mr 3, 5 \n" | |
2237 | "mr 4, 6 \n"); | |
2238 | } | |
2239 | ||
2240 | /* Discard N elements in the stack. Also used for ppc64. */ | |
2241 | ||
2242 | static void | |
2243 | ppc_emit_stack_adjust (int n) | |
2244 | { | |
2245 | uint32_t buf[6]; | |
2246 | uint32_t *p = buf; | |
2247 | ||
2248 | n = n << 3; | |
2249 | if ((n >> 15) != 0) | |
2250 | { | |
2251 | emit_error = 1; | |
2252 | return; | |
2253 | } | |
2254 | ||
2255 | p += GEN_ADDI (p, 30, 30, n); | |
2256 | ||
2257 | emit_insns (buf, p - buf); | |
2258 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2259 | } | |
2260 | ||
2261 | /* Call function FN. */ | |
2262 | ||
2263 | static void | |
2264 | ppc_emit_call (CORE_ADDR fn) | |
2265 | { | |
2266 | uint32_t buf[11]; | |
2267 | uint32_t *p = buf; | |
2268 | ||
2269 | p += gen_call (p, fn, 0, 0); | |
2270 | ||
2271 | emit_insns (buf, p - buf); | |
2272 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2273 | } | |
2274 | ||
2275 | /* FN's prototype is `LONGEST(*fn)(int)'. | |
2276 | TOP = fn (arg1) | |
2277 | */ | |
2278 | ||
2279 | static void | |
2280 | ppc_emit_int_call_1 (CORE_ADDR fn, int arg1) | |
2281 | { | |
2282 | uint32_t buf[15]; | |
2283 | uint32_t *p = buf; | |
2284 | ||
2285 | /* Setup argument. arg1 is a 16-bit value. */ | |
2286 | p += gen_limm (p, 3, (uint32_t) arg1, 0); | |
2287 | p += gen_call (p, fn, 0, 0); | |
2288 | ||
2289 | emit_insns (buf, p - buf); | |
2290 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2291 | ||
2292 | if (__BYTE_ORDER == __LITTLE_ENDIAN) | |
2293 | { | |
2294 | EMIT_ASM ("mr 5, 4\n" | |
2295 | "mr 4, 3\n" | |
2296 | "mr 3, 5\n"); | |
2297 | } | |
2298 | } | |
2299 | ||
2300 | /* FN's prototype is `void(*fn)(int,LONGEST)'. | |
2301 | fn (arg1, TOP) | |
2302 | ||
2303 | TOP should be preserved/restored before/after the call. */ | |
2304 | ||
2305 | static void | |
2306 | ppc_emit_void_call_2 (CORE_ADDR fn, int arg1) | |
2307 | { | |
2308 | uint32_t buf[21]; | |
2309 | uint32_t *p = buf; | |
2310 | ||
2311 | /* Save TOP. 0(30) is next-empty. */ | |
2312 | p += GEN_STW (p, 3, 30, 0); | |
2313 | p += GEN_STW (p, 4, 30, 4); | |
2314 | ||
2315 | /* Setup argument. arg1 is a 16-bit value. */ | |
2316 | if (__BYTE_ORDER == __LITTLE_ENDIAN) | |
2317 | { | |
2318 | p += GEN_MR (p, 5, 4); | |
2319 | p += GEN_MR (p, 6, 3); | |
2320 | } | |
2321 | else | |
2322 | { | |
2323 | p += GEN_MR (p, 5, 3); | |
2324 | p += GEN_MR (p, 6, 4); | |
2325 | } | |
2326 | p += gen_limm (p, 3, (uint32_t) arg1, 0); | |
2327 | p += gen_call (p, fn, 0, 0); | |
2328 | ||
2329 | /* Restore TOP */ | |
2330 | p += GEN_LWZ (p, 3, 30, 0); | |
2331 | p += GEN_LWZ (p, 4, 30, 4); | |
2332 | ||
2333 | emit_insns (buf, p - buf); | |
2334 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2335 | } | |
2336 | ||
2337 | /* Note in the following goto ops: | |
2338 | ||
2339 | When emitting goto, the target address is later relocated by | |
2340 | write_goto_address. OFFSET_P is the offset of the branch instruction | |
2341 | in the code sequence, and SIZE_P is how to relocate the instruction, | |
2342 | recognized by ppc_write_goto_address. In current implementation, | |
2343 | SIZE can be either 24 or 14 for branch of conditional-branch instruction. | |
2344 | */ | |
2345 | ||
2346 | /* If TOP is true, goto somewhere. Otherwise, just fall-through. */ | |
2347 | ||
2348 | static void | |
2349 | ppc_emit_if_goto (int *offset_p, int *size_p) | |
2350 | { | |
2351 | EMIT_ASM ("or. 3, 3, 4 \n" | |
2352 | "lwzu " TOP_FIRST ", 8(30) \n" | |
2353 | "lwz " TOP_SECOND ", 4(30) \n" | |
2354 | "1:bne 0, 1b \n"); | |
2355 | ||
2356 | if (offset_p) | |
2357 | *offset_p = 12; | |
2358 | if (size_p) | |
2359 | *size_p = 14; | |
2360 | } | |
2361 | ||
2362 | /* Unconditional goto. Also used for ppc64. */ | |
2363 | ||
2364 | static void | |
2365 | ppc_emit_goto (int *offset_p, int *size_p) | |
2366 | { | |
2367 | EMIT_ASM ("1:b 1b"); | |
2368 | ||
2369 | if (offset_p) | |
2370 | *offset_p = 0; | |
2371 | if (size_p) | |
2372 | *size_p = 24; | |
2373 | } | |
2374 | ||
2375 | /* Goto if stack[--sp] == TOP */ | |
2376 | ||
2377 | static void | |
2378 | ppc_emit_eq_goto (int *offset_p, int *size_p) | |
2379 | { | |
2380 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2381 | "lwz " TMP_SECOND ", 4(30) \n" | |
2382 | "xor 4, 6, 4 \n" | |
2383 | "xor 3, 5, 3 \n" | |
2384 | "or. 3, 3, 4 \n" | |
2385 | "lwzu " TOP_FIRST ", 8(30) \n" | |
2386 | "lwz " TOP_SECOND ", 4(30) \n" | |
2387 | "1:beq 0, 1b \n"); | |
2388 | ||
2389 | if (offset_p) | |
2390 | *offset_p = 28; | |
2391 | if (size_p) | |
2392 | *size_p = 14; | |
2393 | } | |
2394 | ||
2395 | /* Goto if stack[--sp] != TOP */ | |
2396 | ||
2397 | static void | |
2398 | ppc_emit_ne_goto (int *offset_p, int *size_p) | |
2399 | { | |
2400 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2401 | "lwz " TMP_SECOND ", 4(30) \n" | |
2402 | "xor 4, 6, 4 \n" | |
2403 | "xor 3, 5, 3 \n" | |
2404 | "or. 3, 3, 4 \n" | |
2405 | "lwzu " TOP_FIRST ", 8(30) \n" | |
2406 | "lwz " TOP_SECOND ", 4(30) \n" | |
2407 | "1:bne 0, 1b \n"); | |
2408 | ||
2409 | if (offset_p) | |
2410 | *offset_p = 28; | |
2411 | if (size_p) | |
2412 | *size_p = 14; | |
2413 | } | |
2414 | ||
2415 | /* Goto if stack[--sp] < TOP */ | |
2416 | ||
2417 | static void | |
2418 | ppc_emit_lt_goto (int *offset_p, int *size_p) | |
2419 | { | |
2420 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2421 | "lwz " TMP_SECOND ", 4(30) \n" | |
2422 | "cmplw 6, 6, 4 \n" | |
2423 | "cmpw 7, 5, 3 \n" | |
2424 | /* CR6 bit 0 = low less and high equal */ | |
2425 | "crand 6*4+0, 6*4+0, 7*4+2\n" | |
2426 | /* CR7 bit 0 = (low less and high equal) or high less */ | |
2427 | "cror 7*4+0, 7*4+0, 6*4+0\n" | |
2428 | "lwzu " TOP_FIRST ", 8(30) \n" | |
2429 | "lwz " TOP_SECOND ", 4(30)\n" | |
2430 | "1:blt 7, 1b \n"); | |
2431 | ||
2432 | if (offset_p) | |
2433 | *offset_p = 32; | |
2434 | if (size_p) | |
2435 | *size_p = 14; | |
2436 | } | |
2437 | ||
2438 | /* Goto if stack[--sp] <= TOP */ | |
2439 | ||
2440 | static void | |
2441 | ppc_emit_le_goto (int *offset_p, int *size_p) | |
2442 | { | |
2443 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2444 | "lwz " TMP_SECOND ", 4(30) \n" | |
2445 | "cmplw 6, 6, 4 \n" | |
2446 | "cmpw 7, 5, 3 \n" | |
2447 | /* CR6 bit 0 = low less/equal and high equal */ | |
2448 | "crandc 6*4+0, 7*4+2, 6*4+1\n" | |
2449 | /* CR7 bit 0 = (low less/eq and high equal) or high less */ | |
2450 | "cror 7*4+0, 7*4+0, 6*4+0\n" | |
2451 | "lwzu " TOP_FIRST ", 8(30) \n" | |
2452 | "lwz " TOP_SECOND ", 4(30)\n" | |
2453 | "1:blt 7, 1b \n"); | |
2454 | ||
2455 | if (offset_p) | |
2456 | *offset_p = 32; | |
2457 | if (size_p) | |
2458 | *size_p = 14; | |
2459 | } | |
2460 | ||
2461 | /* Goto if stack[--sp] > TOP */ | |
2462 | ||
2463 | static void | |
2464 | ppc_emit_gt_goto (int *offset_p, int *size_p) | |
2465 | { | |
2466 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2467 | "lwz " TMP_SECOND ", 4(30) \n" | |
2468 | "cmplw 6, 6, 4 \n" | |
2469 | "cmpw 7, 5, 3 \n" | |
2470 | /* CR6 bit 0 = low greater and high equal */ | |
2471 | "crand 6*4+0, 6*4+1, 7*4+2\n" | |
2472 | /* CR7 bit 0 = (low greater and high equal) or high greater */ | |
2473 | "cror 7*4+0, 7*4+1, 6*4+0\n" | |
2474 | "lwzu " TOP_FIRST ", 8(30) \n" | |
2475 | "lwz " TOP_SECOND ", 4(30)\n" | |
2476 | "1:blt 7, 1b \n"); | |
2477 | ||
2478 | if (offset_p) | |
2479 | *offset_p = 32; | |
2480 | if (size_p) | |
2481 | *size_p = 14; | |
2482 | } | |
2483 | ||
2484 | /* Goto if stack[--sp] >= TOP */ | |
2485 | ||
2486 | static void | |
2487 | ppc_emit_ge_goto (int *offset_p, int *size_p) | |
2488 | { | |
2489 | EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" | |
2490 | "lwz " TMP_SECOND ", 4(30) \n" | |
2491 | "cmplw 6, 6, 4 \n" | |
2492 | "cmpw 7, 5, 3 \n" | |
2493 | /* CR6 bit 0 = low ge and high equal */ | |
2494 | "crandc 6*4+0, 7*4+2, 6*4+0\n" | |
2495 | /* CR7 bit 0 = (low ge and high equal) or high greater */ | |
2496 | "cror 7*4+0, 7*4+1, 6*4+0\n" | |
2497 | "lwzu " TOP_FIRST ", 8(30)\n" | |
2498 | "lwz " TOP_SECOND ", 4(30)\n" | |
2499 | "1:blt 7, 1b \n"); | |
2500 | ||
2501 | if (offset_p) | |
2502 | *offset_p = 32; | |
2503 | if (size_p) | |
2504 | *size_p = 14; | |
2505 | } | |
2506 | ||
2507 | /* Relocate previous emitted branch instruction. FROM is the address | |
2508 | of the branch instruction, TO is the goto target address, and SIZE | |
2509 | if the value we set by *SIZE_P before. Currently, it is either | |
2510 | 24 or 14 of branch and conditional-branch instruction. | |
2511 | Also used for ppc64. */ | |
2512 | ||
2513 | static void | |
2514 | ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) | |
2515 | { | |
2516 | long rel = to - from; | |
2517 | uint32_t insn; | |
2518 | int opcd; | |
2519 | ||
2520 | read_inferior_memory (from, (unsigned char *) &insn, 4); | |
2521 | opcd = (insn >> 26) & 0x3f; | |
2522 | ||
2523 | switch (size) | |
2524 | { | |
2525 | case 14: | |
2526 | if (opcd != 16 | |
2527 | || (rel >= (1 << 15) || rel < -(1 << 15))) | |
2528 | emit_error = 1; | |
2529 | insn = (insn & ~0xfffc) | (rel & 0xfffc); | |
2530 | break; | |
2531 | case 24: | |
2532 | if (opcd != 18 | |
2533 | || (rel >= (1 << 25) || rel < -(1 << 25))) | |
2534 | emit_error = 1; | |
2535 | insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc); | |
2536 | break; | |
2537 | default: | |
2538 | emit_error = 1; | |
2539 | } | |
2540 | ||
2541 | if (!emit_error) | |
4196ab2a | 2542 | target_write_memory (from, (unsigned char *) &insn, 4); |
14e2b6d9 MK |
2543 | } |
2544 | ||
2545 | /* Table of emit ops for 32-bit. */ | |
2546 | ||
2547 | static struct emit_ops ppc_emit_ops_impl = | |
2548 | { | |
2549 | ppc_emit_prologue, | |
2550 | ppc_emit_epilogue, | |
2551 | ppc_emit_add, | |
2552 | ppc_emit_sub, | |
2553 | ppc_emit_mul, | |
2554 | ppc_emit_lsh, | |
2555 | ppc_emit_rsh_signed, | |
2556 | ppc_emit_rsh_unsigned, | |
2557 | ppc_emit_ext, | |
2558 | ppc_emit_log_not, | |
2559 | ppc_emit_bit_and, | |
2560 | ppc_emit_bit_or, | |
2561 | ppc_emit_bit_xor, | |
2562 | ppc_emit_bit_not, | |
2563 | ppc_emit_equal, | |
2564 | ppc_emit_less_signed, | |
2565 | ppc_emit_less_unsigned, | |
2566 | ppc_emit_ref, | |
2567 | ppc_emit_if_goto, | |
2568 | ppc_emit_goto, | |
2569 | ppc_write_goto_address, | |
2570 | ppc_emit_const, | |
2571 | ppc_emit_call, | |
2572 | ppc_emit_reg, | |
2573 | ppc_emit_pop, | |
2574 | ppc_emit_stack_flush, | |
2575 | ppc_emit_zero_ext, | |
2576 | ppc_emit_swap, | |
2577 | ppc_emit_stack_adjust, | |
2578 | ppc_emit_int_call_1, | |
2579 | ppc_emit_void_call_2, | |
2580 | ppc_emit_eq_goto, | |
2581 | ppc_emit_ne_goto, | |
2582 | ppc_emit_lt_goto, | |
2583 | ppc_emit_le_goto, | |
2584 | ppc_emit_gt_goto, | |
2585 | ppc_emit_ge_goto | |
2586 | }; | |
2587 | ||
2588 | #ifdef __powerpc64__ | |
2589 | ||
2590 | /* | |
2591 | ||
2592 | Bytecode execution stack frame - 64-bit | |
2593 | ||
2594 | | LR save area (SP + 16) | |
2595 | | CR save area (SP + 8) | |
2596 | SP' -> +- Back chain (SP + 0) | |
2597 | | Save r31 for access saved arguments | |
2598 | | Save r30 for bytecode stack pointer | |
2599 | | Save r4 for incoming argument *value | |
2600 | | Save r3 for incoming argument regs | |
2601 | r30 -> +- Bytecode execution stack | |
2602 | | | |
2603 | | 64-byte (8 doublewords) at initial. | |
2604 | | Expand stack as needed. | |
2605 | | | |
2606 | +- | |
2607 | | Some padding for minimum stack frame. | |
2608 | | 112 for ELFv1. | |
2609 | SP +- Back-chain (SP') | |
2610 | ||
2611 | initial frame size | |
2612 | = 112 + (4 * 8) + 64 | |
2613 | = 208 | |
2614 | ||
2615 | r30 is the stack-pointer for bytecode machine. | |
2616 | It should point to next-empty, so we can use LDU for pop. | |
2617 | r3 is used for cache of TOP value. | |
2618 | It was the first argument, pointer to regs. | |
2619 | r4 is the second argument, pointer to the result. | |
2620 | We should set *result = TOP after leaving this function. | |
2621 | ||
2622 | Note: | |
2623 | * To restore stack at epilogue | |
2624 | => sp = r31 | |
2625 | * To check stack is big enough for bytecode execution. | |
2626 | => r30 - 8 > SP + 112 | |
2627 | * To return execution result. | |
2628 | => 0(r4) = TOP | |
2629 | ||
2630 | */ | |
2631 | ||
2632 | /* Emit prologue in inferior memory. See above comments. */ | |
2633 | ||
2634 | static void | |
2635 | ppc64v1_emit_prologue (void) | |
2636 | { | |
2637 | /* On ELFv1, function pointers really point to function descriptor, | |
2638 | so emit one here. We don't care about contents of words 1 and 2, | |
2639 | so let them just overlap out code. */ | |
2640 | uint64_t opd = current_insn_ptr + 8; | |
2641 | uint32_t buf[2]; | |
2642 | ||
2643 | /* Mind the strict aliasing rules. */ | |
2644 | memcpy (buf, &opd, sizeof buf); | |
2645 | emit_insns(buf, 2); | |
2646 | EMIT_ASM (/* Save return address. */ | |
2647 | "mflr 0 \n" | |
2648 | "std 0, 16(1) \n" | |
2649 | /* Save r30 and incoming arguments. */ | |
2650 | "std 31, -8(1) \n" | |
2651 | "std 30, -16(1) \n" | |
2652 | "std 4, -24(1) \n" | |
2653 | "std 3, -32(1) \n" | |
2654 | /* Point r31 to current r1 for access arguments. */ | |
2655 | "mr 31, 1 \n" | |
2656 | /* Adjust SP. 208 is the initial frame size. */ | |
2657 | "stdu 1, -208(1) \n" | |
2658 | /* Set r30 to pointing stack-top. */ | |
2659 | "addi 30, 1, 168 \n" | |
2660 | /* Initial r3/TOP to 0. */ | |
2661 | "li 3, 0 \n"); | |
2662 | } | |
2663 | ||
2664 | /* Emit prologue in inferior memory. See above comments. */ | |
2665 | ||
2666 | static void | |
2667 | ppc64v2_emit_prologue (void) | |
2668 | { | |
2669 | EMIT_ASM (/* Save return address. */ | |
2670 | "mflr 0 \n" | |
2671 | "std 0, 16(1) \n" | |
2672 | /* Save r30 and incoming arguments. */ | |
2673 | "std 31, -8(1) \n" | |
2674 | "std 30, -16(1) \n" | |
2675 | "std 4, -24(1) \n" | |
2676 | "std 3, -32(1) \n" | |
2677 | /* Point r31 to current r1 for access arguments. */ | |
2678 | "mr 31, 1 \n" | |
2679 | /* Adjust SP. 208 is the initial frame size. */ | |
2680 | "stdu 1, -208(1) \n" | |
2681 | /* Set r30 to pointing stack-top. */ | |
2682 | "addi 30, 1, 168 \n" | |
2683 | /* Initial r3/TOP to 0. */ | |
2684 | "li 3, 0 \n"); | |
2685 | } | |
2686 | ||
2687 | /* Emit epilogue in inferior memory. See above comments. */ | |
2688 | ||
2689 | static void | |
2690 | ppc64_emit_epilogue (void) | |
2691 | { | |
2692 | EMIT_ASM (/* Restore SP. */ | |
2693 | "ld 1, 0(1) \n" | |
2694 | /* *result = TOP */ | |
2695 | "ld 4, -24(1) \n" | |
2696 | "std 3, 0(4) \n" | |
2697 | /* Restore registers. */ | |
2698 | "ld 31, -8(1) \n" | |
2699 | "ld 30, -16(1) \n" | |
2700 | /* Restore LR. */ | |
2701 | "ld 0, 16(1) \n" | |
2702 | /* Return 0 for no-error. */ | |
2703 | "li 3, 0 \n" | |
2704 | "mtlr 0 \n" | |
2705 | "blr \n"); | |
2706 | } | |
2707 | ||
2708 | /* TOP = stack[--sp] + TOP */ | |
2709 | ||
2710 | static void | |
2711 | ppc64_emit_add (void) | |
2712 | { | |
2713 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2714 | "add 3, 4, 3 \n"); | |
2715 | } | |
2716 | ||
2717 | /* TOP = stack[--sp] - TOP */ | |
2718 | ||
2719 | static void | |
2720 | ppc64_emit_sub (void) | |
2721 | { | |
2722 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2723 | "sub 3, 4, 3 \n"); | |
2724 | } | |
2725 | ||
2726 | /* TOP = stack[--sp] * TOP */ | |
2727 | ||
2728 | static void | |
2729 | ppc64_emit_mul (void) | |
2730 | { | |
2731 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2732 | "mulld 3, 4, 3 \n"); | |
2733 | } | |
2734 | ||
2735 | /* TOP = stack[--sp] << TOP */ | |
2736 | ||
2737 | static void | |
2738 | ppc64_emit_lsh (void) | |
2739 | { | |
2740 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2741 | "sld 3, 4, 3 \n"); | |
2742 | } | |
2743 | ||
2744 | /* Top = stack[--sp] >> TOP | |
2745 | (Arithmetic shift right) */ | |
2746 | ||
2747 | static void | |
2748 | ppc64_emit_rsh_signed (void) | |
2749 | { | |
2750 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2751 | "srad 3, 4, 3 \n"); | |
2752 | } | |
2753 | ||
2754 | /* Top = stack[--sp] >> TOP | |
2755 | (Logical shift right) */ | |
2756 | ||
2757 | static void | |
2758 | ppc64_emit_rsh_unsigned (void) | |
2759 | { | |
2760 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2761 | "srd 3, 4, 3 \n"); | |
2762 | } | |
2763 | ||
2764 | /* Emit code for signed-extension specified by ARG. */ | |
2765 | ||
2766 | static void | |
2767 | ppc64_emit_ext (int arg) | |
2768 | { | |
2769 | switch (arg) | |
2770 | { | |
2771 | case 8: | |
2772 | EMIT_ASM ("extsb 3, 3"); | |
2773 | break; | |
2774 | case 16: | |
2775 | EMIT_ASM ("extsh 3, 3"); | |
2776 | break; | |
2777 | case 32: | |
2778 | EMIT_ASM ("extsw 3, 3"); | |
2779 | break; | |
2780 | default: | |
2781 | emit_error = 1; | |
2782 | } | |
2783 | } | |
2784 | ||
2785 | /* Emit code for zero-extension specified by ARG. */ | |
2786 | ||
2787 | static void | |
2788 | ppc64_emit_zero_ext (int arg) | |
2789 | { | |
2790 | switch (arg) | |
2791 | { | |
2792 | case 8: | |
2793 | EMIT_ASM ("rldicl 3,3,0,56"); | |
2794 | break; | |
2795 | case 16: | |
2796 | EMIT_ASM ("rldicl 3,3,0,48"); | |
2797 | break; | |
2798 | case 32: | |
2799 | EMIT_ASM ("rldicl 3,3,0,32"); | |
2800 | break; | |
2801 | default: | |
2802 | emit_error = 1; | |
2803 | } | |
2804 | } | |
2805 | ||
2806 | /* TOP = !TOP | |
2807 | i.e., TOP = (TOP == 0) ? 1 : 0; */ | |
2808 | ||
2809 | static void | |
2810 | ppc64_emit_log_not (void) | |
2811 | { | |
2812 | EMIT_ASM ("cntlzd 3, 3 \n" | |
2813 | "srdi 3, 3, 6 \n"); | |
2814 | } | |
2815 | ||
2816 | /* TOP = stack[--sp] & TOP */ | |
2817 | ||
2818 | static void | |
2819 | ppc64_emit_bit_and (void) | |
2820 | { | |
2821 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2822 | "and 3, 4, 3 \n"); | |
2823 | } | |
2824 | ||
2825 | /* TOP = stack[--sp] | TOP */ | |
2826 | ||
2827 | static void | |
2828 | ppc64_emit_bit_or (void) | |
2829 | { | |
2830 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2831 | "or 3, 4, 3 \n"); | |
2832 | } | |
2833 | ||
2834 | /* TOP = stack[--sp] ^ TOP */ | |
2835 | ||
2836 | static void | |
2837 | ppc64_emit_bit_xor (void) | |
2838 | { | |
2839 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2840 | "xor 3, 4, 3 \n"); | |
2841 | } | |
2842 | ||
2843 | /* TOP = ~TOP | |
2844 | i.e., TOP = ~(TOP | TOP) */ | |
2845 | ||
2846 | static void | |
2847 | ppc64_emit_bit_not (void) | |
2848 | { | |
2849 | EMIT_ASM ("nor 3, 3, 3 \n"); | |
2850 | } | |
2851 | ||
2852 | /* TOP = stack[--sp] == TOP */ | |
2853 | ||
2854 | static void | |
2855 | ppc64_emit_equal (void) | |
2856 | { | |
2857 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2858 | "xor 3, 3, 4 \n" | |
2859 | "cntlzd 3, 3 \n" | |
2860 | "srdi 3, 3, 6 \n"); | |
2861 | } | |
2862 | ||
2863 | /* TOP = stack[--sp] < TOP | |
2864 | (Signed comparison) */ | |
2865 | ||
2866 | static void | |
2867 | ppc64_emit_less_signed (void) | |
2868 | { | |
2869 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2870 | "cmpd 7, 4, 3 \n" | |
2871 | "mfcr 3 \n" | |
2872 | "rlwinm 3, 3, 29, 31, 31 \n"); | |
2873 | } | |
2874 | ||
2875 | /* TOP = stack[--sp] < TOP | |
2876 | (Unsigned comparison) */ | |
2877 | ||
2878 | static void | |
2879 | ppc64_emit_less_unsigned (void) | |
2880 | { | |
2881 | EMIT_ASM ("ldu 4, 8(30) \n" | |
2882 | "cmpld 7, 4, 3 \n" | |
2883 | "mfcr 3 \n" | |
2884 | "rlwinm 3, 3, 29, 31, 31 \n"); | |
2885 | } | |
2886 | ||
2887 | /* Access the memory address in TOP in size of SIZE. | |
2888 | Zero-extend the read value. */ | |
2889 | ||
2890 | static void | |
2891 | ppc64_emit_ref (int size) | |
2892 | { | |
2893 | switch (size) | |
2894 | { | |
2895 | case 1: | |
2896 | EMIT_ASM ("lbz 3, 0(3)"); | |
2897 | break; | |
2898 | case 2: | |
2899 | EMIT_ASM ("lhz 3, 0(3)"); | |
2900 | break; | |
2901 | case 4: | |
2902 | EMIT_ASM ("lwz 3, 0(3)"); | |
2903 | break; | |
2904 | case 8: | |
2905 | EMIT_ASM ("ld 3, 0(3)"); | |
2906 | break; | |
2907 | } | |
2908 | } | |
2909 | ||
2910 | /* TOP = NUM */ | |
2911 | ||
2912 | static void | |
2913 | ppc64_emit_const (LONGEST num) | |
2914 | { | |
2915 | uint32_t buf[5]; | |
2916 | uint32_t *p = buf; | |
2917 | ||
2918 | p += gen_limm (p, 3, num, 1); | |
2919 | ||
2920 | emit_insns (buf, p - buf); | |
2921 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2922 | } | |
2923 | ||
2924 | /* Set TOP to the value of register REG by calling get_raw_reg function | |
2925 | with two argument, collected buffer and register number. */ | |
2926 | ||
2927 | static void | |
2928 | ppc64v1_emit_reg (int reg) | |
2929 | { | |
2930 | uint32_t buf[15]; | |
2931 | uint32_t *p = buf; | |
2932 | ||
2933 | /* fctx->regs is passed in r3 and then saved in 176(1). */ | |
2934 | p += GEN_LD (p, 3, 31, -32); | |
2935 | p += GEN_LI (p, 4, reg); | |
2936 | p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ | |
2937 | p += gen_call (p, get_raw_reg_func_addr (), 1, 1); | |
2938 | p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ | |
2939 | ||
2940 | emit_insns (buf, p - buf); | |
2941 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2942 | } | |
2943 | ||
2944 | /* Likewise, for ELFv2. */ | |
2945 | ||
2946 | static void | |
2947 | ppc64v2_emit_reg (int reg) | |
2948 | { | |
2949 | uint32_t buf[12]; | |
2950 | uint32_t *p = buf; | |
2951 | ||
2952 | /* fctx->regs is passed in r3 and then saved in 176(1). */ | |
2953 | p += GEN_LD (p, 3, 31, -32); | |
2954 | p += GEN_LI (p, 4, reg); | |
2955 | p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ | |
2956 | p += gen_call (p, get_raw_reg_func_addr (), 1, 0); | |
2957 | p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ | |
2958 | ||
2959 | emit_insns (buf, p - buf); | |
2960 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
2961 | } | |
2962 | ||
2963 | /* TOP = stack[--sp] */ | |
2964 | ||
2965 | static void | |
2966 | ppc64_emit_pop (void) | |
2967 | { | |
2968 | EMIT_ASM ("ldu 3, 8(30)"); | |
2969 | } | |
2970 | ||
2971 | /* stack[sp++] = TOP | |
2972 | ||
2973 | Because we may use up bytecode stack, expand 8 doublewords more | |
2974 | if needed. */ | |
2975 | ||
2976 | static void | |
2977 | ppc64_emit_stack_flush (void) | |
2978 | { | |
2979 | /* Make sure bytecode stack is big enough before push. | |
2980 | Otherwise, expand 64-byte more. */ | |
2981 | ||
2982 | EMIT_ASM (" std 3, 0(30) \n" | |
2983 | " addi 4, 30, -(112 + 8) \n" | |
2984 | " cmpd 7, 4, 1 \n" | |
2985 | " bgt 7, 1f \n" | |
2986 | " stdu 31, -64(1) \n" | |
2987 | "1:addi 30, 30, -8 \n"); | |
2988 | } | |
2989 | ||
2990 | /* Swap TOP and stack[sp-1] */ | |
2991 | ||
2992 | static void | |
2993 | ppc64_emit_swap (void) | |
2994 | { | |
2995 | EMIT_ASM ("ld 4, 8(30) \n" | |
2996 | "std 3, 8(30) \n" | |
2997 | "mr 3, 4 \n"); | |
2998 | } | |
2999 | ||
3000 | /* Call function FN - ELFv1. */ | |
3001 | ||
3002 | static void | |
3003 | ppc64v1_emit_call (CORE_ADDR fn) | |
3004 | { | |
3005 | uint32_t buf[13]; | |
3006 | uint32_t *p = buf; | |
3007 | ||
3008 | p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ | |
3009 | p += gen_call (p, fn, 1, 1); | |
3010 | p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ | |
3011 | ||
3012 | emit_insns (buf, p - buf); | |
3013 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
3014 | } | |
3015 | ||
3016 | /* Call function FN - ELFv2. */ | |
3017 | ||
3018 | static void | |
3019 | ppc64v2_emit_call (CORE_ADDR fn) | |
3020 | { | |
3021 | uint32_t buf[10]; | |
3022 | uint32_t *p = buf; | |
3023 | ||
3024 | p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ | |
3025 | p += gen_call (p, fn, 1, 0); | |
3026 | p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ | |
3027 | ||
3028 | emit_insns (buf, p - buf); | |
3029 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
3030 | } | |
3031 | ||
3032 | /* FN's prototype is `LONGEST(*fn)(int)'. | |
3033 | TOP = fn (arg1) | |
3034 | */ | |
3035 | ||
3036 | static void | |
3037 | ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1) | |
3038 | { | |
3039 | uint32_t buf[13]; | |
3040 | uint32_t *p = buf; | |
3041 | ||
3042 | /* Setup argument. arg1 is a 16-bit value. */ | |
3043 | p += gen_limm (p, 3, arg1, 1); | |
3044 | p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ | |
3045 | p += gen_call (p, fn, 1, 1); | |
3046 | p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ | |
3047 | ||
3048 | emit_insns (buf, p - buf); | |
3049 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
3050 | } | |
3051 | ||
3052 | /* Likewise for ELFv2. */ | |
3053 | ||
3054 | static void | |
3055 | ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1) | |
3056 | { | |
3057 | uint32_t buf[10]; | |
3058 | uint32_t *p = buf; | |
3059 | ||
3060 | /* Setup argument. arg1 is a 16-bit value. */ | |
3061 | p += gen_limm (p, 3, arg1, 1); | |
3062 | p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ | |
3063 | p += gen_call (p, fn, 1, 0); | |
3064 | p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ | |
3065 | ||
3066 | emit_insns (buf, p - buf); | |
3067 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
3068 | } | |
3069 | ||
3070 | /* FN's prototype is `void(*fn)(int,LONGEST)'. | |
3071 | fn (arg1, TOP) | |
3072 | ||
3073 | TOP should be preserved/restored before/after the call. */ | |
3074 | ||
3075 | static void | |
3076 | ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1) | |
3077 | { | |
3078 | uint32_t buf[17]; | |
3079 | uint32_t *p = buf; | |
3080 | ||
3081 | /* Save TOP. 0(30) is next-empty. */ | |
3082 | p += GEN_STD (p, 3, 30, 0); | |
3083 | ||
3084 | /* Setup argument. arg1 is a 16-bit value. */ | |
3085 | p += GEN_MR (p, 4, 3); /* mr r4, r3 */ | |
3086 | p += gen_limm (p, 3, arg1, 1); | |
3087 | p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ | |
3088 | p += gen_call (p, fn, 1, 1); | |
3089 | p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ | |
3090 | ||
3091 | /* Restore TOP */ | |
3092 | p += GEN_LD (p, 3, 30, 0); | |
3093 | ||
3094 | emit_insns (buf, p - buf); | |
3095 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
3096 | } | |
3097 | ||
3098 | /* Likewise for ELFv2. */ | |
3099 | ||
3100 | static void | |
3101 | ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1) | |
3102 | { | |
3103 | uint32_t buf[14]; | |
3104 | uint32_t *p = buf; | |
3105 | ||
3106 | /* Save TOP. 0(30) is next-empty. */ | |
3107 | p += GEN_STD (p, 3, 30, 0); | |
3108 | ||
3109 | /* Setup argument. arg1 is a 16-bit value. */ | |
3110 | p += GEN_MR (p, 4, 3); /* mr r4, r3 */ | |
3111 | p += gen_limm (p, 3, arg1, 1); | |
3112 | p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ | |
3113 | p += gen_call (p, fn, 1, 0); | |
3114 | p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ | |
3115 | ||
3116 | /* Restore TOP */ | |
3117 | p += GEN_LD (p, 3, 30, 0); | |
3118 | ||
3119 | emit_insns (buf, p - buf); | |
3120 | gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); | |
3121 | } | |
3122 | ||
3123 | /* If TOP is true, goto somewhere. Otherwise, just fall-through. */ | |
3124 | ||
3125 | static void | |
3126 | ppc64_emit_if_goto (int *offset_p, int *size_p) | |
3127 | { | |
3128 | EMIT_ASM ("cmpdi 7, 3, 0 \n" | |
3129 | "ldu 3, 8(30) \n" | |
3130 | "1:bne 7, 1b \n"); | |
3131 | ||
3132 | if (offset_p) | |
3133 | *offset_p = 8; | |
3134 | if (size_p) | |
3135 | *size_p = 14; | |
3136 | } | |
3137 | ||
3138 | /* Goto if stack[--sp] == TOP */ | |
3139 | ||
3140 | static void | |
3141 | ppc64_emit_eq_goto (int *offset_p, int *size_p) | |
3142 | { | |
3143 | EMIT_ASM ("ldu 4, 8(30) \n" | |
3144 | "cmpd 7, 4, 3 \n" | |
3145 | "ldu 3, 8(30) \n" | |
3146 | "1:beq 7, 1b \n"); | |
3147 | ||
3148 | if (offset_p) | |
3149 | *offset_p = 12; | |
3150 | if (size_p) | |
3151 | *size_p = 14; | |
3152 | } | |
3153 | ||
3154 | /* Goto if stack[--sp] != TOP */ | |
3155 | ||
3156 | static void | |
3157 | ppc64_emit_ne_goto (int *offset_p, int *size_p) | |
3158 | { | |
3159 | EMIT_ASM ("ldu 4, 8(30) \n" | |
3160 | "cmpd 7, 4, 3 \n" | |
3161 | "ldu 3, 8(30) \n" | |
3162 | "1:bne 7, 1b \n"); | |
3163 | ||
3164 | if (offset_p) | |
3165 | *offset_p = 12; | |
3166 | if (size_p) | |
3167 | *size_p = 14; | |
3168 | } | |
3169 | ||
3170 | /* Goto if stack[--sp] < TOP */ | |
3171 | ||
3172 | static void | |
3173 | ppc64_emit_lt_goto (int *offset_p, int *size_p) | |
3174 | { | |
3175 | EMIT_ASM ("ldu 4, 8(30) \n" | |
3176 | "cmpd 7, 4, 3 \n" | |
3177 | "ldu 3, 8(30) \n" | |
3178 | "1:blt 7, 1b \n"); | |
3179 | ||
3180 | if (offset_p) | |
3181 | *offset_p = 12; | |
3182 | if (size_p) | |
3183 | *size_p = 14; | |
3184 | } | |
3185 | ||
3186 | /* Goto if stack[--sp] <= TOP */ | |
3187 | ||
3188 | static void | |
3189 | ppc64_emit_le_goto (int *offset_p, int *size_p) | |
3190 | { | |
3191 | EMIT_ASM ("ldu 4, 8(30) \n" | |
3192 | "cmpd 7, 4, 3 \n" | |
3193 | "ldu 3, 8(30) \n" | |
3194 | "1:ble 7, 1b \n"); | |
3195 | ||
3196 | if (offset_p) | |
3197 | *offset_p = 12; | |
3198 | if (size_p) | |
3199 | *size_p = 14; | |
3200 | } | |
3201 | ||
3202 | /* Goto if stack[--sp] > TOP */ | |
3203 | ||
3204 | static void | |
3205 | ppc64_emit_gt_goto (int *offset_p, int *size_p) | |
3206 | { | |
3207 | EMIT_ASM ("ldu 4, 8(30) \n" | |
3208 | "cmpd 7, 4, 3 \n" | |
3209 | "ldu 3, 8(30) \n" | |
3210 | "1:bgt 7, 1b \n"); | |
3211 | ||
3212 | if (offset_p) | |
3213 | *offset_p = 12; | |
3214 | if (size_p) | |
3215 | *size_p = 14; | |
3216 | } | |
3217 | ||
3218 | /* Goto if stack[--sp] >= TOP */ | |
3219 | ||
3220 | static void | |
3221 | ppc64_emit_ge_goto (int *offset_p, int *size_p) | |
3222 | { | |
3223 | EMIT_ASM ("ldu 4, 8(30) \n" | |
3224 | "cmpd 7, 4, 3 \n" | |
3225 | "ldu 3, 8(30) \n" | |
3226 | "1:bge 7, 1b \n"); | |
3227 | ||
3228 | if (offset_p) | |
3229 | *offset_p = 12; | |
3230 | if (size_p) | |
3231 | *size_p = 14; | |
3232 | } | |
3233 | ||
3234 | /* Table of emit ops for 64-bit ELFv1. */ | |
3235 | ||
3236 | static struct emit_ops ppc64v1_emit_ops_impl = | |
3237 | { | |
3238 | ppc64v1_emit_prologue, | |
3239 | ppc64_emit_epilogue, | |
3240 | ppc64_emit_add, | |
3241 | ppc64_emit_sub, | |
3242 | ppc64_emit_mul, | |
3243 | ppc64_emit_lsh, | |
3244 | ppc64_emit_rsh_signed, | |
3245 | ppc64_emit_rsh_unsigned, | |
3246 | ppc64_emit_ext, | |
3247 | ppc64_emit_log_not, | |
3248 | ppc64_emit_bit_and, | |
3249 | ppc64_emit_bit_or, | |
3250 | ppc64_emit_bit_xor, | |
3251 | ppc64_emit_bit_not, | |
3252 | ppc64_emit_equal, | |
3253 | ppc64_emit_less_signed, | |
3254 | ppc64_emit_less_unsigned, | |
3255 | ppc64_emit_ref, | |
3256 | ppc64_emit_if_goto, | |
3257 | ppc_emit_goto, | |
3258 | ppc_write_goto_address, | |
3259 | ppc64_emit_const, | |
3260 | ppc64v1_emit_call, | |
3261 | ppc64v1_emit_reg, | |
3262 | ppc64_emit_pop, | |
3263 | ppc64_emit_stack_flush, | |
3264 | ppc64_emit_zero_ext, | |
3265 | ppc64_emit_swap, | |
3266 | ppc_emit_stack_adjust, | |
3267 | ppc64v1_emit_int_call_1, | |
3268 | ppc64v1_emit_void_call_2, | |
3269 | ppc64_emit_eq_goto, | |
3270 | ppc64_emit_ne_goto, | |
3271 | ppc64_emit_lt_goto, | |
3272 | ppc64_emit_le_goto, | |
3273 | ppc64_emit_gt_goto, | |
3274 | ppc64_emit_ge_goto | |
3275 | }; | |
3276 | ||
3277 | /* Table of emit ops for 64-bit ELFv2. */ | |
3278 | ||
3279 | static struct emit_ops ppc64v2_emit_ops_impl = | |
3280 | { | |
3281 | ppc64v2_emit_prologue, | |
3282 | ppc64_emit_epilogue, | |
3283 | ppc64_emit_add, | |
3284 | ppc64_emit_sub, | |
3285 | ppc64_emit_mul, | |
3286 | ppc64_emit_lsh, | |
3287 | ppc64_emit_rsh_signed, | |
3288 | ppc64_emit_rsh_unsigned, | |
3289 | ppc64_emit_ext, | |
3290 | ppc64_emit_log_not, | |
3291 | ppc64_emit_bit_and, | |
3292 | ppc64_emit_bit_or, | |
3293 | ppc64_emit_bit_xor, | |
3294 | ppc64_emit_bit_not, | |
3295 | ppc64_emit_equal, | |
3296 | ppc64_emit_less_signed, | |
3297 | ppc64_emit_less_unsigned, | |
3298 | ppc64_emit_ref, | |
3299 | ppc64_emit_if_goto, | |
3300 | ppc_emit_goto, | |
3301 | ppc_write_goto_address, | |
3302 | ppc64_emit_const, | |
3303 | ppc64v2_emit_call, | |
3304 | ppc64v2_emit_reg, | |
3305 | ppc64_emit_pop, | |
3306 | ppc64_emit_stack_flush, | |
3307 | ppc64_emit_zero_ext, | |
3308 | ppc64_emit_swap, | |
3309 | ppc_emit_stack_adjust, | |
3310 | ppc64v2_emit_int_call_1, | |
3311 | ppc64v2_emit_void_call_2, | |
3312 | ppc64_emit_eq_goto, | |
3313 | ppc64_emit_ne_goto, | |
3314 | ppc64_emit_lt_goto, | |
3315 | ppc64_emit_le_goto, | |
3316 | ppc64_emit_gt_goto, | |
3317 | ppc64_emit_ge_goto | |
3318 | }; | |
3319 | ||
3320 | #endif | |
3321 | ||
3322 | /* Implementation of linux_target_ops method "emit_ops". */ | |
3323 | ||
3324 | static struct emit_ops * | |
3325 | ppc_emit_ops (void) | |
3326 | { | |
3327 | #ifdef __powerpc64__ | |
3328 | struct regcache *regcache = get_thread_regcache (current_thread, 0); | |
3329 | ||
3330 | if (register_size (regcache->tdesc, 0) == 8) | |
3331 | { | |
3332 | if (is_elfv2_inferior ()) | |
3333 | return &ppc64v2_emit_ops_impl; | |
3334 | else | |
3335 | return &ppc64v1_emit_ops_impl; | |
3336 | } | |
3337 | #endif | |
3338 | return &ppc_emit_ops_impl; | |
3339 | } | |
3340 | ||
a2174ba4 MK |
3341 | /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */ |
3342 | ||
3343 | static int | |
3344 | ppc_get_ipa_tdesc_idx (void) | |
3345 | { | |
3346 | struct regcache *regcache = get_thread_regcache (current_thread, 0); | |
3347 | const struct target_desc *tdesc = regcache->tdesc; | |
3348 | ||
3349 | #ifdef __powerpc64__ | |
3350 | if (tdesc == tdesc_powerpc_64l) | |
3351 | return PPC_TDESC_BASE; | |
3352 | if (tdesc == tdesc_powerpc_altivec64l) | |
3353 | return PPC_TDESC_ALTIVEC; | |
a2174ba4 MK |
3354 | if (tdesc == tdesc_powerpc_vsx64l) |
3355 | return PPC_TDESC_VSX; | |
3356 | if (tdesc == tdesc_powerpc_isa205_64l) | |
3357 | return PPC_TDESC_ISA205; | |
3358 | if (tdesc == tdesc_powerpc_isa205_altivec64l) | |
3359 | return PPC_TDESC_ISA205_ALTIVEC; | |
3360 | if (tdesc == tdesc_powerpc_isa205_vsx64l) | |
3361 | return PPC_TDESC_ISA205_VSX; | |
7ca18ed6 EBM |
3362 | if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l) |
3363 | return PPC_TDESC_ISA205_PPR_DSCR_VSX; | |
f2cf6173 EBM |
3364 | if (tdesc == tdesc_powerpc_isa207_vsx64l) |
3365 | return PPC_TDESC_ISA207_VSX; | |
8d619c01 EBM |
3366 | if (tdesc == tdesc_powerpc_isa207_htm_vsx64l) |
3367 | return PPC_TDESC_ISA207_HTM_VSX; | |
a2174ba4 MK |
3368 | #endif |
3369 | ||
3370 | if (tdesc == tdesc_powerpc_32l) | |
3371 | return PPC_TDESC_BASE; | |
3372 | if (tdesc == tdesc_powerpc_altivec32l) | |
3373 | return PPC_TDESC_ALTIVEC; | |
a2174ba4 MK |
3374 | if (tdesc == tdesc_powerpc_vsx32l) |
3375 | return PPC_TDESC_VSX; | |
3376 | if (tdesc == tdesc_powerpc_isa205_32l) | |
3377 | return PPC_TDESC_ISA205; | |
3378 | if (tdesc == tdesc_powerpc_isa205_altivec32l) | |
3379 | return PPC_TDESC_ISA205_ALTIVEC; | |
3380 | if (tdesc == tdesc_powerpc_isa205_vsx32l) | |
3381 | return PPC_TDESC_ISA205_VSX; | |
7ca18ed6 EBM |
3382 | if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l) |
3383 | return PPC_TDESC_ISA205_PPR_DSCR_VSX; | |
f2cf6173 EBM |
3384 | if (tdesc == tdesc_powerpc_isa207_vsx32l) |
3385 | return PPC_TDESC_ISA207_VSX; | |
8d619c01 EBM |
3386 | if (tdesc == tdesc_powerpc_isa207_htm_vsx32l) |
3387 | return PPC_TDESC_ISA207_HTM_VSX; | |
a2174ba4 MK |
3388 | if (tdesc == tdesc_powerpc_e500l) |
3389 | return PPC_TDESC_E500; | |
3390 | ||
3391 | return 0; | |
3392 | } | |
3393 | ||
2ec06d2e | 3394 | struct linux_target_ops the_low_target = { |
0d62e5e8 DJ |
3395 | ppc_get_pc, |
3396 | ppc_set_pc, | |
dd373349 AT |
3397 | NULL, /* breakpoint_kind_from_pc */ |
3398 | ppc_sw_breakpoint_from_kind, | |
0d62e5e8 DJ |
3399 | NULL, |
3400 | 0, | |
3401 | ppc_breakpoint_at, | |
657f9cde WW |
3402 | ppc_supports_z_point_type, |
3403 | ppc_insert_point, | |
3404 | ppc_remove_point, | |
5b0a002e UW |
3405 | NULL, |
3406 | NULL, | |
3407 | ppc_collect_ptrace_register, | |
3408 | ppc_supply_ptrace_register, | |
7d00775e AT |
3409 | NULL, /* siginfo_fixup */ |
3410 | NULL, /* new_process */ | |
04ec7890 | 3411 | NULL, /* delete_process */ |
7d00775e | 3412 | NULL, /* new_thread */ |
466eecee | 3413 | NULL, /* delete_thread */ |
7d00775e AT |
3414 | NULL, /* new_fork */ |
3415 | NULL, /* prepare_to_resume */ | |
3416 | NULL, /* process_qsupported */ | |
b04fd3be | 3417 | ppc_supports_tracepoints, |
a2174ba4 MK |
3418 | ppc_get_thread_area, |
3419 | ppc_install_fast_tracepoint_jump_pad, | |
14e2b6d9 | 3420 | ppc_emit_ops, |
a2174ba4 | 3421 | ppc_get_min_fast_tracepoint_insn_len, |
7d00775e AT |
3422 | NULL, /* supports_range_stepping */ |
3423 | NULL, /* breakpoint_kind_from_current_state */ | |
3424 | ppc_supports_hardware_single_step, | |
a2174ba4 MK |
3425 | NULL, /* get_syscall_trapinfo */ |
3426 | ppc_get_ipa_tdesc_idx, | |
2ec06d2e | 3427 | }; |
3aee8918 | 3428 | |
ef0478f6 TBA |
3429 | /* The linux target ops object. */ |
3430 | ||
3431 | linux_process_target *the_linux_target = &the_ppc_target; | |
3432 | ||
3aee8918 PA |
3433 | void |
3434 | initialize_low_arch (void) | |
3435 | { | |
3436 | /* Initialize the Linux target descriptions. */ | |
3437 | ||
3438 | init_registers_powerpc_32l (); | |
3439 | init_registers_powerpc_altivec32l (); | |
3aee8918 PA |
3440 | init_registers_powerpc_vsx32l (); |
3441 | init_registers_powerpc_isa205_32l (); | |
3442 | init_registers_powerpc_isa205_altivec32l (); | |
3443 | init_registers_powerpc_isa205_vsx32l (); | |
7ca18ed6 | 3444 | init_registers_powerpc_isa205_ppr_dscr_vsx32l (); |
f2cf6173 | 3445 | init_registers_powerpc_isa207_vsx32l (); |
8d619c01 | 3446 | init_registers_powerpc_isa207_htm_vsx32l (); |
3aee8918 | 3447 | init_registers_powerpc_e500l (); |
a2174ba4 | 3448 | #if __powerpc64__ |
3aee8918 PA |
3449 | init_registers_powerpc_64l (); |
3450 | init_registers_powerpc_altivec64l (); | |
3aee8918 PA |
3451 | init_registers_powerpc_vsx64l (); |
3452 | init_registers_powerpc_isa205_64l (); | |
3453 | init_registers_powerpc_isa205_altivec64l (); | |
3454 | init_registers_powerpc_isa205_vsx64l (); | |
7ca18ed6 | 3455 | init_registers_powerpc_isa205_ppr_dscr_vsx64l (); |
f2cf6173 | 3456 | init_registers_powerpc_isa207_vsx64l (); |
8d619c01 | 3457 | init_registers_powerpc_isa207_htm_vsx64l (); |
a2174ba4 | 3458 | #endif |
3aee8918 PA |
3459 | |
3460 | initialize_regsets_info (&ppc_regsets_info); | |
3461 | } |