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bf84f706 MR |
1 | /* GNU/Linux/RISC-V specific low level interface, for the remote server |
2 | for GDB. | |
3 | Copyright (C) 2020 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "server.h" | |
21 | ||
22 | #include "linux-low.h" | |
23 | #include "tdesc.h" | |
24 | #include "elf/common.h" | |
25 | #include "nat/riscv-linux-tdesc.h" | |
26 | #include "opcode/riscv.h" | |
27 | ||
28 | /* Work around glibc header breakage causing ELF_NFPREG not to be usable. */ | |
29 | #ifndef NFPREG | |
30 | # define NFPREG 33 | |
31 | #endif | |
32 | ||
ef0478f6 TBA |
33 | /* Linux target op definitions for the RISC-V architecture. */ |
34 | ||
35 | class riscv_target : public linux_process_target | |
36 | { | |
37 | public: | |
38 | ||
aa8d21c9 TBA |
39 | const regs_info *get_regs_info () override; |
40 | ||
797bcff5 TBA |
41 | protected: |
42 | ||
43 | void low_arch_setup () override; | |
daca57a7 TBA |
44 | |
45 | bool low_cannot_fetch_register (int regno) override; | |
46 | ||
47 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
48 | |
49 | bool low_fetch_register (regcache *regcache, int regno) override; | |
ef0478f6 TBA |
50 | }; |
51 | ||
52 | /* The singleton target ops object. */ | |
53 | ||
54 | static riscv_target the_riscv_target; | |
55 | ||
daca57a7 TBA |
56 | bool |
57 | riscv_target::low_cannot_fetch_register (int regno) | |
58 | { | |
59 | gdb_assert_not_reached ("linux target op low_cannot_fetch_register " | |
60 | "is not implemented by the target"); | |
61 | } | |
62 | ||
63 | bool | |
64 | riscv_target::low_cannot_store_register (int regno) | |
65 | { | |
66 | gdb_assert_not_reached ("linux target op low_cannot_store_register " | |
67 | "is not implemented by the target"); | |
68 | } | |
69 | ||
797bcff5 | 70 | /* Implementation of linux target ops method "low_arch_setup". */ |
bf84f706 | 71 | |
797bcff5 TBA |
72 | void |
73 | riscv_target::low_arch_setup () | |
bf84f706 MR |
74 | { |
75 | static const char *expedite_regs[] = { "sp", "pc", NULL }; | |
76 | ||
77 | const riscv_gdbarch_features features | |
78 | = riscv_linux_read_features (lwpid_of (current_thread)); | |
79 | target_desc *tdesc = riscv_create_target_description (features); | |
80 | ||
81 | if (!tdesc->expedite_regs) | |
82 | init_target_desc (tdesc, expedite_regs); | |
83 | current_process ()->tdesc = tdesc; | |
84 | } | |
85 | ||
86 | /* Collect GPRs from REGCACHE into BUF. */ | |
87 | ||
88 | static void | |
89 | riscv_fill_gregset (struct regcache *regcache, void *buf) | |
90 | { | |
91 | const struct target_desc *tdesc = regcache->tdesc; | |
92 | elf_gregset_t *regset = (elf_gregset_t *) buf; | |
93 | int regno = find_regno (tdesc, "zero"); | |
94 | int i; | |
95 | ||
96 | collect_register_by_name (regcache, "pc", *regset); | |
97 | for (i = 1; i < ARRAY_SIZE (*regset); i++) | |
98 | collect_register (regcache, regno + i, *regset + i); | |
99 | } | |
100 | ||
101 | /* Supply GPRs from BUF into REGCACHE. */ | |
102 | ||
103 | static void | |
104 | riscv_store_gregset (struct regcache *regcache, const void *buf) | |
105 | { | |
106 | const elf_gregset_t *regset = (const elf_gregset_t *) buf; | |
107 | const struct target_desc *tdesc = regcache->tdesc; | |
108 | int regno = find_regno (tdesc, "zero"); | |
109 | int i; | |
110 | ||
111 | supply_register_by_name (regcache, "pc", *regset); | |
112 | supply_register_zeroed (regcache, regno); | |
113 | for (i = 1; i < ARRAY_SIZE (*regset); i++) | |
114 | supply_register (regcache, regno + i, *regset + i); | |
115 | } | |
116 | ||
117 | /* Collect FPRs from REGCACHE into BUF. */ | |
118 | ||
119 | static void | |
120 | riscv_fill_fpregset (struct regcache *regcache, void *buf) | |
121 | { | |
122 | const struct target_desc *tdesc = regcache->tdesc; | |
123 | int regno = find_regno (tdesc, "ft0"); | |
124 | int flen = register_size (regcache->tdesc, regno); | |
125 | gdb_byte *regbuf = (gdb_byte *) buf; | |
126 | int i; | |
127 | ||
128 | for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) | |
129 | collect_register (regcache, regno + i, regbuf); | |
130 | collect_register_by_name (regcache, "fcsr", regbuf); | |
131 | } | |
132 | ||
133 | /* Supply FPRs from BUF into REGCACHE. */ | |
134 | ||
135 | static void | |
136 | riscv_store_fpregset (struct regcache *regcache, const void *buf) | |
137 | { | |
138 | const struct target_desc *tdesc = regcache->tdesc; | |
139 | int regno = find_regno (tdesc, "ft0"); | |
140 | int flen = register_size (regcache->tdesc, regno); | |
141 | const gdb_byte *regbuf = (const gdb_byte *) buf; | |
142 | int i; | |
143 | ||
144 | for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) | |
145 | supply_register (regcache, regno + i, regbuf); | |
146 | supply_register_by_name (regcache, "fcsr", regbuf); | |
147 | } | |
148 | ||
149 | /* RISC-V/Linux regsets. FPRs are optional and come in different sizes, | |
150 | so define multiple regsets for them marking them all as OPTIONAL_REGS | |
151 | rather than FP_REGS, so that "regsets_fetch_inferior_registers" picks | |
152 | the right one according to size. */ | |
153 | static struct regset_info riscv_regsets[] = { | |
154 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, | |
155 | sizeof (elf_gregset_t), GENERAL_REGS, | |
156 | riscv_fill_gregset, riscv_store_gregset }, | |
157 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, | |
158 | sizeof (struct __riscv_mc_q_ext_state), OPTIONAL_REGS, | |
159 | riscv_fill_fpregset, riscv_store_fpregset }, | |
160 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, | |
161 | sizeof (struct __riscv_mc_d_ext_state), OPTIONAL_REGS, | |
162 | riscv_fill_fpregset, riscv_store_fpregset }, | |
163 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, | |
164 | sizeof (struct __riscv_mc_f_ext_state), OPTIONAL_REGS, | |
165 | riscv_fill_fpregset, riscv_store_fpregset }, | |
166 | NULL_REGSET | |
167 | }; | |
168 | ||
169 | /* RISC-V/Linux regset information. */ | |
170 | static struct regsets_info riscv_regsets_info = | |
171 | { | |
172 | riscv_regsets, /* regsets */ | |
173 | 0, /* num_regsets */ | |
174 | NULL, /* disabled_regsets */ | |
175 | }; | |
176 | ||
177 | /* Definition of linux_target_ops data member "regs_info". */ | |
178 | static struct regs_info riscv_regs = | |
179 | { | |
180 | NULL, /* regset_bitmap */ | |
181 | NULL, /* usrregs */ | |
182 | &riscv_regsets_info, | |
183 | }; | |
184 | ||
aa8d21c9 | 185 | /* Implementation of linux target ops method "get_regs_info". */ |
bf84f706 | 186 | |
aa8d21c9 TBA |
187 | const regs_info * |
188 | riscv_target::get_regs_info () | |
bf84f706 MR |
189 | { |
190 | return &riscv_regs; | |
191 | } | |
192 | ||
bd70b1f2 | 193 | /* Implementation of linux target ops method "low_fetch_register". */ |
bf84f706 | 194 | |
bd70b1f2 TBA |
195 | bool |
196 | riscv_target::low_fetch_register (regcache *regcache, int regno) | |
bf84f706 MR |
197 | { |
198 | const struct target_desc *tdesc = regcache->tdesc; | |
199 | ||
200 | if (regno != find_regno (tdesc, "zero")) | |
bd70b1f2 | 201 | return false; |
bf84f706 | 202 | supply_register_zeroed (regcache, regno); |
bd70b1f2 | 203 | return true; |
bf84f706 MR |
204 | } |
205 | ||
206 | /* Implementation of linux_target_ops method "get_pc". */ | |
207 | ||
208 | static CORE_ADDR | |
209 | riscv_get_pc (struct regcache *regcache) | |
210 | { | |
211 | elf_gregset_t regset; | |
212 | ||
213 | if (sizeof (regset[0]) == 8) | |
214 | return linux_get_pc_64bit (regcache); | |
215 | else | |
216 | return linux_get_pc_32bit (regcache); | |
217 | } | |
218 | ||
219 | /* Implementation of linux_target_ops method "set_pc". */ | |
220 | ||
221 | static void | |
222 | riscv_set_pc (struct regcache *regcache, CORE_ADDR newpc) | |
223 | { | |
224 | elf_gregset_t regset; | |
225 | ||
226 | if (sizeof (regset[0]) == 8) | |
227 | linux_set_pc_64bit (regcache, newpc); | |
228 | else | |
229 | linux_set_pc_32bit (regcache, newpc); | |
230 | } | |
231 | ||
232 | /* Correct in either endianness. */ | |
233 | static const uint16_t riscv_ibreakpoint[] = { 0x0073, 0x0010 }; | |
234 | static const uint16_t riscv_cbreakpoint = 0x9002; | |
235 | ||
236 | /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". */ | |
237 | ||
238 | static int | |
239 | riscv_breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
240 | { | |
241 | union | |
242 | { | |
243 | gdb_byte bytes[2]; | |
244 | uint16_t insn; | |
245 | } | |
246 | buf; | |
247 | ||
248 | if (target_read_memory (*pcptr, buf.bytes, sizeof (buf.insn)) == 0 | |
249 | && riscv_insn_length (buf.insn == sizeof (riscv_ibreakpoint))) | |
250 | return sizeof (riscv_ibreakpoint); | |
251 | else | |
252 | return sizeof (riscv_cbreakpoint); | |
253 | } | |
254 | ||
255 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ | |
256 | ||
257 | static const gdb_byte * | |
258 | riscv_sw_breakpoint_from_kind (int kind, int *size) | |
259 | { | |
260 | *size = kind; | |
261 | switch (kind) | |
262 | { | |
263 | case sizeof (riscv_ibreakpoint): | |
264 | return (const gdb_byte *) &riscv_ibreakpoint; | |
265 | default: | |
266 | return (const gdb_byte *) &riscv_cbreakpoint; | |
267 | } | |
268 | } | |
269 | ||
270 | /* Implementation of linux_target_ops method "breakpoint_at". */ | |
271 | ||
272 | static int | |
273 | riscv_breakpoint_at (CORE_ADDR pc) | |
274 | { | |
275 | union | |
276 | { | |
277 | gdb_byte bytes[2]; | |
278 | uint16_t insn; | |
279 | } | |
280 | buf; | |
281 | ||
282 | if (target_read_memory (pc, buf.bytes, sizeof (buf.insn)) == 0 | |
283 | && (buf.insn == riscv_cbreakpoint | |
284 | || (buf.insn == riscv_ibreakpoint[0] | |
285 | && target_read_memory (pc + sizeof (buf.insn), buf.bytes, | |
286 | sizeof (buf.insn)) == 0 | |
287 | && buf.insn == riscv_ibreakpoint[1]))) | |
288 | return 1; | |
289 | else | |
290 | return 0; | |
291 | } | |
292 | ||
293 | /* RISC-V/Linux target operations. */ | |
294 | struct linux_target_ops the_low_target = | |
295 | { | |
bf84f706 MR |
296 | riscv_get_pc, |
297 | riscv_set_pc, | |
298 | riscv_breakpoint_kind_from_pc, | |
299 | riscv_sw_breakpoint_from_kind, | |
300 | NULL, /* get_next_pcs */ | |
301 | 0, /* decr_pc_after_break */ | |
302 | riscv_breakpoint_at, | |
303 | }; | |
304 | ||
ef0478f6 TBA |
305 | /* The linux target ops object. */ |
306 | ||
307 | linux_process_target *the_linux_target = &the_riscv_target; | |
308 | ||
bf84f706 MR |
309 | /* Initialize the RISC-V/Linux target. */ |
310 | ||
311 | void | |
312 | initialize_low_arch () | |
313 | { | |
314 | initialize_regsets_info (&riscv_regsets_info); | |
315 | } |