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bf84f706 MR |
1 | /* GNU/Linux/RISC-V specific low level interface, for the remote server |
2 | for GDB. | |
3 | Copyright (C) 2020 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "server.h" | |
21 | ||
22 | #include "linux-low.h" | |
23 | #include "tdesc.h" | |
24 | #include "elf/common.h" | |
25 | #include "nat/riscv-linux-tdesc.h" | |
26 | #include "opcode/riscv.h" | |
27 | ||
28 | /* Work around glibc header breakage causing ELF_NFPREG not to be usable. */ | |
29 | #ifndef NFPREG | |
30 | # define NFPREG 33 | |
31 | #endif | |
32 | ||
ef0478f6 TBA |
33 | /* Linux target op definitions for the RISC-V architecture. */ |
34 | ||
35 | class riscv_target : public linux_process_target | |
36 | { | |
37 | public: | |
38 | ||
aa8d21c9 TBA |
39 | const regs_info *get_regs_info () override; |
40 | ||
797bcff5 TBA |
41 | protected: |
42 | ||
43 | void low_arch_setup () override; | |
daca57a7 TBA |
44 | |
45 | bool low_cannot_fetch_register (int regno) override; | |
46 | ||
47 | bool low_cannot_store_register (int regno) override; | |
ef0478f6 TBA |
48 | }; |
49 | ||
50 | /* The singleton target ops object. */ | |
51 | ||
52 | static riscv_target the_riscv_target; | |
53 | ||
daca57a7 TBA |
54 | bool |
55 | riscv_target::low_cannot_fetch_register (int regno) | |
56 | { | |
57 | gdb_assert_not_reached ("linux target op low_cannot_fetch_register " | |
58 | "is not implemented by the target"); | |
59 | } | |
60 | ||
61 | bool | |
62 | riscv_target::low_cannot_store_register (int regno) | |
63 | { | |
64 | gdb_assert_not_reached ("linux target op low_cannot_store_register " | |
65 | "is not implemented by the target"); | |
66 | } | |
67 | ||
797bcff5 | 68 | /* Implementation of linux target ops method "low_arch_setup". */ |
bf84f706 | 69 | |
797bcff5 TBA |
70 | void |
71 | riscv_target::low_arch_setup () | |
bf84f706 MR |
72 | { |
73 | static const char *expedite_regs[] = { "sp", "pc", NULL }; | |
74 | ||
75 | const riscv_gdbarch_features features | |
76 | = riscv_linux_read_features (lwpid_of (current_thread)); | |
77 | target_desc *tdesc = riscv_create_target_description (features); | |
78 | ||
79 | if (!tdesc->expedite_regs) | |
80 | init_target_desc (tdesc, expedite_regs); | |
81 | current_process ()->tdesc = tdesc; | |
82 | } | |
83 | ||
84 | /* Collect GPRs from REGCACHE into BUF. */ | |
85 | ||
86 | static void | |
87 | riscv_fill_gregset (struct regcache *regcache, void *buf) | |
88 | { | |
89 | const struct target_desc *tdesc = regcache->tdesc; | |
90 | elf_gregset_t *regset = (elf_gregset_t *) buf; | |
91 | int regno = find_regno (tdesc, "zero"); | |
92 | int i; | |
93 | ||
94 | collect_register_by_name (regcache, "pc", *regset); | |
95 | for (i = 1; i < ARRAY_SIZE (*regset); i++) | |
96 | collect_register (regcache, regno + i, *regset + i); | |
97 | } | |
98 | ||
99 | /* Supply GPRs from BUF into REGCACHE. */ | |
100 | ||
101 | static void | |
102 | riscv_store_gregset (struct regcache *regcache, const void *buf) | |
103 | { | |
104 | const elf_gregset_t *regset = (const elf_gregset_t *) buf; | |
105 | const struct target_desc *tdesc = regcache->tdesc; | |
106 | int regno = find_regno (tdesc, "zero"); | |
107 | int i; | |
108 | ||
109 | supply_register_by_name (regcache, "pc", *regset); | |
110 | supply_register_zeroed (regcache, regno); | |
111 | for (i = 1; i < ARRAY_SIZE (*regset); i++) | |
112 | supply_register (regcache, regno + i, *regset + i); | |
113 | } | |
114 | ||
115 | /* Collect FPRs from REGCACHE into BUF. */ | |
116 | ||
117 | static void | |
118 | riscv_fill_fpregset (struct regcache *regcache, void *buf) | |
119 | { | |
120 | const struct target_desc *tdesc = regcache->tdesc; | |
121 | int regno = find_regno (tdesc, "ft0"); | |
122 | int flen = register_size (regcache->tdesc, regno); | |
123 | gdb_byte *regbuf = (gdb_byte *) buf; | |
124 | int i; | |
125 | ||
126 | for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) | |
127 | collect_register (regcache, regno + i, regbuf); | |
128 | collect_register_by_name (regcache, "fcsr", regbuf); | |
129 | } | |
130 | ||
131 | /* Supply FPRs from BUF into REGCACHE. */ | |
132 | ||
133 | static void | |
134 | riscv_store_fpregset (struct regcache *regcache, const void *buf) | |
135 | { | |
136 | const struct target_desc *tdesc = regcache->tdesc; | |
137 | int regno = find_regno (tdesc, "ft0"); | |
138 | int flen = register_size (regcache->tdesc, regno); | |
139 | const gdb_byte *regbuf = (const gdb_byte *) buf; | |
140 | int i; | |
141 | ||
142 | for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) | |
143 | supply_register (regcache, regno + i, regbuf); | |
144 | supply_register_by_name (regcache, "fcsr", regbuf); | |
145 | } | |
146 | ||
147 | /* RISC-V/Linux regsets. FPRs are optional and come in different sizes, | |
148 | so define multiple regsets for them marking them all as OPTIONAL_REGS | |
149 | rather than FP_REGS, so that "regsets_fetch_inferior_registers" picks | |
150 | the right one according to size. */ | |
151 | static struct regset_info riscv_regsets[] = { | |
152 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, | |
153 | sizeof (elf_gregset_t), GENERAL_REGS, | |
154 | riscv_fill_gregset, riscv_store_gregset }, | |
155 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, | |
156 | sizeof (struct __riscv_mc_q_ext_state), OPTIONAL_REGS, | |
157 | riscv_fill_fpregset, riscv_store_fpregset }, | |
158 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, | |
159 | sizeof (struct __riscv_mc_d_ext_state), OPTIONAL_REGS, | |
160 | riscv_fill_fpregset, riscv_store_fpregset }, | |
161 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, | |
162 | sizeof (struct __riscv_mc_f_ext_state), OPTIONAL_REGS, | |
163 | riscv_fill_fpregset, riscv_store_fpregset }, | |
164 | NULL_REGSET | |
165 | }; | |
166 | ||
167 | /* RISC-V/Linux regset information. */ | |
168 | static struct regsets_info riscv_regsets_info = | |
169 | { | |
170 | riscv_regsets, /* regsets */ | |
171 | 0, /* num_regsets */ | |
172 | NULL, /* disabled_regsets */ | |
173 | }; | |
174 | ||
175 | /* Definition of linux_target_ops data member "regs_info". */ | |
176 | static struct regs_info riscv_regs = | |
177 | { | |
178 | NULL, /* regset_bitmap */ | |
179 | NULL, /* usrregs */ | |
180 | &riscv_regsets_info, | |
181 | }; | |
182 | ||
aa8d21c9 | 183 | /* Implementation of linux target ops method "get_regs_info". */ |
bf84f706 | 184 | |
aa8d21c9 TBA |
185 | const regs_info * |
186 | riscv_target::get_regs_info () | |
bf84f706 MR |
187 | { |
188 | return &riscv_regs; | |
189 | } | |
190 | ||
191 | /* Implementation of linux_target_ops method "fetch_register". */ | |
192 | ||
193 | static int | |
194 | riscv_fetch_register (struct regcache *regcache, int regno) | |
195 | { | |
196 | const struct target_desc *tdesc = regcache->tdesc; | |
197 | ||
198 | if (regno != find_regno (tdesc, "zero")) | |
199 | return 0; | |
200 | supply_register_zeroed (regcache, regno); | |
201 | return 1; | |
202 | } | |
203 | ||
204 | /* Implementation of linux_target_ops method "get_pc". */ | |
205 | ||
206 | static CORE_ADDR | |
207 | riscv_get_pc (struct regcache *regcache) | |
208 | { | |
209 | elf_gregset_t regset; | |
210 | ||
211 | if (sizeof (regset[0]) == 8) | |
212 | return linux_get_pc_64bit (regcache); | |
213 | else | |
214 | return linux_get_pc_32bit (regcache); | |
215 | } | |
216 | ||
217 | /* Implementation of linux_target_ops method "set_pc". */ | |
218 | ||
219 | static void | |
220 | riscv_set_pc (struct regcache *regcache, CORE_ADDR newpc) | |
221 | { | |
222 | elf_gregset_t regset; | |
223 | ||
224 | if (sizeof (regset[0]) == 8) | |
225 | linux_set_pc_64bit (regcache, newpc); | |
226 | else | |
227 | linux_set_pc_32bit (regcache, newpc); | |
228 | } | |
229 | ||
230 | /* Correct in either endianness. */ | |
231 | static const uint16_t riscv_ibreakpoint[] = { 0x0073, 0x0010 }; | |
232 | static const uint16_t riscv_cbreakpoint = 0x9002; | |
233 | ||
234 | /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". */ | |
235 | ||
236 | static int | |
237 | riscv_breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
238 | { | |
239 | union | |
240 | { | |
241 | gdb_byte bytes[2]; | |
242 | uint16_t insn; | |
243 | } | |
244 | buf; | |
245 | ||
246 | if (target_read_memory (*pcptr, buf.bytes, sizeof (buf.insn)) == 0 | |
247 | && riscv_insn_length (buf.insn == sizeof (riscv_ibreakpoint))) | |
248 | return sizeof (riscv_ibreakpoint); | |
249 | else | |
250 | return sizeof (riscv_cbreakpoint); | |
251 | } | |
252 | ||
253 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ | |
254 | ||
255 | static const gdb_byte * | |
256 | riscv_sw_breakpoint_from_kind (int kind, int *size) | |
257 | { | |
258 | *size = kind; | |
259 | switch (kind) | |
260 | { | |
261 | case sizeof (riscv_ibreakpoint): | |
262 | return (const gdb_byte *) &riscv_ibreakpoint; | |
263 | default: | |
264 | return (const gdb_byte *) &riscv_cbreakpoint; | |
265 | } | |
266 | } | |
267 | ||
268 | /* Implementation of linux_target_ops method "breakpoint_at". */ | |
269 | ||
270 | static int | |
271 | riscv_breakpoint_at (CORE_ADDR pc) | |
272 | { | |
273 | union | |
274 | { | |
275 | gdb_byte bytes[2]; | |
276 | uint16_t insn; | |
277 | } | |
278 | buf; | |
279 | ||
280 | if (target_read_memory (pc, buf.bytes, sizeof (buf.insn)) == 0 | |
281 | && (buf.insn == riscv_cbreakpoint | |
282 | || (buf.insn == riscv_ibreakpoint[0] | |
283 | && target_read_memory (pc + sizeof (buf.insn), buf.bytes, | |
284 | sizeof (buf.insn)) == 0 | |
285 | && buf.insn == riscv_ibreakpoint[1]))) | |
286 | return 1; | |
287 | else | |
288 | return 0; | |
289 | } | |
290 | ||
291 | /* RISC-V/Linux target operations. */ | |
292 | struct linux_target_ops the_low_target = | |
293 | { | |
bf84f706 MR |
294 | riscv_fetch_register, |
295 | riscv_get_pc, | |
296 | riscv_set_pc, | |
297 | riscv_breakpoint_kind_from_pc, | |
298 | riscv_sw_breakpoint_from_kind, | |
299 | NULL, /* get_next_pcs */ | |
300 | 0, /* decr_pc_after_break */ | |
301 | riscv_breakpoint_at, | |
302 | }; | |
303 | ||
ef0478f6 TBA |
304 | /* The linux target ops object. */ |
305 | ||
306 | linux_process_target *the_linux_target = &the_riscv_target; | |
307 | ||
bf84f706 MR |
308 | /* Initialize the RISC-V/Linux target. */ |
309 | ||
310 | void | |
311 | initialize_low_arch () | |
312 | { | |
313 | initialize_regsets_info (&riscv_regsets_info); | |
314 | } |