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58dbd541 YQ |
1 | /* Target dependent code for GDB on TI C6x systems. |
2 | ||
b811d2c2 | 3 | Copyright (C) 2010-2020 Free Software Foundation, Inc. |
58dbd541 YQ |
4 | Contributed by Andrew Jenner <andrew@codesourcery.com> |
5 | Contributed by Yao Qi <yao@codesourcery.com> | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "server.h" | |
23 | #include "linux-low.h" | |
506fe5f4 YQ |
24 | #include "arch/tic6x.h" |
25 | #include "tdesc.h" | |
58dbd541 | 26 | |
5826e159 | 27 | #include "nat/gdb_ptrace.h" |
58dbd541 YQ |
28 | #include <endian.h> |
29 | ||
30 | #include "gdb_proc_service.h" | |
31 | ||
32 | #ifndef PTRACE_GET_THREAD_AREA | |
33 | #define PTRACE_GET_THREAD_AREA 25 | |
34 | #endif | |
35 | ||
36 | /* There are at most 69 registers accessible in ptrace. */ | |
37 | #define TIC6X_NUM_REGS 69 | |
38 | ||
39 | #include <asm/ptrace.h> | |
40 | ||
ef0478f6 TBA |
41 | /* Linux target op definitions for the TI C6x architecture. */ |
42 | ||
43 | class tic6x_target : public linux_process_target | |
44 | { | |
45 | public: | |
46 | ||
797bcff5 TBA |
47 | protected: |
48 | ||
49 | void low_arch_setup () override; | |
ef0478f6 TBA |
50 | }; |
51 | ||
52 | /* The singleton target ops object. */ | |
53 | ||
54 | static tic6x_target the_tic6x_target; | |
55 | ||
58dbd541 YQ |
56 | /* Defined in auto-generated file tic6x-c64xp-linux.c. */ |
57 | void init_registers_tic6x_c64xp_linux (void); | |
3aee8918 PA |
58 | extern const struct target_desc *tdesc_tic6x_c64xp_linux; |
59 | ||
58dbd541 YQ |
60 | /* Defined in auto-generated file tic6x-c64x-linux.c. */ |
61 | void init_registers_tic6x_c64x_linux (void); | |
3aee8918 PA |
62 | extern const struct target_desc *tdesc_tic6x_c64x_linux; |
63 | ||
58dbd541 YQ |
64 | /* Defined in auto-generated file tic62x-c6xp-linux.c. */ |
65 | void init_registers_tic6x_c62x_linux (void); | |
3aee8918 | 66 | extern const struct target_desc *tdesc_tic6x_c62x_linux; |
58dbd541 YQ |
67 | |
68 | union tic6x_register | |
69 | { | |
70 | unsigned char buf[4]; | |
71 | ||
72 | int reg32; | |
73 | }; | |
74 | ||
75 | /* Return the ptrace ``address'' of register REGNO. */ | |
76 | ||
77 | #if __BYTE_ORDER == __BIG_ENDIAN | |
78 | static int tic6x_regmap_c64xp[] = { | |
79 | /* A0 - A15 */ | |
80 | 53, 52, 55, 54, 57, 56, 59, 58, | |
81 | 61, 60, 63, 62, 65, 64, 67, 66, | |
82 | /* B0 - B15 */ | |
83 | 23, 22, 25, 24, 27, 26, 29, 28, | |
84 | 31, 30, 33, 32, 35, 34, 69, 68, | |
85 | /* CSR PC */ | |
86 | 5, 4, | |
87 | /* A16 - A31 */ | |
88 | 37, 36, 39, 38, 41, 40, 43, 42, | |
89 | 45, 44, 47, 46, 49, 48, 51, 50, | |
90 | /* B16 - B31 */ | |
91 | 7, 6, 9, 8, 11, 10, 13, 12, | |
92 | 15, 14, 17, 16, 19, 18, 21, 20, | |
93 | /* TSR, ILC, RILC */ | |
94 | 1, 2, 3 | |
95 | }; | |
96 | ||
97 | static int tic6x_regmap_c64x[] = { | |
98 | /* A0 - A15 */ | |
99 | 51, 50, 53, 52, 55, 54, 57, 56, | |
100 | 59, 58, 61, 60, 63, 62, 65, 64, | |
101 | /* B0 - B15 */ | |
102 | 21, 20, 23, 22, 25, 24, 27, 26, | |
103 | 29, 28, 31, 30, 33, 32, 67, 66, | |
104 | /* CSR PC */ | |
105 | 3, 2, | |
106 | /* A16 - A31 */ | |
107 | 35, 34, 37, 36, 39, 38, 41, 40, | |
108 | 43, 42, 45, 44, 47, 46, 49, 48, | |
109 | /* B16 - B31 */ | |
110 | 5, 4, 7, 6, 9, 8, 11, 10, | |
111 | 13, 12, 15, 14, 17, 16, 19, 18, | |
112 | -1, -1, -1 | |
113 | }; | |
114 | ||
115 | static int tic6x_regmap_c62x[] = { | |
116 | /* A0 - A15 */ | |
117 | 19, 18, 21, 20, 23, 22, 25, 24, | |
118 | 27, 26, 29, 28, 31, 30, 33, 32, | |
119 | /* B0 - B15 */ | |
120 | 5, 4, 7, 6, 9, 8, 11, 10, | |
121 | 13, 12, 15, 14, 17, 16, 35, 34, | |
122 | /* CSR, PC */ | |
123 | 3, 2, | |
124 | -1, -1, -1, -1, -1, -1, -1, -1, | |
125 | -1, -1, -1, -1, -1, -1, -1, -1, | |
126 | -1, -1, -1, -1, -1, -1, -1, -1, | |
127 | -1, -1, -1, -1, -1, -1, -1, -1, | |
128 | -1, -1, -1 | |
129 | }; | |
130 | ||
131 | #else | |
132 | static int tic6x_regmap_c64xp[] = { | |
133 | /* A0 - A15 */ | |
134 | 52, 53, 54, 55, 56, 57, 58, 59, | |
135 | 60, 61, 62, 63, 64, 65, 66, 67, | |
136 | /* B0 - B15 */ | |
137 | 22, 23, 24, 25, 26, 27, 28, 29, | |
138 | 30, 31, 32, 33, 34, 35, 68, 69, | |
139 | /* CSR PC */ | |
140 | 4, 5, | |
141 | /* A16 - A31 */ | |
142 | 36, 37, 38, 39, 40, 41, 42, 43, | |
143 | 44, 45, 46, 47, 48, 49, 50, 51, | |
144 | /* B16 -B31 */ | |
145 | 6, 7, 8, 9, 10, 11, 12, 13, | |
146 | 14, 15, 16, 17, 18, 19, 20, 31, | |
147 | /* TSR, ILC, RILC */ | |
148 | 0, 3, 2 | |
149 | }; | |
150 | ||
151 | static int tic6x_regmap_c64x[] = { | |
152 | /* A0 - A15 */ | |
153 | 50, 51, 52, 53, 54, 55, 56, 57, | |
154 | 58, 59, 60, 61, 62, 63, 64, 65, | |
155 | /* B0 - B15 */ | |
156 | 20, 21, 22, 23, 24, 25, 26, 27, | |
157 | 28, 29, 30, 31, 32, 33, 66, 67, | |
158 | /* CSR PC */ | |
159 | 2, 3, | |
160 | /* A16 - A31 */ | |
161 | 34, 35, 36, 37, 38, 39, 40, 41, | |
162 | 42, 43, 44, 45, 46, 47, 48, 49, | |
163 | /* B16 - B31 */ | |
164 | 4, 5, 6, 7, 8, 9, 10, 11, | |
165 | 12, 13, 14, 15, 16, 17, 18, 19, | |
166 | -1, -1, -1 | |
167 | }; | |
168 | ||
169 | static int tic6x_regmap_c62x[] = { | |
170 | /* A0 - A15 */ | |
171 | 18, 19, 20, 21, 22, 23, 24, 25, | |
172 | 26, 27, 28, 29, 30, 31, 32, 33, | |
173 | /* B0 - B15 */ | |
174 | 4, 5, 6, 7, 8, 9, 10, 11, | |
175 | 12, 13, 14, 15, 16, 17, 34, 35, | |
176 | /* CSR PC */ | |
177 | 2, 3, | |
178 | -1, -1, -1, -1, -1, -1, -1, -1, | |
179 | -1, -1, -1, -1, -1, -1, -1, -1, | |
180 | -1, -1, -1, -1, -1, -1, -1, -1, | |
181 | -1, -1, -1, -1, -1, -1, -1, -1, | |
182 | -1, -1, -1 | |
183 | }; | |
184 | ||
185 | #endif | |
186 | ||
187 | extern struct linux_target_ops the_low_target; | |
188 | ||
189 | static int *tic6x_regmap; | |
190 | static unsigned int tic6x_breakpoint; | |
dd373349 AT |
191 | #define tic6x_breakpoint_len 4 |
192 | ||
193 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ | |
194 | ||
195 | static const gdb_byte * | |
196 | tic6x_sw_breakpoint_from_kind (int kind, int *size) | |
197 | { | |
198 | *size = tic6x_breakpoint_len; | |
199 | return (const gdb_byte *) &tic6x_breakpoint; | |
200 | } | |
58dbd541 | 201 | |
3491a34c YQ |
202 | static struct usrregs_info tic6x_usrregs_info = |
203 | { | |
204 | TIC6X_NUM_REGS, | |
205 | NULL, /* Set in tic6x_read_description. */ | |
206 | }; | |
3aee8918 PA |
207 | |
208 | static const struct target_desc * | |
506fe5f4 | 209 | tic6x_read_description (enum c6x_feature feature) |
58dbd541 | 210 | { |
506fe5f4 YQ |
211 | static target_desc *tdescs[C6X_LAST] = { }; |
212 | struct target_desc **tdesc = &tdescs[feature]; | |
58dbd541 | 213 | |
506fe5f4 | 214 | if (*tdesc == NULL) |
58dbd541 | 215 | { |
506fe5f4 | 216 | *tdesc = tic6x_create_target_description (feature); |
506fe5f4 | 217 | static const char *expedite_regs[] = { "A15", "PC", NULL }; |
190852c8 | 218 | init_target_desc (*tdesc, expedite_regs); |
58dbd541 | 219 | } |
506fe5f4 YQ |
220 | |
221 | return *tdesc; | |
58dbd541 YQ |
222 | } |
223 | ||
224 | static int | |
225 | tic6x_cannot_fetch_register (int regno) | |
226 | { | |
227 | return (tic6x_regmap[regno] == -1); | |
228 | } | |
229 | ||
230 | static int | |
231 | tic6x_cannot_store_register (int regno) | |
232 | { | |
233 | return (tic6x_regmap[regno] == -1); | |
234 | } | |
235 | ||
236 | static CORE_ADDR | |
237 | tic6x_get_pc (struct regcache *regcache) | |
238 | { | |
239 | union tic6x_register pc; | |
240 | ||
241 | collect_register_by_name (regcache, "PC", pc.buf); | |
242 | return pc.reg32; | |
243 | } | |
244 | ||
245 | static void | |
246 | tic6x_set_pc (struct regcache *regcache, CORE_ADDR pc) | |
247 | { | |
248 | union tic6x_register newpc; | |
249 | ||
250 | newpc.reg32 = pc; | |
251 | supply_register_by_name (regcache, "PC", newpc.buf); | |
252 | } | |
253 | ||
58dbd541 YQ |
254 | static int |
255 | tic6x_breakpoint_at (CORE_ADDR where) | |
256 | { | |
257 | unsigned int insn; | |
258 | ||
52405d85 | 259 | the_target->read_memory (where, (unsigned char *) &insn, 4); |
58dbd541 YQ |
260 | if (insn == tic6x_breakpoint) |
261 | return 1; | |
262 | ||
263 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
264 | one. */ | |
265 | return 0; | |
266 | } | |
267 | ||
268 | /* Fetch the thread-local storage pointer for libthread_db. */ | |
269 | ||
270 | ps_err_e | |
754653a7 | 271 | ps_get_thread_area (struct ps_prochandle *ph, |
58dbd541 YQ |
272 | lwpid_t lwpid, int idx, void **base) |
273 | { | |
274 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
275 | return PS_ERR; | |
276 | ||
277 | /* IDX is the bias from the thread pointer to the beginning of the | |
278 | thread descriptor. It has to be subtracted due to implementation | |
279 | quirks in libthread_db. */ | |
280 | *base = (void *) ((char *) *base - idx); | |
281 | ||
282 | return PS_OK; | |
283 | } | |
284 | ||
285 | static void | |
286 | tic6x_collect_register (struct regcache *regcache, int regno, | |
287 | union tic6x_register *reg) | |
288 | { | |
289 | union tic6x_register tmp_reg; | |
290 | ||
291 | collect_register (regcache, regno, &tmp_reg.reg32); | |
292 | reg->reg32 = tmp_reg.reg32; | |
293 | } | |
294 | ||
295 | static void | |
296 | tic6x_supply_register (struct regcache *regcache, int regno, | |
297 | const union tic6x_register *reg) | |
298 | { | |
299 | int offset = 0; | |
300 | ||
301 | supply_register (regcache, regno, reg->buf + offset); | |
302 | } | |
303 | ||
304 | static void | |
305 | tic6x_fill_gregset (struct regcache *regcache, void *buf) | |
306 | { | |
3491a34c | 307 | auto regset = static_cast<union tic6x_register *> (buf); |
58dbd541 YQ |
308 | int i; |
309 | ||
310 | for (i = 0; i < TIC6X_NUM_REGS; i++) | |
311 | if (tic6x_regmap[i] != -1) | |
312 | tic6x_collect_register (regcache, i, regset + tic6x_regmap[i]); | |
313 | } | |
314 | ||
315 | static void | |
316 | tic6x_store_gregset (struct regcache *regcache, const void *buf) | |
317 | { | |
3491a34c | 318 | const auto regset = static_cast<const union tic6x_register *> (buf); |
58dbd541 YQ |
319 | int i; |
320 | ||
321 | for (i = 0; i < TIC6X_NUM_REGS; i++) | |
322 | if (tic6x_regmap[i] != -1) | |
323 | tic6x_supply_register (regcache, i, regset + tic6x_regmap[i]); | |
324 | } | |
325 | ||
3aee8918 | 326 | static struct regset_info tic6x_regsets[] = { |
58dbd541 YQ |
327 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, TIC6X_NUM_REGS * 4, GENERAL_REGS, |
328 | tic6x_fill_gregset, tic6x_store_gregset }, | |
50bc912a | 329 | NULL_REGSET |
58dbd541 YQ |
330 | }; |
331 | ||
797bcff5 TBA |
332 | void |
333 | tic6x_target::low_arch_setup () | |
3aee8918 | 334 | { |
506fe5f4 YQ |
335 | register unsigned int csr asm ("B2"); |
336 | unsigned int cpuid; | |
337 | enum c6x_feature feature = C6X_CORE; | |
338 | ||
339 | /* Determine the CPU we're running on to find the register order. */ | |
340 | __asm__ ("MVC .S2 CSR,%0" : "=r" (csr) :); | |
341 | cpuid = csr >> 24; | |
342 | switch (cpuid) | |
343 | { | |
344 | case 0x00: /* C62x */ | |
345 | case 0x02: /* C67x */ | |
346 | tic6x_regmap = tic6x_regmap_c62x; | |
347 | tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */ | |
348 | feature = C6X_CORE; | |
349 | break; | |
350 | case 0x03: /* C67x+ */ | |
351 | tic6x_regmap = tic6x_regmap_c64x; | |
352 | tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */ | |
353 | feature = C6X_GP; | |
354 | break; | |
355 | case 0x0c: /* C64x */ | |
356 | tic6x_regmap = tic6x_regmap_c64x; | |
357 | tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */ | |
358 | feature = C6X_GP; | |
359 | break; | |
360 | case 0x10: /* C64x+ */ | |
361 | case 0x14: /* C674x */ | |
362 | case 0x15: /* C66x */ | |
363 | tic6x_regmap = tic6x_regmap_c64xp; | |
364 | tic6x_breakpoint = 0x56454314; /* illegal opcode */ | |
365 | feature = C6X_C6XP; | |
366 | break; | |
367 | default: | |
368 | error ("Unknown CPU ID 0x%02x", cpuid); | |
369 | } | |
370 | tic6x_usrregs_info.regmap = tic6x_regmap; | |
371 | ||
372 | current_process ()->tdesc = tic6x_read_description (feature); | |
3aee8918 PA |
373 | } |
374 | ||
7d00775e AT |
375 | /* Support for hardware single step. */ |
376 | ||
377 | static int | |
378 | tic6x_supports_hardware_single_step (void) | |
379 | { | |
380 | return 1; | |
381 | } | |
382 | ||
3aee8918 PA |
383 | static struct regsets_info tic6x_regsets_info = |
384 | { | |
385 | tic6x_regsets, /* regsets */ | |
386 | 0, /* num_regsets */ | |
387 | NULL, /* disabled_regsets */ | |
388 | }; | |
389 | ||
3aee8918 PA |
390 | static struct regs_info regs_info = |
391 | { | |
392 | NULL, /* regset_bitmap */ | |
393 | &tic6x_usrregs_info, | |
394 | &tic6x_regsets_info | |
395 | }; | |
396 | ||
397 | static const struct regs_info * | |
398 | tic6x_regs_info (void) | |
399 | { | |
400 | return ®s_info; | |
401 | } | |
402 | ||
58dbd541 | 403 | struct linux_target_ops the_low_target = { |
3aee8918 | 404 | tic6x_regs_info, |
58dbd541 YQ |
405 | tic6x_cannot_fetch_register, |
406 | tic6x_cannot_store_register, | |
c14dfd32 | 407 | NULL, /* fetch_register */ |
58dbd541 YQ |
408 | tic6x_get_pc, |
409 | tic6x_set_pc, | |
dd373349 AT |
410 | NULL, /* breakpoint_kind_from_pc */ |
411 | tic6x_sw_breakpoint_from_kind, | |
58dbd541 YQ |
412 | NULL, |
413 | 0, | |
414 | tic6x_breakpoint_at, | |
7d00775e AT |
415 | NULL, /* supports_z_point_type */ |
416 | NULL, /* insert_point */ | |
417 | NULL, /* remove_point */ | |
418 | NULL, /* stopped_by_watchpoint */ | |
419 | NULL, /* stopped_data_address */ | |
420 | NULL, /* collect_ptrace_register */ | |
421 | NULL, /* supply_ptrace_register */ | |
422 | NULL, /* siginfo_fixup */ | |
423 | NULL, /* new_process */ | |
04ec7890 | 424 | NULL, /* delete_process */ |
7d00775e | 425 | NULL, /* new_thread */ |
466eecee | 426 | NULL, /* delete_thread */ |
7d00775e AT |
427 | NULL, /* new_fork */ |
428 | NULL, /* prepare_to_resume */ | |
429 | NULL, /* process_qsupported */ | |
430 | NULL, /* supports_tracepoints */ | |
431 | NULL, /* get_thread_area */ | |
432 | NULL, /* install_fast_tracepoint_jump_pad */ | |
433 | NULL, /* emit_ops */ | |
434 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
435 | NULL, /* supports_range_stepping */ | |
436 | NULL, /* breakpoint_kind_from_current_state */ | |
437 | tic6x_supports_hardware_single_step, | |
58dbd541 | 438 | }; |
3aee8918 | 439 | |
506fe5f4 | 440 | #if GDB_SELF_TEST |
268a13a5 | 441 | #include "gdbsupport/selftest.h" |
506fe5f4 YQ |
442 | |
443 | namespace selftests { | |
444 | namespace tdesc { | |
445 | static void | |
446 | tic6x_tdesc_test () | |
447 | { | |
448 | SELF_CHECK (*tdesc_tic6x_c62x_linux == *tic6x_read_description (C6X_CORE)); | |
449 | SELF_CHECK (*tdesc_tic6x_c64x_linux == *tic6x_read_description (C6X_GP)); | |
450 | SELF_CHECK (*tdesc_tic6x_c64xp_linux == *tic6x_read_description (C6X_C6XP)); | |
451 | } | |
452 | } | |
453 | } | |
454 | #endif | |
455 | ||
ef0478f6 TBA |
456 | /* The linux target ops object. */ |
457 | ||
458 | linux_process_target *the_linux_target = &the_tic6x_target; | |
459 | ||
3aee8918 PA |
460 | void |
461 | initialize_low_arch (void) | |
462 | { | |
506fe5f4 | 463 | #if GDB_SELF_TEST |
3aee8918 PA |
464 | /* Initialize the Linux target descriptions. */ |
465 | init_registers_tic6x_c64xp_linux (); | |
466 | init_registers_tic6x_c64x_linux (); | |
467 | init_registers_tic6x_c62x_linux (); | |
468 | ||
506fe5f4 YQ |
469 | selftests::register_test ("tic6x-tdesc", selftests::tdesc::tic6x_tdesc_test); |
470 | #endif | |
471 | ||
3aee8918 PA |
472 | initialize_regsets_info (&tic6x_regsets_info); |
473 | } |