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Implement and document --gc-keep-exported
[deliverable/binutils-gdb.git] / include / ChangeLog
CommitLineData
22185505 12016-12-16 fincs <fincs.alt1@gmail.com>
2
3 * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
4
5e7fc731
MR		 52016-12-14 Maciej W. Rozycki <macro@imgtec.com>
6
7 * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
8 typedef as `elf_internal_abiflags_v0'.
9
a6a51754
RL		 102016-12-13 Renlin Li <renlin.li@arm.com>
11
12 * opcode/aarch64.h (aarch64_operand_class): Remove
13 AARCH64_OPND_CLASS_CP_REG.
14 (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
15 AARCH64_OPND_Cm to AARCH64_OPND_CRm.
16 (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
17
64c11183
MR		 182016-12-09 Maciej W. Rozycki <macro@imgtec.com>
19
20 * opcode/mips.h: Remove references to `>' operand code.
21
4b078115
MR		 222016-12-07 Maciej W. Rozycki <macro@imgtec.com>
23
24 * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
25
b8760d2c
MR		 262016-12-07 Maciej W. Rozycki <macro@imgtec.com>
27
28 * opcode/mips.h (ASE_DSPR3): Add a comment.
29
a12fd8e1
SN		 302016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
31
32 * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
33 (ARM_ARCH_V8_3A): New.
34
abe7c33b
CZ		 352016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
36
37 * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
38 instruction classes.
39
6884417a
JM		 402016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
41
42 * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
43 hwcaps2.
44
08dc996f
AM		 452016-11-22 Alan Modra <amodra@gmail.com>
46
47 PR 20744
48 * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
49
535aade6
DT		 502016-11-03 David Tolnay <dtolnay@gmail.com>
51 Mark Wielaard <mark@klomp.org>
52
53 * demangle.h (DMGL_RUST): New macro.
54 (DMGL_STYLE_MASK): Add DMGL_RUST.
55 (demangling_styles): Add dlang_rust.
56 (RUST_DEMANGLING_STYLE_STRING): New macro.
57 (RUST_DEMANGLING): New macro.
58 (rust_demangle): New prototype.
59 (rust_is_mangled): Likewise.
60 (rust_demangle_sym): Likewise.
61
a4ddf8dc
JM		 622016-11-07 Jason Merrill <jason@redhat.com>
63
64 * demangle.h (enum demangle_component_type): Add
65 DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
66
c2c4ff8d
SN		 672016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
68
69 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
70 AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
71 (enum aarch64_op): Add OP_FCMLA_ELEM.
72
3f06e550
SN		 732016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
74
75 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
76 (enum aarch64_insn_class): Add ldst_imm10.
77
c84364ec
SN		 782016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
79
80 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
81
1924ff75
SN		 822016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
83
84 * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
85 (AARCH64_ARCH_V8_3): Define.
86 (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
87
d46a2165
TP		 882016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
89
90 * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
91 (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
92 (ARM_ARCH_V8M_MAIN_DSP): Likewise.
93
5a736821
GM		 942016-11-03 Graham Markall <graham.markall@embecosm.com>
95
96 * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
97
bdfe53e3
AB		 982016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
99
100 * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
101 fields.
102 (struct arc_long_opcode): Delete.
103 (struct arc_operand): Change types for insert and extract
104 handlers.
105
2e272202
GM		 1062016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
107
108 * opcode/arc.h: Make macros 64-bit safe.
109
06fe285f
GM		 1102016-11-03 Graham Markall <graham.markall@embecosm.com>
111
112 * opcode/arc.h (arc_opcode_len): Declare.
113 (ARC_SHORT): Delete.
114
e23eba97
NC		 1152016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
116 Andrew Waterman <andrew@sifive.com>
117
118 Add support for RISC-V architecture.
119 * dis-asm.h: Add prototypes for print_insn_riscv and
120 print_riscv_disassembler_options.
121 * elf/riscv.h: New file.
122 * opcode/riscv-opc.h: New file.
123 * opcode/riscv.h: New file.
124
6d913794
NC		 1252016-10-17 Nick Clifton <nickc@redhat.com>
126
127 * elf/common.h (DT_SYMTAB_SHNDX): Define.
128 (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
129 (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
130 (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
131 (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
132 (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
133 (ELFOSABI_OPENVOS): Define.
134 (GRP_MASKOS, GRP_MASKPROC): Define.
135
b4f6af8e
PA		 1362016-10-14 Pedro Alves <palves@redhat.com>
137
138 * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
139 OVERRIDE): Define as empty.
140 [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
141 __final.
142 [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
143 empty.
144
d118ee37
PA		 1452016-10-14 Pedro Alves <palves@redhat.com>
146
147 * ansidecl.h (GCC_FINAL): Delete.
148 (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
149
e5b06ef0
CZ		 1502016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
151
152 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
153
a5721ba2
AM		 1542016-09-29 Alan Modra <amodra@gmail.com>
155
156 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
157
2b848ebd
CZ		 1582016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
159
160 * opcode/arc.h (insn_class_t): Add two new classes.
161
005d79fd
AM		 1622016-09-26 Alan Modra <amodra@gmail.com>
163
164 * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
165
bb7eff52
RS		 1662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
167
168 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
169
c0890d26
RS		 1702016-09-21 Richard Sandiford <richard.sandiford@arm.com>
171
172 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
173 (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
174 (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
175 (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
176
116b6019
RS		 1772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
178
179 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
180 (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
181 (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
182 aarch64_insn_classes.
183
047cd301
RS		 1842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
185
186 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
187 (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
188 (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
189
165d4950
RS		 1902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
191
192 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
193 (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
194 (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
195
e950b345
RS		 1962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
197
198 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
199 (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
200 (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
201 (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
202 (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
203 (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
204 (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
205 (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
206 (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
207 (AARCH64_OPND_SVE_UIMM8_53): Likewise.
208 (aarch64_sve_dupm_mov_immediate_p): Declare.
209
98907a70
RS		 2102016-09-21 Richard Sandiford <richard.sandiford@arm.com>
211
212 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
213 (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
214 (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
215 (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
216 (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
217
4df068de
RS		 2182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
219
220 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
221 (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
222 (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
223 (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
224 (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
225 (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
226 (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
227 (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
228 (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
229 (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
230 (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
231 (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
232 (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
233 (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
234 (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
235 (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
236 Likewise.
237
2442d846
RS		 2382016-09-21 Richard Sandiford <richard.sandiford@arm.com>
239
240 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
241 aarch64_opnd.
242 (AARCH64_MOD_MUL): New aarch64_modifier_kind.
243 (aarch64_opnd_info): Make shifter.amount an int64_t and
244 rearrange the fields.
245
245d2e3f
RS		 2462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
247
248 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
249 (AARCH64_OPND_SVE_PRFOP): Likewise.
250 (aarch64_sve_pattern_array): Declare.
251 (aarch64_sve_prfop_array): Likewise.
252
d50c751e
RS		 2532016-09-21 Richard Sandiford <richard.sandiford@arm.com>
254
255 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
256 (AARCH64_OPND_QLF_P_M): Likewise.
257
f11ad6bc
RS		 2582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
259
260 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
261 aarch64_operand_class.
262 (AARCH64_OPND_CLASS_PRED_REG): Likewise.
263 (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
264 (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
265 (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
266 (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
267 (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
268 (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
269 (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
270
0c608d6b
RS		 2712016-09-21 Richard Sandiford <richard.sandiford@arm.com>
272
273 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
274 (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
275
4989adac
RS		 2762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
277
278 * opcode/aarch64.h (F_STRICT): New flag.
279
27e5a270
RE		 2802016-09-07 Richard Earnshaw <rearnsha@arm.com>
281
282 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
283
a87aa054
CM		 2842016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
285 * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
286 SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
287 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
288 relocation.
289
4ba2ef8f
TP		 2902016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
291
292 * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
293 (ARM_SET_SYM_CMSE_SPCL): Likewise.
294
dfdaec14
AJ		 2952016-08-01 Andrew Jenner <andrew@codesourcery.com>
296
297 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
298
fa3fcee7
NC		 2992016-07-29 Aldy Hernandez <aldyh@redhat.com>
300
301 * libiberty.h (MAX_ALLOCA_SIZE): New macro.
302
db18dbab
GM		 3032016-07-27 Graham Markall <graham.markall@embecosm.com>
304
305 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
306 ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
307 ARC_NUM_ADDRTYPES.
308 * opcode/arc.h: Add BMU to insn_class_t enum.
309 * opcode/arc.h: Add PMU to insn_class_t enum.
310
37fd5ef3
CZ		 3112016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
312
313 * dis-asm.h: Declare print_arc_disassembler_options.
314
76359541
TP		 3152016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
316
317 * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
318 out_implib_bfd fields.
319
fa1c0170
CZ		 3202016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
321
322 * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
323
f0728ee3
AV		 3242016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
325
326 * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
327 (SHF_ARM_PURECODE): ... this.
328
93d8990c
SN		 3292016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
330
331 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
332 (AARCH64_CPU_HAS_ANY_FEATURES): New.
333 (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
334 (AARCH64_OPCODE_HAS_FEATURE): Remove.
335
534dbe46
MW		 3362016-06-30 Matthew Wahab <matthew.wahab@arm.com>
337
338 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
339 of enabled FPU features.
340
042c94de
TS		 3412016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
342
343 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
344 SPARC_OPCODE_ARCH_MAX into the enum.
345
dab26bf4
RS		 3462016-06-28 Richard Sandiford <richard.sandiford@arm.com>
347
348 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
349
c9775dde
MR		 3502016-06-28 Maciej W. Rozycki <macro@imgtec.com>
351
352 * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
353
7c2c4aa1
TS		 3542016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
355
356 * elf/xtensa.h (xtensa_make_property_section): New prototype.
357
b00f86d0
JB		 3582016-06-24 John Baldwin <jhb@FreeBSD.org>
359
360 * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
361 (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
362 (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
363 (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
364
ce440d63
GM		 3652016-06-23 Graham Markall <graham.markall@embecosm.com>
366
367 * opcode/arc.h: Make insn_class_t alphabetical again.
368
6b477896
TS		 3692016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
370
371 * elf/dlx.h: Wrap in extern C.
372 * elf/xtensa.h: Likewise.
373 * opcode/arc.h: Likewise.
374
6edaf4d7
TS		 3752016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
376
377 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
378 tilegx_pipeline.
379
bdd582db
GM		 3802016-06-21 Graham Markall <graham.markall@embecosm.com>
381
382 * opcode/arc.h: Add nps400 extension and instruction
383 subclass.
384 Remove ARC_OPCODE_NPS400
385 * elf/arc.h: Remove E_ARC_MACH_NPS400
386
4f26fb3a
JM		 3872016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
388
389 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
390 SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
391 SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
392 SPARC_OPCODE_ARCH_V9M.
393
99a54ef6
JB		 3942016-06-14 John Baldwin <jhb@FreeBSD.org>
395
396 * opcode/msp430-decode.h (MSP430_Size): Remove.
397 (Msp430_Opcode_Decoded): Change type of size to int.
398
0eaf2e1b
AM		 3992016-06-11 Alan Modra <amodra@gmail.com>
400
401 * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
402
337c570c
JM		 4032016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
404
405 * opcode/sparc.h: Add missing documentation for hyperprivileged
406 registers in rd (%) and rs1 ($).
407
14b57c7c
AM		 4082016-06-07 Alan Modra <amodra@gmail.com>
409
410 * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
411 PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
412 PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
413 PPC_APUINFO_VLE: Define.
414
4d1464f2
MW		 4152016-06-07 Matthew Wahab <matthew.wahab@arm.com>
416
417 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
418 entries.
419 (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
420
4eb6f892
AB		 4212016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
422
423 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
424 (struct arc_long_opcode): New structure.
425 (arc_long_opcodes): Declare.
426 (arc_num_long_opcodes): Declare.
427
1fe0971e
TS		 4282016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
429
430 * elf/mips.h: Add extern "C".
431 * elf/sh.h: Likewise.
432 * opcode/d10v.h: Likewise.
433 * opcode/d30v.h: Likewise.
434 * opcode/ia64.h: Likewise.
435 * opcode/mips.h: Likewise.
436 * opcode/ppc.h: Likewise.
437 * opcode/sparc.h: Likewise.
438 * opcode/tic6x.h: Likewise.
439 * opcode/v850.h: Likewise.
440
1a72702b
AM		 4412016-05-28 Alan Modra <amodra@gmail.com>
442
443 * bfdlink.h (struct bfd_link_callbacks): Update comments.
444 Return void from multiple_definition, multiple_common,
445 add_to_set, constructor, warning, undefined_symbol,
446 reloc_overflow, reloc_dangerous and unattached_reloc.
447
94740f9c
TS		 4482016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
449
450 * opcode/metag.h: wrap declarations in extern "C".
451
d9eca1df
CZ		 4522016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
453
454 * opcode/arc.h (insn_subclass_t): Add COND.
455 (flag_class_t): Add F_CLASS_EXTEND.
456
c810e0b8
CZ		 4572016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
458
459 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
460 insn_class.
461 (struct arc_flag_class): Renamed attribute class to flag_class.
462
3d207518
TS		 4632016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
464
465 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
466 plain symbol.
467
5ff087ac
TT		 4682016-04-29 Tom Tromey <tom@tromey.com>
469
470 * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
471 DW_LANG_Rust_old>: New constants.
472
8f4f9071
MF		 4732016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
474
475 * elf/mips.h (AFL_ASE_DSPR3): New macro.
476 (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
477 * opcode/mips.h (ASE_DSPR3): New macro.
478
39d911fc
TP		 4792016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
480 Nick Clifton <nickc@redhat.com>
481
482 * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
483 enumerator.
484 (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
485 (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
486 (ARM_SYM_BRANCH_TYPE): Replace by ...
487 (ARM_GET_SYM_BRANCH_TYPE): This and ...
488 (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
489 BFD_ASSERT is defined or not.
490
15afaa63
TP		 4912016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
492
493 * elf/arm.h (Tag_DSP_extension): Define.
494
d942732e
TP		 4952016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
496
497 * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
498
16a1fa25
TP		 4992016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
500
501 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
502 (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
503 (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
504 for the high core bits.
505
945e0f82
CZ		 5062016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
507
508 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
509 (ARC_SYNTAX_NOP): Likewsie.
510 (ARC_OP1_MUST_BE_IMM): Update defined value.
511 (ARC_OP1_IMM_IMPLIED): Likewise.
512 (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
513
4bd13cde
NC		 5142016-04-28 Nick Clifton <nickc@redhat.com>
515
516 PR target/19722
517 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
518
a6a4679f
AM		 5192016-04-27 Alan Modra <amodra@gmail.com>
520
521 * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
522 undef. Formatting.
523
4f3b23b3
NC		 5242016-04-21 Nick Clifton <nickc@redhat.com>
525
526 * bfdlink.h: Add prototype for bfd_link_check_relocs.
527
d9689752
L		 5282016-04-20 H.J. Lu <hongjiu.lu@intel.com>
529
530 * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
531
52176c67
AB		 5322016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
533
534 * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
535
537aefaf
AB		 5362016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
537
538 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
539
c8f785f2
AB		 5402016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
541
542 * opcode/arc.h (insn_class_t): Add NET and ACL class.
543
4b0c052e
AB		 5442016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
545
546 * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
547 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
548
f36e33da
CZ		 5492016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
550
551 * opcode/arc.h (flag_class_t): Update.
552 (ARC_OPCODE_NONE): Define.
553 (ARC_OPCODE_ARCALL): Likewise.
554 (ARC_OPCODE_ARCFPX): Likewise.
555 (ARC_REGISTER_READONLY): Likewise.
556 (ARC_REGISTER_WRITEONLY): Likewise.
557 (ARC_REGISTER_NOSHORT_CUT): Likewise.
558 (arc_aux_reg): Add cpu.
559
b99747ae
CZ		 5602016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
561
562 * opcode/arc.h (arc_num_opcodes): Remove.
563 (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
564 (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
565 (ARC_SUFFIX_FLAG): Define.
566 (flags_none, flags_f, flags_cc, flags_ccf): Declare.
567 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
568 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
569 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
570 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
571 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
572 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
573 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
574 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
575 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
576
5772016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
578
579 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
580 (ARC_FPUDA): Define.
581 (arc_aux_reg): Add new field.
582
5832016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
094fb063
CZ		 584
585 * opcode/arc-func.h (replace_bits24): Changed.
586 (replace_bits24_be): Created.
587
f2dd8838
CZ		 5882016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
589
b99747ae
CZ		 590 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
591 (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
592 (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
593 (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
594 (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
595 (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
596 (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
597 (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
598 (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
599 (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
600 (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
601 (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
602 (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
603 (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
f2dd8838 604
b9bb4a93
TS		 6052016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
606
607 * opcode/i960.h: Add const qualifiers.
608 * opcode/tic4x.h (struct tic4x_inst): Likewise.
609
e23e8ebe
AB		 6102016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
611
612 * opcodes/arc.h (insn_class_t): Add BITOP type.
613
1ae8ab47
AB		 6142016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
615
616 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
617 new classes instead.
618
8699fc3e
AB		 6192016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
620
621 * elf/arc.h (E_ARC_MACH_NPS400): Define.
622 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
623
a9522a21
AB		 6242016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
625
626 * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
627
c0334580
AB		 6282016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
629
630 * elf/arc.h (EF_ARC_MACH): Delete.
631 (EF_ARC_MACH_MSK): Remove out of date comment.
632
24740d83
AB		 6332016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
634
635 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
636
4c10bbaa
L		 6372016-03-15 H.J. Lu <hongjiu.lu@intel.com>
638
639 PR ld/19807
640 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
641
72f3b6aa
CZ		 6422016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
643 Andrew Burgess <andrew.burgess@embecosm.com>
644
645 * elf/arc-reloc.def: Add a call to ME within the formula for each
646 relocation that requires middle-endian correction.
647
f86f5863
TS		 6482016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
649
650 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
651 * opcode/h8300.h (struct h8_opcode): Likewise.
652 * opcode/hppa.h (struct pa_opcode): Likewise.
653 * opcode/msp430.h: Likewise.
654 * opcode/spu.h (struct spu_opcode): Likewise.
655 * opcode/tic30.h (struct _register): Likewise.
656 * opcode/tic4x.h (struct tic4x_register): Likewise.
657 (struct tic4x_cond): Likewise.
658 (struct tic4x_indirect): Likewise.
659 (struct tic4x_inst): Likewise.
660 * opcode/visium.h (struct reg_entry): Likewise.
661
643afb90
MW		 6622016-03-04 Matthew Wahab <matthew.wahab@arm.com>
663
664 * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
665 (ARM_CPU_HAS_FEATURE): Add comment.
666
3f1f41f5
L		 6672016-03-03 Than McIntosh <thanm@google.com>
668
669 * plugin-api.h: Add new hooks to the plugin transfer vector to
670 to support querying section alignment and section size.
671 (ld_plugin_get_input_section_alignment): New hook.
672 (ld_plugin_get_input_section_size): New hook.
673 (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
674 and LDPT_GET_INPUT_SECTION_SIZE.
675 (ld_plugin_tv): Add tv_get_input_section_alignment and
676 tv_get_input_section_size.
677
9b738e36 6782016-03-03 Evgenii Stepanov <eugenis@google.com>
95ecdfbf
ES		 679
680 * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
681
11e5f1ec
L		 6822016-02-26 H.J. Lu <hongjiu.lu@intel.com>
683
684 PR ld/19645
685 * bfdlink.h (bfd_link_elf_stt_common): New enum.
686 (bfd_link_info): Add elf_stt_common.
687
aec6b87e
L		 6882016-02-26 H.J. Lu <hongjiu.lu@intel.com>
689
690 PR ld/19636
691 PR ld/19704
692 PR ld/19719
693 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
694
b8ec4e87
JW		 6952016-02-19 Matthew Wahab <matthew.wahab@arm.com>
696 Jiong Wang <jiong.wang@arm.com>
697
698 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
699
4670103e
CZ		 7002016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
701 Janek van Oirschot <jvanoirs@synopsys.com>
702
b99747ae
CZ		 703 * opcode/arc.h (arc_opcode arc_relax_opcodes)
704 (arc_num_relax_opcodes): Declare.
4670103e 705
609332f1
NC		 7062016-02-09 Nick Clifton <nickc@redhat.com>
707
708 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
709 * opcode/nds32.h (nds32_r45map): Likewise.
710 (nds32_r54map): Likewise.
711 * opcode/visium.h (gen_reg_table): Likewise.
712 (fp_reg_table, cc_table, opcode_table): Likewise.
713
24f5f69a
AM		 7142016-02-09 Alan Modra <amodra@gmail.com>
715
716 PR 16583
717 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
718
c1d9289f
NC		 7192016-02-04 Nick Clifton <nickc@redhat.com>
720
721 PR target/19561
722 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
723 (RRUX): Synthesise using case 2 rather than 7.
724
f4ddf30f
JB		 7252016-01-19 John Baldwin <jhb@FreeBSD.org>
726
727 * elf/common.h (NT_FREEBSD_THRMISC): Define.
728 (NT_FREEBSD_PROCSTAT_PROC): Define.
729 (NT_FREEBSD_PROCSTAT_FILES): Define.
730 (NT_FREEBSD_PROCSTAT_VMMAP): Define.
731 (NT_FREEBSD_PROCSTAT_GROUPS): Define.
732 (NT_FREEBSD_PROCSTAT_UMASK): Define.
733 (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
734 (NT_FREEBSD_PROCSTAT_OSREL): Define.
735 (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
736 (NT_FREEBSD_PROCSTAT_AUXV): Define.
737
34e967a5
MC		 7382016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
739 Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
740
741 * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
742 (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
743 (ARC_TLS_LE_32): Fixed formula.
744 (ARC_TLS_GD_LD): Use new special function.
745 * opcode/arc-func.h: Changed all the replacement
746 functions to clear the patching bits before doing an or it with the value
747 argument.
748
9ae678af
NC		 7492016-01-18 Nick Clifton <nickc@redhat.com>
750
751 PR ld/19440
752 * coff/internal.h (internal_syment): Use int to hold section
753 number.
754 (N_UNDEF): Cast to int not short.
755 (N_ABS): Likewise.
756 (N_DEBUG): Likewise.
757 (N_TV): Likewise.
758 (P_TV): Likewise.
759
4849dfd8
NC		 7602016-01-11 Nick Clifton <nickc@redhat.com>
761
762 Import this change from GCC mainline:
763
764 2016-01-07 Mike Frysinger <vapier@gentoo.org>
765
766 * longlong.h: Change !__SHMEDIA__ to
767 (!defined (__SHMEDIA__) || !__SHMEDIA__).
768 Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
769
b31e4803
MR		 7702016-01-06 Maciej W. Rozycki <macro@imgtec.com>
771
772 * opcode/mips.h: Add a summary of MIPS16 operand codes.
773
b36c1ccb
MF		 7742016-01-05 Mike Frysinger <vapier@gentoo.org>
775
776 * libiberty.h (dupargv): Change arg to char * const *.
777 (writeargv, countargv): Likewise.
778
6f2750fe
AM		 7792016-01-01 Alan Modra <amodra@gmail.com>
780
781 Update year range in copyright notice of all files.
782
3499769a
AM		 783For older changes see ChangeLog-0415, aout/ChangeLog-9115,
784cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
785mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
786som/ChangeLog-1015, and vms/ChangeLog-1015
787\f
788Copyright (C) 2016 Free Software Foundation, Inc.
789
790Copying and distribution of this file, with or without modification,
791are permitted in any medium without royalty provided the copyright
792notice and this notice are preserved.
793
794Local Variables:
795mode: change-log
796left-margin: 8
797fill-column: 74
798version-control: never
799End:
GDB Binutils - Deliverables
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