Commit | Line | Data |
---|---|---|
5663e321 AM |
1 | 2019-05-24 Alan Modra <amodra@gmail.com> |
2 | ||
3 | * elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC), | |
4 | (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30), | |
5 | (R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34), | |
6 | (R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC), | |
7 | (R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34), | |
8 | (R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34), | |
9 | (R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34), | |
10 | (R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34), | |
11 | (R_PPC64_D28, R_PPC64_PCREL28): Define. | |
12 | ||
dd7efa79 PB |
13 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
14 | Alan Modra <amodra@gmail.com> | |
15 | ||
16 | * dis-asm.h (WIDE_OUTPUT): Define. | |
17 | * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. | |
18 | (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), | |
19 | (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. | |
20 | ||
8ebe6212 JM |
21 | 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> |
22 | ||
23 | * elf/bpf.h: New file. | |
24 | ||
a7ad558c AV |
25 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
26 | ||
27 | * elf/arm.h (Tag_MVE_arch): Define new enum value. | |
28 | * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features. | |
29 | ||
28ed815a MM |
30 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
31 | ||
32 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 | |
33 | operand. | |
34 | ||
fd1dc4a0 MM |
35 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
36 | ||
37 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs | |
38 | iclass. | |
39 | ||
31e36ab3 MM |
40 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
41 | ||
42 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. | |
43 | ||
1be5f94f MM |
44 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
45 | ||
46 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd | |
47 | iclass. | |
48 | ||
3c17238b MM |
49 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
50 | ||
51 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 | |
52 | operand. | |
53 | (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. | |
54 | ||
cd50a87a MM |
55 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
56 | ||
57 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. | |
58 | ||
3c705960 MM |
59 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
60 | ||
61 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. | |
62 | ||
0a57e14f MM |
63 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
64 | ||
65 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. | |
66 | ||
c469c864 MM |
67 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
68 | ||
69 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. | |
70 | ||
116adc27 MM |
71 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
72 | ||
73 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. | |
74 | ||
3bd82c86 MM |
75 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
76 | ||
77 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. | |
78 | ||
adccc507 MM |
79 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
80 | ||
81 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. | |
82 | ||
7ce2460a MM |
83 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
84 | ||
85 | * opcode/aarch64.h (AARCH64_FEATURE_SVE2 | |
86 | AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, | |
87 | AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New | |
88 | feature macros. | |
89 | ||
41cee089 FS |
90 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
91 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
92 | ||
93 | * opcode/mips.h (ASE_EVA_R6): New macro. | |
94 | (M_LLWPE_AB, M_SCWPE_AB): New enum values. | |
95 | ||
b83b4b13 SD |
96 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
97 | ||
98 | * opcode/aarch64.h (AARCH64_FEATURE_TME): New. | |
99 | (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. | |
100 | ||
a45328b9 AB |
101 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
102 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
103 | ||
104 | * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. | |
105 | (M_SCWP_AB, M_SCDP_AB): Likewise. | |
106 | ||
cd092337 MR |
107 | 2019-04-25 Maciej W. Rozycki <macro@linux-mips.org> |
108 | ||
109 | * opcode/mips.h: Update comment for MIPS32 CODE20 operand. | |
110 | ||
1889da70 AV |
111 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
112 | ||
113 | * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. | |
114 | ||
1caf72a5 AV |
115 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
116 | ||
117 | * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. | |
118 | ||
e5d6e09e AV |
119 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
120 | ||
121 | * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. | |
122 | ||
031254f2 AV |
123 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
124 | ||
125 | * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. | |
126 | (MAX_TAG_CPU_ARCH): Set value to above macro. | |
127 | * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. | |
128 | (ARM_AEXT_V8_1M_MAIN): Likewise. | |
129 | (ARM_AEXT2_V8_1M_MAIN): Likewise. | |
130 | (ARM_ARCH_V8_1M_MAIN): Likewise. | |
131 | ||
bd7ceb8d SD |
132 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
133 | ||
134 | * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. | |
135 | ||
462cac58 L |
136 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
137 | ||
138 | * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New. | |
139 | ||
07ffcfec AM |
140 | 2019-04-07 Alan Modra <amodra@gmail.com> |
141 | ||
142 | Merge from gcc. | |
143 | 2019-04-03 Vineet Gupta <vgupta@synopsys.com> | |
144 | PR89877 | |
145 | * longlong.h [__arc__] (add_ssaaaa): Add cc clobber. | |
146 | (sub_ddmmss): Likewise. | |
147 | ||
5b9c07b2 L |
148 | 2019-04-06 H.J. Lu <hongjiu.lu@intel.com> |
149 | ||
150 | * bfdlink.h (bfd_link_info): Remove x86-specific linker options. | |
151 | ||
34ef62f4 AV |
152 | 2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com> |
153 | ||
154 | * opcode/arm.h (FPU_NEON_ARMV8_1): New. | |
155 | (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1. | |
156 | (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise. | |
157 | (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise. | |
158 | (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New. | |
159 | (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New. | |
160 | (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New. | |
161 | (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New. | |
162 | ||
96a86c01 AM |
163 | 2019-03-28 Alan Modra <amodra@gmail.com> |
164 | ||
165 | PR 24390 | |
166 | * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. | |
167 | ||
53b2f36b TC |
168 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
169 | ||
170 | * dis-asm.h (struct disassemble_info): Add stop_offset. | |
171 | ||
1dbade74 SD |
172 | 2019-03-13 Sudakshina Das <sudi.das@arm.com> |
173 | ||
174 | * elf/aarch64.h (DT_AARCH64_PAC_PLT): New. | |
175 | ||
37c18eed SD |
176 | 2019-03-13 Sudakshina Das <sudi.das@arm.com> |
177 | Szabolcs Nagy <szabolcs.nagy@arm.com> | |
178 | ||
179 | * elf/aarch64.h (DT_AARCH64_BTI_PLT): New. | |
180 | ||
cd702818 SD |
181 | 2019-03-13 Sudakshina Das <sudi.das@arm.com> |
182 | ||
183 | * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New. | |
184 | (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New. | |
185 | (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New. | |
186 | ||
e6c3b5bf AH |
187 | 2019-02-20 Alan Hayward <alan.hayward@arm.com> |
188 | ||
189 | * elf/common.h (NT_ARM_PAC_MASK): Add define. | |
190 | ||
91d78b81 SJ |
191 | 2019-02-15 Saagar Jha <saagar@saagarjha.com> |
192 | ||
193 | * mach-o/loader.h: Use new OS names in comments. | |
194 | ||
e2077304 | 195 | 2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be> |
196 | ||
197 | * splay-tree.h (splay_tree_delete_key_fn): Update comment. | |
198 | (splay_tree_delete_value_fn): Likewise. | |
199 | ||
fc60b8c8 AK |
200 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
201 | ||
202 | * opcode/s390.h (enum s390_opcode_cpu_val): Add | |
203 | S390_OPCODE_ARCH13. | |
204 | ||
550fd7bf SD |
205 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
206 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
207 | ||
208 | * opcode/aarch64.h (enum aarch64_opnd): Remove | |
209 | AARCH64_OPND_ADDR_SIMPLE_2. | |
210 | (enum aarch64_insn_class): Remove ldstgv_indexed. | |
211 | ||
71ba91e1 TT |
212 | 2019-01-22 Tom Tromey <tom@tromey.com> |
213 | ||
214 | * coff/ecoff.h: Include coff/sym.h. | |
215 | ||
f974f26c NC |
216 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
217 | ||
218 | 2.32 branch created. | |
219 | ||
2dc8dd17 JW |
220 | 2019-01-16 Kito Cheng <kito@andestech.com> |
221 | ||
222 | * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. | |
223 | (Tag_RISCV_arch): Likewise. | |
224 | (Tag_RISCV_priv_spec): Likewise. | |
225 | (Tag_RISCV_priv_spec_minor): Likewise. | |
226 | (Tag_RISCV_priv_spec_revision): Likewise. | |
227 | (Tag_RISCV_unaligned_access): Likewise. | |
228 | (Tag_RISCV_stack_align): Likewise. | |
229 | ||
8f0a2148 ПК |
230 | 2019-01-14 Pavel I. Kryukov <kryukov@frtk.ru> |
231 | ||
232 | * dis-asm.h: include <string.h> | |
233 | ||
1910070b NC |
234 | 2019-01-10 Nick Clifton <nickc@redhat.com> |
235 | ||
236 | * Merge from GCC: | |
237 | 2018-12-22 Jason Merrill <jason@redhat.com> | |
238 | ||
239 | * demangle.h: Remove support for ancient GNU (pre-3.0), Lucid, | |
240 | ARM, HP, and EDG demangling styles. | |
241 | ||
a08da33e SL |
242 | 2019-01-09 Sandra Loosemore <sandra@codesourcery.com> |
243 | ||
244 | Merge from GCC: | |
245 | PR other/16615 | |
246 | ||
247 | * libiberty.h: Mechanically replace "can not" with "cannot". | |
248 | * plugin-api.h: Likewise. | |
249 | ||
59581069 YS |
250 | 2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp> |
251 | ||
252 | * elf/rx.h (EF_RX_CPU_MASK): Update new bits. | |
253 | (E_FLAG_RX_V3): New RXv3 type. | |
254 | * opcode/rx.h (RX_Size): Add double size. | |
255 | (RX_Operand_Type): Add double FPU registers. | |
256 | (RX_Opcode_ID): Add new instuctions. | |
257 | ||
82704155 AM |
258 | 2019-01-01 Alan Modra <amodra@gmail.com> |
259 | ||
260 | Update year range in copyright notice of all files. | |
261 | ||
d5c04e1b | 262 | For older changes see ChangeLog-2018 |
3499769a | 263 | \f |
d5c04e1b | 264 | Copyright (C) 2019 Free Software Foundation, Inc. |
3499769a AM |
265 | |
266 | Copying and distribution of this file, with or without modification, | |
267 | are permitted in any medium without royalty provided the copyright | |
268 | notice and this notice are preserved. | |
269 | ||
270 | Local Variables: | |
271 | mode: change-log | |
272 | left-margin: 8 | |
273 | fill-column: 74 | |
274 | version-control: never | |
275 | End: |