projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| dd7efa79 PB |
1 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
| 2 | Alan Modra <amodra@gmail.com> | |
| 3 | ||
| 4 | * dis-asm.h (WIDE_OUTPUT): Define. | |
| 5 | * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. | |
| 6 | (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), | |
| 7 | (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. | |
| 8 | ||
| 8ebe6212 JM |
9 | 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 10 | ||
| 11 | * elf/bpf.h: New file. | |
| 12 | ||
| a7ad558c AV |
13 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 14 | ||
| 15 | * elf/arm.h (Tag_MVE_arch): Define new enum value. | |
| 16 | * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features. | |
| 17 | ||
| 28ed815a MM |
18 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 19 | ||
| 20 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 | |
| 21 | operand. | |
| 22 | ||
| fd1dc4a0 MM |
23 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 24 | ||
| 25 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs | |
| 26 | iclass. | |
| 27 | ||
| 31e36ab3 MM |
28 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 29 | ||
| 30 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. | |
| 31 | ||
| 1be5f94f MM |
32 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 33 | ||
| 34 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd | |
| 35 | iclass. | |
| 36 | ||
| 3c17238b MM |
37 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 38 | ||
| 39 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 | |
| 40 | operand. | |
| 41 | (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. | |
| 42 | ||
| cd50a87a MM |
43 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 44 | ||
| 45 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. | |
| 46 | ||
| 3c705960 MM |
47 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 48 | ||
| 49 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. | |
| 50 | ||
| 0a57e14f MM |
51 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 52 | ||
| 53 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. | |
| 54 | ||
| c469c864 MM |
55 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 56 | ||
| 57 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. | |
| 58 | ||
| 116adc27 MM |
59 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 60 | ||
| 61 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. | |
| 62 | ||
| 3bd82c86 MM |
63 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 64 | ||
| 65 | * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. | |
| 66 | ||
| adccc507 MM |
67 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 68 | ||
| 69 | * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. | |
| 70 | ||
| 7ce2460a MM |
71 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 72 | ||
| 73 | * opcode/aarch64.h (AARCH64_FEATURE_SVE2 | |
| 74 | AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, | |
| 75 | AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New | |
| 76 | feature macros. | |
| 77 | ||
| 41cee089 FS |
78 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
| 79 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
| 80 | ||
| 81 | * opcode/mips.h (ASE_EVA_R6): New macro. | |
| 82 | (M_LLWPE_AB, M_SCWPE_AB): New enum values. | |
| 83 | ||
| b83b4b13 SD |
84 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
| 85 | ||
| 86 | * opcode/aarch64.h (AARCH64_FEATURE_TME): New. | |
| 87 | (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. | |
| 88 | ||
| a45328b9 AB |
89 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
| 90 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
| 91 | ||
| 92 | * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. | |
| 93 | (M_SCWP_AB, M_SCDP_AB): Likewise. | |
| 94 | ||
| cd092337 MR |
95 | 2019-04-25 Maciej W. Rozycki <macro@linux-mips.org> |
| 96 | ||
| 97 | * opcode/mips.h: Update comment for MIPS32 CODE20 operand. | |
| 98 | ||
| 1889da70 AV |
99 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 100 | ||
| 101 | * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. | |
| 102 | ||
| 1caf72a5 AV |
103 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 104 | ||
| 105 | * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. | |
| 106 | ||
| e5d6e09e AV |
107 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 108 | ||
| 109 | * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. | |
| 110 | ||
| 031254f2 AV |
111 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 112 | ||
| 113 | * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. | |
| 114 | (MAX_TAG_CPU_ARCH): Set value to above macro. | |
| 115 | * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. | |
| 116 | (ARM_AEXT_V8_1M_MAIN): Likewise. | |
| 117 | (ARM_AEXT2_V8_1M_MAIN): Likewise. | |
| 118 | (ARM_ARCH_V8_1M_MAIN): Likewise. | |
| 119 | ||
| bd7ceb8d SD |
120 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
| 121 | ||
| 122 | * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. | |
| 123 | ||
| 462cac58 L |
124 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
| 125 | ||
| 126 | * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New. | |
| 127 | ||
| 07ffcfec AM |
128 | 2019-04-07 Alan Modra <amodra@gmail.com> |
| 129 | ||
| 130 | Merge from gcc. | |
| 131 | 2019-04-03 Vineet Gupta <vgupta@synopsys.com> | |
| 132 | PR89877 | |
| 133 | * longlong.h [__arc__] (add_ssaaaa): Add cc clobber. | |
| 134 | (sub_ddmmss): Likewise. | |
| 135 | ||
| 5b9c07b2 L |
136 | 2019-04-06 H.J. Lu <hongjiu.lu@intel.com> |
| 137 | ||
| 138 | * bfdlink.h (bfd_link_info): Remove x86-specific linker options. | |
| 139 | ||
| 34ef62f4 AV |
140 | 2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 141 | ||
| 142 | * opcode/arm.h (FPU_NEON_ARMV8_1): New. | |
| 143 | (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1. | |
| 144 | (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise. | |
| 145 | (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise. | |
| 146 | (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New. | |
| 147 | (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New. | |
| 148 | (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New. | |
| 149 | (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New. | |
| 150 | ||
| 96a86c01 AM |
151 | 2019-03-28 Alan Modra <amodra@gmail.com> |
| 152 | ||
| 153 | PR 24390 | |
| 154 | * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. | |
| 155 | ||
| 53b2f36b TC |
156 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 157 | ||
| 158 | * dis-asm.h (struct disassemble_info): Add stop_offset. | |
| 159 | ||
| 1dbade74 SD |
160 | 2019-03-13 Sudakshina Das <sudi.das@arm.com> |
| 161 | ||
| 162 | * elf/aarch64.h (DT_AARCH64_PAC_PLT): New. | |
| 163 | ||
| 37c18eed SD |
164 | 2019-03-13 Sudakshina Das <sudi.das@arm.com> |
| 165 | Szabolcs Nagy <szabolcs.nagy@arm.com> | |
| 166 | ||
| 167 | * elf/aarch64.h (DT_AARCH64_BTI_PLT): New. | |
| 168 | ||
| cd702818 SD |
169 | 2019-03-13 Sudakshina Das <sudi.das@arm.com> |
| 170 | ||
| 171 | * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New. | |
| 172 | (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New. | |
| 173 | (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New. | |
| 174 | ||
| e6c3b5bf AH |
175 | 2019-02-20 Alan Hayward <alan.hayward@arm.com> |
| 176 | ||
| 177 | * elf/common.h (NT_ARM_PAC_MASK): Add define. | |
| 178 | ||
| 91d78b81 SJ |
179 | 2019-02-15 Saagar Jha <saagar@saagarjha.com> |
| 180 | ||
| 181 | * mach-o/loader.h: Use new OS names in comments. | |
| 182 | ||
| e2077304 | 183 | 2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be> |
| 184 | ||
| 185 | * splay-tree.h (splay_tree_delete_key_fn): Update comment. | |
| 186 | (splay_tree_delete_value_fn): Likewise. | |
| 187 | ||
| fc60b8c8 AK |
188 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
| 189 | ||
| 190 | * opcode/s390.h (enum s390_opcode_cpu_val): Add | |
| 191 | S390_OPCODE_ARCH13. | |
| 192 | ||
| 550fd7bf SD |
193 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 194 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
| 195 | ||
| 196 | * opcode/aarch64.h (enum aarch64_opnd): Remove | |
| 197 | AARCH64_OPND_ADDR_SIMPLE_2. | |
| 198 | (enum aarch64_insn_class): Remove ldstgv_indexed. | |
| 199 | ||
| 71ba91e1 TT |
200 | 2019-01-22 Tom Tromey <tom@tromey.com> |
| 201 | ||
| 202 | * coff/ecoff.h: Include coff/sym.h. | |
| 203 | ||
| f974f26c NC |
204 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
| 205 | ||
| 206 | 2.32 branch created. | |
| 207 | ||
| 2dc8dd17 JW |
208 | 2019-01-16 Kito Cheng <kito@andestech.com> |
| 209 | ||
| 210 | * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. | |
| 211 | (Tag_RISCV_arch): Likewise. | |
| 212 | (Tag_RISCV_priv_spec): Likewise. | |
| 213 | (Tag_RISCV_priv_spec_minor): Likewise. | |
| 214 | (Tag_RISCV_priv_spec_revision): Likewise. | |
| 215 | (Tag_RISCV_unaligned_access): Likewise. | |
| 216 | (Tag_RISCV_stack_align): Likewise. | |
| 217 | ||
| 8f0a2148 ПК |
218 | 2019-01-14 Pavel I. Kryukov <kryukov@frtk.ru> |
| 219 | ||
| 220 | * dis-asm.h: include <string.h> | |
| 221 | ||
| 1910070b NC |
222 | 2019-01-10 Nick Clifton <nickc@redhat.com> |
| 223 | ||
| 224 | * Merge from GCC: | |
| 225 | 2018-12-22 Jason Merrill <jason@redhat.com> | |
| 226 | ||
| 227 | * demangle.h: Remove support for ancient GNU (pre-3.0), Lucid, | |
| 228 | ARM, HP, and EDG demangling styles. | |
| 229 | ||
| a08da33e SL |
230 | 2019-01-09 Sandra Loosemore <sandra@codesourcery.com> |
| 231 | ||
| 232 | Merge from GCC: | |
| 233 | PR other/16615 | |
| 234 | ||
| 235 | * libiberty.h: Mechanically replace "can not" with "cannot". | |
| 236 | * plugin-api.h: Likewise. | |
| 237 | ||
| 59581069 YS |
238 | 2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp> |
| 239 | ||
| 240 | * elf/rx.h (EF_RX_CPU_MASK): Update new bits. | |
| 241 | (E_FLAG_RX_V3): New RXv3 type. | |
| 242 | * opcode/rx.h (RX_Size): Add double size. | |
| 243 | (RX_Operand_Type): Add double FPU registers. | |
| 244 | (RX_Opcode_ID): Add new instuctions. | |
| 245 | ||
| 82704155 AM |
246 | 2019-01-01 Alan Modra <amodra@gmail.com> |
| 247 | ||
| 248 | Update year range in copyright notice of all files. | |
| 249 | ||
| d5c04e1b | 250 | For older changes see ChangeLog-2018 |
| 3499769a | 251 | \f |
| d5c04e1b | 252 | Copyright (C) 2019 Free Software Foundation, Inc. |
| 3499769a AM |
253 | |
| 254 | Copying and distribution of this file, with or without modification, | |
| 255 | are permitted in any medium without royalty provided the copyright | |
| 256 | notice and this notice are preserved. | |
| 257 | ||
| 258 | Local Variables: | |
| 259 | mode: change-log | |
| 260 | left-margin: 8 | |
| 261 | fill-column: 74 | |
| 262 | version-control: never | |
| 263 | End: |