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FINAL/OVERRIDE: Define to empty on g++ < 4.7
[deliverable/binutils-gdb.git] / include / ChangeLog
CommitLineData
b4f6af8e
PA		 12016-10-14 Pedro Alves <palves@redhat.com>
2
3 * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
4 OVERRIDE): Define as empty.
5 [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
6 __final.
7 [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
8 empty.
9
d118ee37
PA		 102016-10-14 Pedro Alves <palves@redhat.com>
11
12 * ansidecl.h (GCC_FINAL): Delete.
13 (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
14
e5b06ef0
CZ		 152016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
16
17 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
18
a5721ba2
AM		 192016-09-29 Alan Modra <amodra@gmail.com>
20
21 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
22
2b848ebd
CZ		 232016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
24
25 * opcode/arc.h (insn_class_t): Add two new classes.
26
005d79fd
AM		 272016-09-26 Alan Modra <amodra@gmail.com>
28
29 * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
30
bb7eff52
RS		 312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
32
33 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
34
c0890d26
RS		 352016-09-21 Richard Sandiford <richard.sandiford@arm.com>
36
37 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
38 (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
39 (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
40 (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
41
116b6019
RS		 422016-09-21 Richard Sandiford <richard.sandiford@arm.com>
43
44 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
45 (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
46 (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
47 aarch64_insn_classes.
48
047cd301
RS		 492016-09-21 Richard Sandiford <richard.sandiford@arm.com>
50
51 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
52 (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
53 (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
54
165d4950
RS		 552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
56
57 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
58 (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
59 (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
60
e950b345
RS		 612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
62
63 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
64 (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
65 (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
66 (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
67 (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
68 (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
69 (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
70 (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
71 (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
72 (AARCH64_OPND_SVE_UIMM8_53): Likewise.
73 (aarch64_sve_dupm_mov_immediate_p): Declare.
74
98907a70
RS		 752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
76
77 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
78 (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
79 (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
80 (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
81 (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
82
4df068de
RS		 832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
84
85 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
86 (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
87 (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
88 (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
89 (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
90 (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
91 (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
92 (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
93 (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
94 (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
95 (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
96 (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
97 (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
98 (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
99 (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
100 (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
101 Likewise.
102
2442d846
RS		 1032016-09-21 Richard Sandiford <richard.sandiford@arm.com>
104
105 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
106 aarch64_opnd.
107 (AARCH64_MOD_MUL): New aarch64_modifier_kind.
108 (aarch64_opnd_info): Make shifter.amount an int64_t and
109 rearrange the fields.
110
245d2e3f
RS		 1112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
112
113 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
114 (AARCH64_OPND_SVE_PRFOP): Likewise.
115 (aarch64_sve_pattern_array): Declare.
116 (aarch64_sve_prfop_array): Likewise.
117
d50c751e
RS		 1182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
119
120 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
121 (AARCH64_OPND_QLF_P_M): Likewise.
122
f11ad6bc
RS		 1232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
124
125 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
126 aarch64_operand_class.
127 (AARCH64_OPND_CLASS_PRED_REG): Likewise.
128 (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
129 (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
130 (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
131 (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
132 (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
133 (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
134 (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
135
0c608d6b
RS		 1362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
137
138 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
139 (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
140
4989adac
RS		 1412016-09-21 Richard Sandiford <richard.sandiford@arm.com>
142
143 * opcode/aarch64.h (F_STRICT): New flag.
144
27e5a270
RE		 1452016-09-07 Richard Earnshaw <rearnsha@arm.com>
146
147 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
148
a87aa054
CM		 1492016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
150 * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
151 SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
152 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
153 relocation.
154
4ba2ef8f
TP		 1552016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
156
157 * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
158 (ARM_SET_SYM_CMSE_SPCL): Likewise.
159
dfdaec14
AJ		 1602016-08-01 Andrew Jenner <andrew@codesourcery.com>
161
162 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
163
fa3fcee7
NC		 1642016-07-29 Aldy Hernandez <aldyh@redhat.com>
165
166 * libiberty.h (MAX_ALLOCA_SIZE): New macro.
167
db18dbab
GM		 1682016-07-27 Graham Markall <graham.markall@embecosm.com>
169
170 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
171 ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
172 ARC_NUM_ADDRTYPES.
173 * opcode/arc.h: Add BMU to insn_class_t enum.
174 * opcode/arc.h: Add PMU to insn_class_t enum.
175
37fd5ef3
CZ		 1762016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
177
178 * dis-asm.h: Declare print_arc_disassembler_options.
179
76359541
TP		 1802016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
181
182 * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
183 out_implib_bfd fields.
184
fa1c0170
CZ		 1852016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
186
187 * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
188
f0728ee3
AV		 1892016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
190
191 * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
192 (SHF_ARM_PURECODE): ... this.
193
93d8990c
SN		 1942016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
195
196 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
197 (AARCH64_CPU_HAS_ANY_FEATURES): New.
198 (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
199 (AARCH64_OPCODE_HAS_FEATURE): Remove.
200
534dbe46
MW		 2012016-06-30 Matthew Wahab <matthew.wahab@arm.com>
202
203 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
204 of enabled FPU features.
205
042c94de
TS		 2062016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
207
208 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
209 SPARC_OPCODE_ARCH_MAX into the enum.
210
dab26bf4
RS		 2112016-06-28 Richard Sandiford <richard.sandiford@arm.com>
212
213 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
214
c9775dde
MR		 2152016-06-28 Maciej W. Rozycki <macro@imgtec.com>
216
217 * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
218
7c2c4aa1
TS		 2192016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
220
221 * elf/xtensa.h (xtensa_make_property_section): New prototype.
222
b00f86d0
JB		 2232016-06-24 John Baldwin <jhb@FreeBSD.org>
224
225 * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
226 (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
227 (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
228 (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
229
ce440d63
GM		 2302016-06-23 Graham Markall <graham.markall@embecosm.com>
231
232 * opcode/arc.h: Make insn_class_t alphabetical again.
233
6b477896
TS		 2342016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
235
236 * elf/dlx.h: Wrap in extern C.
237 * elf/xtensa.h: Likewise.
238 * opcode/arc.h: Likewise.
239
6edaf4d7
TS		 2402016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
241
242 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
243 tilegx_pipeline.
244
bdd582db
GM		 2452016-06-21 Graham Markall <graham.markall@embecosm.com>
246
247 * opcode/arc.h: Add nps400 extension and instruction
248 subclass.
249 Remove ARC_OPCODE_NPS400
250 * elf/arc.h: Remove E_ARC_MACH_NPS400
251
4f26fb3a
JM		 2522016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
253
254 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
255 SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
256 SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
257 SPARC_OPCODE_ARCH_V9M.
258
99a54ef6
JB		 2592016-06-14 John Baldwin <jhb@FreeBSD.org>
260
261 * opcode/msp430-decode.h (MSP430_Size): Remove.
262 (Msp430_Opcode_Decoded): Change type of size to int.
263
0eaf2e1b
AM		 2642016-06-11 Alan Modra <amodra@gmail.com>
265
266 * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
267
337c570c
JM		 2682016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
269
270 * opcode/sparc.h: Add missing documentation for hyperprivileged
271 registers in rd (%) and rs1 ($).
272
14b57c7c
AM		 2732016-06-07 Alan Modra <amodra@gmail.com>
274
275 * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
276 PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
277 PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
278 PPC_APUINFO_VLE: Define.
279
4d1464f2
MW		 2802016-06-07 Matthew Wahab <matthew.wahab@arm.com>
281
282 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
283 entries.
284 (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
285
4eb6f892
AB		 2862016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
287
288 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
289 (struct arc_long_opcode): New structure.
290 (arc_long_opcodes): Declare.
291 (arc_num_long_opcodes): Declare.
292
1fe0971e
TS		 2932016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
294
295 * elf/mips.h: Add extern "C".
296 * elf/sh.h: Likewise.
297 * opcode/d10v.h: Likewise.
298 * opcode/d30v.h: Likewise.
299 * opcode/ia64.h: Likewise.
300 * opcode/mips.h: Likewise.
301 * opcode/ppc.h: Likewise.
302 * opcode/sparc.h: Likewise.
303 * opcode/tic6x.h: Likewise.
304 * opcode/v850.h: Likewise.
305
1a72702b
AM		 3062016-05-28 Alan Modra <amodra@gmail.com>
307
308 * bfdlink.h (struct bfd_link_callbacks): Update comments.
309 Return void from multiple_definition, multiple_common,
310 add_to_set, constructor, warning, undefined_symbol,
311 reloc_overflow, reloc_dangerous and unattached_reloc.
312
94740f9c
TS		 3132016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
314
315 * opcode/metag.h: wrap declarations in extern "C".
316
d9eca1df
CZ		 3172016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
318
319 * opcode/arc.h (insn_subclass_t): Add COND.
320 (flag_class_t): Add F_CLASS_EXTEND.
321
c810e0b8
CZ		 3222016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
323
324 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
325 insn_class.
326 (struct arc_flag_class): Renamed attribute class to flag_class.
327
3d207518
TS		 3282016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
329
330 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
331 plain symbol.
332
5ff087ac
TT		 3332016-04-29 Tom Tromey <tom@tromey.com>
334
335 * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
336 DW_LANG_Rust_old>: New constants.
337
8f4f9071
MF		 3382016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
339
340 * elf/mips.h (AFL_ASE_DSPR3): New macro.
341 (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
342 * opcode/mips.h (ASE_DSPR3): New macro.
343
39d911fc
TP		 3442016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
345 Nick Clifton <nickc@redhat.com>
346
347 * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
348 enumerator.
349 (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
350 (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
351 (ARM_SYM_BRANCH_TYPE): Replace by ...
352 (ARM_GET_SYM_BRANCH_TYPE): This and ...
353 (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
354 BFD_ASSERT is defined or not.
355
15afaa63
TP		 3562016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
357
358 * elf/arm.h (Tag_DSP_extension): Define.
359
d942732e
TP		 3602016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
361
362 * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
363
16a1fa25
TP		 3642016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
365
366 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
367 (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
368 (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
369 for the high core bits.
370
945e0f82
CZ		 3712016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
372
373 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
374 (ARC_SYNTAX_NOP): Likewsie.
375 (ARC_OP1_MUST_BE_IMM): Update defined value.
376 (ARC_OP1_IMM_IMPLIED): Likewise.
377 (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
378
4bd13cde
NC		 3792016-04-28 Nick Clifton <nickc@redhat.com>
380
381 PR target/19722
382 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
383
a6a4679f
AM		 3842016-04-27 Alan Modra <amodra@gmail.com>
385
386 * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
387 undef. Formatting.
388
4f3b23b3
NC		 3892016-04-21 Nick Clifton <nickc@redhat.com>
390
391 * bfdlink.h: Add prototype for bfd_link_check_relocs.
392
d9689752
L		 3932016-04-20 H.J. Lu <hongjiu.lu@intel.com>
394
395 * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
396
52176c67
AB		 3972016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
398
399 * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
400
537aefaf
AB		 4012016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
402
403 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
404
c8f785f2
AB		 4052016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
406
407 * opcode/arc.h (insn_class_t): Add NET and ACL class.
408
4b0c052e
AB		 4092016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
410
411 * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
412 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
413
f36e33da
CZ		 4142016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
415
416 * opcode/arc.h (flag_class_t): Update.
417 (ARC_OPCODE_NONE): Define.
418 (ARC_OPCODE_ARCALL): Likewise.
419 (ARC_OPCODE_ARCFPX): Likewise.
420 (ARC_REGISTER_READONLY): Likewise.
421 (ARC_REGISTER_WRITEONLY): Likewise.
422 (ARC_REGISTER_NOSHORT_CUT): Likewise.
423 (arc_aux_reg): Add cpu.
424
b99747ae
CZ		 4252016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
426
427 * opcode/arc.h (arc_num_opcodes): Remove.
428 (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
429 (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
430 (ARC_SUFFIX_FLAG): Define.
431 (flags_none, flags_f, flags_cc, flags_ccf): Declare.
432 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
433 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
434 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
435 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
436 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
437 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
438 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
439 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
440 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
441
4422016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
443
444 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
445 (ARC_FPUDA): Define.
446 (arc_aux_reg): Add new field.
447
4482016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
094fb063
CZ		 449
450 * opcode/arc-func.h (replace_bits24): Changed.
451 (replace_bits24_be): Created.
452
f2dd8838
CZ		 4532016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
454
b99747ae
CZ		 455 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
456 (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
457 (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
458 (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
459 (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
460 (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
461 (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
462 (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
463 (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
464 (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
465 (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
466 (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
467 (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
468 (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
f2dd8838 469
b9bb4a93
TS		 4702016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
471
472 * opcode/i960.h: Add const qualifiers.
473 * opcode/tic4x.h (struct tic4x_inst): Likewise.
474
e23e8ebe
AB		 4752016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
476
477 * opcodes/arc.h (insn_class_t): Add BITOP type.
478
1ae8ab47
AB		 4792016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
480
481 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
482 new classes instead.
483
8699fc3e
AB		 4842016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
485
486 * elf/arc.h (E_ARC_MACH_NPS400): Define.
487 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
488
a9522a21
AB		 4892016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
490
491 * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
492
c0334580
AB		 4932016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
494
495 * elf/arc.h (EF_ARC_MACH): Delete.
496 (EF_ARC_MACH_MSK): Remove out of date comment.
497
24740d83
AB		 4982016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
499
500 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
501
4c10bbaa
L		 5022016-03-15 H.J. Lu <hongjiu.lu@intel.com>
503
504 PR ld/19807
505 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
506
72f3b6aa
CZ		 5072016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
508 Andrew Burgess <andrew.burgess@embecosm.com>
509
510 * elf/arc-reloc.def: Add a call to ME within the formula for each
511 relocation that requires middle-endian correction.
512
f86f5863
TS		 5132016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
514
515 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
516 * opcode/h8300.h (struct h8_opcode): Likewise.
517 * opcode/hppa.h (struct pa_opcode): Likewise.
518 * opcode/msp430.h: Likewise.
519 * opcode/spu.h (struct spu_opcode): Likewise.
520 * opcode/tic30.h (struct _register): Likewise.
521 * opcode/tic4x.h (struct tic4x_register): Likewise.
522 (struct tic4x_cond): Likewise.
523 (struct tic4x_indirect): Likewise.
524 (struct tic4x_inst): Likewise.
525 * opcode/visium.h (struct reg_entry): Likewise.
526
643afb90
MW		 5272016-03-04 Matthew Wahab <matthew.wahab@arm.com>
528
529 * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
530 (ARM_CPU_HAS_FEATURE): Add comment.
531
3f1f41f5
L		 5322016-03-03 Than McIntosh <thanm@google.com>
533
534 * plugin-api.h: Add new hooks to the plugin transfer vector to
535 to support querying section alignment and section size.
536 (ld_plugin_get_input_section_alignment): New hook.
537 (ld_plugin_get_input_section_size): New hook.
538 (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
539 and LDPT_GET_INPUT_SECTION_SIZE.
540 (ld_plugin_tv): Add tv_get_input_section_alignment and
541 tv_get_input_section_size.
542
9b738e36 5432016-03-03 Evgenii Stepanov <eugenis@google.com>
95ecdfbf
ES		 544
545 * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
546
11e5f1ec
L		 5472016-02-26 H.J. Lu <hongjiu.lu@intel.com>
548
549 PR ld/19645
550 * bfdlink.h (bfd_link_elf_stt_common): New enum.
551 (bfd_link_info): Add elf_stt_common.
552
aec6b87e
L		 5532016-02-26 H.J. Lu <hongjiu.lu@intel.com>
554
555 PR ld/19636
556 PR ld/19704
557 PR ld/19719
558 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
559
b8ec4e87
JW		 5602016-02-19 Matthew Wahab <matthew.wahab@arm.com>
561 Jiong Wang <jiong.wang@arm.com>
562
563 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
564
4670103e
CZ		 5652016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
566 Janek van Oirschot <jvanoirs@synopsys.com>
567
b99747ae
CZ		 568 * opcode/arc.h (arc_opcode arc_relax_opcodes)
569 (arc_num_relax_opcodes): Declare.
4670103e 570
609332f1
NC		 5712016-02-09 Nick Clifton <nickc@redhat.com>
572
573 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
574 * opcode/nds32.h (nds32_r45map): Likewise.
575 (nds32_r54map): Likewise.
576 * opcode/visium.h (gen_reg_table): Likewise.
577 (fp_reg_table, cc_table, opcode_table): Likewise.
578
24f5f69a
AM		 5792016-02-09 Alan Modra <amodra@gmail.com>
580
581 PR 16583
582 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
583
c1d9289f
NC		 5842016-02-04 Nick Clifton <nickc@redhat.com>
585
586 PR target/19561
587 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
588 (RRUX): Synthesise using case 2 rather than 7.
589
f4ddf30f
JB		 5902016-01-19 John Baldwin <jhb@FreeBSD.org>
591
592 * elf/common.h (NT_FREEBSD_THRMISC): Define.
593 (NT_FREEBSD_PROCSTAT_PROC): Define.
594 (NT_FREEBSD_PROCSTAT_FILES): Define.
595 (NT_FREEBSD_PROCSTAT_VMMAP): Define.
596 (NT_FREEBSD_PROCSTAT_GROUPS): Define.
597 (NT_FREEBSD_PROCSTAT_UMASK): Define.
598 (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
599 (NT_FREEBSD_PROCSTAT_OSREL): Define.
600 (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
601 (NT_FREEBSD_PROCSTAT_AUXV): Define.
602
34e967a5
MC		 6032016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
604 Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
605
606 * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
607 (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
608 (ARC_TLS_LE_32): Fixed formula.
609 (ARC_TLS_GD_LD): Use new special function.
610 * opcode/arc-func.h: Changed all the replacement
611 functions to clear the patching bits before doing an or it with the value
612 argument.
613
9ae678af
NC		 6142016-01-18 Nick Clifton <nickc@redhat.com>
615
616 PR ld/19440
617 * coff/internal.h (internal_syment): Use int to hold section
618 number.
619 (N_UNDEF): Cast to int not short.
620 (N_ABS): Likewise.
621 (N_DEBUG): Likewise.
622 (N_TV): Likewise.
623 (P_TV): Likewise.
624
4849dfd8
NC		 6252016-01-11 Nick Clifton <nickc@redhat.com>
626
627 Import this change from GCC mainline:
628
629 2016-01-07 Mike Frysinger <vapier@gentoo.org>
630
631 * longlong.h: Change !__SHMEDIA__ to
632 (!defined (__SHMEDIA__) || !__SHMEDIA__).
633 Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
634
b31e4803
MR		 6352016-01-06 Maciej W. Rozycki <macro@imgtec.com>
636
637 * opcode/mips.h: Add a summary of MIPS16 operand codes.
638
b36c1ccb
MF		 6392016-01-05 Mike Frysinger <vapier@gentoo.org>
640
641 * libiberty.h (dupargv): Change arg to char * const *.
642 (writeargv, countargv): Likewise.
643
6f2750fe
AM		 6442016-01-01 Alan Modra <amodra@gmail.com>
645
646 Update year range in copyright notice of all files.
647
3499769a
AM		 648For older changes see ChangeLog-0415, aout/ChangeLog-9115,
649cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
650mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
651som/ChangeLog-1015, and vms/ChangeLog-1015
652\f
653Copyright (C) 2016 Free Software Foundation, Inc.
654
655Copying and distribution of this file, with or without modification,
656are permitted in any medium without royalty provided the copyright
657notice and this notice are preserved.
658
659Local Variables:
660mode: change-log
661left-margin: 8
662fill-column: 74
663version-control: never
664End:
GDB Binutils - Deliverables
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