Commit | Line | Data |
---|---|---|
e23eba97 NC |
1 | 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com> |
2 | Andrew Waterman <andrew@sifive.com> | |
3 | ||
4 | Add support for RISC-V architecture. | |
5 | * dis-asm.h: Add prototypes for print_insn_riscv and | |
6 | print_riscv_disassembler_options. | |
7 | * elf/riscv.h: New file. | |
8 | * opcode/riscv-opc.h: New file. | |
9 | * opcode/riscv.h: New file. | |
10 | ||
6d913794 NC |
11 | 2016-10-17 Nick Clifton <nickc@redhat.com> |
12 | ||
13 | * elf/common.h (DT_SYMTAB_SHNDX): Define. | |
14 | (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define. | |
15 | (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define. | |
16 | (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define. | |
17 | (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define. | |
18 | (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define. | |
19 | (ELFOSABI_OPENVOS): Define. | |
20 | (GRP_MASKOS, GRP_MASKPROC): Define. | |
21 | ||
b4f6af8e PA |
22 | 2016-10-14 Pedro Alves <palves@redhat.com> |
23 | ||
24 | * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL, | |
25 | OVERRIDE): Define as empty. | |
26 | [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as | |
27 | __final. | |
28 | [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as | |
29 | empty. | |
30 | ||
d118ee37 PA |
31 | 2016-10-14 Pedro Alves <palves@redhat.com> |
32 | ||
33 | * ansidecl.h (GCC_FINAL): Delete. | |
34 | (OVERRIDE, FINAL): New, moved from gcc/coretypes.h. | |
35 | ||
e5b06ef0 CZ |
36 | 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com> |
37 | ||
38 | * opcode/arc.h (ARC_OPCODE_ARCV2): New define. | |
39 | ||
a5721ba2 AM |
40 | 2016-09-29 Alan Modra <amodra@gmail.com> |
41 | ||
42 | * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define. | |
43 | ||
2b848ebd CZ |
44 | 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com> |
45 | ||
46 | * opcode/arc.h (insn_class_t): Add two new classes. | |
47 | ||
005d79fd AM |
48 | 2016-09-26 Alan Modra <amodra@gmail.com> |
49 | ||
50 | * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values. | |
51 | ||
bb7eff52 RS |
52 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
53 | ||
54 | * opcode/aarch64.h (aarch64_cond): Bump array size to 4. | |
55 | ||
c0890d26 RS |
56 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
57 | ||
58 | * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro. | |
59 | (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi) | |
60 | (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P) | |
61 | (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops. | |
62 | ||
116b6019 RS |
63 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
64 | ||
65 | * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc) | |
66 | (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred) | |
67 | (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New | |
68 | aarch64_insn_classes. | |
69 | ||
047cd301 RS |
70 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
71 | ||
72 | * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd. | |
73 | (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd) | |
74 | (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise. | |
75 | ||
165d4950 RS |
76 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
77 | ||
78 | * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd. | |
79 | (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO) | |
80 | (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise. | |
81 | ||
e950b345 RS |
82 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
83 | ||
84 | * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd. | |
85 | (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM) | |
86 | (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM) | |
87 | (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED) | |
88 | (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED) | |
89 | (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5) | |
90 | (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6) | |
91 | (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3) | |
92 | (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8) | |
93 | (AARCH64_OPND_SVE_UIMM8_53): Likewise. | |
94 | (aarch64_sve_dupm_mov_immediate_p): Declare. | |
95 | ||
98907a70 RS |
96 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
97 | ||
98 | * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd. | |
99 | (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL) | |
100 | (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL) | |
101 | (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise. | |
102 | (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind. | |
103 | ||
4df068de RS |
104 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
105 | ||
106 | * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd. | |
107 | (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4) | |
108 | (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR) | |
109 | (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2) | |
110 | (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX) | |
111 | (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2) | |
112 | (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ) | |
113 | (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2) | |
114 | (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14) | |
115 | (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14) | |
116 | (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14) | |
117 | (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14) | |
118 | (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5) | |
119 | (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4) | |
120 | (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL) | |
121 | (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW): | |
122 | Likewise. | |
123 | ||
2442d846 RS |
124 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
125 | ||
126 | * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New | |
127 | aarch64_opnd. | |
128 | (AARCH64_MOD_MUL): New aarch64_modifier_kind. | |
129 | (aarch64_opnd_info): Make shifter.amount an int64_t and | |
130 | rearrange the fields. | |
131 | ||
245d2e3f RS |
132 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
133 | ||
134 | * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd. | |
135 | (AARCH64_OPND_SVE_PRFOP): Likewise. | |
136 | (aarch64_sve_pattern_array): Declare. | |
137 | (aarch64_sve_prfop_array): Likewise. | |
138 | ||
d50c751e RS |
139 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
140 | ||
141 | * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier. | |
142 | (AARCH64_OPND_QLF_P_M): Likewise. | |
143 | ||
f11ad6bc RS |
144 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
145 | ||
146 | * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New | |
147 | aarch64_operand_class. | |
148 | (AARCH64_OPND_CLASS_PRED_REG): Likewise. | |
149 | (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5) | |
150 | (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16) | |
151 | (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt) | |
152 | (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd) | |
153 | (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn) | |
154 | (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN) | |
155 | (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds. | |
156 | ||
0c608d6b RS |
157 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
158 | ||
159 | * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field. | |
160 | (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind. | |
161 | ||
4989adac RS |
162 | 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> |
163 | ||
164 | * opcode/aarch64.h (F_STRICT): New flag. | |
165 | ||
27e5a270 RE |
166 | 2016-09-07 Richard Earnshaw <rearnsha@arm.com> |
167 | ||
168 | * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture. | |
169 | ||
a87aa054 CM |
170 | 2016-08-26 Cupertino Miranda <cmiranda@synopsys.com> |
171 | * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12, | |
172 | SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations. | |
173 | * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12 | |
174 | relocation. | |
175 | ||
4ba2ef8f TP |
176 | 2016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com> |
177 | ||
178 | * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro. | |
179 | (ARM_SET_SYM_CMSE_SPCL): Likewise. | |
180 | ||
dfdaec14 AJ |
181 | 2016-08-01 Andrew Jenner <andrew@codesourcery.com> |
182 | ||
183 | * opcode/ppc.h (PPC_OPCODE_E200Z4): New define. | |
184 | ||
fa3fcee7 NC |
185 | 2016-07-29 Aldy Hernandez <aldyh@redhat.com> |
186 | ||
187 | * libiberty.h (MAX_ALLOCA_SIZE): New macro. | |
188 | ||
db18dbab GM |
189 | 2016-07-27 Graham Markall <graham.markall@embecosm.com> |
190 | ||
191 | * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE, | |
192 | ARC_OPERAND_COLON. Add the arc_nps_address_type enum and | |
193 | ARC_NUM_ADDRTYPES. | |
194 | * opcode/arc.h: Add BMU to insn_class_t enum. | |
195 | * opcode/arc.h: Add PMU to insn_class_t enum. | |
196 | ||
37fd5ef3 CZ |
197 | 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com> |
198 | ||
199 | * dis-asm.h: Declare print_arc_disassembler_options. | |
200 | ||
76359541 TP |
201 | 2016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
202 | ||
203 | * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and | |
204 | out_implib_bfd fields. | |
205 | ||
fa1c0170 CZ |
206 | 2016-07-14 Claudiu Zissulescu <claziss@synopsys.com> |
207 | ||
208 | * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation. | |
209 | ||
f0728ee3 AV |
210 | 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> |
211 | ||
212 | * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ... | |
213 | (SHF_ARM_PURECODE): ... this. | |
214 | ||
93d8990c SN |
215 | 2016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com> |
216 | ||
217 | * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New. | |
218 | (AARCH64_CPU_HAS_ANY_FEATURES): New. | |
219 | (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES. | |
220 | (AARCH64_OPCODE_HAS_FEATURE): Remove. | |
221 | ||
534dbe46 MW |
222 | 2016-06-30 Matthew Wahab <matthew.wahab@arm.com> |
223 | ||
224 | * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set | |
225 | of enabled FPU features. | |
226 | ||
042c94de TS |
227 | 2016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
228 | ||
229 | * opcode/sparc.h (enum sparc_opcode_arch_val): Move | |
230 | SPARC_OPCODE_ARCH_MAX into the enum. | |
231 | ||
dab26bf4 RS |
232 | 2016-06-28 Richard Sandiford <richard.sandiford@arm.com> |
233 | ||
234 | * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t. | |
235 | ||
c9775dde MR |
236 | 2016-06-28 Maciej W. Rozycki <macro@imgtec.com> |
237 | ||
238 | * elf/mips.h (R_MIPS16_PC16_S1): New relocation. | |
239 | ||
7c2c4aa1 TS |
240 | 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
241 | ||
242 | * elf/xtensa.h (xtensa_make_property_section): New prototype. | |
243 | ||
b00f86d0 JB |
244 | 2016-06-24 John Baldwin <jhb@FreeBSD.org> |
245 | ||
246 | * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY) | |
247 | (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS) | |
248 | (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN) | |
249 | (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define. | |
250 | ||
ce440d63 GM |
251 | 2016-06-23 Graham Markall <graham.markall@embecosm.com> |
252 | ||
253 | * opcode/arc.h: Make insn_class_t alphabetical again. | |
254 | ||
6b477896 TS |
255 | 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
256 | ||
257 | * elf/dlx.h: Wrap in extern C. | |
258 | * elf/xtensa.h: Likewise. | |
259 | * opcode/arc.h: Likewise. | |
260 | ||
6edaf4d7 TS |
261 | 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
262 | ||
263 | * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into | |
264 | tilegx_pipeline. | |
265 | ||
bdd582db GM |
266 | 2016-06-21 Graham Markall <graham.markall@embecosm.com> |
267 | ||
268 | * opcode/arc.h: Add nps400 extension and instruction | |
269 | subclass. | |
270 | Remove ARC_OPCODE_NPS400 | |
271 | * elf/arc.h: Remove E_ARC_MACH_NPS400 | |
272 | ||
4f26fb3a JM |
273 | 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> |
274 | ||
275 | * opcode/sparc.h (enum sparc_opcode_arch_val): Add | |
276 | SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D, | |
277 | SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and | |
278 | SPARC_OPCODE_ARCH_V9M. | |
279 | ||
99a54ef6 JB |
280 | 2016-06-14 John Baldwin <jhb@FreeBSD.org> |
281 | ||
282 | * opcode/msp430-decode.h (MSP430_Size): Remove. | |
283 | (Msp430_Opcode_Decoded): Change type of size to int. | |
284 | ||
0eaf2e1b AM |
285 | 2016-06-11 Alan Modra <amodra@gmail.com> |
286 | ||
287 | * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define. | |
288 | ||
337c570c JM |
289 | 2016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com> |
290 | ||
291 | * opcode/sparc.h: Add missing documentation for hyperprivileged | |
292 | registers in rd (%) and rs1 ($). | |
293 | ||
14b57c7c AM |
294 | 2016-06-07 Alan Modra <amodra@gmail.com> |
295 | ||
296 | * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, | |
297 | PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, | |
298 | PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, | |
299 | PPC_APUINFO_VLE: Define. | |
300 | ||
4d1464f2 MW |
301 | 2016-06-07 Matthew Wahab <matthew.wahab@arm.com> |
302 | ||
303 | * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding | |
304 | entries. | |
305 | (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS. | |
306 | ||
4eb6f892 AB |
307 | 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com> |
308 | ||
309 | * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. | |
310 | (struct arc_long_opcode): New structure. | |
311 | (arc_long_opcodes): Declare. | |
312 | (arc_num_long_opcodes): Declare. | |
313 | ||
1fe0971e TS |
314 | 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
315 | ||
316 | * elf/mips.h: Add extern "C". | |
317 | * elf/sh.h: Likewise. | |
318 | * opcode/d10v.h: Likewise. | |
319 | * opcode/d30v.h: Likewise. | |
320 | * opcode/ia64.h: Likewise. | |
321 | * opcode/mips.h: Likewise. | |
322 | * opcode/ppc.h: Likewise. | |
323 | * opcode/sparc.h: Likewise. | |
324 | * opcode/tic6x.h: Likewise. | |
325 | * opcode/v850.h: Likewise. | |
326 | ||
1a72702b AM |
327 | 2016-05-28 Alan Modra <amodra@gmail.com> |
328 | ||
329 | * bfdlink.h (struct bfd_link_callbacks): Update comments. | |
330 | Return void from multiple_definition, multiple_common, | |
331 | add_to_set, constructor, warning, undefined_symbol, | |
332 | reloc_overflow, reloc_dangerous and unattached_reloc. | |
333 | ||
94740f9c TS |
334 | 2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
335 | ||
336 | * opcode/metag.h: wrap declarations in extern "C". | |
337 | ||
d9eca1df CZ |
338 | 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> |
339 | ||
340 | * opcode/arc.h (insn_subclass_t): Add COND. | |
341 | (flag_class_t): Add F_CLASS_EXTEND. | |
342 | ||
c810e0b8 CZ |
343 | 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> |
344 | ||
345 | * opcode/arc.h (struct arc_opcode): Renamed attribute class to | |
346 | insn_class. | |
347 | (struct arc_flag_class): Renamed attribute class to flag_class. | |
348 | ||
3d207518 TS |
349 | 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
350 | ||
351 | * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of | |
352 | plain symbol. | |
353 | ||
5ff087ac TT |
354 | 2016-04-29 Tom Tromey <tom@tromey.com> |
355 | ||
356 | * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust, | |
357 | DW_LANG_Rust_old>: New constants. | |
358 | ||
8f4f9071 MF |
359 | 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com> |
360 | ||
361 | * elf/mips.h (AFL_ASE_DSPR3): New macro. | |
362 | (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3. | |
363 | * opcode/mips.h (ASE_DSPR3): New macro. | |
364 | ||
39d911fc TP |
365 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
366 | Nick Clifton <nickc@redhat.com> | |
367 | ||
368 | * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE | |
369 | enumerator. | |
370 | (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro. | |
371 | (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise. | |
372 | (ARM_SYM_BRANCH_TYPE): Replace by ... | |
373 | (ARM_GET_SYM_BRANCH_TYPE): This and ... | |
374 | (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether | |
375 | BFD_ASSERT is defined or not. | |
376 | ||
15afaa63 TP |
377 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
378 | ||
379 | * elf/arm.h (Tag_DSP_extension): Define. | |
380 | ||
d942732e TP |
381 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
382 | ||
383 | * arm.h (ARM_FSET_CPU_SUBSET): Define macro. | |
384 | ||
16a1fa25 TP |
385 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
386 | ||
387 | * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit. | |
388 | (ARM_AEXT2_V8M_MAIN): New architecture extension feature set. | |
389 | (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M | |
390 | for the high core bits. | |
391 | ||
945e0f82 CZ |
392 | 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> |
393 | ||
394 | * opcode/arc.h (ARC_SYNTAX_1OP): Declare | |
395 | (ARC_SYNTAX_NOP): Likewsie. | |
396 | (ARC_OP1_MUST_BE_IMM): Update defined value. | |
397 | (ARC_OP1_IMM_IMPLIED): Likewise. | |
398 | (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare. | |
399 | ||
4bd13cde NC |
400 | 2016-04-28 Nick Clifton <nickc@redhat.com> |
401 | ||
402 | PR target/19722 | |
403 | * opcode/aarch64.h (struct aarch64_opcode): Add verifier field. | |
404 | ||
a6a4679f AM |
405 | 2016-04-27 Alan Modra <amodra@gmail.com> |
406 | ||
407 | * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to | |
408 | undef. Formatting. | |
409 | ||
4f3b23b3 NC |
410 | 2016-04-21 Nick Clifton <nickc@redhat.com> |
411 | ||
412 | * bfdlink.h: Add prototype for bfd_link_check_relocs. | |
413 | ||
d9689752 L |
414 | 2016-04-20 H.J. Lu <hongjiu.lu@intel.com> |
415 | ||
416 | * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input. | |
417 | ||
52176c67 AB |
418 | 2016-04-20 Andrew Burgess <andrew.burgess@embecosm.com> |
419 | ||
420 | * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula. | |
421 | ||
537aefaf AB |
422 | 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> |
423 | ||
424 | * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8. | |
425 | ||
c8f785f2 AB |
426 | 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> |
427 | ||
428 | * opcode/arc.h (insn_class_t): Add NET and ACL class. | |
429 | ||
4b0c052e AB |
430 | 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> |
431 | ||
432 | * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. | |
433 | * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. | |
434 | ||
f36e33da CZ |
435 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
436 | ||
437 | * opcode/arc.h (flag_class_t): Update. | |
438 | (ARC_OPCODE_NONE): Define. | |
439 | (ARC_OPCODE_ARCALL): Likewise. | |
440 | (ARC_OPCODE_ARCFPX): Likewise. | |
441 | (ARC_REGISTER_READONLY): Likewise. | |
442 | (ARC_REGISTER_WRITEONLY): Likewise. | |
443 | (ARC_REGISTER_NOSHORT_CUT): Likewise. | |
444 | (arc_aux_reg): Add cpu. | |
445 | ||
b99747ae CZ |
446 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
447 | ||
448 | * opcode/arc.h (arc_num_opcodes): Remove. | |
449 | (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM) | |
450 | (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND) | |
451 | (ARC_SUFFIX_FLAG): Define. | |
452 | (flags_none, flags_f, flags_cc, flags_ccf): Declare. | |
453 | (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) | |
454 | (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) | |
455 | (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) | |
456 | (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) | |
457 | (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) | |
458 | (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) | |
459 | (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) | |
460 | (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) | |
461 | (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. | |
462 | ||
463 | 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> | |
464 | ||
465 | * opcode/arc.h (DPA, DPX, SPX): New subclass enums. | |
466 | (ARC_FPUDA): Define. | |
467 | (arc_aux_reg): Add new field. | |
468 | ||
469 | 2016-04-05 Cupertino Miranda <cmiranda@synopsys.com> | |
094fb063 CZ |
470 | |
471 | * opcode/arc-func.h (replace_bits24): Changed. | |
472 | (replace_bits24_be): Created. | |
473 | ||
f2dd8838 CZ |
474 | 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> |
475 | ||
b99747ae CZ |
476 | * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass. |
477 | (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP) | |
478 | (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL) | |
479 | (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU) | |
480 | (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS) | |
481 | (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL) | |
482 | (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC) | |
483 | (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC) | |
484 | (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU) | |
485 | (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS) | |
486 | (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL) | |
487 | (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C) | |
488 | (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL) | |
489 | (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define. | |
f2dd8838 | 490 | |
b9bb4a93 TS |
491 | 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
492 | ||
493 | * opcode/i960.h: Add const qualifiers. | |
494 | * opcode/tic4x.h (struct tic4x_inst): Likewise. | |
495 | ||
e23e8ebe AB |
496 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
497 | ||
498 | * opcodes/arc.h (insn_class_t): Add BITOP type. | |
499 | ||
1ae8ab47 AB |
500 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
501 | ||
502 | * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3 | |
503 | new classes instead. | |
504 | ||
8699fc3e AB |
505 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
506 | ||
507 | * elf/arc.h (E_ARC_MACH_NPS400): Define. | |
508 | * opcode/arc.h (ARC_OPCODE_NPS400): Define. | |
509 | ||
a9522a21 AB |
510 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
511 | ||
512 | * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment. | |
513 | ||
c0334580 AB |
514 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
515 | ||
516 | * elf/arc.h (EF_ARC_MACH): Delete. | |
517 | (EF_ARC_MACH_MSK): Remove out of date comment. | |
518 | ||
24740d83 AB |
519 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
520 | ||
521 | * opcode/arc.h (ARC_OPCODE_BASE): Delete. | |
522 | ||
4c10bbaa L |
523 | 2016-03-15 H.J. Lu <hongjiu.lu@intel.com> |
524 | ||
525 | PR ld/19807 | |
526 | * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check. | |
527 | ||
72f3b6aa CZ |
528 | 2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com> |
529 | Andrew Burgess <andrew.burgess@embecosm.com> | |
530 | ||
531 | * elf/arc-reloc.def: Add a call to ME within the formula for each | |
532 | relocation that requires middle-endian correction. | |
533 | ||
f86f5863 TS |
534 | 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
535 | ||
536 | * opcode/dlx.h (struct dlx_opcode): Add const qualifiers. | |
537 | * opcode/h8300.h (struct h8_opcode): Likewise. | |
538 | * opcode/hppa.h (struct pa_opcode): Likewise. | |
539 | * opcode/msp430.h: Likewise. | |
540 | * opcode/spu.h (struct spu_opcode): Likewise. | |
541 | * opcode/tic30.h (struct _register): Likewise. | |
542 | * opcode/tic4x.h (struct tic4x_register): Likewise. | |
543 | (struct tic4x_cond): Likewise. | |
544 | (struct tic4x_indirect): Likewise. | |
545 | (struct tic4x_inst): Likewise. | |
546 | * opcode/visium.h (struct reg_entry): Likewise. | |
547 | ||
643afb90 MW |
548 | 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> |
549 | ||
550 | * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA. | |
551 | (ARM_CPU_HAS_FEATURE): Add comment. | |
552 | ||
3f1f41f5 L |
553 | 2016-03-03 Than McIntosh <thanm@google.com> |
554 | ||
555 | * plugin-api.h: Add new hooks to the plugin transfer vector to | |
556 | to support querying section alignment and section size. | |
557 | (ld_plugin_get_input_section_alignment): New hook. | |
558 | (ld_plugin_get_input_section_size): New hook. | |
559 | (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT | |
560 | and LDPT_GET_INPUT_SECTION_SIZE. | |
561 | (ld_plugin_tv): Add tv_get_input_section_alignment and | |
562 | tv_get_input_section_size. | |
563 | ||
9b738e36 | 564 | 2016-03-03 Evgenii Stepanov <eugenis@google.com> |
95ecdfbf ES |
565 | |
566 | * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3. | |
567 | ||
11e5f1ec L |
568 | 2016-02-26 H.J. Lu <hongjiu.lu@intel.com> |
569 | ||
570 | PR ld/19645 | |
571 | * bfdlink.h (bfd_link_elf_stt_common): New enum. | |
572 | (bfd_link_info): Add elf_stt_common. | |
573 | ||
aec6b87e L |
574 | 2016-02-26 H.J. Lu <hongjiu.lu@intel.com> |
575 | ||
576 | PR ld/19636 | |
577 | PR ld/19704 | |
578 | PR ld/19719 | |
579 | * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak. | |
580 | ||
b8ec4e87 JW |
581 | 2016-02-19 Matthew Wahab <matthew.wahab@arm.com> |
582 | Jiong Wang <jiong.wang@arm.com> | |
583 | ||
584 | * opcode/arm.h (ARM_EXT2_FP16_INSN): New. | |
585 | ||
4670103e CZ |
586 | 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com> |
587 | Janek van Oirschot <jvanoirs@synopsys.com> | |
588 | ||
b99747ae CZ |
589 | * opcode/arc.h (arc_opcode arc_relax_opcodes) |
590 | (arc_num_relax_opcodes): Declare. | |
4670103e | 591 | |
609332f1 NC |
592 | 2016-02-09 Nick Clifton <nickc@redhat.com> |
593 | ||
594 | * opcode/metag.h (metag_scondtab): Mark as possibly unused. | |
595 | * opcode/nds32.h (nds32_r45map): Likewise. | |
596 | (nds32_r54map): Likewise. | |
597 | * opcode/visium.h (gen_reg_table): Likewise. | |
598 | (fp_reg_table, cc_table, opcode_table): Likewise. | |
599 | ||
24f5f69a AM |
600 | 2016-02-09 Alan Modra <amodra@gmail.com> |
601 | ||
602 | PR 16583 | |
603 | * elf/common.h (AT_SUN_HWCAP): Undef before defining. | |
604 | ||
c1d9289f NC |
605 | 2016-02-04 Nick Clifton <nickc@redhat.com> |
606 | ||
607 | PR target/19561 | |
608 | * opcode/msp430.h (IGNORE_CARRY_BIT): New define. | |
609 | (RRUX): Synthesise using case 2 rather than 7. | |
610 | ||
f4ddf30f JB |
611 | 2016-01-19 John Baldwin <jhb@FreeBSD.org> |
612 | ||
613 | * elf/common.h (NT_FREEBSD_THRMISC): Define. | |
614 | (NT_FREEBSD_PROCSTAT_PROC): Define. | |
615 | (NT_FREEBSD_PROCSTAT_FILES): Define. | |
616 | (NT_FREEBSD_PROCSTAT_VMMAP): Define. | |
617 | (NT_FREEBSD_PROCSTAT_GROUPS): Define. | |
618 | (NT_FREEBSD_PROCSTAT_UMASK): Define. | |
619 | (NT_FREEBSD_PROCSTAT_RLIMIT): Define. | |
620 | (NT_FREEBSD_PROCSTAT_OSREL): Define. | |
621 | (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define. | |
622 | (NT_FREEBSD_PROCSTAT_AUXV): Define. | |
623 | ||
34e967a5 MC |
624 | 2016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com> |
625 | Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com> | |
626 | ||
627 | * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT) | |
628 | (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9) | |
629 | (ARC_TLS_LE_32): Fixed formula. | |
630 | (ARC_TLS_GD_LD): Use new special function. | |
631 | * opcode/arc-func.h: Changed all the replacement | |
632 | functions to clear the patching bits before doing an or it with the value | |
633 | argument. | |
634 | ||
9ae678af NC |
635 | 2016-01-18 Nick Clifton <nickc@redhat.com> |
636 | ||
637 | PR ld/19440 | |
638 | * coff/internal.h (internal_syment): Use int to hold section | |
639 | number. | |
640 | (N_UNDEF): Cast to int not short. | |
641 | (N_ABS): Likewise. | |
642 | (N_DEBUG): Likewise. | |
643 | (N_TV): Likewise. | |
644 | (P_TV): Likewise. | |
645 | ||
4849dfd8 NC |
646 | 2016-01-11 Nick Clifton <nickc@redhat.com> |
647 | ||
648 | Import this change from GCC mainline: | |
649 | ||
650 | 2016-01-07 Mike Frysinger <vapier@gentoo.org> | |
651 | ||
652 | * longlong.h: Change !__SHMEDIA__ to | |
653 | (!defined (__SHMEDIA__) || !__SHMEDIA__). | |
654 | Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__. | |
655 | ||
b31e4803 MR |
656 | 2016-01-06 Maciej W. Rozycki <macro@imgtec.com> |
657 | ||
658 | * opcode/mips.h: Add a summary of MIPS16 operand codes. | |
659 | ||
b36c1ccb MF |
660 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
661 | ||
662 | * libiberty.h (dupargv): Change arg to char * const *. | |
663 | (writeargv, countargv): Likewise. | |
664 | ||
6f2750fe AM |
665 | 2016-01-01 Alan Modra <amodra@gmail.com> |
666 | ||
667 | Update year range in copyright notice of all files. | |
668 | ||
3499769a AM |
669 | For older changes see ChangeLog-0415, aout/ChangeLog-9115, |
670 | cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415, | |
671 | mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415, | |
672 | som/ChangeLog-1015, and vms/ChangeLog-1015 | |
673 | \f | |
674 | Copyright (C) 2016 Free Software Foundation, Inc. | |
675 | ||
676 | Copying and distribution of this file, with or without modification, | |
677 | are permitted in any medium without royalty provided the copyright | |
678 | notice and this notice are preserved. | |
679 | ||
680 | Local Variables: | |
681 | mode: change-log | |
682 | left-margin: 8 | |
683 | fill-column: 74 | |
684 | version-control: never | |
685 | End: |